1 # script for stm32f0x family
4 # stm32 devices support SWD transports only.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
11 set _CHIPNAME stm32f0x
14 if { [info exists ENDIAN] } {
20 # Work-area is a space in RAM used for flash programming
22 if { [info exists WORKAREASIZE] } {
23 set _WORKAREASIZE $WORKAREASIZE
25 set _WORKAREASIZE 0x1000
29 if { [info exists CPUTAPID] } {
30 set _CPUTAPID $CPUTAPID
32 # See STM Document RM0091
34 set _CPUTAPID 0x0bb11477
37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
39 set _TARGETNAME $_CHIPNAME.cpu
40 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
42 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
44 # flash size will be probed
45 set _FLASHNAME $_CHIPNAME.flash
46 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
48 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
51 adapter_nsrst_delay 100
53 # if srst is not fitted use SYSRESETREQ to
54 # perform a soft reset
55 cortex_m reset_config sysresetreq