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flash: samd: add missing ID for SAMD20E18A
[openocd.git] / src / flash / nor / at91samd.c
blob7d25b4c5148853ce45cdac30fd584d612379b553
1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26
27 #define SAMD_NUM_SECTORS 16
28
29 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
30 #define SAMD_DSU 0x41002000 /* Device Service Unit */
31 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
32
33 #define SAMD_DSU_DID 0x18 /* Device ID register */
34
35 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
36 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
37 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
38 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
39 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
40 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
41 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
42
43 #define SAMD_CMDEX_KEY 0xA5UL
44 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
45
46 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
47 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
48 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
49 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
50 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
51 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
52 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
53 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
54 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
55 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
56 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
57 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
58
59 /* Known identifiers */
60 #define SAMD_PROCESSOR_M0 0x01
61 #define SAMD_FAMILY_D 0x00
62 #define SAMD_SERIES_20 0x00
63 #define SAMD_SERIES_21 0x01
64 #define SAMD_SERIES_10 0x02
65 #define SAMD_SERIES_11 0x03
66
67 struct samd_part {
68 uint8_t id;
69 const char *name;
70 uint32_t flash_kb;
71 uint32_t ram_kb;
72 };
73
74 /* Known SAMD10 parts */
75 static const struct samd_part samd10_parts[] = {
76 { 0x0, "SAMD10D14AMU", 16, 4 },
77 { 0x1, "SAMD10D13AMU", 8, 4 },
78 { 0x2, "SAMD10D12AMU", 4, 4 },
79 { 0x3, "SAMD10D14ASU", 16, 4 },
80 { 0x4, "SAMD10D13ASU", 8, 4 },
81 { 0x5, "SAMD10D12ASU", 4, 4 },
82 { 0x6, "SAMD10C14A", 16, 4 },
83 { 0x7, "SAMD10C13A", 8, 4 },
84 { 0x8, "SAMD10C12A", 4, 4 },
85 };
86
87 /* Known SAMD11 parts */
88 static const struct samd_part samd11_parts[] = {
89 { 0x0, "SAMD11D14AMU", 16, 4 },
90 { 0x1, "SAMD11D13AMU", 8, 4 },
91 { 0x2, "SAMD11D12AMU", 4, 4 },
92 { 0x3, "SAMD11D14ASU", 16, 4 },
93 { 0x4, "SAMD11D13ASU", 8, 4 },
94 { 0x5, "SAMD11D12ASU", 4, 4 },
95 { 0x6, "SAMD11C14A", 16, 4 },
96 { 0x7, "SAMD11C13A", 8, 4 },
97 { 0x8, "SAMD11C12A", 4, 4 },
98 };
99
100 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
101 static const struct samd_part samd20_parts[] = {
102 { 0x0, "SAMD20J18A", 256, 32 },
103 { 0x1, "SAMD20J17A", 128, 16 },
104 { 0x2, "SAMD20J16A", 64, 8 },
105 { 0x3, "SAMD20J15A", 32, 4 },
106 { 0x4, "SAMD20J14A", 16, 2 },
107 { 0x5, "SAMD20G18A", 256, 32 },
108 { 0x6, "SAMD20G17A", 128, 16 },
109 { 0x7, "SAMD20G16A", 64, 8 },
110 { 0x8, "SAMD20G15A", 32, 4 },
111 { 0x9, "SAMD20G14A", 16, 2 },
112 { 0xA, "SAMD20E18A", 256, 32 },
113 { 0xB, "SAMD20E17A", 128, 16 },
114 { 0xC, "SAMD20E16A", 64, 8 },
115 { 0xD, "SAMD20E15A", 32, 4 },
116 { 0xE, "SAMD20E14A", 16, 2 },
117 };
118
119 /* Known SAMD21 parts. */
120 static const struct samd_part samd21_parts[] = {
121 { 0x0, "SAMD21J18A", 256, 32 },
122 { 0x1, "SAMD21J17A", 128, 16 },
123 { 0x2, "SAMD21J16A", 64, 8 },
124 { 0x3, "SAMD21J15A", 32, 4 },
125 { 0x4, "SAMD21J14A", 16, 2 },
126 { 0x5, "SAMD21G18A", 256, 32 },
127 { 0x6, "SAMD21G17A", 128, 16 },
128 { 0x7, "SAMD21G16A", 64, 8 },
129 { 0x8, "SAMD21G15A", 32, 4 },
130 { 0x9, "SAMD21G14A", 16, 2 },
131 { 0xA, "SAMD21E18A", 256, 32 },
132 { 0xB, "SAMD21E17A", 128, 16 },
133 { 0xC, "SAMD21E16A", 64, 8 },
134 { 0xD, "SAMD21E15A", 32, 4 },
135 { 0xE, "SAMD21E14A", 16, 2 },
136 };
137
138 /* Known SAMR21 parts. */
139 static const struct samd_part samr21_parts[] = {
140 { 0x19, "SAMR21G18A", 256, 32 },
141 { 0x1A, "SAMR21G17A", 128, 32 },
142 { 0x1B, "SAMR21G16A", 64, 32 },
143 { 0x1C, "SAMR21E18A", 256, 32 },
144 { 0x1D, "SAMR21E17A", 128, 32 },
145 { 0x1E, "SAMR21E16A", 64, 32 },
146 };
147
148
149 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
150 * processor ID, family ID, and series ID are used to determine which exact
151 * family this is and then we can use the corresponding table. */
152 struct samd_family {
153 uint8_t processor;
154 uint8_t family;
155 uint8_t series;
156 const struct samd_part *parts;
157 size_t num_parts;
158 };
159
160 /* Known SAMD families */
161 static const struct samd_family samd_families[] = {
162 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
163 samd20_parts, ARRAY_SIZE(samd20_parts) },
164 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
165 samd21_parts, ARRAY_SIZE(samd21_parts) },
166 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
167 samr21_parts, ARRAY_SIZE(samr21_parts) },
168 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
169 samd10_parts, ARRAY_SIZE(samd10_parts) },
170 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
171 samd11_parts, ARRAY_SIZE(samd11_parts) },
172 };
173
174 struct samd_info {
175 uint32_t page_size;
176 int num_pages;
177 int sector_size;
178
179 bool probed;
180 struct target *target;
181 struct samd_info *next;
182 };
183
184 static struct samd_info *samd_chips;
185
186 static const struct samd_part *samd_find_part(uint32_t id)
187 {
188 uint8_t processor = (id >> 28);
189 uint8_t family = (id >> 24) & 0x0F;
190 uint8_t series = (id >> 16) & 0xFF;
191 uint8_t devsel = id & 0xFF;
192
193 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
194 if (samd_families[i].processor == processor &&
195 samd_families[i].series == series &&
196 samd_families[i].family == family) {
197 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
198 if (samd_families[i].parts[j].id == devsel)
199 return &samd_families[i].parts[j];
200 }
201 }
202 }
203
204 return NULL;
205 }
206
207 static int samd_protect_check(struct flash_bank *bank)
208 {
209 int res;
210 uint16_t lock;
211
212 res = target_read_u16(bank->target,
213 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
214 if (res != ERROR_OK)
215 return res;
216
217 /* Lock bits are active-low */
218 for (int i = 0; i < bank->num_sectors; i++)
219 bank->sectors[i].is_protected = !(lock & (1<<i));
220
221 return ERROR_OK;
222 }
223
224 static int samd_probe(struct flash_bank *bank)
225 {
226 uint32_t id, param;
227 int res;
228 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
229 const struct samd_part *part;
230
231 if (chip->probed)
232 return ERROR_OK;
233
234 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
235 if (res != ERROR_OK) {
236 LOG_ERROR("Couldn't read Device ID register");
237 return res;
238 }
239
240 part = samd_find_part(id);
241 if (part == NULL) {
242 LOG_ERROR("Couldn't find part correspoding to DID %08" PRIx32, id);
243 return ERROR_FAIL;
244 }
245
246 res = target_read_u32(bank->target,
247 SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
248 if (res != ERROR_OK) {
249 LOG_ERROR("Couldn't read NVM Parameters register");
250 return res;
251 }
252
253 bank->size = part->flash_kb * 1024;
254
255 chip->sector_size = bank->size / SAMD_NUM_SECTORS;
256
257 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n) so
258 * 0 is 8KB and 7 is 1024KB. */
259 chip->page_size = (8 << ((param >> 16) & 0x7));
260 /* The NVMP field (bits 15:0) indicates the total number of pages */
261 chip->num_pages = param & 0xFFFF;
262
263 /* Sanity check: the total flash size in the DSU should match the page size
264 * multiplied by the number of pages. */
265 if (bank->size != chip->num_pages * chip->page_size) {
266 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
267 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
268 part->flash_kb, chip->num_pages, chip->page_size);
269 }
270
271 /* Allocate the sector table */
272 bank->num_sectors = SAMD_NUM_SECTORS;
273 bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
274 if (!bank->sectors)
275 return ERROR_FAIL;
276
277 /* Fill out the sector information: all SAMD sectors are the same size and
278 * there is always a fixed number of them. */
279 for (int i = 0; i < bank->num_sectors; i++) {
280 bank->sectors[i].size = chip->sector_size;
281 bank->sectors[i].offset = i * chip->sector_size;
282 /* mark as unknown */
283 bank->sectors[i].is_erased = -1;
284 bank->sectors[i].is_protected = -1;
285 }
286
287 samd_protect_check(bank);
288
289 /* Done */
290 chip->probed = true;
291
292 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
293 part->flash_kb, part->ram_kb);
294
295 return ERROR_OK;
296 }
297
298 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
299 {
300 int res;
301 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
302
303 res = ERROR_OK;
304
305 for (int s = first; s <= last; s++) {
306 if (set != bank->sectors[s].is_protected) {
307 /* Load an address that is within this sector (we use offset 0) */
308 res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
309 s * chip->sector_size);
310 if (res != ERROR_OK)
311 goto exit;
312
313 /* Tell the controller to lock that sector */
314
315 uint16_t cmd = (set) ?
316 SAMD_NVM_CMD(SAMD_NVM_CMD_LR) :
317 SAMD_NVM_CMD(SAMD_NVM_CMD_UR);
318
319 res = target_write_u16(bank->target,
320 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
321 cmd);
322 if (res != ERROR_OK)
323 goto exit;
324 }
325 }
326 exit:
327 samd_protect_check(bank);
328
329 return res;
330 }
331
332 static bool samd_check_error(struct flash_bank *bank)
333 {
334 int ret;
335 bool error;
336 uint16_t status;
337
338 ret = target_read_u16(bank->target,
339 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
340 if (ret != ERROR_OK) {
341 LOG_ERROR("Can't read NVM status");
342 return true;
343 }
344
345 if (status & 0x001C) {
346 if (status & (1 << 4)) /* NVME */
347 LOG_ERROR("SAMD: NVM Error");
348 if (status & (1 << 3)) /* LOCKE */
349 LOG_ERROR("SAMD: NVM lock error");
350 if (status & (1 << 2)) /* PROGE */
351 LOG_ERROR("SAMD: NVM programming error");
352
353 error = true;
354 } else {
355 error = false;
356 }
357
358 /* Clear the error conditions by writing a one to them */
359 ret = target_write_u16(bank->target,
360 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
361 if (ret != ERROR_OK)
362 LOG_ERROR("Can't clear NVM error conditions");
363
364 return error;
365 }
366
367 static int samd_erase_row(struct flash_bank *bank, uint32_t address)
368 {
369 int res;
370 bool error = false;
371
372 /* Set an address contained in the row to be erased */
373 res = target_write_u32(bank->target,
374 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
375 if (res == ERROR_OK) {
376 /* Issue the Erase Row command to erase that row */
377 res = target_write_u16(bank->target,
378 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
379 SAMD_NVM_CMD(SAMD_NVM_CMD_ER));
380
381 /* Check (and clear) error conditions */
382 error = samd_check_error(bank);
383 }
384
385 if (res != ERROR_OK || error) {
386 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
387 return ERROR_FAIL;
388 }
389
390 return ERROR_OK;
391 }
392
393 static int samd_erase(struct flash_bank *bank, int first, int last)
394 {
395 int res;
396 int rows_in_sector;
397 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
398
399 if (bank->target->state != TARGET_HALTED) {
400 LOG_ERROR("Target not halted");
401
402 return ERROR_TARGET_NOT_HALTED;
403 }
404
405 if (!chip->probed) {
406 if (samd_probe(bank) != ERROR_OK)
407 return ERROR_FLASH_BANK_NOT_PROBED;
408 }
409
410 /* The SAMD NVM has row erase granularity. There are four pages in a row
411 * and the number of rows in a sector depends on the sector size, which in
412 * turn depends on the Flash capacity as there is a fixed number of
413 * sectors. */
414 rows_in_sector = chip->sector_size / (chip->page_size * 4);
415
416 /* For each sector to be erased */
417 for (int s = first; s <= last; s++) {
418 if (bank->sectors[s].is_protected) {
419 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
420 return ERROR_FLASH_OPERATION_FAILED;
421 }
422
423 if (!bank->sectors[s].is_erased) {
424 /* For each row in that sector */
425 for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
426 res = samd_erase_row(bank, r * chip->page_size * 4);
427 if (res != ERROR_OK) {
428 LOG_ERROR("SAMD: failed to erase sector %d", s);
429 return res;
430 }
431 }
432
433 bank->sectors[s].is_erased = 1;
434 }
435 }
436
437 return ERROR_OK;
438 }
439
440 static struct flash_sector *samd_find_sector_by_address(struct flash_bank *bank, uint32_t address)
441 {
442 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
443
444 for (int i = 0; i < bank->num_sectors; i++) {
445 if (bank->sectors[i].offset <= address &&
446 address < bank->sectors[i].offset + chip->sector_size)
447 return &bank->sectors[i];
448 }
449 return NULL;
450 }
451
452 /* Write an entire row (four pages) from host buffer 'buf' to row-aligned
453 * 'address' in the Flash. */
454 static int samd_write_row(struct flash_bank *bank, uint32_t address,
455 const uint8_t *buf)
456 {
457 int res;
458 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
459
460 struct flash_sector *sector = samd_find_sector_by_address(bank, address);
461
462 if (!sector) {
463 LOG_ERROR("Can't find sector corresponding to address 0x%08" PRIx32, address);
464 return ERROR_FLASH_OPERATION_FAILED;
465 }
466
467 if (sector->is_protected) {
468 LOG_ERROR("Trying to write to a protected sector at 0x%08" PRIx32, address);
469 return ERROR_FLASH_OPERATION_FAILED;
470 }
471
472 /* Erase the row that we'll be writing to */
473 res = samd_erase_row(bank, address);
474 if (res != ERROR_OK)
475 return res;
476
477 /* Now write the pages in this row. */
478 for (unsigned int i = 0; i < 4; i++) {
479 bool error;
480
481 /* Write the page contents to the target's page buffer. A page write
482 * is issued automatically once the last location is written in the
483 * page buffer (ie: a complete page has been written out). */
484 res = target_write_memory(bank->target, address, 4,
485 chip->page_size / 4, buf);
486 if (res != ERROR_OK) {
487 LOG_ERROR("%s: %d", __func__, __LINE__);
488 return res;
489 }
490
491 error = samd_check_error(bank);
492 if (error)
493 return ERROR_FAIL;
494
495 /* Next page */
496 address += chip->page_size;
497 buf += chip->page_size;
498 }
499
500 sector->is_erased = 0;
501
502 return res;
503 }
504
505 /* Write partial contents into row-aligned 'address' on the Flash from host
506 * buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */
507 static int samd_write_row_partial(struct flash_bank *bank, uint32_t address,
508 const uint8_t *buf, uint32_t row_offset, uint32_t nb)
509 {
510 int res;
511 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
512 uint32_t row_size = chip->page_size * 4;
513 uint8_t *rb = malloc(row_size);
514 if (!rb)
515 return ERROR_FAIL;
516
517 assert(row_offset + nb < row_size);
518 assert((address % row_size) == 0);
519
520 /* Retrieve the full row contents from Flash */
521 res = target_read_memory(bank->target, address, 4, row_size / 4, rb);
522 if (res != ERROR_OK) {
523 free(rb);
524 return res;
525 }
526
527 /* Insert our partial row over the data from Flash */
528 memcpy(rb + (row_offset % row_size), buf, nb);
529
530 /* Write the row back out */
531 res = samd_write_row(bank, address, rb);
532 free(rb);
533
534 return res;
535 }
536
537 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
538 uint32_t offset, uint32_t count)
539 {
540 int res;
541 uint32_t address;
542 uint32_t nb = 0;
543 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
544 uint32_t row_size = chip->page_size * 4;
545
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548
549 return ERROR_TARGET_NOT_HALTED;
550 }
551
552 if (!chip->probed) {
553 if (samd_probe(bank) != ERROR_OK)
554 return ERROR_FLASH_BANK_NOT_PROBED;
555 }
556
557 if (offset % row_size) {
558 /* We're starting at an unaligned offset so we'll write a partial row
559 * comprising that offset and up to the end of that row. */
560 nb = row_size - (offset % row_size);
561 if (nb > count)
562 nb = count;
563 } else if (count < row_size) {
564 /* We're writing an aligned but partial row. */
565 nb = count;
566 }
567
568 address = (offset / row_size) * row_size + bank->base;
569
570 if (nb > 0) {
571 res = samd_write_row_partial(bank, address, buffer,
572 offset % row_size, nb);
573 if (res != ERROR_OK)
574 return res;
575
576 /* We're done with the row contents */
577 count -= nb;
578 offset += nb;
579 buffer += row_size;
580 }
581
582 /* There's at least one aligned row to write out. */
583 if (count >= row_size) {
584 int nr = count / row_size + ((count % row_size) ? 1 : 0);
585 unsigned int r = 0;
586
587 for (unsigned int i = address / row_size;
588 (i < (address / row_size) + nr) && count > 0; i++) {
589 address = (i * row_size) + bank->base;
590
591 if (count >= row_size) {
592 res = samd_write_row(bank, address, buffer + (r * row_size));
593 /* Advance one row */
594 offset += row_size;
595 count -= row_size;
596 } else {
597 res = samd_write_row_partial(bank, address,
598 buffer + (r * row_size), 0, count);
599 /* We're done after this. */
600 offset += count;
601 count = 0;
602 }
603
604 r++;
605
606 if (res != ERROR_OK)
607 return res;
608 }
609 }
610
611 return ERROR_OK;
612 }
613
614 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
615 {
616 struct samd_info *chip = samd_chips;
617
618 while (chip) {
619 if (chip->target == bank->target)
620 break;
621 chip = chip->next;
622 }
623
624 if (!chip) {
625 /* Create a new chip */
626 chip = calloc(1, sizeof(*chip));
627 if (!chip)
628 return ERROR_FAIL;
629
630 chip->target = bank->target;
631 chip->probed = false;
632
633 bank->driver_priv = chip;
634
635 /* Insert it into the chips list (at head) */
636 chip->next = samd_chips;
637 samd_chips = chip;
638 }
639
640 if (bank->base != SAMD_FLASH) {
641 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
642 "[at91samd series] )",
643 bank->base, SAMD_FLASH);
644 return ERROR_FAIL;
645 }
646
647 return ERROR_OK;
648 }
649
650 COMMAND_HANDLER(samd_handle_info_command)
651 {
652 return ERROR_OK;
653 }
654
655 static const struct command_registration at91samd_exec_command_handlers[] = {
656 {
657 .name = "info",
658 .handler = samd_handle_info_command,
659 .mode = COMMAND_EXEC,
660 .help = "Print information about the current at91samd chip"
661 "and its flash configuration.",
662 },
663 COMMAND_REGISTRATION_DONE
664 };
665
666 static const struct command_registration at91samd_command_handlers[] = {
667 {
668 .name = "at91samd",
669 .mode = COMMAND_ANY,
670 .help = "at91samd flash command group",
671 .usage = "",
672 .chain = at91samd_exec_command_handlers,
673 },
674 COMMAND_REGISTRATION_DONE
675 };
676
677 struct flash_driver at91samd_flash = {
678 .name = "at91samd",
679 .commands = at91samd_command_handlers,
680 .flash_bank_command = samd_flash_bank_command,
681 .erase = samd_erase,
682 .protect = samd_protect,
683 .write = samd_write,
684 .read = default_flash_read,
685 .probe = samd_probe,
686 .auto_probe = samd_probe,
687 .erase_check = default_flash_blank_check,
688 .protect_check = samd_protect_check,
689 };
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