src/target/cortex_m.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2006 by Magnus Lundin                                   *
   8  *   lundin@mlu.mine.nu                                                    *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  ***************************************************************************/
  13
  14 #ifndef OPENOCD_TARGET_CORTEX_M_H
  15 #define OPENOCD_TARGET_CORTEX_M_H
  16
  17 #include "armv7m.h"
  18 #include "helper/bits.h"
  19
  20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
  21
  22 #define SYSTEM_CONTROL_BASE 0x400FE000
  23
  24 #define ITM_TER0        0xE0000E00
  25 #define ITM_TPR         0xE0000E40
  26 #define ITM_TCR         0xE0000E80
  27 #define ITM_TCR_ITMENA_BIT      BIT(0)
  28 #define ITM_TCR_BUSY_BIT        BIT(23)
  29 #define ITM_LAR         0xE0000FB0
  30 #define ITM_LAR_KEY     0xC5ACCE55
  31
  32 #define CPUID           0xE000ED00
  33
  34 #define ARM_CPUID_IMPLEMENTOR_POS       24
  35 #define ARM_CPUID_IMPLEMENTOR_MASK      (0xFF << ARM_CPUID_IMPLEMENTOR_POS)
  36 #define ARM_CPUID_PARTNO_POS            4
  37 #define ARM_CPUID_PARTNO_MASK           (0xFFF << ARM_CPUID_PARTNO_POS)
  38
  39 #define ARM_MAKE_CPUID(impl, partno)    ((((impl) << ARM_CPUID_IMPLEMENTOR_POS) & ARM_CPUID_IMPLEMENTOR_MASK) | \
  40         (((partno) << ARM_CPUID_PARTNO_POS)  & ARM_CPUID_PARTNO_MASK))
  41
  42 /** Known Arm Cortex masked CPU Ids
  43  * This includes the implementor and part number, but _not_ the revision or
  44  * patch fields.
  45  */
  46 enum cortex_m_impl_part {
  47         CORTEX_M_PARTNO_INVALID,
  48         STAR_MC1_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
  49         CORTEX_M0_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC20),
  50         CORTEX_M1_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC21),
  51         CORTEX_M3_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC23),
  52         CORTEX_M4_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC24),
  53         CORTEX_M7_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC27),
  54         CORTEX_M0P_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC60),
  55         CORTEX_M23_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD20),
  56         CORTEX_M33_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
  57         CORTEX_M35P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
  58         CORTEX_M55_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
  59         REALTEK_M200_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd20),
  60         REALTEK_M300_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd22),
  61 };
  62
  63 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
  64 #define CORTEX_M_F_HAS_FPV4               BIT(0)
  65 #define CORTEX_M_F_HAS_FPV5               BIT(1)
  66 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K  BIT(2)
  67
  68 struct cortex_m_part_info {
  69         enum cortex_m_impl_part impl_part;
  70         const char *name;
  71         enum arm_arch arch;
  72         uint32_t flags;
  73 };
  74
  75 /* Debug Control Block */
  76 #define DCB_DHCSR       0xE000EDF0
  77 #define DCB_DCRSR       0xE000EDF4
  78 #define DCB_DCRDR       0xE000EDF8
  79 #define DCB_DEMCR       0xE000EDFC
  80 #define DCB_DSCSR       0xE000EE08
  81
  82 #define DAUTHSTATUS     0xE000EFB8
  83 #define DAUTHSTATUS_SID_MASK    0x00000030
  84
  85 #define DCRSR_WNR       BIT(16)
  86
  87 #define DWT_CTRL        0xE0001000
  88 #define DWT_CYCCNT      0xE0001004
  89 #define DWT_PCSR        0xE000101C
  90 #define DWT_COMP0       0xE0001020
  91 #define DWT_MASK0       0xE0001024
  92 #define DWT_FUNCTION0   0xE0001028
  93 #define DWT_DEVARCH             0xE0001FBC
  94
  95 #define DWT_DEVARCH_ARMV8M      0x101A02
  96
  97 #define FP_CTRL         0xE0002000
  98 #define FP_REMAP        0xE0002004
  99 #define FP_COMP0        0xE0002008
 100 #define FP_COMP1        0xE000200C
 101 #define FP_COMP2        0xE0002010
 102 #define FP_COMP3        0xE0002014
 103 #define FP_COMP4        0xE0002018
 104 #define FP_COMP5        0xE000201C
 105 #define FP_COMP6        0xE0002020
 106 #define FP_COMP7        0xE0002024
 107
 108 #define FPU_CPACR       0xE000ED88
 109 #define FPU_FPCCR       0xE000EF34
 110 #define FPU_FPCAR       0xE000EF38
 111 #define FPU_FPDSCR      0xE000EF3C
 112
 113 #define TPIU_SSPSR      0xE0040000
 114 #define TPIU_CSPSR      0xE0040004
 115 #define TPIU_ACPR       0xE0040010
 116 #define TPIU_SPPR       0xE00400F0
 117 #define TPIU_FFSR       0xE0040300
 118 #define TPIU_FFCR       0xE0040304
 119 #define TPIU_FSCR       0xE0040308
 120
 121 /* Maximum SWO prescaler value. */
 122 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
 123
 124 /* DCB_DHCSR bit and field definitions */
 125 #define DBGKEY          (0xA05Ful << 16)
 126 #define C_DEBUGEN       BIT(0)
 127 #define C_HALT          BIT(1)
 128 #define C_STEP          BIT(2)
 129 #define C_MASKINTS      BIT(3)
 130 #define S_REGRDY        BIT(16)
 131 #define S_HALT          BIT(17)
 132 #define S_SLEEP         BIT(18)
 133 #define S_LOCKUP        BIT(19)
 134 #define S_RETIRE_ST     BIT(24)
 135 #define S_RESET_ST      BIT(25)
 136
 137 /* DCB_DEMCR bit and field definitions */
 138 #define TRCENA                  BIT(24)
 139 #define VC_HARDERR              BIT(10)
 140 #define VC_INTERR               BIT(9)
 141 #define VC_BUSERR               BIT(8)
 142 #define VC_STATERR              BIT(7)
 143 #define VC_CHKERR               BIT(6)
 144 #define VC_NOCPERR              BIT(5)
 145 #define VC_MMERR                BIT(4)
 146 #define VC_CORERESET    BIT(0)
 147
 148 /* DCB_DSCSR bit and field definitions */
 149 #define DSCSR_CDS               BIT(16)
 150
 151 /* NVIC registers */
 152 #define NVIC_ICTR               0xE000E004
 153 #define NVIC_ISE0               0xE000E100
 154 #define NVIC_ICSR               0xE000ED04
 155 #define NVIC_AIRCR              0xE000ED0C
 156 #define NVIC_SHCSR              0xE000ED24
 157 #define NVIC_CFSR               0xE000ED28
 158 #define NVIC_MMFSRB             0xE000ED28
 159 #define NVIC_BFSRB              0xE000ED29
 160 #define NVIC_USFSRH             0xE000ED2A
 161 #define NVIC_HFSR               0xE000ED2C
 162 #define NVIC_DFSR               0xE000ED30
 163 #define NVIC_MMFAR              0xE000ED34
 164 #define NVIC_BFAR               0xE000ED38
 165 #define NVIC_SFSR               0xE000EDE4
 166 #define NVIC_SFAR               0xE000EDE8
 167
 168 /* NVIC_AIRCR bits */
 169 #define AIRCR_VECTKEY           (0x5FAul << 16)
 170 #define AIRCR_SYSRESETREQ       BIT(2)
 171 #define AIRCR_VECTCLRACTIVE     BIT(1)
 172 #define AIRCR_VECTRESET         BIT(0)
 173 /* NVIC_SHCSR bits */
 174 #define SHCSR_BUSFAULTENA       BIT(17)
 175 /* NVIC_DFSR bits */
 176 #define DFSR_HALTED                     1
 177 #define DFSR_BKPT                       2
 178 #define DFSR_DWTTRAP            4
 179 #define DFSR_VCATCH                     8
 180 #define DFSR_EXTERNAL           16
 181
 182 #define FPCR_CODE 0
 183 #define FPCR_LITERAL 1
 184 #define FPCR_REPLACE_REMAP  (0ul << 30)
 185 #define FPCR_REPLACE_BKPT_LOW  (1ul << 30)
 186 #define FPCR_REPLACE_BKPT_HIGH  (2ul << 30)
 187 #define FPCR_REPLACE_BKPT_BOTH  (3ul << 30)
 188
 189 struct cortex_m_fp_comparator {
 190         bool used;
 191         int type;
 192         uint32_t fpcr_value;
 193         uint32_t fpcr_address;
 194 };
 195
 196 struct cortex_m_dwt_comparator {
 197         bool used;
 198         uint32_t comp;
 199         uint32_t mask;
 200         uint32_t function;
 201         uint32_t dwt_comparator_address;
 202 };
 203
 204 enum cortex_m_soft_reset_config {
 205         CORTEX_M_RESET_SYSRESETREQ,
 206         CORTEX_M_RESET_VECTRESET,
 207 };
 208
 209 enum cortex_m_isrmasking_mode {
 210         CORTEX_M_ISRMASK_AUTO,
 211         CORTEX_M_ISRMASK_OFF,
 212         CORTEX_M_ISRMASK_ON,
 213         CORTEX_M_ISRMASK_STEPONLY,
 214 };
 215
 216 struct cortex_m_common {
 217         unsigned int common_magic;
 218
 219         struct armv7m_common armv7m;
 220
 221         /* Context information */
 222         uint32_t dcb_dhcsr;
 223         uint32_t dcb_dhcsr_cumulated_sticky;
 224         /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
 225         bool dcb_dhcsr_sticky_is_recent;
 226         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 227         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 228
 229         /* Flash Patch and Breakpoint (FPB) */
 230         unsigned int fp_num_lit;
 231         unsigned int fp_num_code;
 232         int fp_rev;
 233         bool fpb_enabled;
 234         struct cortex_m_fp_comparator *fp_comparator_list;
 235
 236         /* Data Watchpoint and Trace (DWT) */
 237         unsigned int dwt_num_comp;
 238         unsigned int dwt_comp_available;
 239         uint32_t dwt_devarch;
 240         struct cortex_m_dwt_comparator *dwt_comparator_list;
 241         struct reg_cache *dwt_cache;
 242
 243         enum cortex_m_soft_reset_config soft_reset_config;
 244         bool vectreset_supported;
 245         enum cortex_m_isrmasking_mode isrmasking_mode;
 246
 247         const struct cortex_m_part_info *core_info;
 248
 249         bool slow_register_read;        /* A register has not been ready, poll S_REGRDY */
 250
 251         uint64_t apsel;
 252
 253         /* Whether this target has the erratum that makes C_MASKINTS not apply to
 254          * already pending interrupts */
 255         bool maskints_erratum;
 256 };
 257
 258 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
 259 {
 260         return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
 261 }
 262
 263 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
 264 {
 265         if (!is_cortex_m_or_hla(cortex_m))
 266                 return false;
 267
 268         return !cortex_m->armv7m.is_hla_target;
 269 }
 270
 271 /**
 272  * @returns the pointer to the target specific struct
 273  * without matching a magic number.
 274  * Use in target specific service routines, where the correct
 275  * type of arch_info is certain.
 276  */
 277 static inline struct cortex_m_common *
 278 target_to_cm(struct target *target)
 279 {
 280         return container_of(target->arch_info,
 281                         struct cortex_m_common, armv7m.arm);
 282 }
 283
 284 /**
 285  * @returns the pointer to the target specific struct
 286  * or NULL if the magic number does not match.
 287  * Use in a flash driver or any place where mismatch of the arch_info
 288  * type can happen.
 289  */
 290 static inline struct cortex_m_common *
 291 target_to_cortex_m_safe(struct target *target)
 292 {
 293         /* Check the parent types first to prevent peeking memory too far
 294          * from arch_info pointer */
 295         if (!target_to_armv7m_safe(target))
 296                 return NULL;
 297
 298         struct cortex_m_common *cortex_m = target_to_cm(target);
 299         if (!is_cortex_m_or_hla(cortex_m))
 300                 return NULL;
 301
 302         return cortex_m;
 303 }
 304
 305 /**
 306  * @returns cached value of the cpuid, masked for implementation and part.
 307  * or CORTEX_M_PARTNO_INVALID if the magic number does not match
 308  * or core_info is not initialised.
 309  */
 310 static inline enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
 311 {
 312         struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
 313         if (!cortex_m)
 314                 return CORTEX_M_PARTNO_INVALID;
 315
 316         if (!cortex_m->core_info)
 317                 return CORTEX_M_PARTNO_INVALID;
 318
 319         return cortex_m->core_info->impl_part;
 320 }
 321
 322 int cortex_m_examine(struct target *target);
 323 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
 324 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
 325 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 326 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
 327 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 328 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 329 void cortex_m_enable_breakpoints(struct target *target);
 330 void cortex_m_enable_watchpoints(struct target *target);
 331 void cortex_m_deinit_target(struct target *target);
 332 int cortex_m_profiling(struct target *target, uint32_t *samples,
 333         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 334
 335 #endif /* OPENOCD_TARGET_CORTEX_M_H */