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Transform 'u8' to 'uint8_t' in src/flash
[openocd.git] / src / flash / nand.c
blob7895311513920b0a62eb2d23619ebf2a941c29a1
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "time_support.h"
29 #include "fileio.h"
30
31 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
32 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
33 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
34 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38
39 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
41 static int nand_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
42 //static int nand_read_plain(struct nand_device_s *device, u32 address, uint8_t *data, u32 data_size);
43
44 static int nand_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
45
46 /* NAND flash controller
47 */
48 extern nand_flash_controller_t davinci_nand_controller;
49 extern nand_flash_controller_t lpc3180_nand_controller;
50 extern nand_flash_controller_t orion_nand_controller;
51 extern nand_flash_controller_t s3c2410_nand_controller;
52 extern nand_flash_controller_t s3c2412_nand_controller;
53 extern nand_flash_controller_t s3c2440_nand_controller;
54 extern nand_flash_controller_t s3c2443_nand_controller;
55
56 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
57
58 static nand_flash_controller_t *nand_flash_controllers[] =
59 {
60 &davinci_nand_controller,
61 &lpc3180_nand_controller,
62 &orion_nand_controller,
63 &s3c2410_nand_controller,
64 &s3c2412_nand_controller,
65 &s3c2440_nand_controller,
66 &s3c2443_nand_controller,
67 /* &boundary_scan_nand_controller, */
68 NULL
69 };
70
71 /* configured NAND devices and NAND Flash command handler */
72 static nand_device_t *nand_devices = NULL;
73 static command_t *nand_cmd;
74
75 /* Chip ID list
76 *
77 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
78 * options
79 *
80 * Pagesize; 0, 256, 512
81 * 0 get this information from the extended chip ID
82 * 256 256 Byte page size
83 * 512 512 Byte page size
84 */
85 static nand_info_t nand_flash_ids[] =
86 {
87 /* start "museum" IDs */
88 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
89 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
90 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
91 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
92 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
93 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
94 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
95 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
97 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
98
99 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
100 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
101 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
102 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
103 /* end "museum" IDs */
104
105 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
106 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
107 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
108 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
109
110 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
111 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
112 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
113 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
114
115 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
116 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
117 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
119
120 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
121 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
122 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
124 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
125 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127
128 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
129
130 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
131 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
132 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
133 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
134
135 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
136 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
137 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
138 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
139
140 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
141 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
142 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
143 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
144
145 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
146 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
147 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
148 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
149
150 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
151 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
152 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
153 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
154
155 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
156 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
157 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
158 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
159
160 {NULL, 0, 0, 0, 0, 0 }
161 };
162
163 /* Manufacturer ID list
164 */
165 static nand_manufacturer_t nand_manuf_ids[] =
166 {
167 {0x0, "unknown"},
168 {NAND_MFR_TOSHIBA, "Toshiba"},
169 {NAND_MFR_SAMSUNG, "Samsung"},
170 {NAND_MFR_FUJITSU, "Fujitsu"},
171 {NAND_MFR_NATIONAL, "National"},
172 {NAND_MFR_RENESAS, "Renesas"},
173 {NAND_MFR_STMICRO, "ST Micro"},
174 {NAND_MFR_HYNIX, "Hynix"},
175 {NAND_MFR_MICRON, "Micron"},
176 {0x0, NULL},
177 };
178
179 /*
180 * Define default oob placement schemes for large and small page devices
181 */
182
183 #if 0
184 static nand_ecclayout_t nand_oob_8 = {
185 .eccbytes = 3,
186 .eccpos = {0, 1, 2},
187 .oobfree = {
188 {.offset = 3,
189 .length = 2},
190 {.offset = 6,
191 .length = 2}}
192 };
193 #endif
194
195 static nand_ecclayout_t nand_oob_16 = {
196 .eccbytes = 6,
197 .eccpos = {0, 1, 2, 3, 6, 7},
198 .oobfree = {
199 {.offset = 8,
200 . length = 8}}
201 };
202
203 static nand_ecclayout_t nand_oob_64 = {
204 .eccbytes = 24,
205 .eccpos = {
206 40, 41, 42, 43, 44, 45, 46, 47,
207 48, 49, 50, 51, 52, 53, 54, 55,
208 56, 57, 58, 59, 60, 61, 62, 63},
209 .oobfree = {
210 {.offset = 2,
211 .length = 38}}
212 };
213
214 /* nand device <nand_controller> [controller options]
215 */
216 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
217 {
218 int i;
219 int retval;
220
221 if (argc < 1)
222 {
223 LOG_WARNING("incomplete flash device nand configuration");
224 return ERROR_FLASH_BANK_INVALID;
225 }
226
227 for (i = 0; nand_flash_controllers[i]; i++)
228 {
229 nand_device_t *p, *c;
230
231 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
232 {
233 /* register flash specific commands */
234 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
235 {
236 LOG_ERROR("couldn't register '%s' commands", args[0]);
237 return retval;
238 }
239
240 c = malloc(sizeof(nand_device_t));
241
242 c->controller = nand_flash_controllers[i];
243 c->controller_priv = NULL;
244 c->manufacturer = NULL;
245 c->device = NULL;
246 c->bus_width = 0;
247 c->address_cycles = 0;
248 c->page_size = 0;
249 c->use_raw = 0;
250 c->next = NULL;
251
252 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
253 {
254 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
255 free(c);
256 return ERROR_OK;
257 }
258
259 /* put NAND device in linked list */
260 if (nand_devices)
261 {
262 /* find last flash device */
263 for (p = nand_devices; p && p->next; p = p->next);
264 if (p)
265 p->next = c;
266 }
267 else
268 {
269 nand_devices = c;
270 }
271
272 return ERROR_OK;
273 }
274 }
275
276 /* no valid NAND controller was found (i.e. the configuration option,
277 * didn't match one of the compiled-in controllers)
278 */
279 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
280 LOG_ERROR("compiled-in NAND flash controllers:");
281 for (i = 0; nand_flash_controllers[i]; i++)
282 {
283 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
284 }
285
286 return ERROR_OK;
287 }
288
289 int nand_register_commands(struct command_context_s *cmd_ctx)
290 {
291 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
292
293 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
294
295 return ERROR_OK;
296 }
297
298 int nand_init(struct command_context_s *cmd_ctx)
299 {
300 if (nand_devices)
301 {
302 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
303 "list configured NAND flash devices");
304 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
305 "print info about NAND flash device <num>");
306 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
307 "identify NAND flash device <num>");
308 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
309 "check NAND flash device <num> for bad blocks [<offset> <length>]");
310 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
311 "erase blocks on NAND flash device <num> <offset> <length>");
312 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
313 "dump from NAND flash device <num> <filename> "
314 "<offset> <length> [oob_raw|oob_only]");
315 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
316 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc|oob_softecc_kw]");
317 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
318 "raw access to NAND flash device <num> ['enable'|'disable']");
319 }
320
321 return ERROR_OK;
322 }
323
324 nand_device_t *get_nand_device_by_num(int num)
325 {
326 nand_device_t *p;
327 int i = 0;
328
329 for (p = nand_devices; p; p = p->next)
330 {
331 if (i++ == num)
332 {
333 return p;
334 }
335 }
336
337 return NULL;
338 }
339
340 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
341 {
342 u32 page = 0x0;
343 int i;
344 uint8_t oob[6];
345
346 if ((first < 0) || (first >= device->num_blocks))
347 first = 0;
348
349 if ((last >= device->num_blocks) || (last == -1))
350 last = device->num_blocks - 1;
351
352 for (i = first; i < last; i++)
353 {
354 nand_read_page(device, page, NULL, 0, oob, 6);
355
356 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
357 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
358 ((device->page_size == 2048) && (oob[0] != 0xff))))
359 {
360 LOG_WARNING("bad block: %i", i);
361 device->blocks[i].is_bad = 1;
362 }
363 else
364 {
365 device->blocks[i].is_bad = 0;
366 }
367
368 page += (device->erase_size / device->page_size);
369 }
370
371 return ERROR_OK;
372 }
373
374 int nand_read_status(struct nand_device_s *device, uint8_t *status)
375 {
376 if (!device->device)
377 return ERROR_NAND_DEVICE_NOT_PROBED;
378
379 /* Send read status command */
380 device->controller->command(device, NAND_CMD_STATUS);
381
382 alive_sleep(1);
383
384 /* read status */
385 if (device->device->options & NAND_BUSWIDTH_16)
386 {
387 u16 data;
388 device->controller->read_data(device, &data);
389 *status = data & 0xff;
390 }
391 else
392 {
393 device->controller->read_data(device, status);
394 }
395
396 return ERROR_OK;
397 }
398
399 static int nand_poll_ready(struct nand_device_s *device, int timeout)
400 {
401 uint8_t status;
402
403 device->controller->command(device, NAND_CMD_STATUS);
404 do {
405 if (device->device->options & NAND_BUSWIDTH_16) {
406 u16 data;
407 device->controller->read_data(device, &data);
408 status = data & 0xff;
409 } else {
410 device->controller->read_data(device, &status);
411 }
412 if (status & NAND_STATUS_READY)
413 break;
414 alive_sleep(1);
415 } while (timeout--);
416
417 return (status & NAND_STATUS_READY) != 0;
418 }
419
420 int nand_probe(struct nand_device_s *device)
421 {
422 uint8_t manufacturer_id, device_id;
423 uint8_t id_buff[6];
424 int retval;
425 int i;
426
427 /* clear device data */
428 device->device = NULL;
429 device->manufacturer = NULL;
430
431 /* clear device parameters */
432 device->bus_width = 0;
433 device->address_cycles = 0;
434 device->page_size = 0;
435 device->erase_size = 0;
436
437 /* initialize controller (device parameters are zero, use controller default) */
438 if ((retval = device->controller->init(device) != ERROR_OK))
439 {
440 switch (retval)
441 {
442 case ERROR_NAND_OPERATION_FAILED:
443 LOG_DEBUG("controller initialization failed");
444 return ERROR_NAND_OPERATION_FAILED;
445 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
446 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
447 return ERROR_NAND_OPERATION_FAILED;
448 default:
449 LOG_ERROR("BUG: unknown controller initialization failure");
450 return ERROR_NAND_OPERATION_FAILED;
451 }
452 }
453
454 device->controller->command(device, NAND_CMD_RESET);
455 device->controller->reset(device);
456
457 device->controller->command(device, NAND_CMD_READID);
458 device->controller->address(device, 0x0);
459
460 if (device->bus_width == 8)
461 {
462 device->controller->read_data(device, &manufacturer_id);
463 device->controller->read_data(device, &device_id);
464 }
465 else
466 {
467 u16 data_buf;
468 device->controller->read_data(device, &data_buf);
469 manufacturer_id = data_buf & 0xff;
470 device->controller->read_data(device, &data_buf);
471 device_id = data_buf & 0xff;
472 }
473
474 for (i = 0; nand_flash_ids[i].name; i++)
475 {
476 if (nand_flash_ids[i].id == device_id)
477 {
478 device->device = &nand_flash_ids[i];
479 break;
480 }
481 }
482
483 for (i = 0; nand_manuf_ids[i].name; i++)
484 {
485 if (nand_manuf_ids[i].id == manufacturer_id)
486 {
487 device->manufacturer = &nand_manuf_ids[i];
488 break;
489 }
490 }
491
492 if (!device->manufacturer)
493 {
494 device->manufacturer = &nand_manuf_ids[0];
495 device->manufacturer->id = manufacturer_id;
496 }
497
498 if (!device->device)
499 {
500 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
501 manufacturer_id, device_id);
502 return ERROR_NAND_OPERATION_FAILED;
503 }
504
505 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
506
507 /* initialize device parameters */
508
509 /* bus width */
510 if (device->device->options & NAND_BUSWIDTH_16)
511 device->bus_width = 16;
512 else
513 device->bus_width = 8;
514
515 /* Do we need extended device probe information? */
516 if (device->device->page_size == 0 ||
517 device->device->erase_size == 0)
518 {
519 if (device->bus_width == 8)
520 {
521 device->controller->read_data(device, id_buff+3);
522 device->controller->read_data(device, id_buff+4);
523 device->controller->read_data(device, id_buff+5);
524 }
525 else
526 {
527 u16 data_buf;
528
529 device->controller->read_data(device, &data_buf);
530 id_buff[3] = data_buf;
531
532 device->controller->read_data(device, &data_buf);
533 id_buff[4] = data_buf;
534
535 device->controller->read_data(device, &data_buf);
536 id_buff[5] = data_buf >> 8;
537 }
538 }
539
540 /* page size */
541 if (device->device->page_size == 0)
542 {
543 device->page_size = 1 << (10 + (id_buff[4] & 3));
544 }
545 else if (device->device->page_size == 256)
546 {
547 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
548 return ERROR_NAND_OPERATION_FAILED;
549 }
550 else
551 {
552 device->page_size = device->device->page_size;
553 }
554
555 /* number of address cycles */
556 if (device->page_size <= 512)
557 {
558 /* small page devices */
559 if (device->device->chip_size <= 32)
560 device->address_cycles = 3;
561 else if (device->device->chip_size <= 8*1024)
562 device->address_cycles = 4;
563 else
564 {
565 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
566 device->address_cycles = 5;
567 }
568 }
569 else
570 {
571 /* large page devices */
572 if (device->device->chip_size <= 128)
573 device->address_cycles = 4;
574 else if (device->device->chip_size <= 32*1024)
575 device->address_cycles = 5;
576 else
577 {
578 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
579 device->address_cycles = 6;
580 }
581 }
582
583 /* erase size */
584 if (device->device->erase_size == 0)
585 {
586 switch ((id_buff[4] >> 4) & 3) {
587 case 0:
588 device->erase_size = 64 << 10;
589 break;
590 case 1:
591 device->erase_size = 128 << 10;
592 break;
593 case 2:
594 device->erase_size = 256 << 10;
595 break;
596 case 3:
597 device->erase_size =512 << 10;
598 break;
599 }
600 }
601 else
602 {
603 device->erase_size = device->device->erase_size;
604 }
605
606 /* initialize controller, but leave parameters at the controllers default */
607 if ((retval = device->controller->init(device) != ERROR_OK))
608 {
609 switch (retval)
610 {
611 case ERROR_NAND_OPERATION_FAILED:
612 LOG_DEBUG("controller initialization failed");
613 return ERROR_NAND_OPERATION_FAILED;
614 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
615 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
616 device->bus_width, device->address_cycles, device->page_size);
617 return ERROR_NAND_OPERATION_FAILED;
618 default:
619 LOG_ERROR("BUG: unknown controller initialization failure");
620 return ERROR_NAND_OPERATION_FAILED;
621 }
622 }
623
624 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
625 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
626
627 for (i = 0; i < device->num_blocks; i++)
628 {
629 device->blocks[i].size = device->erase_size;
630 device->blocks[i].offset = i * device->erase_size;
631 device->blocks[i].is_erased = -1;
632 device->blocks[i].is_bad = -1;
633 }
634
635 return ERROR_OK;
636 }
637
638 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
639 {
640 int i;
641 u32 page;
642 uint8_t status;
643 int retval;
644
645 if (!device->device)
646 return ERROR_NAND_DEVICE_NOT_PROBED;
647
648 if ((first_block < 0) || (last_block > device->num_blocks))
649 return ERROR_INVALID_ARGUMENTS;
650
651 /* make sure we know if a block is bad before erasing it */
652 for (i = first_block; i <= last_block; i++)
653 {
654 if (device->blocks[i].is_bad == -1)
655 {
656 nand_build_bbt(device, i, last_block);
657 break;
658 }
659 }
660
661 for (i = first_block; i <= last_block; i++)
662 {
663 /* Send erase setup command */
664 device->controller->command(device, NAND_CMD_ERASE1);
665
666 page = i * (device->erase_size / device->page_size);
667
668 /* Send page address */
669 if (device->page_size <= 512)
670 {
671 /* row */
672 device->controller->address(device, page & 0xff);
673 device->controller->address(device, (page >> 8) & 0xff);
674
675 /* 3rd cycle only on devices with more than 32 MiB */
676 if (device->address_cycles >= 4)
677 device->controller->address(device, (page >> 16) & 0xff);
678
679 /* 4th cycle only on devices with more than 8 GiB */
680 if (device->address_cycles >= 5)
681 device->controller->address(device, (page >> 24) & 0xff);
682 }
683 else
684 {
685 /* row */
686 device->controller->address(device, page & 0xff);
687 device->controller->address(device, (page >> 8) & 0xff);
688
689 /* 3rd cycle only on devices with more than 128 MiB */
690 if (device->address_cycles >= 5)
691 device->controller->address(device, (page >> 16) & 0xff);
692 }
693
694 /* Send erase confirm command */
695 device->controller->command(device, NAND_CMD_ERASE2);
696
697 retval = device->controller->nand_ready ?
698 device->controller->nand_ready(device, 1000) :
699 nand_poll_ready(device, 1000);
700 if (!retval) {
701 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
702 return ERROR_NAND_OPERATION_TIMEOUT;
703 }
704
705 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
706 {
707 LOG_ERROR("couldn't read status");
708 return ERROR_NAND_OPERATION_FAILED;
709 }
710
711 if (status & 0x1)
712 {
713 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
714 return ERROR_NAND_OPERATION_FAILED;
715 }
716
717 device->blocks[i].is_erased = 1;
718 }
719
720 return ERROR_OK;
721 }
722
723 #if 0
724 static int nand_read_plain(struct nand_device_s *device, u32 address, uint8_t *data, u32 data_size)
725 {
726 uint8_t *page;
727
728 if (!device->device)
729 return ERROR_NAND_DEVICE_NOT_PROBED;
730
731 if (address % device->page_size)
732 {
733 LOG_ERROR("reads need to be page aligned");
734 return ERROR_NAND_OPERATION_FAILED;
735 }
736
737 page = malloc(device->page_size);
738
739 while (data_size > 0 )
740 {
741 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
742 u32 page_address;
743
744
745 page_address = address / device->page_size;
746
747 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
748
749 memcpy(data, page, thisrun_size);
750
751 address += thisrun_size;
752 data += thisrun_size;
753 data_size -= thisrun_size;
754 }
755
756 free(page);
757
758 return ERROR_OK;
759 }
760
761 static int nand_write_plain(struct nand_device_s *device, u32 address, uint8_t *data, u32 data_size)
762 {
763 uint8_t *page;
764
765 if (!device->device)
766 return ERROR_NAND_DEVICE_NOT_PROBED;
767
768 if (address % device->page_size)
769 {
770 LOG_ERROR("writes need to be page aligned");
771 return ERROR_NAND_OPERATION_FAILED;
772 }
773
774 page = malloc(device->page_size);
775
776 while (data_size > 0 )
777 {
778 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
779 u32 page_address;
780
781 memset(page, 0xff, device->page_size);
782 memcpy(page, data, thisrun_size);
783
784 page_address = address / device->page_size;
785
786 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
787
788 address += thisrun_size;
789 data += thisrun_size;
790 data_size -= thisrun_size;
791 }
792
793 free(page);
794
795 return ERROR_OK;
796 }
797 #endif
798
799 int nand_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
800 {
801 u32 block;
802
803 if (!device->device)
804 return ERROR_NAND_DEVICE_NOT_PROBED;
805
806 block = page / (device->erase_size / device->page_size);
807 if (device->blocks[block].is_erased == 1)
808 device->blocks[block].is_erased = 0;
809
810 if (device->use_raw || device->controller->write_page == NULL)
811 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
812 else
813 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
814 }
815
816 static int nand_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
817 {
818 if (!device->device)
819 return ERROR_NAND_DEVICE_NOT_PROBED;
820
821 if (device->use_raw || device->controller->read_page == NULL)
822 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
823 else
824 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
825 }
826
827 int nand_read_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
828 {
829 u32 i;
830
831 if (!device->device)
832 return ERROR_NAND_DEVICE_NOT_PROBED;
833
834 if (device->page_size <= 512)
835 {
836 /* small page device */
837 if (data)
838 device->controller->command(device, NAND_CMD_READ0);
839 else
840 device->controller->command(device, NAND_CMD_READOOB);
841
842 /* column (always 0, we start at the beginning of a page/OOB area) */
843 device->controller->address(device, 0x0);
844
845 /* row */
846 device->controller->address(device, page & 0xff);
847 device->controller->address(device, (page >> 8) & 0xff);
848
849 /* 4th cycle only on devices with more than 32 MiB */
850 if (device->address_cycles >= 4)
851 device->controller->address(device, (page >> 16) & 0xff);
852
853 /* 5th cycle only on devices with more than 8 GiB */
854 if (device->address_cycles >= 5)
855 device->controller->address(device, (page >> 24) & 0xff);
856 }
857 else
858 {
859 /* large page device */
860 device->controller->command(device, NAND_CMD_READ0);
861
862 /* column (0 when we start at the beginning of a page,
863 * or 2048 for the beginning of OOB area)
864 */
865 device->controller->address(device, 0x0);
866 if (data)
867 device->controller->address(device, 0x0);
868 else
869 device->controller->address(device, 0x8);
870
871 /* row */
872 device->controller->address(device, page & 0xff);
873 device->controller->address(device, (page >> 8) & 0xff);
874
875 /* 5th cycle only on devices with more than 128 MiB */
876 if (device->address_cycles >= 5)
877 device->controller->address(device, (page >> 16) & 0xff);
878
879 /* large page devices need a start command */
880 device->controller->command(device, NAND_CMD_READSTART);
881 }
882
883 if (device->controller->nand_ready) {
884 if (!device->controller->nand_ready(device, 100))
885 return ERROR_NAND_OPERATION_TIMEOUT;
886 } else {
887 alive_sleep(1);
888 }
889
890 if (data)
891 {
892 if (device->controller->read_block_data != NULL)
893 (device->controller->read_block_data)(device, data, data_size);
894 else
895 {
896 for (i = 0; i < data_size;)
897 {
898 if (device->device->options & NAND_BUSWIDTH_16)
899 {
900 device->controller->read_data(device, data);
901 data += 2;
902 i += 2;
903 }
904 else
905 {
906 device->controller->read_data(device, data);
907 data += 1;
908 i += 1;
909 }
910 }
911 }
912 }
913
914 if (oob)
915 {
916 if (device->controller->read_block_data != NULL)
917 (device->controller->read_block_data)(device, oob, oob_size);
918 else
919 {
920 for (i = 0; i < oob_size;)
921 {
922 if (device->device->options & NAND_BUSWIDTH_16)
923 {
924 device->controller->read_data(device, oob);
925 oob += 2;
926 i += 2;
927 }
928 else
929 {
930 device->controller->read_data(device, oob);
931 oob += 1;
932 i += 1;
933 }
934 }
935 }
936 }
937
938 return ERROR_OK;
939 }
940
941 int nand_write_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
942 {
943 u32 i;
944 int retval;
945 uint8_t status;
946
947 if (!device->device)
948 return ERROR_NAND_DEVICE_NOT_PROBED;
949
950 device->controller->command(device, NAND_CMD_SEQIN);
951
952 if (device->page_size <= 512)
953 {
954 /* column (always 0, we start at the beginning of a page/OOB area) */
955 device->controller->address(device, 0x0);
956
957 /* row */
958 device->controller->address(device, page & 0xff);
959 device->controller->address(device, (page >> 8) & 0xff);
960
961 /* 4th cycle only on devices with more than 32 MiB */
962 if (device->address_cycles >= 4)
963 device->controller->address(device, (page >> 16) & 0xff);
964
965 /* 5th cycle only on devices with more than 8 GiB */
966 if (device->address_cycles >= 5)
967 device->controller->address(device, (page >> 24) & 0xff);
968 }
969 else
970 {
971 /* column (0 when we start at the beginning of a page,
972 * or 2048 for the beginning of OOB area)
973 */
974 device->controller->address(device, 0x0);
975 if (data)
976 device->controller->address(device, 0x0);
977 else
978 device->controller->address(device, 0x8);
979
980 /* row */
981 device->controller->address(device, page & 0xff);
982 device->controller->address(device, (page >> 8) & 0xff);
983
984 /* 5th cycle only on devices with more than 128 MiB */
985 if (device->address_cycles >= 5)
986 device->controller->address(device, (page >> 16) & 0xff);
987 }
988
989 if (data)
990 {
991 if (device->controller->write_block_data != NULL)
992 (device->controller->write_block_data)(device, data, data_size);
993 else
994 {
995 for (i = 0; i < data_size;)
996 {
997 if (device->device->options & NAND_BUSWIDTH_16)
998 {
999 u16 data_buf = le_to_h_u16(data);
1000 device->controller->write_data(device, data_buf);
1001 data += 2;
1002 i += 2;
1003 }
1004 else
1005 {
1006 device->controller->write_data(device, *data);
1007 data += 1;
1008 i += 1;
1009 }
1010 }
1011 }
1012 }
1013
1014 if (oob)
1015 {
1016 if (device->controller->write_block_data != NULL)
1017 (device->controller->write_block_data)(device, oob, oob_size);
1018 else
1019 {
1020 for (i = 0; i < oob_size;)
1021 {
1022 if (device->device->options & NAND_BUSWIDTH_16)
1023 {
1024 u16 oob_buf = le_to_h_u16(data);
1025 device->controller->write_data(device, oob_buf);
1026 oob += 2;
1027 i += 2;
1028 }
1029 else
1030 {
1031 device->controller->write_data(device, *oob);
1032 oob += 1;
1033 i += 1;
1034 }
1035 }
1036 }
1037 }
1038
1039 device->controller->command(device, NAND_CMD_PAGEPROG);
1040
1041 retval = device->controller->nand_ready ?
1042 device->controller->nand_ready(device, 100) :
1043 nand_poll_ready(device, 100);
1044 if (!retval)
1045 return ERROR_NAND_OPERATION_TIMEOUT;
1046
1047 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1048 {
1049 LOG_ERROR("couldn't read status");
1050 return ERROR_NAND_OPERATION_FAILED;
1051 }
1052
1053 if (status & NAND_STATUS_FAIL)
1054 {
1055 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1056 return ERROR_NAND_OPERATION_FAILED;
1057 }
1058
1059 return ERROR_OK;
1060 }
1061
1062 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1063 {
1064 nand_device_t *p;
1065 int i;
1066
1067 if (!nand_devices)
1068 {
1069 command_print(cmd_ctx, "no NAND flash devices configured");
1070 return ERROR_OK;
1071 }
1072
1073 for (p = nand_devices, i = 0; p; p = p->next, i++)
1074 {
1075 if (p->device)
1076 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1077 i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1078 else
1079 command_print(cmd_ctx, "#%i: not probed", i);
1080 }
1081
1082 return ERROR_OK;
1083 }
1084
1085 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1086 {
1087 nand_device_t *p;
1088 int i = 0;
1089 int j = 0;
1090 int first = -1;
1091 int last = -1;
1092
1093 switch (argc) {
1094 default:
1095 return ERROR_COMMAND_SYNTAX_ERROR;
1096 case 1:
1097 first = 0;
1098 last = INT32_MAX;
1099 break;
1100 case 2:
1101 first = last = strtoul(args[1], NULL, 0);
1102 break;
1103 case 3:
1104 first = strtoul(args[1], NULL, 0);
1105 last = strtoul(args[2], NULL, 0);
1106 break;
1107 }
1108
1109 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1110 if (p)
1111 {
1112 if (p->device)
1113 {
1114 if (first >= p->num_blocks)
1115 first = p->num_blocks - 1;
1116
1117 if (last >= p->num_blocks)
1118 last = p->num_blocks - 1;
1119
1120 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1121 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1122
1123 for (j = first; j <= last; j++)
1124 {
1125 char *erase_state, *bad_state;
1126
1127 if (p->blocks[j].is_erased == 0)
1128 erase_state = "not erased";
1129 else if (p->blocks[j].is_erased == 1)
1130 erase_state = "erased";
1131 else
1132 erase_state = "erase state unknown";
1133
1134 if (p->blocks[j].is_bad == 0)
1135 bad_state = "";
1136 else if (p->blocks[j].is_bad == 1)
1137 bad_state = " (marked bad)";
1138 else
1139 bad_state = " (block condition unknown)";
1140
1141 command_print(cmd_ctx, "\t#%i: 0x%8.8x (%dkB) %s%s",
1142 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1143 erase_state, bad_state);
1144 }
1145 }
1146 else
1147 {
1148 command_print(cmd_ctx, "#%s: not probed", args[0]);
1149 }
1150 }
1151
1152 return ERROR_OK;
1153 }
1154
1155 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1156 {
1157 nand_device_t *p;
1158 int retval;
1159
1160 if (argc != 1)
1161 {
1162 return ERROR_COMMAND_SYNTAX_ERROR;
1163 }
1164
1165 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1166 if (p)
1167 {
1168 if ((retval = nand_probe(p)) == ERROR_OK)
1169 {
1170 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1171 }
1172 else if (retval == ERROR_NAND_OPERATION_FAILED)
1173 {
1174 command_print(cmd_ctx, "probing failed for NAND flash device");
1175 }
1176 else
1177 {
1178 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1179 }
1180 }
1181 else
1182 {
1183 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1184 }
1185
1186 return ERROR_OK;
1187 }
1188
1189 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1190 {
1191 nand_device_t *p;
1192 int retval;
1193
1194 if (argc != 3)
1195 {
1196 return ERROR_COMMAND_SYNTAX_ERROR;
1197
1198 }
1199
1200 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1201 if (p)
1202 {
1203 char *cp;
1204 unsigned long offset;
1205 unsigned long length;
1206
1207 offset = strtoul(args[1], &cp, 0);
1208 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1209 {
1210 return ERROR_INVALID_ARGUMENTS;
1211 }
1212 offset /= p->erase_size;
1213
1214 length = strtoul(args[2], &cp, 0);
1215 if (*cp || length == ULONG_MAX || length % p->erase_size)
1216 {
1217 return ERROR_INVALID_ARGUMENTS;
1218 }
1219 length -= 1;
1220 length /= p->erase_size;
1221
1222 retval = nand_erase(p, offset, offset + length);
1223 if (retval == ERROR_OK)
1224 {
1225 command_print(cmd_ctx, "successfully erased blocks "
1226 "%lu to %lu on NAND flash device '%s'",
1227 offset, offset + length, p->device->name);
1228 }
1229 else if (retval == ERROR_NAND_OPERATION_FAILED)
1230 {
1231 command_print(cmd_ctx, "erase failed");
1232 }
1233 else
1234 {
1235 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1236 }
1237 }
1238 else
1239 {
1240 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1241 }
1242
1243 return ERROR_OK;
1244 }
1245
1246 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1247 {
1248 nand_device_t *p;
1249 int retval;
1250 int first = -1;
1251 int last = -1;
1252
1253 if ((argc < 1) || (argc > 3) || (argc == 2))
1254 {
1255 return ERROR_COMMAND_SYNTAX_ERROR;
1256
1257 }
1258
1259 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1260 if (!p) {
1261 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds",
1262 args[0]);
1263 return ERROR_INVALID_ARGUMENTS;
1264 }
1265
1266 if (argc == 3)
1267 {
1268 char *cp;
1269 unsigned long offset;
1270 unsigned long length;
1271
1272 offset = strtoul(args[1], &cp, 0);
1273 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1274 {
1275 return ERROR_INVALID_ARGUMENTS;
1276 }
1277 offset /= p->erase_size;
1278
1279 length = strtoul(args[2], &cp, 0);
1280 if (*cp || length == ULONG_MAX || length % p->erase_size)
1281 {
1282 return ERROR_INVALID_ARGUMENTS;
1283 }
1284 length -= 1;
1285 length /= p->erase_size;
1286
1287 first = offset;
1288 last = offset + length;
1289 }
1290
1291 retval = nand_build_bbt(p, first, last);
1292 if (retval == ERROR_OK)
1293 {
1294 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1295 "use \"nand info\" command to list blocks");
1296 }
1297 else if (retval == ERROR_NAND_OPERATION_FAILED)
1298 {
1299 command_print(cmd_ctx, "error when checking for bad blocks on "
1300 "NAND flash device");
1301 }
1302 else
1303 {
1304 command_print(cmd_ctx, "unknown error when checking for bad "
1305 "blocks on NAND flash device");
1306 }
1307
1308 return ERROR_OK;
1309 }
1310
1311 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1312 {
1313 u32 offset;
1314 u32 binary_size;
1315 u32 buf_cnt;
1316 enum oob_formats oob_format = NAND_OOB_NONE;
1317
1318 fileio_t fileio;
1319
1320 duration_t duration;
1321 char *duration_text;
1322
1323 nand_device_t *p;
1324
1325 if (argc < 3)
1326 {
1327 return ERROR_COMMAND_SYNTAX_ERROR;
1328
1329 }
1330
1331 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1332 if (p)
1333 {
1334 uint8_t *page = NULL;
1335 u32 page_size = 0;
1336 uint8_t *oob = NULL;
1337 u32 oob_size = 0;
1338 const int *eccpos = NULL;
1339
1340 offset = strtoul(args[2], NULL, 0);
1341
1342 if (argc > 3)
1343 {
1344 int i;
1345 for (i = 3; i < argc; i++)
1346 {
1347 if (!strcmp(args[i], "oob_raw"))
1348 oob_format |= NAND_OOB_RAW;
1349 else if (!strcmp(args[i], "oob_only"))
1350 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1351 else if (!strcmp(args[i], "oob_softecc"))
1352 oob_format |= NAND_OOB_SW_ECC;
1353 else if (!strcmp(args[i], "oob_softecc_kw"))
1354 oob_format |= NAND_OOB_SW_ECC_KW;
1355 else
1356 {
1357 command_print(cmd_ctx, "unknown option: %s", args[i]);
1358 return ERROR_COMMAND_SYNTAX_ERROR;
1359 }
1360 }
1361 }
1362
1363 duration_start_measure(&duration);
1364
1365 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1366 {
1367 return ERROR_OK;
1368 }
1369
1370 buf_cnt = binary_size = fileio.size;
1371
1372 if (!(oob_format & NAND_OOB_ONLY))
1373 {
1374 page_size = p->page_size;
1375 page = malloc(p->page_size);
1376 }
1377
1378 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1379 {
1380 if (p->page_size == 512) {
1381 oob_size = 16;
1382 eccpos = nand_oob_16.eccpos;
1383 } else if (p->page_size == 2048) {
1384 oob_size = 64;
1385 eccpos = nand_oob_64.eccpos;
1386 }
1387 oob = malloc(oob_size);
1388 }
1389
1390 if (offset % p->page_size)
1391 {
1392 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1393 fileio_close(&fileio);
1394 free(oob);
1395 free(page);
1396 return ERROR_OK;
1397 }
1398
1399 while (buf_cnt > 0)
1400 {
1401 u32 size_read;
1402
1403 if (NULL != page)
1404 {
1405 fileio_read(&fileio, page_size, page, &size_read);
1406 buf_cnt -= size_read;
1407 if (size_read < page_size)
1408 {
1409 memset(page + size_read, 0xff, page_size - size_read);
1410 }
1411 }
1412
1413 if (oob_format & NAND_OOB_SW_ECC)
1414 {
1415 u32 i, j;
1416 uint8_t ecc[3];
1417 memset(oob, 0xff, oob_size);
1418 for (i = 0, j = 0; i < page_size; i += 256) {
1419 nand_calculate_ecc(p, page+i, ecc);
1420 oob[eccpos[j++]] = ecc[0];
1421 oob[eccpos[j++]] = ecc[1];
1422 oob[eccpos[j++]] = ecc[2];
1423 }
1424 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1425 {
1426 /*
1427 * In this case eccpos is not used as
1428 * the ECC data is always stored contigously
1429 * at the end of the OOB area. It consists
1430 * of 10 bytes per 512-byte data block.
1431 */
1432 u32 i;
1433 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1434 memset(oob, 0xff, oob_size);
1435 for (i = 0; i < page_size; i += 512) {
1436 nand_calculate_ecc_kw(p, page+i, ecc);
1437 ecc += 10;
1438 }
1439 }
1440 else if (NULL != oob)
1441 {
1442 fileio_read(&fileio, oob_size, oob, &size_read);
1443 buf_cnt -= size_read;
1444 if (size_read < oob_size)
1445 {
1446 memset(oob + size_read, 0xff, oob_size - size_read);
1447 }
1448 }
1449
1450 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1451 {
1452 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1453 args[1], args[0], offset);
1454
1455 fileio_close(&fileio);
1456 free(oob);
1457 free(page);
1458
1459 return ERROR_OK;
1460 }
1461 offset += page_size;
1462 }
1463
1464 fileio_close(&fileio);
1465 free(oob);
1466 free(page);
1467 oob = NULL;
1468 page = NULL;
1469 duration_stop_measure(&duration, &duration_text);
1470 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1471 args[1], args[0], offset, duration_text);
1472 free(duration_text);
1473 duration_text = NULL;
1474 }
1475 else
1476 {
1477 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1478 }
1479
1480 return ERROR_OK;
1481 }
1482
1483 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1484 {
1485 nand_device_t *p;
1486
1487 if (argc < 4)
1488 {
1489 return ERROR_COMMAND_SYNTAX_ERROR;
1490 }
1491
1492 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1493 if (p)
1494 {
1495 if (p->device)
1496 {
1497 fileio_t fileio;
1498 duration_t duration;
1499 char *duration_text;
1500 int retval;
1501
1502 uint8_t *page = NULL;
1503 u32 page_size = 0;
1504 uint8_t *oob = NULL;
1505 u32 oob_size = 0;
1506 u32 address = strtoul(args[2], NULL, 0);
1507 u32 size = strtoul(args[3], NULL, 0);
1508 u32 bytes_done = 0;
1509 enum oob_formats oob_format = NAND_OOB_NONE;
1510
1511 if (argc > 4)
1512 {
1513 int i;
1514 for (i = 4; i < argc; i++)
1515 {
1516 if (!strcmp(args[i], "oob_raw"))
1517 oob_format |= NAND_OOB_RAW;
1518 else if (!strcmp(args[i], "oob_only"))
1519 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1520 else
1521 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1522 }
1523 }
1524
1525 if ((address % p->page_size) || (size % p->page_size))
1526 {
1527 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1528 return ERROR_OK;
1529 }
1530
1531 if (!(oob_format & NAND_OOB_ONLY))
1532 {
1533 page_size = p->page_size;
1534 page = malloc(p->page_size);
1535 }
1536
1537 if (oob_format & NAND_OOB_RAW)
1538 {
1539 if (p->page_size == 512)
1540 oob_size = 16;
1541 else if (p->page_size == 2048)
1542 oob_size = 64;
1543 oob = malloc(oob_size);
1544 }
1545
1546 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1547 {
1548 return ERROR_OK;
1549 }
1550
1551 duration_start_measure(&duration);
1552
1553 while (size > 0)
1554 {
1555 u32 size_written;
1556 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1557 {
1558 command_print(cmd_ctx, "reading NAND flash page failed");
1559 free(page);
1560 free(oob);
1561 fileio_close(&fileio);
1562 return ERROR_OK;
1563 }
1564
1565 if (NULL != page)
1566 {
1567 fileio_write(&fileio, page_size, page, &size_written);
1568 bytes_done += page_size;
1569 }
1570
1571 if (NULL != oob)
1572 {
1573 fileio_write(&fileio, oob_size, oob, &size_written);
1574 bytes_done += oob_size;
1575 }
1576
1577 size -= p->page_size;
1578 address += p->page_size;
1579 }
1580
1581 free(page);
1582 page = NULL;
1583 free(oob);
1584 oob = NULL;
1585 fileio_close(&fileio);
1586
1587 duration_stop_measure(&duration, &duration_text);
1588 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1589 free(duration_text);
1590 duration_text = NULL;
1591 }
1592 else
1593 {
1594 command_print(cmd_ctx, "#%s: not probed", args[0]);
1595 }
1596 }
1597 else
1598 {
1599 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1600 }
1601
1602 return ERROR_OK;
1603 }
1604
1605 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1606 {
1607 nand_device_t *p;
1608
1609 if ((argc < 1) || (argc > 2))
1610 {
1611 return ERROR_COMMAND_SYNTAX_ERROR;
1612 }
1613
1614 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1615 if (p)
1616 {
1617 if (p->device)
1618 {
1619 if (argc == 2)
1620 {
1621 if (strcmp("enable", args[1]) == 0)
1622 {
1623 p->use_raw = 1;
1624 }
1625 else if (strcmp("disable", args[1]) == 0)
1626 {
1627 p->use_raw = 0;
1628 }
1629 else
1630 {
1631 return ERROR_COMMAND_SYNTAX_ERROR;
1632 }
1633 }
1634
1635 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1636 }
1637 else
1638 {
1639 command_print(cmd_ctx, "#%s: not probed", args[0]);
1640 }
1641 }
1642 else
1643 {
1644 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1645 }
1646
1647 return ERROR_OK;
1648 }
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