1 # SPDX-License-Identifier: GPL-2.0-or-later
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
13 # CoreSight Debug Access Port (DAP)
14 if { [info exists DAP_TAPID] } {
15 set _DAP_TAPID $DAP_TAPID
17 # TAPID is from FreeScale!
18 set _DAP_TAPID 0x1890101d
21 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
22 -expected-id $_DAP_TAPID
24 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
26 # AXI: Main SOC bus on AP #0
27 target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
29 # 4x Cortex-A53 on AP #6
30 set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
31 set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
33 cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \
34 -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]
35 cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \
36 -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]
37 cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \
38 -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]
39 cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \
40 -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]
41 target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \
42 -cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]
43 target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \
44 -cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine
45 target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \
46 -cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine
47 target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \
48 -cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine
50 # 2x Cortex-A72 on AP #6
51 set _A72_DBGBASE {0x80210000 0x80310000}
52 set _A72_CTIBASE {0x80220000 0x80220000}
54 cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \
55 -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]
56 cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \
57 -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]
58 target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \
59 -cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine
60 target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \
61 -cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine
73 # always running imx SC firmware
74 target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1
76 # AHB from SCU perspective
77 target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4
79 # Cortex-M4 M4_0 core on AP #2 (default off)
80 target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \
83 # Cortex-M4 M4_1 core on AP #3 (default off)
84 target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \
88 target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6
90 # Default target is boot core a53.0
91 targets $_CHIPNAME.a53.0