tcl/cpu/arc/hs.tcl

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #  Copyright (C) 2015, 2020 Synopsys, Inc.
   4 #  Anton Kolesov <anton.kolesov@synopsys.com>
   5 #  Didin Evgeniy <didin@synopsys.com>
   6
   7 source [find cpu/arc/v2.tcl]
   8
   9 proc arc_hs_examine_target { target } {
  10         # Will set current target for us.
  11         arc_v2_examine_target $target
  12 }
  13
  14 proc arc_hs_init_regs { } {
  15         arc_v2_init_regs
  16
  17         [target current] configure \
  18                 -event examine-end "arc_hs_examine_target [target current]"
  19 }
  20
  21 # Scripts in "target" folder should call this function instead of direct
  22 # invocation of arc_common_reset.
  23 proc arc_hs_reset { {target ""} } {
  24         arc_v2_reset $target
  25
  26         # Invalidate L2 cache if there is one.
  27         set l2_config [$target arc jtag get-aux-reg 0x901]
  28         # Will return 0, if cache is not present and register doesn't exist.
  29         set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  30         if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
  31                 puts "L2 cache is present and not disabled"
  32
  33                 # Wait until BUSY bit is 0.
  34                 puts "Invalidating L2 cache..."
  35                 $target arc jtag set-aux-reg 0x905 1
  36                 # Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
  37                 # https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
  38                 set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  39                 set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  40                 while { ($l2_ctrl & 0x100) != 0 } {
  41                         set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  42                 }
  43
  44                 # Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
  45                 # operation already flushed everything.
  46                 if { ($l2_ctrl & 0x40) == 0 } {
  47                         puts "Flushing L2 cache..."
  48                         $target arc jtag set-aux-reg 0x904 1
  49                         set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  50                         set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  51                         while { [expr {$l2_ctrl & 0x100}] != 0 } {
  52                                 set l2_ctrl [$target arc jtag get-aux-reg 0x903]
  53                         }
  54                 }
  55
  56                 puts "L2 cache has been flushed and invalidated."
  57         }
  58 }