1 # script for stm32f7x family
4 # stm32f7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f7x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 128kB
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x20000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0385
31 # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
32 set _CPUTAPID 0x5ba00477
34 set _CPUTAPID 0x5ba02477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
41 jtag newtap $_CHIPNAME bs -irlen 5
44 set _TARGETNAME $_CHIPNAME.cpu
45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
49 set _FLASHNAME $_CHIPNAME.flash
50 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
52 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
55 adapter_nsrst_delay 100
60 # use hardware reset, connect under reset
61 reset_config srst_only srst_nogate
64 # if srst is not fitted use SYSRESETREQ to
65 # perform a soft reset
66 cortex_m reset_config sysresetreq
69 $_TARGETNAME configure -event examine-end {
70 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
71 mmw 0xE0042004 0x00000007 0
73 # Stop watchdog counters during halt
74 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
75 mmw 0xE0042008 0x00001800 0
78 $_TARGETNAME configure -event trace-config {
79 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
80 # change this value accordingly to configure trace pins
82 mmw 0xE0042004 0x00000020 0