1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
53 /* END ATMEL COPYRIGHT */
69 #include "time_support.h"
71 #define REG_NAME_WIDTH (12)
74 #define FLASH_BANK0_BASE 0x00080000
75 #define FLASH_BANK1_BASE 0x00100000
77 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
78 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
79 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
80 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
81 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
82 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
83 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
84 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
85 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
86 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
87 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
88 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
89 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
90 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
91 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
92 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
93 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
94 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
96 #define offset_EFC_FMR 0
97 #define offset_EFC_FCR 4
98 #define offset_EFC_FSR 8
99 #define offset_EFC_FRR 12
103 _tomhz( uint32_t freq_hz
)
107 f
= ((float)(freq_hz
)) / 1000000.0;
111 // How the chip is configured.
113 uint32_t unique_id
[4];
117 uint32_t mainosc_freq
;
127 #define SAM3_CHIPID_CIDR (0x400E0740)
128 uint32_t CHIPID_CIDR
;
129 #define SAM3_CHIPID_EXID (0x400E0744)
130 uint32_t CHIPID_EXID
;
132 #define SAM3_SUPC_CR (0x400E1210)
135 #define SAM3_PMC_BASE (0x400E0400)
136 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
138 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
140 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
142 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
144 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
146 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
148 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
150 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
152 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
154 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
156 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
158 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
160 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
162 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
167 struct sam3_bank_private
{
169 // DANGER: THERE ARE DRAGONS HERE..
170 // NOTE: If you add more 'ghost' pointers
171 // be aware that you must *manually* update
172 // these pointers in the function sam3_GetDetails()
173 // See the comment "Here there be dragons"
175 // so we can find the chip we belong to
176 struct sam3_chip
*pChip
;
177 // so we can find the orginal bank pointer
179 unsigned bank_number
;
180 uint32_t controller_address
;
181 uint32_t base_address
;
185 unsigned sector_size
;
189 struct sam3_chip_details
{
190 // THERE ARE DRAGONS HERE..
191 // note: If you add pointers here
192 // becareful about them as they
193 // may need to be updated inside
194 // the function: "sam3_GetDetails()
195 // which copy/overwrites the
196 // 'runtime' copy of this structure
197 uint32_t chipid_cidr
;
201 #define SAM3_N_NVM_BITS 3
202 unsigned gpnvm
[SAM3_N_NVM_BITS
];
203 unsigned total_flash_size
;
204 unsigned total_sram_size
;
206 #define SAM3_MAX_FLASH_BANKS 2
207 // these are "initialized" from the global const data
208 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
213 struct sam3_chip
*next
;
216 // this is "initialized" from the global const structure
217 struct sam3_chip_details details
;
225 struct sam3_reg_list
{
226 uint32_t address
; size_t struct_offset
; const char *name
;
227 void (*explain_func
)( struct sam3_chip
*pInfo
);
231 static struct sam3_chip
*all_sam3_chips
;
233 static struct sam3_chip
*
234 get_current_sam3(struct command_context_s
*cmd_ctx
)
237 static struct sam3_chip
*p
;
239 t
= get_current_target( cmd_ctx
);
241 command_print( cmd_ctx
, "No current target?");
247 // this should not happen
248 // the command is not registered until the chip is created?
249 command_print( cmd_ctx
, "No SAM3 chips exist?");
254 if ( p
->target
== t
){
259 command_print( cmd_ctx
, "Cannot find SAM3 chip?");
264 // these are used to *initialize* the "pChip->details" structure.
265 static const struct sam3_chip_details all_sam3_details
[] = {
267 .chipid_cidr
= 0x28100960,
268 .name
= "at91sam3u4e",
269 .total_flash_size
= 256 * 1024,
270 .total_sram_size
= 52 * 1024,
274 // System boots at address 0x0
275 // gpnvm[1] = selects boot code
277 // boot is via "SAMBA" (rom)
280 // Selection is via gpnvm[2]
283 // NOTE: banks 0 & 1 switch places
285 // Bank0 is the boot rom
287 // Bank1 is the boot rom
294 .base_address
= FLASH_BANK0_BASE
,
295 .controller_address
= 0x400e0800,
297 .size_bytes
= 128 * 1024,
308 .base_address
= FLASH_BANK1_BASE
,
309 .controller_address
= 0x400e0a00,
311 .size_bytes
= 128 * 1024,
319 .chipid_cidr
= 0x281a0760,
320 .name
= "at91sam3u2e",
321 .total_flash_size
= 128 * 1024,
322 .total_sram_size
= 36 * 1024,
326 // System boots at address 0x0
327 // gpnvm[1] = selects boot code
329 // boot is via "SAMBA" (rom)
332 // Selection is via gpnvm[2]
339 .base_address
= FLASH_BANK0_BASE
,
340 .controller_address
= 0x400e0800,
342 .size_bytes
= 128 * 1024,
355 .chipid_cidr
= 0x28190560,
356 .name
= "at91sam3u1e",
357 .total_flash_size
= 64 * 1024,
358 .total_sram_size
= 20 * 1024,
362 // System boots at address 0x0
363 // gpnvm[1] = selects boot code
365 // boot is via "SAMBA" (rom)
368 // Selection is via gpnvm[2]
377 .base_address
= FLASH_BANK0_BASE
,
378 .controller_address
= 0x400e0800,
380 .size_bytes
= 64 * 1024,
394 .chipid_cidr
= 0x28000960,
395 .name
= "at91sam3u4c",
396 .total_flash_size
= 256 * 1024,
397 .total_sram_size
= 52 * 1024,
401 // System boots at address 0x0
402 // gpnvm[1] = selects boot code
404 // boot is via "SAMBA" (rom)
407 // Selection is via gpnvm[2]
410 // NOTE: banks 0 & 1 switch places
412 // Bank0 is the boot rom
414 // Bank1 is the boot rom
421 .base_address
= FLASH_BANK0_BASE
,
422 .controller_address
= 0x400e0800,
424 .size_bytes
= 128 * 1024,
435 .base_address
= FLASH_BANK1_BASE
,
436 .controller_address
= 0x400e0a00,
438 .size_bytes
= 128 * 1024,
446 .chipid_cidr
= 0x280a0760,
447 .name
= "at91sam3u2c",
448 .total_flash_size
= 128 * 1024,
449 .total_sram_size
= 36 * 1024,
453 // System boots at address 0x0
454 // gpnvm[1] = selects boot code
456 // boot is via "SAMBA" (rom)
459 // Selection is via gpnvm[2]
466 .base_address
= FLASH_BANK0_BASE
,
467 .controller_address
= 0x400e0800,
469 .size_bytes
= 128 * 1024,
482 .chipid_cidr
= 0x28090560,
483 .name
= "at91sam3u1c",
484 .total_flash_size
= 64 * 1024,
485 .total_sram_size
= 20 * 1024,
489 // System boots at address 0x0
490 // gpnvm[1] = selects boot code
492 // boot is via "SAMBA" (rom)
495 // Selection is via gpnvm[2]
504 .base_address
= FLASH_BANK0_BASE
,
505 .controller_address
= 0x400e0800,
507 .size_bytes
= 64 * 1024,
528 /***********************************************************************
529 **********************************************************************
530 **********************************************************************
531 **********************************************************************
532 **********************************************************************
533 **********************************************************************/
534 /* *ATMEL* style code - from the SAM3 driver code */
536 /** Get the current status of the EEFC
538 * the value of some status bits (LOCKE, PROGE).
539 * @param pPrivate - info about the bank
540 * @param v - result goes here
543 EFC_GetStatus( struct sam3_bank_private
*pPrivate
, uint32_t *v
)
546 r
= target_read_u32( pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FSR
, v
);
547 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
549 ((unsigned int)((*v
>> 2) & 1)),
550 ((unsigned int)((*v
>> 1) & 1)),
551 ((unsigned int)((*v
>> 0) & 1)));
556 /** Get the result of the last executed command.
557 * @param pPrivate - info about the bank
558 * @param v - result goes here
561 EFC_GetResult( struct sam3_bank_private
*pPrivate
, uint32_t *v
)
565 r
= target_read_u32( pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FRR
, &rv
);
569 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
574 EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
575 unsigned command
, unsigned argument
)
584 // Check command & argument
587 case AT91C_EFC_FCMD_WP
:
588 case AT91C_EFC_FCMD_WPL
:
589 case AT91C_EFC_FCMD_EWP
:
590 case AT91C_EFC_FCMD_EWPL
:
591 // case AT91C_EFC_FCMD_EPL:
592 // case AT91C_EFC_FCMD_EPA:
593 case AT91C_EFC_FCMD_SLB
:
594 case AT91C_EFC_FCMD_CLB
:
595 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
596 if ( argument
>= n
){
597 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
601 case AT91C_EFC_FCMD_SFB
:
602 case AT91C_EFC_FCMD_CFB
:
603 if ( argument
>= pPrivate
->pChip
->details
.n_gpnvms
){
604 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
605 pPrivate
->pChip
->details
.n_gpnvms
);
609 case AT91C_EFC_FCMD_GETD
:
610 case AT91C_EFC_FCMD_EA
:
611 case AT91C_EFC_FCMD_GLB
:
612 case AT91C_EFC_FCMD_GFB
:
613 case AT91C_EFC_FCMD_STUI
:
614 case AT91C_EFC_FCMD_SPUI
:
615 if ( argument
!= 0 ){
616 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
620 LOG_ERROR("Unknown command %d", command
);
624 if ( command
== AT91C_EFC_FCMD_SPUI
){
625 // this is a very special situation.
626 // Situation (1) - error/retry - see below
627 // And we are being called recursively
628 // Situation (2) - normal, finished reading unique id
630 // it should be "ready"
631 EFC_GetStatus( pPrivate
, &v
);
637 // we have done this before
638 // the controller is not responding.
639 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate
->bank_number
);
643 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
644 pPrivate
->bank_number
);
645 // we do that by issuing the *STOP* command
646 EFC_StartCommand( pPrivate
, AT91C_EFC_FCMD_SPUI
, 0 );
647 // above is recursive, and further recursion is blocked by
648 // if ( command == AT91C_EFC_FCMD_SPUI ) above
654 v
= (0x5A << 24) | (argument
<< 8) | command
;
655 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)) );
656 r
= target_write_u32( pPrivate
->pBank
->target
,
657 pPrivate
->controller_address
+ offset_EFC_FCR
,
659 if ( r
!= ERROR_OK
){
660 LOG_DEBUG("Error Write failed");
665 /** Performs the given command and wait until its completion (or an error).
667 * @param pPrivate - info about the bank
668 * @param command - Command to perform.
669 * @param argument - Optional command argument.
670 * @param status - put command status bits here
673 EFC_PerformCommand( struct sam3_bank_private
*pPrivate
,
681 long long ms_now
, ms_end
;
688 r
= EFC_StartCommand( pPrivate
, command
, argument
);
689 if ( r
!= ERROR_OK
){
693 ms_end
= 500 + timeval_ms();
697 r
= EFC_GetStatus( pPrivate
, &v
);
698 if ( r
!= ERROR_OK
){
701 ms_now
= timeval_ms();
702 if ( ms_now
> ms_end
){
704 LOG_ERROR("Command timeout");
708 while ( (v
& 1) == 0 )
723 /** Read the unique ID.
725 * \param pPrivate - info about the bank
727 * The unique ID is stored in the 'pPrivate' structure.
731 FLASHD_ReadUniqueID ( struct sam3_bank_private
*pPrivate
)
737 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
738 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
739 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
740 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
743 r
= EFC_StartCommand( pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
748 for( x
= 0 ; x
< 4 ; x
++ ){
749 r
= target_read_u32( pPrivate
->pChip
->target
,
750 pPrivate
->pBank
->base
+ (x
* 4),
755 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
758 r
= EFC_PerformCommand( pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
759 LOG_DEBUG("End: R=%d, id=0x%08x, 0x%08x, 0x%08x, 0x%08x",
761 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
762 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
763 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
764 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
769 /** Erases the entire flash.
770 * @param pPrivate - the info about the bank.
773 FLASHD_EraseEntireBank( struct sam3_bank_private
*pPrivate
)
776 return EFC_PerformCommand( pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
781 /** Gets current GPNVM state.
782 * @param pPrivate - info about the bank.
783 * @param gpnvm - GPNVM bit index.
784 * @param puthere - result stored here.
787 //------------------------------------------------------------------------------
789 FLASHD_GetGPNVM( struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
795 if ( pPrivate
->bank_number
!= 0 ){
796 LOG_ERROR("GPNVM only works with Bank0");
800 if ( gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
){
801 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
802 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
807 r
= EFC_PerformCommand( pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
808 if ( r
!= ERROR_OK
){
813 r
= EFC_GetResult(pPrivate
, &v
);
816 // Check if GPNVM is set
817 // get the bit and make it a 0/1
818 *puthere
= (v
>> gpnvm
) & 1;
827 /** Clears the selected GPNVM bit.
828 * @param gpnvm GPNVM index.
830 * Returns 0 if successful; otherwise returns an error code.
833 FLASHD_ClrGPNVM( struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
839 if ( pPrivate
->bank_number
!= 0 ){
840 LOG_ERROR("GPNVM only works with Bank0");
844 if ( gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
){
845 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
846 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
850 r
= FLASHD_GetGPNVM( pPrivate
, gpnvm
, &v
);
851 if ( r
!= ERROR_OK
){
852 LOG_DEBUG("Failed: %d",r
);
855 r
= EFC_PerformCommand( pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
856 LOG_DEBUG("End: %d",r
);
862 /** Sets the selected GPNVM bit.
863 * @param gpnvm GPNVM index.
867 FLASHD_SetGPNVM( struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
872 if ( pPrivate
->bank_number
!= 0 ){
873 LOG_ERROR("GPNVM only works with Bank0");
877 if ( gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
){
878 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
879 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
883 r
= FLASHD_GetGPNVM( pPrivate
, gpnvm
, &v
);
884 if ( r
!= ERROR_OK
){
892 r
= EFC_PerformCommand( pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
898 /** Returns a bit field (at most 64) of locked regions within a page.
899 * @param pPrivate - info about the bank
900 * @param v - where to store locked bits
901 * \param end End address of range.
905 FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
909 r
= EFC_PerformCommand( pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
910 if ( r
== ERROR_OK
){
911 r
= EFC_GetResult(pPrivate
, v
);
913 LOG_DEBUG("End: %d",r
);
918 /**Unlocks all the regions in the given address range.
920 * \param start_sector - first sector to unlock
921 * \param end_sector - last (inclusive) to unlock
925 FLASHD_Unlock( struct sam3_bank_private
*pPrivate
,
926 unsigned start_sector
,
927 unsigned end_sector
)
932 uint32_t pages_per_sector
;
934 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
936 /* Unlock all pages */
937 while (start_sector
<= end_sector
){
938 pg
= start_sector
* pages_per_sector
;
940 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
953 * @param start_sector - first sector to lock
954 * @param end_sector - last sector (inclusive) to lock
959 FLASHD_Lock( struct sam3_bank_private
*pPrivate
,
960 unsigned start_sector
,
961 unsigned end_sector
)
965 uint32_t pages_per_sector
;
968 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
971 while (start_sector
<= end_sector
){
972 pg
= start_sector
* pages_per_sector
;
974 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
984 /****** END SAM3 CODE ********/
986 /* begin helpful debug code */
989 sam3_sprintf( struct sam3_chip
*pChip
, const char *fmt
, ... )
993 if ( pChip
->mbuf
== NULL
){
997 membuf_vsprintf( pChip
->mbuf
, fmt
, ap
);
1001 // print the fieldname, the field value, in dec & hex, and return field value
1003 sam3_reg_fieldname( struct sam3_chip
*pChip
,
1004 const char *regname
,
1013 // extract the field
1015 v
= v
& ((1 << width
)-1);
1025 sam3_sprintf( pChip
, "\t%*s: %*d [0x%0*x] ",
1026 REG_NAME_WIDTH
, regname
,
1033 static const char _unknown
[] = "unknown";
1034 static const char * const eproc_names
[] = {
1053 #define nvpsize2 nvpsize // these two tables are identical
1054 static const char * const nvpsize
[] = {
1067 "1024K bytes", // 12
1069 "2048K bytes", // 14
1074 static const char * const sramsize
[] = {
1094 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1095 { 0x19, "AT91SAM9xx Series" },
1096 { 0x29, "AT91SAM9XExx Series" },
1097 { 0x34, "AT91x34 Series" },
1098 { 0x37, "CAP7 Series" },
1099 { 0x39, "CAP9 Series" },
1100 { 0x3B, "CAP11 Series" },
1101 { 0x40, "AT91x40 Series" },
1102 { 0x42, "AT91x42 Series" },
1103 { 0x55, "AT91x55 Series" },
1104 { 0x60, "AT91SAM7Axx Series" },
1105 { 0x61, "AT91SAM7AQxx Series" },
1106 { 0x63, "AT91x63 Series" },
1107 { 0x70, "AT91SAM7Sxx Series" },
1108 { 0x71, "AT91SAM7XCxx Series" },
1109 { 0x72, "AT91SAM7SExx Series" },
1110 { 0x73, "AT91SAM7Lxx Series" },
1111 { 0x75, "AT91SAM7Xxx Series" },
1112 { 0x76, "AT91SAM7SLxx Series" },
1113 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1114 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1115 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1116 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1117 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1118 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1119 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1120 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1121 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1122 { 0x92, "AT91x92 Series" },
1123 { 0xF0, "AT75Cxx Series" },
1128 static const char * const nvptype
[] = {
1130 "romless or onchip flash", // 1
1131 "embedded flash memory", // 2
1132 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1133 "sram emulating flash", // 4
1140 static const char *_yes_or_no( uint32_t v
)
1149 static const char * const _rc_freq
[] = {
1150 "4 MHz", "8 MHz", "12 MHz", "reserved"
1154 sam3_explain_ckgr_mor( struct sam3_chip
*pChip
)
1159 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1 );
1160 sam3_sprintf( pChip
, "(main xtal enabled: %s)\n",
1162 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1 );
1163 sam3_sprintf( pChip
, "(main osc bypass: %s)\n",
1165 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 2, 1 );
1166 sam3_sprintf( pChip
, "(onchip RC-OSC enabled: %s)\n",
1168 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3 );
1169 sam3_sprintf( pChip
, "(onchip RC-OSC freq: %s)\n",
1172 pChip
->cfg
.rc_freq
= 0;
1176 pChip
->cfg
.rc_freq
= 0;
1178 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1181 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1184 pChip
->cfg
.rc_freq
= 12* 1000 * 1000;
1189 v
= sam3_reg_fieldname(pChip
,"MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8 );
1190 sam3_sprintf( pChip
, "(startup clks, time= %f uSecs)\n",
1191 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1192 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1 );
1193 sam3_sprintf( pChip
, "(mainosc source: %s)\n",
1194 v
? "external xtal" : "internal RC");
1196 v
= sam3_reg_fieldname(pChip
,"CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1 );
1197 sam3_sprintf(pChip
, "(clock failure enabled: %s)\n",
1204 sam3_explain_chipid_cidr( struct sam3_chip
*pChip
)
1210 sam3_reg_fieldname( pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5 );
1211 sam3_sprintf(pChip
,"\n");
1213 v
= sam3_reg_fieldname( pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3 );
1214 sam3_sprintf( pChip
, "%s\n", eproc_names
[v
]);
1216 v
= sam3_reg_fieldname( pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4 );
1217 sam3_sprintf( pChip
, "%s\n", nvpsize
[v
]);
1219 v
= sam3_reg_fieldname( pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4 );
1220 sam3_sprintf( pChip
, "%s\n", nvpsize2
[v
]);
1222 v
= sam3_reg_fieldname( pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16,4 );
1223 sam3_sprintf( pChip
, "%s\n", sramsize
[ v
] );
1225 v
= sam3_reg_fieldname( pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8 );
1227 for( x
= 0 ; archnames
[x
].name
; x
++ ){
1228 if ( v
== archnames
[x
].value
){
1229 cp
= archnames
[x
].name
;
1234 sam3_sprintf( pChip
, "%s\n", cp
);
1236 v
= sam3_reg_fieldname( pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3 );
1237 sam3_sprintf( pChip
, "%s\n", nvptype
[ v
] );
1239 v
= sam3_reg_fieldname( pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1 );
1240 sam3_sprintf(pChip
, "(exists: %s)\n", _yes_or_no(v
));
1244 sam3_explain_ckgr_mcfr( struct sam3_chip
*pChip
)
1249 v
= sam3_reg_fieldname( pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1 );
1250 sam3_sprintf( pChip
, "(main ready: %s)\n", _yes_or_no( v
));
1252 v
= sam3_reg_fieldname( pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16 );
1254 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1255 pChip
->cfg
.mainosc_freq
= v
;
1257 sam3_sprintf(pChip
, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1259 pChip
->cfg
.slow_freq
/ 1000,
1260 pChip
->cfg
.slow_freq
% 1000);
1265 sam3_explain_ckgr_plla( struct sam3_chip
*pChip
)
1269 diva
= sam3_reg_fieldname( pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8 );
1270 sam3_sprintf(pChip
,"\n");
1271 mula
= sam3_reg_fieldname( pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11 );
1272 sam3_sprintf(pChip
,"\n");
1273 pChip
->cfg
.plla_freq
= 0;
1275 sam3_sprintf(pChip
,"\tPLLA Freq: (Disabled,mula=0)\n");
1276 } else if ( diva
== 0 ){
1277 sam3_sprintf(pChip
,"\tPLLA Freq: (Disabled,diva=0)\n");
1278 } else if ( diva
== 1 ){
1279 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+1));
1280 sam3_sprintf(pChip
,"\tPLLA Freq: %3.03f MHz\n",
1281 _tomhz( pChip
->cfg
.plla_freq
));
1287 sam3_explain_mckr( struct sam3_chip
*pChip
)
1289 uint32_t css
, pres
,fin
;
1293 css
= sam3_reg_fieldname( pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2 );
1296 fin
= pChip
->cfg
.slow_freq
;
1300 fin
= pChip
->cfg
.mainosc_freq
;
1304 fin
= pChip
->cfg
.plla_freq
;
1308 if ( pChip
->cfg
.CKGR_UCKR
& (1 << 16) ){
1309 fin
= 480 * 1000 * 1000;
1313 cp
= "upll (*ERROR* UPLL is disabled)";
1318 sam3_sprintf( pChip
, "%s (%3.03f Mhz)\n",
1321 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3 );
1322 switch ( pres
& 0x07 ){
1325 cp
= "selected clock";
1355 sam3_sprintf( pChip
, "(%s)\n", cp
);
1357 // sam3 has a *SINGLE* clock -
1358 // other at91 series parts have divisors for these.
1359 pChip
->cfg
.cpu_freq
= fin
;
1360 pChip
->cfg
.mclk_freq
= fin
;
1361 pChip
->cfg
.fclk_freq
= fin
;
1362 sam3_sprintf( pChip
, "\t\tResult CPU Freq: %3.03f\n",
1367 static struct sam3_chip
*
1368 target2sam3( target_t
*pTarget
)
1370 struct sam3_chip
*pChip
;
1372 if (pTarget
== NULL
){
1376 pChip
= all_sam3_chips
;
1378 if (pChip
->target
== pTarget
){
1379 break; // return below
1381 pChip
= pChip
->next
;
1389 sam3_get_reg_ptr( struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
1391 // this function exists to help
1392 // keep funky offsetof() errors
1393 // and casting from causing bugs
1395 // By using prototypes - we can detect what would
1396 // be casting errors.
1398 return ((uint32_t *)( ((char *)(pCfg
)) + pList
->struct_offset
));
1402 #define SAM3_ENTRY( NAME, FUNC ) { .address = SAM3_ ## NAME, .struct_offset = offsetof( struct sam3_cfg, NAME ), #NAME, FUNC }
1403 static const struct sam3_reg_list sam3_all_regs
[] = {
1404 SAM3_ENTRY( CKGR_MOR
, sam3_explain_ckgr_mor
),
1405 SAM3_ENTRY( CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
1406 SAM3_ENTRY( CKGR_PLLAR
, sam3_explain_ckgr_plla
),
1407 SAM3_ENTRY( CKGR_UCKR
, NULL
),
1408 SAM3_ENTRY( PMC_FSMR
, NULL
),
1409 SAM3_ENTRY( PMC_FSPR
, NULL
),
1410 SAM3_ENTRY( PMC_IMR
, NULL
),
1411 SAM3_ENTRY( PMC_MCKR
, sam3_explain_mckr
),
1412 SAM3_ENTRY( PMC_PCK0
, NULL
),
1413 SAM3_ENTRY( PMC_PCK1
, NULL
),
1414 SAM3_ENTRY( PMC_PCK2
, NULL
),
1415 SAM3_ENTRY( PMC_PCSR
, NULL
),
1416 SAM3_ENTRY( PMC_SCSR
, NULL
),
1417 SAM3_ENTRY( PMC_SR
, NULL
),
1418 SAM3_ENTRY( CHIPID_CIDR
, sam3_explain_chipid_cidr
),
1419 SAM3_ENTRY( CHIPID_EXID
, NULL
),
1420 SAM3_ENTRY( SUPC_CR
, NULL
),
1422 // TERMINATE THE LIST
1430 static struct sam3_bank_private
*
1431 get_sam3_bank_private( flash_bank_t
*bank
)
1433 return (struct sam3_bank_private
*)(bank
->driver_priv
);
1437 * Given a pointer to where it goes in the structure..
1438 * Determine the register name, address from the all registers table.
1440 static const struct sam3_reg_list
*
1441 sam3_GetReg( struct sam3_chip
*pChip
, uint32_t *goes_here
)
1443 const struct sam3_reg_list
*pReg
;
1445 pReg
= &(sam3_all_regs
[0]);
1447 uint32_t *pPossible
;
1449 // calculate where this one go..
1450 // it is "possibly" this register.
1452 pPossible
= ((uint32_t *)( ((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
1454 // well? Is it this register
1455 if ( pPossible
== goes_here
){
1463 // This is *TOTAL*PANIC* - we are totally screwed.
1464 LOG_ERROR("INVALID SAM3 REGISTER");
1470 sam3_ReadThisReg( struct sam3_chip
*pChip
, uint32_t *goes_here
)
1472 const struct sam3_reg_list
*pReg
;
1475 pReg
= sam3_GetReg( pChip
, goes_here
);
1480 r
= target_read_u32( pChip
->target
, pReg
->address
, goes_here
);
1481 if ( r
!= ERROR_OK
){
1482 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1483 pReg
->name
, (unsigned)(pReg
->address
), r
);
1491 sam3_ReadAllRegs( struct sam3_chip
*pChip
)
1494 const struct sam3_reg_list
*pReg
;
1496 pReg
= &(sam3_all_regs
[0]);
1497 while ( pReg
->name
){
1498 r
= sam3_ReadThisReg( pChip
,
1499 sam3_get_reg_ptr( &(pChip
->cfg
), pReg
) );
1500 if ( r
!= ERROR_OK
){
1501 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1502 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
1514 sam3_GetInfo( struct sam3_chip
*pChip
)
1516 const struct sam3_reg_list
*pReg
;
1519 membuf_reset( pChip
->mbuf
);
1522 pReg
= &(sam3_all_regs
[0]);
1525 LOG_DEBUG("Start: %s", pReg
->name
);
1526 regval
= *sam3_get_reg_ptr( &(pChip
->cfg
), pReg
);
1527 sam3_sprintf(pChip
, "%*s: [0x%08x] -> 0x%08x\n",
1532 if ( pReg
->explain_func
){
1533 (*(pReg
->explain_func
))( pChip
);
1535 LOG_DEBUG("End: %s", pReg
->name
);
1538 sam3_sprintf(pChip
," rc-osc: %3.03f MHz\n", _tomhz( pChip
->cfg
.rc_freq
));
1539 sam3_sprintf(pChip
," mainosc: %3.03f MHz\n", _tomhz( pChip
->cfg
.mainosc_freq
));
1540 sam3_sprintf(pChip
," plla: %3.03f MHz\n", _tomhz( pChip
->cfg
.plla_freq
));
1541 sam3_sprintf(pChip
," cpu-freq: %3.03f MHz\n", _tomhz( pChip
->cfg
.cpu_freq
));
1542 sam3_sprintf(pChip
,"mclk-freq: %3.03f MHz\n", _tomhz( pChip
->cfg
.mclk_freq
));
1545 sam3_sprintf( pChip
, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1546 pChip
->cfg
.unique_id
[0],
1547 pChip
->cfg
.unique_id
[1],
1548 pChip
->cfg
.unique_id
[2],
1549 pChip
->cfg
.unique_id
[3]);
1557 sam3_erase_check(struct flash_bank_s
*bank
)
1562 if (bank
->target
->state
!= TARGET_HALTED
) {
1563 LOG_ERROR("Target not halted");
1564 return ERROR_TARGET_NOT_HALTED
;
1566 if ( 0 == bank
->num_sectors
){
1567 LOG_ERROR("Target: not supported/not probed\n");
1571 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1572 for( x
= 0 ; x
< bank
->num_sectors
; x
++ ){
1573 bank
->sectors
[x
].is_erased
= 1;
1581 sam3_protect_check(struct flash_bank_s
*bank
)
1586 struct sam3_bank_private
*pPrivate
;
1589 if (bank
->target
->state
!= TARGET_HALTED
) {
1590 LOG_ERROR("Target not halted");
1591 return ERROR_TARGET_NOT_HALTED
;
1594 pPrivate
= get_sam3_bank_private(bank
);
1596 LOG_ERROR("no private for this bank?");
1599 if ( !(pPrivate
->probed
) ){
1600 return ERROR_FLASH_BANK_NOT_PROBED
;
1603 r
= FLASHD_GetLockBits( pPrivate
, &v
);
1604 if ( r
!= ERROR_OK
){
1605 LOG_DEBUG("Failed: %d",r
);
1609 for( x
= 0 ; x
< pPrivate
->nsectors
; x
++ ){
1610 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
1617 sam3_flash_bank_command(struct command_context_s
*cmd_ctx
,
1621 struct flash_bank_s
*bank
)
1623 struct sam3_chip
*pChip
;
1625 pChip
= all_sam3_chips
;
1627 // is this an existing chip?
1629 if ( pChip
->target
== bank
->target
){
1632 pChip
= pChip
->next
;
1636 // this is a *NEW* chip
1637 pChip
= calloc( 1, sizeof(struct sam3_chip
) );
1639 LOG_ERROR("NO RAM!");
1642 pChip
->target
= bank
->target
;
1644 pChip
->next
= all_sam3_chips
;
1645 all_sam3_chips
= pChip
;
1646 pChip
->target
= bank
->target
;
1647 // assumption is this runs at 32khz
1648 pChip
->cfg
.slow_freq
= 32768;
1650 pChip
->mbuf
= membuf_new();
1651 if ( !(pChip
->mbuf
) ){
1652 LOG_ERROR("no memory");
1657 switch ( bank
->base
){
1659 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1660 ((unsigned int)(bank
->base
)),
1661 ((unsigned int)(FLASH_BANK0_BASE
)),
1662 ((unsigned int)(FLASH_BANK1_BASE
)));
1665 case FLASH_BANK0_BASE
:
1666 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1667 bank
->bank_number
= 0;
1668 pChip
->details
.bank
[0].pChip
= pChip
;
1669 pChip
->details
.bank
[0].pBank
= bank
;
1671 case FLASH_BANK1_BASE
:
1672 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
1673 bank
->bank_number
= 1;
1674 pChip
->details
.bank
[1].pChip
= pChip
;
1675 pChip
->details
.bank
[1].pBank
= bank
;
1679 // we initialize after probing.
1684 sam3_GetDetails( struct sam3_bank_private
*pPrivate
)
1686 const struct sam3_chip_details
*pDetails
;
1687 struct sam3_chip
*pChip
;
1689 flash_bank_t
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
1695 pDetails
= all_sam3_details
;
1696 while ( pDetails
->name
){
1697 if ( pDetails
->chipid_cidr
== pPrivate
->pChip
->cfg
.CHIPID_CIDR
){
1703 if ( pDetails
->name
== NULL
){
1704 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1705 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
) );
1706 // Help the victim, print details about the chip
1707 membuf_reset( pPrivate
->pChip
->mbuf
);
1708 membuf_sprintf( pPrivate
->pChip
->mbuf
,
1709 "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1710 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
1711 sam3_explain_chipid_cidr( pPrivate
->pChip
);
1712 cp
= membuf_strtok( pPrivate
->pChip
->mbuf
, "\n", &vp
);
1714 LOG_INFO("%s", cp
);
1715 cp
= membuf_strtok( NULL
, "\n", &vp
);
1720 // DANGER: THERE ARE DRAGONS HERE
1722 // get our pChip - it is going
1723 // to be over-written shortly
1724 pChip
= pPrivate
->pChip
;
1726 // Note that, in reality:
1728 // pPrivate = &(pChip->details.bank[0])
1729 // or pPrivate = &(pChip->details.bank[1])
1732 // save the "bank" pointers
1733 for( x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++ ){
1734 saved_banks
[ x
] = pChip
->details
.bank
[x
].pBank
;
1737 // Overwrite the "details" structure.
1738 memcpy( &(pPrivate
->pChip
->details
),
1740 sizeof(pPrivate
->pChip
->details
));
1742 // now fix the ghosted pointers
1743 for( x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++ ){
1744 pChip
->details
.bank
[x
].pChip
= pChip
;
1745 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
1748 // update the *BANK*SIZE*
1757 _sam3_probe(struct flash_bank_s
*bank
, int noise
)
1761 struct sam3_bank_private
*pPrivate
;
1764 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
1765 if (bank
->target
->state
!= TARGET_HALTED
)
1767 LOG_ERROR("Target not halted");
1768 return ERROR_TARGET_NOT_HALTED
;
1771 pPrivate
= get_sam3_bank_private( bank
);
1773 LOG_ERROR("Invalid/unknown bank number\n");
1777 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
1778 if ( r
!= ERROR_OK
){
1784 r
= sam3_GetInfo( pPrivate
->pChip
);
1785 if ( r
!= ERROR_OK
){
1788 if ( !(pPrivate
->pChip
->probed
) ){
1789 pPrivate
->pChip
->probed
= 1;
1791 r
= sam3_GetDetails( pPrivate
);
1792 if ( r
!= ERROR_OK
){
1797 // update the flash bank size
1798 for( x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++ ){
1799 if ( bank
->base
== pPrivate
->pChip
->details
.bank
[0].base_address
){
1800 bank
->size
= pPrivate
->pChip
->details
.bank
[0].size_bytes
;
1805 if ( bank
->sectors
== NULL
){
1806 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof( (bank
->sectors
)[0] )));
1807 if ( bank
->sectors
== NULL
){
1808 LOG_ERROR("No memory!");
1811 bank
->num_sectors
= pPrivate
->nsectors
;
1813 for( x
= 0 ; ((int)(x
)) < bank
->num_sectors
; x
++ ){
1814 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
1815 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
1817 bank
->sectors
[x
].is_erased
= -1;
1818 bank
->sectors
[x
].is_protected
= -1;
1822 pPrivate
->probed
= 1;
1824 r
= sam3_protect_check( bank
);
1825 if ( r
!= ERROR_OK
){
1829 LOG_DEBUG("Bank = %d, nbanks = %d",
1830 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
1831 if ( (pPrivate
->bank_number
+1) == pPrivate
->pChip
->details
.n_banks
){
1833 // it appears to be associated with the *last* flash bank.
1834 FLASHD_ReadUniqueID(pPrivate
);
1841 sam3_probe(struct flash_bank_s
*bank
)
1843 return _sam3_probe( bank
, 1 );
1847 sam3_auto_probe(struct flash_bank_s
*bank
)
1849 return _sam3_probe( bank
, 0 );
1855 sam3_erase(struct flash_bank_s
*bank
, int first
, int last
)
1857 struct sam3_bank_private
*pPrivate
;
1861 if (bank
->target
->state
!= TARGET_HALTED
) {
1862 LOG_ERROR("Target not halted");
1863 return ERROR_TARGET_NOT_HALTED
;
1866 r
= sam3_auto_probe( bank
);
1867 if ( r
!= ERROR_OK
){
1868 LOG_DEBUG("Here,r=%d",r
);
1872 pPrivate
= get_sam3_bank_private( bank
);
1873 if ( !(pPrivate
->probed
) ){
1874 return ERROR_FLASH_BANK_NOT_PROBED
;
1877 if ( (first
== 0) && ((last
+1)== ((int)(pPrivate
->nsectors
))) ){
1880 return FLASHD_EraseEntireBank( pPrivate
);
1882 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1887 sam3_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
1889 struct sam3_bank_private
*pPrivate
;
1893 if (bank
->target
->state
!= TARGET_HALTED
) {
1894 LOG_ERROR("Target not halted");
1895 return ERROR_TARGET_NOT_HALTED
;
1898 pPrivate
= get_sam3_bank_private( bank
);
1899 if ( !(pPrivate
->probed
) ){
1900 return ERROR_FLASH_BANK_NOT_PROBED
;
1904 r
= FLASHD_Lock( pPrivate
, (unsigned)(first
), (unsigned)(last
));
1906 r
= FLASHD_Unlock( pPrivate
, (unsigned)(first
), (unsigned)(last
));
1908 LOG_DEBUG("End: r=%d",r
);
1916 sam3_info( flash_bank_t
*bank
, char *buf
, int buf_size
)
1918 if (bank
->target
->state
!= TARGET_HALTED
) {
1919 LOG_ERROR("Target not halted");
1920 return ERROR_TARGET_NOT_HALTED
;
1927 sam3_page_read( struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
1932 adr
= pagenum
* pPrivate
->page_size
;
1933 adr
+= adr
+ pPrivate
->base_address
;
1935 r
= target_read_memory( pPrivate
->pChip
->target
,
1937 4, /* THIS*MUST*BE* in 32bit values */
1938 pPrivate
->page_size
/ 4,
1940 if ( r
!= ERROR_OK
){
1941 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr
) );
1946 // The code below is basically this:
1948 // arm-none-eabi-gcc -mthumb -mcpu=cortex-m3 -O9 -S ./foobar.c -o foobar.s
1950 // Only the *CPU* can write to the flash buffer.
1951 // the DAP cannot... so - we download this 28byte thing
1952 // Run the algorithm - (below)
1953 // to program the device
1955 // ========================================
1956 // #include <stdint.h>
1960 // const uint32_t *src;
1962 // volatile uint32_t *base;
1967 // uint32_t sam3_function( struct foo *p )
1969 // volatile uint32_t *v;
1971 // const uint32_t *s;
1989 // } while ( !(r&1) )
1993 // ========================================
1997 static const uint8_t
1998 sam3_page_write_opcodes
[] = {
1999 // 24 0000 0446 mov r4, r0
2001 // 25 0002 6168 ldr r1, [r4, #4]
2003 // 26 0004 0068 ldr r0, [r0, #0]
2005 // 27 0006 A268 ldr r2, [r4, #8]
2007 // 28 @ lr needed for prologue
2009 // 30 0008 51F8043B ldr r3, [r1], #4
2010 0x51,0xf8,0x04,0x3b,
2011 // 31 000c 12F1FF32 adds r2, r2, #-1
2012 0x12,0xf1,0xff,0x32,
2013 // 32 0010 40F8043B str r3, [r0], #4
2014 0x40,0xf8,0x04,0x3b,
2015 // 33 0014 F8D1 bne .L2
2017 // 34 0016 E268 ldr r2, [r4, #12]
2019 // 35 0018 2369 ldr r3, [r4, #16]
2021 // 36 001a 5360 str r3, [r2, #4]
2023 // 37 001c 0832 adds r2, r2, #8
2026 // 39 001e 1068 ldr r0, [r2, #0]
2028 // 40 0020 10F0010F tst r0, #1
2029 0x10,0xf0,0x01,0x0f,
2030 // 41 0024 FBD0 beq .L4
2033 // 43 0026 FEE7 b .done
2039 sam3_page_write( struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2045 adr
= pagenum
* pPrivate
->page_size
;
2046 adr
+= (adr
+ pPrivate
->base_address
);
2048 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
) );
2049 r
= target_write_memory( pPrivate
->pChip
->target
,
2051 4, /* THIS*MUST*BE* in 32bit values */
2052 pPrivate
->page_size
/ 4,
2054 if ( r
!= ERROR_OK
){
2055 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr
) );
2059 r
= EFC_PerformCommand( pPrivate
,
2060 // send Erase & Write Page
2065 if ( r
!= ERROR_OK
){
2066 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr
) );
2068 if ( status
& (1 << 2) ){
2069 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
) );
2072 if ( status
& (1 << 1) ){
2073 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
) );
2084 sam3_write(struct flash_bank_s
*bank
,
2093 unsigned page_offset
;
2094 struct sam3_bank_private
*pPrivate
;
2095 uint8_t *pagebuffer
;
2097 // ignore dumb requests
2102 if (bank
->target
->state
!= TARGET_HALTED
) {
2103 LOG_ERROR("Target not halted");
2104 return ERROR_TARGET_NOT_HALTED
;
2107 pPrivate
= get_sam3_bank_private(bank
);
2108 if ( !(pPrivate
->probed
) ){
2109 return ERROR_FLASH_BANK_NOT_PROBED
;
2113 if ( (offset
+ count
) > pPrivate
->size_bytes
){
2114 LOG_ERROR("Flash write error - past end of bank");
2115 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2116 (unsigned int)(offset
),
2117 (unsigned int)(count
),
2118 (unsigned int)(pPrivate
->size_bytes
) );
2122 pagebuffer
= alloca( pPrivate
->page_size
);
2124 // what page do we start & end in?
2125 page_cur
= offset
/ pPrivate
->page_size
;
2126 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2128 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2129 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
) );
2131 // Special case: all one page
2134 // (1) non-aligned start
2136 // (3) non-aligned end.
2138 // Handle special case - all one page.
2139 if ( page_cur
== page_end
){
2140 LOG_DEBUG("Special case, all in one page");
2141 r
= sam3_page_read( pPrivate
, page_cur
, pagebuffer
);
2142 if ( r
!= ERROR_OK
){
2146 page_offset
= (offset
& (pPrivate
->page_size
-1));
2147 memcpy( pagebuffer
+ page_offset
,
2151 r
= sam3_page_write( pPrivate
, page_cur
, pagebuffer
);
2152 if ( r
!= ERROR_OK
){
2158 // non-aligned start
2159 page_offset
= offset
& (pPrivate
->page_size
- 1);
2161 LOG_DEBUG("Not-Aligned start");
2163 r
= sam3_page_read( pPrivate
, page_cur
, pagebuffer
);
2164 if ( r
!= ERROR_OK
){
2168 // over-write with new data
2169 n
= (pPrivate
->page_size
- page_offset
);
2170 memcpy( pagebuffer
+ page_offset
,
2174 r
= sam3_page_write( pPrivate
, page_cur
, pagebuffer
);
2175 if ( r
!= ERROR_OK
){
2185 // intermediate large pages
2186 // also - the final *terminal*
2187 // if that terminal page is a full page
2188 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count=0x%08x",
2189 (int)page_cur
, (int)page_end
, (unsigned int)(count
) );
2191 while ( (page_cur
< page_end
) &&
2192 (count
>= pPrivate
->page_size
) ){
2193 r
= sam3_page_write( pPrivate
, page_cur
, buffer
);
2194 if ( r
!= ERROR_OK
){
2197 count
-= pPrivate
->page_size
;
2198 buffer
+= pPrivate
->page_size
;
2202 // terminal partial page?
2204 LOG_DEBUG("Terminal partial page, count=0x%08x", (unsigned int)(count
));
2205 // we have a partial page
2206 r
= sam3_page_read( pPrivate
, page_cur
, pagebuffer
);
2207 if ( r
!= ERROR_OK
){
2210 // data goes at start
2211 memcpy( pagebuffer
, buffer
, count
);
2212 r
= sam3_page_write( pPrivate
, page_cur
, pagebuffer
);
2213 if ( r
!= ERROR_OK
){
2224 sam3_handle_info_command( struct command_context_s
*cmd_ctx
, char *cmd
, char **argv
, int argc
)
2226 struct sam3_chip
*pChip
;
2232 pChip
= get_current_sam3(cmd_ctx
);
2239 // bank0 must exist before we can do anything
2240 if ( pChip
->details
.bank
[0].pBank
== NULL
){
2243 command_print( cmd_ctx
,
2244 "Please define bank %d via command: flash bank %s ... ",
2246 at91sam3_flash
.name
);
2250 // if bank 0 is not probed, then probe it
2251 if ( !(pChip
->details
.bank
[0].probed
) ){
2252 r
= sam3_auto_probe( pChip
->details
.bank
[0].pBank
);
2253 if ( r
!= ERROR_OK
){
2257 // above garentees the "chip details" structure is valid
2258 // and thus, bank private areas are valid
2259 // and we have a SAM3 chip, what a concept!
2262 // auto-probe other banks, 0 done above
2263 for( x
= 1 ; x
< SAM3_MAX_FLASH_BANKS
; x
++ ){
2264 // skip banks not present
2265 if ( !(pChip
->details
.bank
[x
].present
) ){
2269 if ( pChip
->details
.bank
[x
].pBank
== NULL
){
2273 if ( pChip
->details
.bank
[x
].probed
){
2277 r
= sam3_auto_probe( pChip
->details
.bank
[x
].pBank
);
2278 if ( r
!= ERROR_OK
){
2284 r
= sam3_GetInfo( pChip
);
2285 if ( r
!= ERROR_OK
){
2286 LOG_DEBUG("Sam3Info, Failed %d\n",r
);
2292 cp
= membuf_strtok( pChip
->mbuf
, "\n", &vp
);
2294 command_print(cmd_ctx
,"%s", cp
);
2295 cp
= membuf_strtok( NULL
, "\n", &vp
);
2301 sam3_handle_gpnvm_command( struct command_context_s
*cmd_ctx
, char *cmd
, char **argv
, int argc
)
2306 struct sam3_chip
*pChip
;
2308 pChip
= get_current_sam3(cmd_ctx
);
2313 if ( pChip
->target
->state
!= TARGET_HALTED
){
2314 LOG_ERROR("sam3 - target not halted");
2315 return ERROR_TARGET_NOT_HALTED
;
2319 if ( pChip
->details
.bank
[0].pBank
== NULL
){
2320 command_print( cmd_ctx
, "Bank0 must be defined first via: flash bank %s ...",
2321 at91sam3_flash
.name
);
2324 if ( !pChip
->details
.bank
[0].probed
){
2325 r
= sam3_auto_probe( pChip
->details
.bank
[0].pBank
);
2326 if ( r
!= ERROR_OK
){
2334 command_print(cmd_ctx
,"Too many parameters\n");
2335 return ERROR_COMMAND_SYNTAX_ERROR
;
2345 if ( (0 == strcmp( argv
[0], "show" )) && (0 == strcmp( argv
[1], "all" )) ){
2348 r
= parse_u32( argv
[1], &v32
);
2349 if ( r
!= ERROR_OK
){
2350 command_print( cmd_ctx
, "Not a number: %s", argv
[1] );
2358 if ( 0 == strcmp( "show", argv
[0] ) ){
2361 for( x
= 0 ; x
< pChip
->details
.n_gpnvms
; x
++ ){
2362 r
= FLASHD_GetGPNVM( &(pChip
->details
.bank
[0]), x
, &v
);
2363 if ( r
!= ERROR_OK
){
2366 command_print(cmd_ctx
, "sam3-gpnvm%u: %u", x
, v
);
2370 if ( (who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
) ){
2371 r
= FLASHD_GetGPNVM( &(pChip
->details
.bank
[0]), who
, &v
);
2372 command_print(cmd_ctx
, "sam3-gpnvm%u: %u", who
, v
);
2375 command_print(cmd_ctx
, "sam3-gpnvm invalid GPNVM: %u", who
);
2376 return ERROR_COMMAND_SYNTAX_ERROR
;
2381 command_print( cmd_ctx
, "Missing GPNVM number");
2382 return ERROR_COMMAND_SYNTAX_ERROR
;
2385 if ( 0 == strcmp( "set", argv
[0] ) ){
2386 r
= FLASHD_SetGPNVM( &(pChip
->details
.bank
[0]), who
);
2387 } else if ( (0 == strcmp( "clr", argv
[0] )) ||
2388 (0 == strcmp( "clear", argv
[0])) ){ // quietly accept both
2389 r
= FLASHD_ClrGPNVM( &(pChip
->details
.bank
[0]), who
);
2391 command_print( cmd_ctx
, "Unkown command: %s", argv
[0] );
2392 r
= ERROR_COMMAND_SYNTAX_ERROR
;
2398 sam3_handle_slowclk_command( struct command_context_s
*cmd_ctx
, char *cmd
, char **argv
, int argc
)
2403 struct sam3_chip
*pChip
;
2405 pChip
= get_current_sam3(cmd_ctx
);
2417 r
= parse_u32( argv
[0], &v
);
2419 // absurd slow clock of 200Khz?
2420 command_print(cmd_ctx
,"Absurd/illegal slow clock freq: %d\n", (int)(v
));
2421 return ERROR_COMMAND_SYNTAX_ERROR
;
2423 pChip
->cfg
.slow_freq
= v
;
2428 command_print( cmd_ctx
,"Too many parameters");
2429 return ERROR_COMMAND_SYNTAX_ERROR
;
2432 command_print( cmd_ctx
, "Slowclk freq: %d.%03dkhz",
2433 (int)(pChip
->cfg
.slow_freq
/ 1000),
2434 (int)(pChip
->cfg
.slow_freq
% 1000));
2439 static int sam3_registered
;
2441 sam3_register_commands( struct command_context_s
*cmd_ctx
)
2445 // only register once
2446 if ( !sam3_registered
){
2449 pCmd
= register_command( cmd_ctx
, NULL
, "at91sam3", NULL
, COMMAND_ANY
, NULL
);
2450 register_command( cmd_ctx
, pCmd
,
2452 sam3_handle_gpnvm_command
,
2454 "at91sam3 gpnvm [action [<BIT>], by default 'show', otherwise set|clear BIT");
2455 register_command( cmd_ctx
, pCmd
,
2457 sam3_handle_info_command
,
2459 "at91sam3 info - print information about the current sam3 chip");
2460 register_command( cmd_ctx
, pCmd
,
2462 sam3_handle_slowclk_command
,
2464 "at91sam3 slowclk [VALUE] set the slowclock frequency (default 32768hz)");
2470 flash_driver_t at91sam3_flash
=
2473 .register_commands
= sam3_register_commands
,
2475 .flash_bank_command
= sam3_flash_bank_command
,
2476 .erase
= sam3_erase
,
2477 .protect
= sam3_protect
,
2478 .write
= sam3_write
,
2479 .probe
= sam3_probe
,
2480 .auto_probe
= sam3_auto_probe
,
2481 .erase_check
= sam3_erase_check
,
2482 .protect_check
= sam3_protect_check
,
2489 * Local Variables: **
2491 * c-basic-offset: 4 **