1 /***************************************************************************
2 * Copyright (C) 2005, 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
27 #ifndef EMBEDDED_ICE_H
28 #define EMBEDDED_ICE_H
30 #include "arm7_9_common.h"
37 EICE_W0_ADDR_VALUE
= 4,
38 EICE_W0_ADDR_MASK
= 5,
39 EICE_W0_DATA_VALUE
= 6,
40 EICE_W0_DATA_MASK
= 7,
41 EICE_W0_CONTROL_VALUE
= 8,
42 EICE_W0_CONTROL_MASK
= 9,
43 EICE_W1_ADDR_VALUE
= 10,
44 EICE_W1_ADDR_MASK
= 11,
45 EICE_W1_DATA_VALUE
= 12,
46 EICE_W1_DATA_MASK
= 13,
47 EICE_W1_CONTROL_VALUE
= 14,
48 EICE_W1_CONTROL_MASK
= 15,
53 EICE_DBG_CONTROL_ICEDIS
= 5,
54 EICE_DBG_CONTROL_MONEN
= 4,
55 EICE_DBG_CONTROL_INTDIS
= 2,
56 EICE_DBG_CONTROL_DBGRQ
= 1,
57 EICE_DBG_CONTROL_DBGACK
= 0,
61 EICE_DBG_STATUS_IJBIT
= 5,
62 EICE_DBG_STATUS_ITBIT
= 4,
63 EICE_DBG_STATUS_SYSCOMP
= 3,
64 EICE_DBG_STATUS_IFEN
= 2,
65 EICE_DBG_STATUS_DBGRQ
= 1,
66 EICE_DBG_STATUS_DBGACK
= 0
70 EICE_W_CTRL_ENABLE
= 0x100,
71 EICE_W_CTRL_RANGE
= 0x80,
72 EICE_W_CTRL_CHAIN
= 0x40,
73 EICE_W_CTRL_EXTERN
= 0x20,
74 EICE_W_CTRL_nTRANS
= 0x10,
75 EICE_W_CTRL_nOPC
= 0x8,
76 EICE_W_CTRL_MAS
= 0x6,
77 EICE_W_CTRL_ITBIT
= 0x2,
82 EICE_COMM_CTRL_WBIT
= 1,
83 EICE_COMM_CTRL_RBIT
= 0
86 struct embeddedice_reg
{
88 struct arm_jtag
*jtag_info
;
91 struct reg_cache
*embeddedice_build_reg_cache(struct target
*target
,
92 struct arm7_9_common
*arm7_9
);
94 int embeddedice_setup(struct target
*target
);
96 int embeddedice_read_reg(struct reg
*reg
);
97 int embeddedice_read_reg_w_check(struct reg
*reg
,
98 uint8_t *check_value
, uint8_t *check_mask
);
100 void embeddedice_write_reg(struct reg
*reg
, uint32_t value
);
101 void embeddedice_store_reg(struct reg
*reg
);
103 void embeddedice_set_reg(struct reg
*reg
, uint32_t value
);
105 int embeddedice_receive(struct arm_jtag
*jtag_info
, uint32_t *data
, uint32_t size
);
106 int embeddedice_send(struct arm_jtag
*jtag_info
, uint32_t *data
, uint32_t size
);
108 int embeddedice_handshake(struct arm_jtag
*jtag_info
, int hsbit
, uint32_t timeout
);
110 /* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be
111 * this faster version of embeddedice_write_reg
113 static inline void embeddedice_write_reg_inner(struct jtag_tap
*tap
, int reg_addr
, uint32_t value
)
115 static const int embeddedice_num_bits
[] = {32, 6};
119 values
[1] = (1 << 5) | reg_addr
;
121 jtag_add_dr_out(tap
, 2, embeddedice_num_bits
, values
, TAP_IDLE
);
124 void embeddedice_write_dcc(struct jtag_tap
*tap
, int reg_addr
, const uint8_t *buffer
,
125 int little
, int count
);
127 #endif /* EMBEDDED_ICE_H */