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Delete commented out code. Add a bit of error checking.
[openocd.git] / src / target / arm11.c
blobc41adfa3bf779df3f6d1e6ec28437072743a9ca5
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
34
35
36 #if 0
37 #define _DEBUG_INSTRUCTION_EXECUTION_
38 #endif
39
40 #if 0
41 #define FNC_INFO LOG_DEBUG("-")
42 #else
43 #define FNC_INFO
44 #endif
45
46 #if 1
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #else
49 #define FNC_INFO_NOTIMPLEMENTED
50 #endif
51
52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
53
54 bool arm11_config_memwrite_burst = true;
55 bool arm11_config_memwrite_error_fatal = true;
56 uint32_t arm11_vcr = 0;
57 bool arm11_config_step_irq_enable = false;
58 bool arm11_config_hardware_step = false;
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 ARM11_HANDLER(quit),
101 };
102
103 int arm11_regs_arch_type = -1;
104
105
106 enum arm11_regtype
107 {
108 ARM11_REGISTER_CORE,
109 ARM11_REGISTER_CPSR,
110
111 ARM11_REGISTER_FX,
112 ARM11_REGISTER_FPS,
113
114 ARM11_REGISTER_FIQ,
115 ARM11_REGISTER_SVC,
116 ARM11_REGISTER_ABT,
117 ARM11_REGISTER_IRQ,
118 ARM11_REGISTER_UND,
119 ARM11_REGISTER_MON,
120
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
127
128 /* debug regs */
129 ARM11_REGISTER_DSCR,
130 ARM11_REGISTER_WDTR,
131 ARM11_REGISTER_RDTR,
132 };
133
134
135 typedef struct arm11_reg_defs_s
136 {
137 char * name;
138 uint32_t num;
139 int gdb_num;
140 enum arm11_regtype type;
141 } arm11_reg_defs_t;
142
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
145 {
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
162
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
173 #endif
174
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
176
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
186
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
190
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
194
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
198
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
202
203 /* ARM1176 only */
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
207 #endif
208
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
213 };
214
215 enum arm11_regcache_ids
216 {
217 ARM11_RC_R0,
218 ARM11_RC_RX = ARM11_RC_R0,
219
220 ARM11_RC_R1,
221 ARM11_RC_R2,
222 ARM11_RC_R3,
223 ARM11_RC_R4,
224 ARM11_RC_R5,
225 ARM11_RC_R6,
226 ARM11_RC_R7,
227 ARM11_RC_R8,
228 ARM11_RC_R9,
229 ARM11_RC_R10,
230 ARM11_RC_R11,
231 ARM11_RC_R12,
232 ARM11_RC_R13,
233 ARM11_RC_SP = ARM11_RC_R13,
234 ARM11_RC_R14,
235 ARM11_RC_LR = ARM11_RC_R14,
236 ARM11_RC_R15,
237 ARM11_RC_PC = ARM11_RC_R15,
238
239 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_F0,
241 ARM11_RC_FX = ARM11_RC_F0,
242 ARM11_RC_F1,
243 ARM11_RC_F2,
244 ARM11_RC_F3,
245 ARM11_RC_F4,
246 ARM11_RC_F5,
247 ARM11_RC_F6,
248 ARM11_RC_F7,
249 ARM11_RC_FPS,
250 #endif
251
252 ARM11_RC_CPSR,
253
254 #if ARM11_REGCACHE_MODEREGS
255 ARM11_RC_R8_FIQ,
256 ARM11_RC_R9_FIQ,
257 ARM11_RC_R10_FIQ,
258 ARM11_RC_R11_FIQ,
259 ARM11_RC_R12_FIQ,
260 ARM11_RC_R13_FIQ,
261 ARM11_RC_R14_FIQ,
262 ARM11_RC_SPSR_FIQ,
263
264 ARM11_RC_R13_SVC,
265 ARM11_RC_R14_SVC,
266 ARM11_RC_SPSR_SVC,
267
268 ARM11_RC_R13_ABT,
269 ARM11_RC_R14_ABT,
270 ARM11_RC_SPSR_ABT,
271
272 ARM11_RC_R13_IRQ,
273 ARM11_RC_R14_IRQ,
274 ARM11_RC_SPSR_IRQ,
275
276 ARM11_RC_R13_UND,
277 ARM11_RC_R14_UND,
278 ARM11_RC_SPSR_UND,
279
280 ARM11_RC_R13_MON,
281 ARM11_RC_R14_MON,
282 ARM11_RC_SPSR_MON,
283 #endif
284
285 ARM11_RC_DSCR,
286 ARM11_RC_WDTR,
287 ARM11_RC_RDTR,
288
289 ARM11_RC_MAX,
290 };
291
292 #define ARM11_GDB_REGISTER_COUNT 26
293
294 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295
296 reg_t arm11_gdb_dummy_fp_reg =
297 {
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
299 };
300
301 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
302
303 reg_t arm11_gdb_dummy_fps_reg =
304 {
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 };
307
308
309
310 /** Check and if necessary take control of the system
311 *
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
316 */
317 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
318 {
319 FNC_INFO;
320
321 uint32_t dscr_local_tmp_copy;
322
323 if (!dscr)
324 {
325 dscr = &dscr_local_tmp_copy;
326
327 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
328 }
329
330 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
331 {
332 LOG_DEBUG("Bringing target into debug mode");
333
334 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
335 arm11_write_DSCR(arm11, *dscr);
336
337 /* add further reset initialization here */
338
339 arm11->simulate_reset_on_next_halt = true;
340
341 if (*dscr & ARM11_DSCR_CORE_HALTED)
342 {
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
346 * the target.
347 */
348
349 arm11->target->state = TARGET_HALTED;
350 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 }
352 else
353 {
354 arm11->target->state = TARGET_RUNNING;
355 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
356 }
357
358 arm11_sc7_clear_vbw(arm11);
359 }
360
361 return ERROR_OK;
362 }
363
364
365
366 #define R(x) \
367 (arm11->reg_values[ARM11_RC_##x])
368
369 /** Save processor state.
370 *
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
373 *
374 */
375 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
376 {
377 int retval;
378 FNC_INFO;
379
380 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
381 {
382 arm11->reg_list[i].valid = 1;
383 arm11->reg_list[i].dirty = 0;
384 }
385
386 /* Save DSCR */
387 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
388
389 /* Save wDTR */
390
391 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
392 {
393 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
394
395 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
396
397 scan_field_t chain5_fields[3];
398
399 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
400 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
402
403 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
404 }
405 else
406 {
407 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
408 }
409
410
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
414
415 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
416
417 /* this executes JTAG queue: */
418
419 arm11_write_DSCR(arm11, new_dscr);
420
421
422 /* From the spec:
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
425
426 /** \todo TODO: Test drain write buffer. */
427
428 #if 0
429 while (1)
430 {
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
433
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11, 0xee070f9a);
436
437 uint32_t dscr = arm11_read_DSCR(arm11);
438
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
440
441 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
442 {
443 arm11_run_instr_no_data1(arm11, 0xe320f000);
444
445 dscr = arm11_read_DSCR(arm11);
446
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
448
449 break;
450 }
451 }
452 #endif
453
454 retval = arm11_run_instr_data_prepare(arm11);
455 if (retval != ERROR_OK)
456 return retval;
457
458 /* save r0 - r14 */
459
460 /** \todo TODO: handle other mode registers */
461
462 for (size_t i = 0; i < 15; i++)
463 {
464 /* MCR p14,0,R?,c0,c5,0 */
465 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
466 if (retval != ERROR_OK)
467 return retval;
468 }
469
470 /* save rDTR */
471
472 /* check rDTRfull in DSCR */
473
474 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
475 {
476 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
477 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
478 if (retval != ERROR_OK)
479 return retval;
480 }
481 else
482 {
483 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
484 }
485
486 /* save CPSR */
487
488 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
489 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
490 if (retval != ERROR_OK)
491 return retval;
492
493 /* save PC */
494
495 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
496 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
497 if (retval != ERROR_OK)
498 return retval;
499
500 /* adjust PC depending on ARM state */
501
502 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
503 {
504 arm11->reg_values[ARM11_RC_PC] -= 0;
505 }
506 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
507 {
508 arm11->reg_values[ARM11_RC_PC] -= 4;
509 }
510 else /* ARM state */
511 {
512 arm11->reg_values[ARM11_RC_PC] -= 8;
513 }
514
515 if (arm11->simulate_reset_on_next_halt)
516 {
517 arm11->simulate_reset_on_next_halt = false;
518
519 LOG_DEBUG("Reset c1 Control Register");
520
521 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
522
523 /* MCR p15,0,R0,c1,c0,0 */
524 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
525 if (retval != ERROR_OK)
526 return retval;
527
528 }
529
530 retval = arm11_run_instr_data_finish(arm11);
531 if (retval != ERROR_OK)
532 return retval;
533
534 arm11_dump_reg_changes(arm11);
535
536 return ERROR_OK;
537 }
538
539 void arm11_dump_reg_changes(arm11_common_t * arm11)
540 {
541
542 if (!(debug_level >= LOG_LVL_DEBUG))
543 {
544 return;
545 }
546
547 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
548 {
549 if (!arm11->reg_list[i].valid)
550 {
551 if (arm11->reg_history[i].valid)
552 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
553 }
554 else
555 {
556 if (arm11->reg_history[i].valid)
557 {
558 if (arm11->reg_history[i].value != arm11->reg_values[i])
559 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
560 }
561 else
562 {
563 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
564 }
565 }
566 }
567 }
568
569 /** Restore processor state
570 *
571 * This is called in preparation for the RESTART function.
572 *
573 */
574 int arm11_leave_debug_state(arm11_common_t * arm11)
575 {
576 FNC_INFO;
577 int retval;
578
579 retval = arm11_run_instr_data_prepare(arm11);
580 if (retval != ERROR_OK)
581 return retval;
582
583 /** \todo TODO: handle other mode registers */
584
585 /* restore R1 - R14 */
586
587 for (size_t i = 1; i < 15; i++)
588 {
589 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
590 continue;
591
592 /* MRC p14,0,r?,c0,c5,0 */
593 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
594
595 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
596 }
597
598 retval = arm11_run_instr_data_finish(arm11);
599 if (retval != ERROR_OK)
600 return retval;
601
602 /* spec says clear wDTR and rDTR; we assume they are clear as
603 otherwise our programming would be sloppy */
604 {
605 uint32_t DSCR;
606
607 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
608
609 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
610 {
611 /*
612 The wDTR/rDTR two registers that are used to send/receive data to/from
613 the core in tandem with corresponding instruction codes that are
614 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
615 registers hold data that was written by one side (CPU or JTAG) and not
616 read out by the other side.
617 */
618 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
619 return ERROR_FAIL;
620 }
621 }
622
623 retval = arm11_run_instr_data_prepare(arm11);
624 if (retval != ERROR_OK)
625 return retval;
626
627 /* restore original wDTR */
628
629 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
630 {
631 /* MCR p14,0,R0,c0,c5,0 */
632 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
633 if (retval != ERROR_OK)
634 return retval;
635 }
636
637 /* restore CPSR */
638
639 /* MSR CPSR,R0*/
640 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
641 if (retval != ERROR_OK)
642 return retval;
643
644
645 /* restore PC */
646
647 /* MOV PC,R0 */
648 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
649 if (retval != ERROR_OK)
650 return retval;
651
652
653 /* restore R0 */
654
655 /* MRC p14,0,r0,c0,c5,0 */
656 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
657
658 retval = arm11_run_instr_data_finish(arm11);
659 if (retval != ERROR_OK)
660 return retval;
661
662 /* restore DSCR */
663
664 arm11_write_DSCR(arm11, R(DSCR));
665
666 /* restore rDTR */
667
668 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
669 {
670 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
671
672 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
673
674 scan_field_t chain5_fields[3];
675
676 uint8_t Ready = 0; /* ignored */
677 uint8_t Valid = 0; /* ignored */
678
679 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
680 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
681 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
682
683 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
684 }
685
686 arm11_record_register_history(arm11);
687
688 return ERROR_OK;
689 }
690
691 void arm11_record_register_history(arm11_common_t * arm11)
692 {
693 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
694 {
695 arm11->reg_history[i].value = arm11->reg_values[i];
696 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
697
698 arm11->reg_list[i].valid = 0;
699 arm11->reg_list[i].dirty = 0;
700 }
701 }
702
703
704 /* poll current target status */
705 int arm11_poll(struct target_s *target)
706 {
707 FNC_INFO;
708 int retval;
709
710 arm11_common_t * arm11 = target->arch_info;
711
712 uint32_t dscr;
713
714 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
715
716 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
717
718 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
719
720 if (dscr & ARM11_DSCR_CORE_HALTED)
721 {
722 if (target->state != TARGET_HALTED)
723 {
724 enum target_state old_state = target->state;
725
726 LOG_DEBUG("enter TARGET_HALTED");
727 target->state = TARGET_HALTED;
728 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
729 retval = arm11_on_enter_debug_state(arm11);
730 if (retval != ERROR_OK)
731 return retval;
732
733 target_call_event_callbacks(target,
734 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
735 }
736 }
737 else
738 {
739 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
740 {
741 LOG_DEBUG("enter TARGET_RUNNING");
742 target->state = TARGET_RUNNING;
743 target->debug_reason = DBG_REASON_NOTHALTED;
744 }
745 }
746
747 return ERROR_OK;
748 }
749 /* architecture specific status reply */
750 int arm11_arch_state(struct target_s *target)
751 {
752 arm11_common_t * arm11 = target->arch_info;
753
754 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
755 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
756 R(CPSR),
757 R(PC));
758
759 return ERROR_OK;
760 }
761
762 /* target request support */
763 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
764 {
765 FNC_INFO_NOTIMPLEMENTED;
766
767 return ERROR_OK;
768 }
769
770 /* target execution control */
771 int arm11_halt(struct target_s *target)
772 {
773 FNC_INFO;
774
775 arm11_common_t * arm11 = target->arch_info;
776
777 LOG_DEBUG("target->state: %s",
778 target_state_name(target));
779
780 if (target->state == TARGET_UNKNOWN)
781 {
782 arm11->simulate_reset_on_next_halt = true;
783 }
784
785 if (target->state == TARGET_HALTED)
786 {
787 LOG_DEBUG("target was already halted");
788 return ERROR_OK;
789 }
790
791 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
792
793 CHECK_RETVAL(jtag_execute_queue());
794
795 uint32_t dscr;
796
797 int i = 0;
798 while (1)
799 {
800 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
801
802 if (dscr & ARM11_DSCR_CORE_HALTED)
803 break;
804
805
806 long long then = 0;
807 if (i == 1000)
808 {
809 then = timeval_ms();
810 }
811 if (i >= 1000)
812 {
813 if ((timeval_ms()-then) > 1000)
814 {
815 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
816 return ERROR_FAIL;
817 }
818 }
819 i++;
820 }
821
822 arm11_on_enter_debug_state(arm11);
823
824 enum target_state old_state = target->state;
825
826 target->state = TARGET_HALTED;
827 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
828
829 CHECK_RETVAL(
830 target_call_event_callbacks(target,
831 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
832
833 return ERROR_OK;
834 }
835
836 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
837 {
838 FNC_INFO;
839
840 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
841 // current, address, handle_breakpoints, debug_execution);
842
843 arm11_common_t * arm11 = target->arch_info;
844
845 LOG_DEBUG("target->state: %s",
846 target_state_name(target));
847
848
849 if (target->state != TARGET_HALTED)
850 {
851 LOG_ERROR("Target not halted");
852 return ERROR_TARGET_NOT_HALTED;
853 }
854
855 if (!current)
856 R(PC) = address;
857
858 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
859
860 /* clear breakpoints/watchpoints and VCR*/
861 arm11_sc7_clear_vbw(arm11);
862
863 /* Set up breakpoints */
864 if (!debug_execution)
865 {
866 /* check if one matches PC and step over it if necessary */
867
868 breakpoint_t * bp;
869
870 for (bp = target->breakpoints; bp; bp = bp->next)
871 {
872 if (bp->address == R(PC))
873 {
874 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
875 arm11_step(target, 1, 0, 0);
876 break;
877 }
878 }
879
880 /* set all breakpoints */
881
882 size_t brp_num = 0;
883
884 for (bp = target->breakpoints; bp; bp = bp->next)
885 {
886 arm11_sc7_action_t brp[2];
887
888 brp[0].write = 1;
889 brp[0].address = ARM11_SC7_BVR0 + brp_num;
890 brp[0].value = bp->address;
891 brp[1].write = 1;
892 brp[1].address = ARM11_SC7_BCR0 + brp_num;
893 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
894
895 arm11_sc7_run(arm11, brp, asizeof(brp));
896
897 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
898
899 brp_num++;
900 }
901
902 arm11_sc7_set_vcr(arm11, arm11_vcr);
903 }
904
905 arm11_leave_debug_state(arm11);
906
907 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
908
909 CHECK_RETVAL(jtag_execute_queue());
910
911 int i = 0;
912 while (1)
913 {
914 uint32_t dscr;
915
916 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
917
918 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
919
920 if (dscr & ARM11_DSCR_CORE_RESTARTED)
921 break;
922
923
924 long long then = 0;
925 if (i == 1000)
926 {
927 then = timeval_ms();
928 }
929 if (i >= 1000)
930 {
931 if ((timeval_ms()-then) > 1000)
932 {
933 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
934 return ERROR_FAIL;
935 }
936 }
937 i++;
938 }
939
940 if (!debug_execution)
941 {
942 target->state = TARGET_RUNNING;
943 target->debug_reason = DBG_REASON_NOTHALTED;
944
945 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
946 }
947 else
948 {
949 target->state = TARGET_DEBUG_RUNNING;
950 target->debug_reason = DBG_REASON_NOTHALTED;
951
952 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
953 }
954
955 return ERROR_OK;
956 }
957
958
959 static int armv4_5_to_arm11(int reg)
960 {
961 if (reg < 16)
962 return reg;
963 switch (reg)
964 {
965 case ARMV4_5_CPSR:
966 return ARM11_RC_CPSR;
967 case 16:
968 /* FIX!!! handle thumb better! */
969 return ARM11_RC_CPSR;
970 default:
971 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
972 exit(-1);
973 }
974 }
975
976
977 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
978 {
979 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
980
981 reg=armv4_5_to_arm11(reg);
982
983 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
984 }
985
986 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
987 {
988 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
989
990 reg=armv4_5_to_arm11(reg);
991
992 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
993 }
994
995 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
996 {
997 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
998
999 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
1000 }
1001
1002 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
1003 {
1004 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1005
1006 /* FIX!!!! we should implement thumb for arm11 */
1007 return ARMV4_5_STATE_ARM;
1008 }
1009
1010 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
1011 {
1012 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1013
1014 /* FIX!!!! we should implement thumb for arm11 */
1015 LOG_ERROR("Not implemetned!");
1016 }
1017
1018
1019 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1020 {
1021 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1022
1023 /* FIX!!!! we should implement something that returns the current mode here!!! */
1024 return ARMV4_5_MODE_USR;
1025 }
1026
1027 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1028 {
1029 struct arm_sim_interface sim;
1030
1031 sim.user_data=target->arch_info;
1032 sim.get_reg=&arm11_sim_get_reg;
1033 sim.set_reg=&arm11_sim_set_reg;
1034 sim.get_reg_mode=&arm11_sim_get_reg;
1035 sim.set_reg_mode=&arm11_sim_set_reg;
1036 sim.get_cpsr=&arm11_sim_get_cpsr;
1037 sim.get_mode=&arm11_sim_get_mode;
1038 sim.get_state=&arm11_sim_get_state;
1039 sim.set_state=&arm11_sim_set_state;
1040
1041 return arm_simulate_step_core(target, dry_run_pc, &sim);
1042
1043 }
1044
1045 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1046 {
1047 FNC_INFO;
1048
1049 LOG_DEBUG("target->state: %s",
1050 target_state_name(target));
1051
1052 if (target->state != TARGET_HALTED)
1053 {
1054 LOG_WARNING("target was not halted");
1055 return ERROR_TARGET_NOT_HALTED;
1056 }
1057
1058 arm11_common_t * arm11 = target->arch_info;
1059
1060 if (!current)
1061 R(PC) = address;
1062
1063 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1064
1065
1066 /** \todo TODO: Thumb not supported here */
1067
1068 uint32_t next_instruction;
1069
1070 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1071
1072 /* skip over BKPT */
1073 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1074 {
1075 R(PC) += 4;
1076 arm11->reg_list[ARM11_RC_PC].valid = 1;
1077 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1078 LOG_DEBUG("Skipping BKPT");
1079 }
1080 /* skip over Wait for interrupt / Standby */
1081 /* mcr 15, 0, r?, cr7, cr0, {4} */
1082 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1083 {
1084 R(PC) += 4;
1085 arm11->reg_list[ARM11_RC_PC].valid = 1;
1086 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1087 LOG_DEBUG("Skipping WFI");
1088 }
1089 /* ignore B to self */
1090 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1091 {
1092 LOG_DEBUG("Not stepping jump to self");
1093 }
1094 else
1095 {
1096 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1097 * with this. */
1098
1099 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1100 * the VCR might be something worth looking into. */
1101
1102
1103 /* Set up breakpoint for stepping */
1104
1105 arm11_sc7_action_t brp[2];
1106
1107 brp[0].write = 1;
1108 brp[0].address = ARM11_SC7_BVR0;
1109 brp[1].write = 1;
1110 brp[1].address = ARM11_SC7_BCR0;
1111
1112 if (arm11_config_hardware_step)
1113 {
1114 /* hardware single stepping be used if possible or is it better to
1115 * always use the same code path? Hardware single stepping is not supported
1116 * on all hardware
1117 */
1118 brp[0].value = R(PC);
1119 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1120 } else
1121 {
1122 /* sets a breakpoint on the next PC(calculated by simulation),
1123 */
1124 uint32_t next_pc;
1125 int retval;
1126 retval = arm11_simulate_step(target, &next_pc);
1127 if (retval != ERROR_OK)
1128 return retval;
1129
1130 brp[0].value = next_pc;
1131 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1132 }
1133
1134 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1135
1136 /* resume */
1137
1138
1139 if (arm11_config_step_irq_enable)
1140 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1141 else
1142 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1143
1144
1145 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1146
1147 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1148
1149 CHECK_RETVAL(jtag_execute_queue());
1150
1151 /* wait for halt */
1152 int i = 0;
1153 while (1)
1154 {
1155 uint32_t dscr;
1156
1157 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1158
1159 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1160
1161 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1162 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1163 break;
1164
1165 long long then = 0;
1166 if (i == 1000)
1167 {
1168 then = timeval_ms();
1169 }
1170 if (i >= 1000)
1171 {
1172 if ((timeval_ms()-then) > 1000)
1173 {
1174 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1175 return ERROR_FAIL;
1176 }
1177 }
1178 i++;
1179 }
1180
1181 /* clear breakpoint */
1182 arm11_sc7_clear_vbw(arm11);
1183
1184 /* save state */
1185 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1186
1187 /* restore default state */
1188 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1189
1190 }
1191
1192 // target->state = TARGET_HALTED;
1193 target->debug_reason = DBG_REASON_SINGLESTEP;
1194
1195 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1196
1197 return ERROR_OK;
1198 }
1199
1200 int arm11_assert_reset(target_t *target)
1201 {
1202 FNC_INFO;
1203
1204 /* FIX! we really should assert srst here, but
1205 * how do we reset the target into the halted state?
1206 *
1207 * Also arm11 behaves "funny" when srst is asserted
1208 * (as of writing the rules are not understood).
1209 */
1210 if (target->reset_halt)
1211 {
1212 CHECK_RETVAL(target_halt(target));
1213 }
1214
1215 return ERROR_OK;
1216 }
1217
1218 int arm11_deassert_reset(target_t *target)
1219 {
1220 return ERROR_OK;
1221 }
1222
1223 int arm11_soft_reset_halt(struct target_s *target)
1224 {
1225 FNC_INFO_NOTIMPLEMENTED;
1226
1227 return ERROR_OK;
1228 }
1229
1230 /* target register access for gdb */
1231 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1232 {
1233 FNC_INFO;
1234
1235 arm11_common_t * arm11 = target->arch_info;
1236
1237 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1238 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1239
1240 for (size_t i = 16; i < 24; i++)
1241 {
1242 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1243 }
1244
1245 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1246
1247 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1248 {
1249 if (arm11_reg_defs[i].gdb_num == -1)
1250 continue;
1251
1252 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1253 }
1254
1255 return ERROR_OK;
1256 }
1257
1258 /* target memory access
1259 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1260 * count: number of items of <size>
1261 *
1262 * arm11_config_memrw_no_increment - in the future we may want to be able
1263 * to read/write a range of data to a "port". a "port" is an action on
1264 * read memory address for some peripheral.
1265 */
1266 int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1267 bool arm11_config_memrw_no_increment)
1268 {
1269 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1270 int retval;
1271
1272 FNC_INFO;
1273
1274 if (target->state != TARGET_HALTED)
1275 {
1276 LOG_WARNING("target was not halted");
1277 return ERROR_TARGET_NOT_HALTED;
1278 }
1279
1280 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1281
1282 arm11_common_t * arm11 = target->arch_info;
1283
1284 retval = arm11_run_instr_data_prepare(arm11);
1285 if (retval != ERROR_OK)
1286 return retval;
1287
1288 /* MRC p14,0,r0,c0,c5,0 */
1289 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1290 if (retval != ERROR_OK)
1291 return retval;
1292
1293 switch (size)
1294 {
1295 case 1:
1296 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1297 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1298
1299 for (size_t i = 0; i < count; i++)
1300 {
1301 /* ldrb r1, [r0], #1 */
1302 /* ldrb r1, [r0] */
1303 arm11_run_instr_no_data1(arm11,
1304 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1305
1306 uint32_t res;
1307 /* MCR p14,0,R1,c0,c5,0 */
1308 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1309
1310 *buffer++ = res;
1311 }
1312
1313 break;
1314
1315 case 2:
1316 {
1317 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1318
1319 for (size_t i = 0; i < count; i++)
1320 {
1321 /* ldrh r1, [r0], #2 */
1322 arm11_run_instr_no_data1(arm11,
1323 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1324
1325 uint32_t res;
1326
1327 /* MCR p14,0,R1,c0,c5,0 */
1328 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1329
1330 uint16_t svalue = res;
1331 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1332 }
1333
1334 break;
1335 }
1336
1337 case 4:
1338 {
1339 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1340 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1341 uint32_t *words = (uint32_t *)buffer;
1342
1343 /* LDC p14,c5,[R0],#4 */
1344 /* LDC p14,c5,[R0] */
1345 arm11_run_instr_data_from_core(arm11, instr, words, count);
1346 break;
1347 }
1348 }
1349
1350 return arm11_run_instr_data_finish(arm11);
1351 }
1352
1353 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1354 {
1355 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1356 }
1357
1358 /*
1359 * arm11_config_memrw_no_increment - in the future we may want to be able
1360 * to read/write a range of data to a "port". a "port" is an action on
1361 * read memory address for some peripheral.
1362 */
1363 int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1364 bool arm11_config_memrw_no_increment)
1365 {
1366 int retval;
1367 FNC_INFO;
1368
1369 if (target->state != TARGET_HALTED)
1370 {
1371 LOG_WARNING("target was not halted");
1372 return ERROR_TARGET_NOT_HALTED;
1373 }
1374
1375 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1376
1377 arm11_common_t * arm11 = target->arch_info;
1378
1379 retval = arm11_run_instr_data_prepare(arm11);
1380 if (retval != ERROR_OK)
1381 return retval;
1382
1383 /* MRC p14,0,r0,c0,c5,0 */
1384 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1385 if (retval != ERROR_OK)
1386 return retval;
1387
1388 /* burst writes are not used for single words as those may well be
1389 * reset init script writes.
1390 *
1391 * The other advantage is that as burst writes are default, we'll
1392 * now exercise both burst and non-burst code paths with the
1393 * default settings, increasing code coverage.
1394 */
1395 bool burst = arm11_config_memwrite_burst && (count > 1);
1396
1397 switch (size)
1398 {
1399 case 1:
1400 {
1401 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1402
1403 for (size_t i = 0; i < count; i++)
1404 {
1405 /* MRC p14,0,r1,c0,c5,0 */
1406 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1407 if (retval != ERROR_OK)
1408 return retval;
1409
1410 /* strb r1, [r0], #1 */
1411 /* strb r1, [r0] */
1412 retval = arm11_run_instr_no_data1(arm11,
1413 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1414 if (retval != ERROR_OK)
1415 return retval;
1416 }
1417
1418 break;
1419 }
1420
1421 case 2:
1422 {
1423 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1424
1425 for (size_t i = 0; i < count; i++)
1426 {
1427 uint16_t value;
1428 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1429
1430 /* MRC p14,0,r1,c0,c5,0 */
1431 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1432 if (retval != ERROR_OK)
1433 return retval;
1434
1435 /* strh r1, [r0], #2 */
1436 /* strh r1, [r0] */
1437 retval = arm11_run_instr_no_data1(arm11,
1438 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1439 if (retval != ERROR_OK)
1440 return retval;
1441 }
1442
1443 break;
1444 }
1445
1446 case 4: {
1447 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1448
1449 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1450 uint32_t *words = (uint32_t*)buffer;
1451
1452 if (!burst)
1453 {
1454 /* STC p14,c5,[R0],#4 */
1455 /* STC p14,c5,[R0]*/
1456 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1457 if (retval != ERROR_OK)
1458 return retval;
1459 }
1460 else
1461 {
1462 /* STC p14,c5,[R0],#4 */
1463 /* STC p14,c5,[R0]*/
1464 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1465 if (retval != ERROR_OK)
1466 return retval;
1467 }
1468
1469 break;
1470 }
1471 }
1472
1473 /* r0 verification */
1474 if (!arm11_config_memrw_no_increment)
1475 {
1476 uint32_t r0;
1477
1478 /* MCR p14,0,R0,c0,c5,0 */
1479 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1480 if (retval != ERROR_OK)
1481 return retval;
1482
1483 if (address + size * count != r0)
1484 {
1485 LOG_ERROR("Data transfer failed. Expected end "
1486 "address 0x%08x, got 0x%08x",
1487 (unsigned) (address + size * count),
1488 (unsigned) r0);
1489
1490 if (burst)
1491 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1492
1493 if (arm11_config_memwrite_error_fatal)
1494 return ERROR_FAIL;
1495 }
1496 }
1497
1498 return arm11_run_instr_data_finish(arm11);
1499 }
1500
1501 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1502 {
1503 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1504 }
1505
1506 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1507 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1508 {
1509 FNC_INFO;
1510
1511 if (target->state != TARGET_HALTED)
1512 {
1513 LOG_WARNING("target was not halted");
1514 return ERROR_TARGET_NOT_HALTED;
1515 }
1516
1517 return arm11_write_memory(target, address, 4, count, buffer);
1518 }
1519
1520 /* here we have nothing target specific to contribute, so we fail and then the
1521 * fallback code will read data from the target and calculate the CRC on the
1522 * host.
1523 */
1524 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1525 {
1526 return ERROR_FAIL;
1527 }
1528
1529 /* target break-/watchpoint control
1530 * rw: 0 = write, 1 = read, 2 = access
1531 */
1532 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1533 {
1534 FNC_INFO;
1535
1536 arm11_common_t * arm11 = target->arch_info;
1537
1538 #if 0
1539 if (breakpoint->type == BKPT_SOFT)
1540 {
1541 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1542 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1543 }
1544 #endif
1545
1546 if (!arm11->free_brps)
1547 {
1548 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1549 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1550 }
1551
1552 if (breakpoint->length != 4)
1553 {
1554 LOG_DEBUG("only breakpoints of four bytes length supported");
1555 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1556 }
1557
1558 arm11->free_brps--;
1559
1560 return ERROR_OK;
1561 }
1562
1563 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1564 {
1565 FNC_INFO;
1566
1567 arm11_common_t * arm11 = target->arch_info;
1568
1569 arm11->free_brps++;
1570
1571 return ERROR_OK;
1572 }
1573
1574 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1575 {
1576 FNC_INFO_NOTIMPLEMENTED;
1577
1578 return ERROR_OK;
1579 }
1580
1581 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1582 {
1583 FNC_INFO_NOTIMPLEMENTED;
1584
1585 return ERROR_OK;
1586 }
1587
1588 // HACKHACKHACK - FIXME mode/state
1589 /* target algorithm support */
1590 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1591 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1592 int timeout_ms, void *arch_info)
1593 {
1594 arm11_common_t *arm11 = target->arch_info;
1595 // enum armv4_5_state core_state = arm11->core_state;
1596 // enum armv4_5_mode core_mode = arm11->core_mode;
1597 uint32_t context[16];
1598 uint32_t cpsr;
1599 int exit_breakpoint_size = 0;
1600 int retval = ERROR_OK;
1601 LOG_DEBUG("Running algorithm");
1602
1603
1604 if (target->state != TARGET_HALTED)
1605 {
1606 LOG_WARNING("target not halted");
1607 return ERROR_TARGET_NOT_HALTED;
1608 }
1609
1610 // FIXME
1611 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1612 // return ERROR_FAIL;
1613
1614 // Save regs
1615 for (size_t i = 0; i < 16; i++)
1616 {
1617 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1618 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1619 }
1620
1621 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1622 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1623
1624 for (int i = 0; i < num_mem_params; i++)
1625 {
1626 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1627 }
1628
1629 // Set register parameters
1630 for (int i = 0; i < num_reg_params; i++)
1631 {
1632 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1633 if (!reg)
1634 {
1635 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1636 exit(-1);
1637 }
1638
1639 if (reg->size != reg_params[i].size)
1640 {
1641 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1642 exit(-1);
1643 }
1644 arm11_set_reg(reg,reg_params[i].value);
1645 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1646 }
1647
1648 exit_breakpoint_size = 4;
1649
1650 /* arm11->core_state = arm11_algorithm_info->core_state;
1651 if (arm11->core_state == ARMV4_5_STATE_ARM)
1652 exit_breakpoint_size = 4;
1653 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1654 exit_breakpoint_size = 2;
1655 else
1656 {
1657 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1658 exit(-1);
1659 }
1660 */
1661
1662
1663 /* arm11 at this point only supports ARM not THUMB mode
1664 however if this test needs to be reactivated the current state can be read back
1665 from CPSR */
1666 #if 0
1667 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1668 {
1669 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1670 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1671 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1672 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1673 }
1674 #endif
1675
1676 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1677 {
1678 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1679 retval = ERROR_TARGET_FAILURE;
1680 goto restore;
1681 }
1682
1683 // no debug, otherwise breakpoint is not set
1684 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1685
1686 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1687
1688 if (target->state != TARGET_HALTED)
1689 {
1690 CHECK_RETVAL(target_halt(target));
1691
1692 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1693
1694 retval = ERROR_TARGET_TIMEOUT;
1695
1696 goto del_breakpoint;
1697 }
1698
1699 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1700 {
1701 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1702 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1703 retval = ERROR_TARGET_TIMEOUT;
1704 goto del_breakpoint;
1705 }
1706
1707 for (int i = 0; i < num_mem_params; i++)
1708 {
1709 if (mem_params[i].direction != PARAM_OUT)
1710 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1711 }
1712
1713 for (int i = 0; i < num_reg_params; i++)
1714 {
1715 if (reg_params[i].direction != PARAM_OUT)
1716 {
1717 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1718 if (!reg)
1719 {
1720 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1721 exit(-1);
1722 }
1723
1724 if (reg->size != reg_params[i].size)
1725 {
1726 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1727 exit(-1);
1728 }
1729
1730 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1731 }
1732 }
1733
1734 del_breakpoint:
1735 breakpoint_remove(target, exit_point);
1736
1737 restore:
1738 // Restore context
1739 for (size_t i = 0; i < 16; i++)
1740 {
1741 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1742 arm11->reg_list[i].name, context[i]);
1743 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1744 }
1745 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1746 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1747
1748 // arm11->core_state = core_state;
1749 // arm11->core_mode = core_mode;
1750
1751 return retval;
1752 }
1753
1754 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1755 {
1756 FNC_INFO;
1757
1758 NEW(arm11_common_t, arm11, 1);
1759
1760 arm11->target = target;
1761
1762 if (target->tap == NULL)
1763 return ERROR_FAIL;
1764
1765 if (target->tap->ir_length != 5)
1766 {
1767 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1768 return ERROR_COMMAND_SYNTAX_ERROR;
1769 }
1770
1771 target->arch_info = arm11;
1772
1773 return ERROR_OK;
1774 }
1775
1776 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1777 {
1778 /* Initialize anything we can set up without talking to the target */
1779 return arm11_build_reg_cache(target);
1780 }
1781
1782 /* talk to the target and set things up */
1783 int arm11_examine(struct target_s *target)
1784 {
1785 int retval;
1786
1787 FNC_INFO;
1788
1789 arm11_common_t * arm11 = target->arch_info;
1790
1791 /* check IDCODE */
1792
1793 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1794
1795 scan_field_t idcode_field;
1796
1797 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1798
1799 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1800
1801 /* check DIDR */
1802
1803 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1804
1805 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1806
1807 scan_field_t chain0_fields[2];
1808
1809 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1810 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1811
1812 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1813
1814 CHECK_RETVAL(jtag_execute_queue());
1815
1816 switch (arm11->device_id & 0x0FFFF000)
1817 {
1818 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1819 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1820 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1821 default:
1822 {
1823 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1824 return ERROR_FAIL;
1825 }
1826 }
1827
1828 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1829
1830 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1831 arm11->debug_version != ARM11_DEBUG_V61)
1832 {
1833 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1834 return ERROR_FAIL;
1835 }
1836
1837 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1838 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1839
1840 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1841 arm11->free_brps = arm11->brp;
1842 arm11->free_wrps = arm11->wrp;
1843
1844 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1845 arm11->device_id,
1846 (int)(arm11->implementor),
1847 arm11->didr);
1848
1849 /* as a side-effect this reads DSCR and thus
1850 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1851 * as suggested by the spec.
1852 */
1853
1854 retval = arm11_check_init(arm11, NULL);
1855 if (retval != ERROR_OK)
1856 return retval;
1857
1858 target_set_examined(target);
1859
1860 return ERROR_OK;
1861 }
1862
1863 int arm11_quit(void)
1864 {
1865 FNC_INFO_NOTIMPLEMENTED;
1866
1867 return ERROR_OK;
1868 }
1869
1870 /** Load a register that is marked !valid in the register cache */
1871 int arm11_get_reg(reg_t *reg)
1872 {
1873 FNC_INFO;
1874
1875 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1876
1877 if (target->state != TARGET_HALTED)
1878 {
1879 LOG_WARNING("target was not halted");
1880 return ERROR_TARGET_NOT_HALTED;
1881 }
1882
1883 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1884
1885 #if 0
1886 arm11_common_t *arm11 = target->arch_info;
1887 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1888 #endif
1889
1890 return ERROR_OK;
1891 }
1892
1893 /** Change a value in the register cache */
1894 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1895 {
1896 FNC_INFO;
1897
1898 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1899 arm11_common_t *arm11 = target->arch_info;
1900 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1901
1902 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1903 reg->valid = 1;
1904 reg->dirty = 1;
1905
1906 return ERROR_OK;
1907 }
1908
1909 int arm11_build_reg_cache(target_t *target)
1910 {
1911 arm11_common_t *arm11 = target->arch_info;
1912
1913 NEW(reg_cache_t, cache, 1);
1914 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1915 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1916
1917 if (arm11_regs_arch_type == -1)
1918 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1919
1920 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1921 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1922
1923 arm11->reg_list = reg_list;
1924
1925 /* Build the process context cache */
1926 cache->name = "arm11 registers";
1927 cache->next = NULL;
1928 cache->reg_list = reg_list;
1929 cache->num_regs = ARM11_REGCACHE_COUNT;
1930
1931 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1932 (*cache_p) = cache;
1933
1934 arm11->core_cache = cache;
1935 // armv7m->process_context = cache;
1936
1937 size_t i;
1938
1939 /* Not very elegant assertion */
1940 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1941 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1942 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1943 {
1944 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1945 exit(-1);
1946 }
1947
1948 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1949 {
1950 reg_t * r = reg_list + i;
1951 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1952 arm11_reg_state_t * rs = arm11_reg_states + i;
1953
1954 r->name = rd->name;
1955 r->size = 32;
1956 r->value = (uint8_t *)(arm11->reg_values + i);
1957 r->dirty = 0;
1958 r->valid = 0;
1959 r->bitfield_desc = NULL;
1960 r->num_bitfields = 0;
1961 r->arch_type = arm11_regs_arch_type;
1962 r->arch_info = rs;
1963
1964 rs->def_index = i;
1965 rs->target = target;
1966 }
1967
1968 return ERROR_OK;
1969 }
1970
1971 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1972 {
1973 if (argc == 0)
1974 {
1975 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1976 return ERROR_OK;
1977 }
1978
1979 if (argc != 1)
1980 return ERROR_COMMAND_SYNTAX_ERROR;
1981
1982 switch (args[0][0])
1983 {
1984 case '0': /* 0 */
1985 case 'f': /* false */
1986 case 'F':
1987 case 'd': /* disable */
1988 case 'D':
1989 *var = false;
1990 break;
1991
1992 case '1': /* 1 */
1993 case 't': /* true */
1994 case 'T':
1995 case 'e': /* enable */
1996 case 'E':
1997 *var = true;
1998 break;
1999 }
2000
2001 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2002
2003 return ERROR_OK;
2004 }
2005
2006 #define BOOL_WRAPPER(name, print_name) \
2007 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
2008 { \
2009 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
2010 }
2011
2012 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2013 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2014 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2015 BOOL_WRAPPER(hardware_step, "hardware single step")
2016
2017 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2018 {
2019 if (argc == 1)
2020 {
2021 arm11_vcr = strtoul(args[0], NULL, 0);
2022 }
2023 else if (argc != 0)
2024 {
2025 return ERROR_COMMAND_SYNTAX_ERROR;
2026 }
2027
2028 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2029 return ERROR_OK;
2030 }
2031
2032 const uint32_t arm11_coproc_instruction_limits[] =
2033 {
2034 15, /* coprocessor */
2035 7, /* opcode 1 */
2036 15, /* CRn */
2037 15, /* CRm */
2038 7, /* opcode 2 */
2039 0xFFFFFFFF, /* value */
2040 };
2041
2042 arm11_common_t * arm11_find_target(const char * arg)
2043 {
2044 jtag_tap_t * tap;
2045 target_t * t;
2046
2047 tap = jtag_tap_by_string(arg);
2048
2049 if (!tap)
2050 return 0;
2051
2052 for (t = all_targets; t; t = t->next)
2053 {
2054 if (t->tap != tap)
2055 continue;
2056
2057 /* if (t->type == arm11_target) */
2058 if (0 == strcmp(target_get_name(t), "arm11"))
2059 return t->arch_info;
2060 }
2061
2062 return 0;
2063 }
2064
2065 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2066 {
2067 int retval;
2068
2069 if (argc != (read ? 6 : 7))
2070 {
2071 LOG_ERROR("Invalid number of arguments.");
2072 return ERROR_COMMAND_SYNTAX_ERROR;
2073 }
2074
2075 arm11_common_t * arm11 = arm11_find_target(args[0]);
2076
2077 if (!arm11)
2078 {
2079 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2080 return ERROR_COMMAND_SYNTAX_ERROR;
2081 }
2082
2083 if (arm11->target->state != TARGET_HALTED)
2084 {
2085 LOG_WARNING("target was not halted");
2086 return ERROR_TARGET_NOT_HALTED;
2087 }
2088
2089 uint32_t values[6];
2090
2091 for (size_t i = 0; i < (read ? 5 : 6); i++)
2092 {
2093 values[i] = strtoul(args[i + 1], NULL, 0);
2094
2095 if (values[i] > arm11_coproc_instruction_limits[i])
2096 {
2097 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2098 (long)(i + 2),
2099 arm11_coproc_instruction_limits[i]);
2100 return ERROR_COMMAND_SYNTAX_ERROR;
2101 }
2102 }
2103
2104 uint32_t instr = 0xEE000010 |
2105 (values[0] << 8) |
2106 (values[1] << 21) |
2107 (values[2] << 16) |
2108 (values[3] << 0) |
2109 (values[4] << 5);
2110
2111 if (read)
2112 instr |= 0x00100000;
2113
2114 retval = arm11_run_instr_data_prepare(arm11);
2115 if (retval != ERROR_OK)
2116 return retval;
2117
2118 if (read)
2119 {
2120 uint32_t result;
2121 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2122 if (retval != ERROR_OK)
2123 return retval;
2124
2125 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2126 (int)(values[0]),
2127 (int)(values[1]),
2128 (int)(values[2]),
2129 (int)(values[3]),
2130 (int)(values[4]), result, result);
2131 }
2132 else
2133 {
2134 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2135 if (retval != ERROR_OK)
2136 return retval;
2137
2138 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2139 (int)(values[0]), (int)(values[1]),
2140 values[5],
2141 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2142 }
2143
2144 return arm11_run_instr_data_finish(arm11);
2145 }
2146
2147 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2148 {
2149 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2150 }
2151
2152 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2153 {
2154 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2155 }
2156
2157 int arm11_register_commands(struct command_context_s *cmd_ctx)
2158 {
2159 FNC_INFO;
2160
2161 command_t *top_cmd, *mw_cmd;
2162
2163 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2164 NULL, COMMAND_ANY, NULL);
2165
2166 /* "hardware_step" is only here to check if the default
2167 * simulate + breakpoint implementation is broken.
2168 * TEMPORARY! NOT DOCUMENTED!
2169 */
2170 register_command(cmd_ctx, top_cmd, "hardware_step",
2171 arm11_handle_bool_hardware_step, COMMAND_ANY,
2172 "DEBUG ONLY - Hardware single stepping"
2173 " (default: disabled)");
2174
2175 register_command(cmd_ctx, top_cmd, "mcr",
2176 arm11_handle_mcr, COMMAND_ANY,
2177 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2178
2179 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2180 NULL, COMMAND_ANY, NULL);
2181 register_command(cmd_ctx, mw_cmd, "burst",
2182 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2183 "Enable/Disable non-standard but fast burst mode"
2184 " (default: enabled)");
2185 register_command(cmd_ctx, mw_cmd, "error_fatal",
2186 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2187 "Terminate program if transfer error was found"
2188 " (default: enabled)");
2189
2190 register_command(cmd_ctx, top_cmd, "mrc",
2191 arm11_handle_mrc, COMMAND_ANY,
2192 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2193 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2194 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2195 "Enable interrupts while stepping"
2196 " (default: disabled)");
2197 register_command(cmd_ctx, top_cmd, "vcr",
2198 arm11_handle_vcr, COMMAND_ANY,
2199 "Control (Interrupt) Vector Catch Register");
2200
2201 return ERROR_OK;
2202 }
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