src/target/quark_x10xx.c

   1 /*
   2  * Copyright(c) 2013 Intel Corporation.
   3  *
   4  * Adrian Burns (adrian.burns@intel.com)
   5  * Thomas Faust (thomas.faust@intel.com)
   6  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
   7  * Julien Carreno (julien.carreno@intel.com)
   8  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22  *
  23  * Contact Information:
  24  * Intel Corporation
  25  */
  26
  27 /*
  28  * @file
  29  * Debugger for Intel Quark SoC X1000
  30  * Intel Quark X10xx is the first product in the Quark family of SoCs.
  31  * It is an IA-32 (Pentium x86 ISA) compatible SoC. The core CPU in the
  32  * X10xx is codenamed Lakemont. Lakemont version 1 (LMT1) is used in X10xx.
  33  * The CPU TAP (Lakemont TAP) is used for software debug and the CLTAP is
  34  * used for SoC level operations.
  35  * Useful docs are here: https://communities.intel.com/community/makers/documentation
  36  * Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
  37  * Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
  38  * Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
  39  *
  40  * This file implements any Quark SoC specific features such as resetbreak (TODO)
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include <helper/log.h>
  48
  49 #include "target.h"
  50 #include "target_type.h"
  51 #include "lakemont.h"
  52 #include "x86_32_common.h"
  53
  54 int quark_x10xx_target_create(struct target *t, Jim_Interp *interp)
  55 {
  56         struct x86_32_common *x86_32 = calloc(1, sizeof(struct x86_32_common));
  57         if (x86_32 == NULL) {
  58                 LOG_ERROR("%s out of memory", __func__);
  59                 return ERROR_FAIL;
  60         }
  61         x86_32_common_init_arch_info(t, x86_32);
  62         lakemont_init_arch_info(t, x86_32);
  63         return ERROR_OK;
  64 }
  65
  66 int quark_x10xx_init_target(struct command_context *cmd_ctx, struct target *t)
  67 {
  68         return lakemont_init_target(cmd_ctx, t);
  69 }
  70
  71 struct target_type quark_x10xx_target = {
  72         .name = "quark_x10xx",
  73         /* Quark X1000 SoC */
  74         .target_create = quark_x10xx_target_create,
  75         .init_target = quark_x10xx_init_target,
  76         /* lakemont probemode specific code */
  77         .poll = lakemont_poll,
  78         .arch_state = lakemont_arch_state,
  79         .halt = lakemont_halt,
  80         .resume = lakemont_resume,
  81         .step = lakemont_step,
  82         .assert_reset = lakemont_reset_assert,
  83         .deassert_reset = lakemont_reset_deassert,
  84         /* common x86 code */
  85         .commands = x86_32_command_handlers,
  86         .get_gdb_reg_list = x86_32_get_gdb_reg_list,
  87         .read_memory = x86_32_common_read_memory,
  88         .write_memory = x86_32_common_write_memory,
  89         .add_breakpoint = x86_32_common_add_breakpoint,
  90         .remove_breakpoint = x86_32_common_remove_breakpoint,
  91         .add_watchpoint = x86_32_common_add_watchpoint,
  92         .remove_watchpoint = x86_32_common_remove_watchpoint,
  93         .virt2phys = x86_32_common_virt2phys,
  94         .read_phys_memory = x86_32_common_read_phys_mem,
  95         .write_phys_memory = x86_32_common_write_phys_mem,
  96         .mmu = x86_32_common_mmu,
  97 };