1 # -------------------------------------------------------------------------
2 # KaRo TX25 CPU Module on a StarterkitV base board
3 # http://www.karo-electronics.com/tx25.html
4 # -------------------------------------------------------------------------
7 source [find tcl/target/imx25.cfg]
9 #-------------------------------------------------------------------------
11 #-------------------------------------------------------------------------
13 nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
16 $_TARGETNAME configure -event gdb-attach { reset init }
17 $_TARGETNAME configure -event reset-init { tx25_init }
22 #-------------------------------------------------------------------------
23 # AIPS setup - Only setup MPROTx registers. The PACR default values are good.
24 # Set all MPROTx to be non-bufferable, trusted for R/W,
25 # not forced to user-mode.
26 #-------------------------------------------------------------------------
28 mww 0x43f00000 0x77777777
29 mww 0x43f00004 0x77777777
30 mww 0x53f00000 0x77777777
31 mww 0x53f00004 0x77777777
35 #-------------------------------------------------------------------------
36 # MAX (Multi-Layer AHB Crossbar Switch) setup
37 # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
38 #-------------------------------------------------------------------------
40 mww 0x43f04000 0x00043210
41 mww 0x43f04100 0x00043210
42 mww 0x43f04200 0x00043210
43 mww 0x43f04300 0x00043210
44 mww 0x43f04400 0x00043210
46 # SGPCR - always park on last master
53 # MGPCR - restore default values
60 # Configure M3IF registers
61 # M3IF Control Register (M3IFCTL) for MX25
62 # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
63 # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
64 # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
65 # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
66 # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
67 # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
68 # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
69 # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
72 mww 0xb8003000 0x00000001
74 #-------------------------------------------------------------------------
76 #-------------------------------------------------------------------------
78 # Set the Clock CTL (HRM p. 355)
79 mww 0x53F80008 0x20034000
81 # Setup Clock Gating CTL 0-2 (HRM p. 357)
82 mww 0x53F8000C 0x1fffffff
83 mww 0x53F80010 0xffffffff
84 mww 0x53F80014 0x000fdfff
86 #-------------------------------------------------------------------------
87 # SDRAM initialization
88 #-------------------------------------------------------------------------
91 mww 0x43FAC454 0x00000800
93 # reset (set up ESDMISC)
94 mww 0xB8001010 0x00000002
96 # Setup for SDRAM Bank 0
97 #-------------------------------------------------------------------------
100 mww 0xB8001004 0x00095728
102 # CTL SMode = Precharge command
103 mww 0xB8001000 0x92116480
104 mww 0x80000400 0x00000000
106 # CTL SMode = Auto Refresh command
107 mww 0xB8001000 0xA2116480
117 # CTL SMode = Load Mode Register command
118 mww 0xB8001000 0xB2116480
122 mww 0xB8001000 0x82116480
124 # Setup for SDRAM Bank 1
125 #-------------------------------------------------------------------------
128 mww 0xB800100C 0x00095728
130 # CTL SMode = Precharge command
131 mww 0xB8001008 0x92116480
132 mww 0x90000400 0x00000000
134 # CTL SMode = Auto Refresh command
135 mww 0xB8001008 0xA2116480
136 mww 0x90000000 0x00000000
137 mww 0x90000000 0x00000000
138 mww 0x90000000 0x00000000
139 mww 0x90000000 0x00000000
140 mww 0x90000000 0x00000000
141 mww 0x90000000 0x00000000
142 mww 0x90000000 0x00000000
143 mww 0x90000000 0x00000000
145 # CTL SMode = Load Mode Register command
146 mww 0xB8001008 0xB2116480
150 mww 0xB8001008 0x82116480
153 #-------------------------------------------------------------------------
155 mww 0x43FAC02C 0x00000015
156 mww 0x53FD0000 0x01000000
157 mww 0x53FD0004 0x00000080