target/arm_adi_v5: fix sync CSW cache on apreg write
[openocd.git] / tcl / board / stm32l0discovery.cfg
blobaabbf8170a25d4b91bba82408b4ec3ff7ce8ed23
1 # This is an STM32L053 discovery board with a single STM32L053 chip.
2 # http://www.st.com/web/en/catalog/tools/PF260319
4 source [find interface/stlink.cfg]
6 transport select hla_swd
8 set WORKAREASIZE 0x2000
9 source [find target/stm32l0.cfg]
11 reset_config srst_only