target/arm_adi_v5: fix sync CSW cache on apreg write
[openocd.git] / tcl / board / st_nucleo_f103rb.cfg
blobe1990dcf4795641bea9360ef028cbb404c3d71ac
1 # This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.
2 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875
4 source [find interface/stlink.cfg]
6 transport select hla_swd
8 source [find target/stm32f1x.cfg]
10 reset_config srst_only