3 source [find interface/ftdi/sheevaplug.cfg]
4 source [find target/feroceon.cfg]
8 $_TARGETNAME configure \
9 -work-area-phys 0x10000000 \
10 -work-area-size 65536 \
13 arm7_9 dcc_downloads enable
15 # this assumes the hardware default peripherals location before u-Boot moves it
16 set _FLASHNAME $_CHIPNAME.flash
17 nand device $_FLASHNAME orion 0 0xd8000000
19 proc sheevaplug_init { } {
21 # We need to assert DBGRQ while holding nSRST down.
22 # However DBGACK will be set only when nSRST is released.
23 # Furthermore, the JTAG interface doesn't respond at all when
24 # the CPU is in the WFI (wait for interrupts) state, so it is
25 # possible that initial tap examination failed. So let's
26 # re-examine the target again here when nSRST is asserted which
27 # should then succeed.
29 feroceon.cpu arp_examine
34 arm mcr 15 0 0 1 0 0x00052078
36 mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
37 mww 0xD0001404 0x39543000 ;# Dunit Control Low Register
38 mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
39 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
40 mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
41 mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
42 mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
43 mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
44 mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
45 mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
46 mww 0xD0001428 0x00085520 ;# Dunit Control High Register
47 mww 0xD000147c 0x00008552 ;# Dunit Control High Register
48 mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
49 mww 0xD0001508 0x10000000 ;# CS1n Base Register
50 mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
51 mww 0xD0001514 0x00000000 ;# CS2n Size Register
52 mww 0xD000151C 0x00000000 ;# CS3n Size Register
53 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
54 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
55 mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
56 mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
57 mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
58 mww 0xD0020204 0x00000000 ;# "
59 mww 0xD0020204 0x00000000 ;# "
60 mww 0xD0020204 0x00000000 ;# "
61 mww 0xD0020204 0x00000000 ;# "
62 mww 0xD0020204 0x00000000 ;# "
63 mww 0xD0020204 0x00000000 ;# "
64 mww 0xD0020204 0x00000000 ;# "
65 mww 0xD0020204 0x00000000 ;# "
66 mww 0xD0020204 0x00000000 ;# "
67 mww 0xD0020204 0x00000000 ;# "
68 mww 0xD0020204 0x00000000 ;# "
69 mww 0xD0020204 0x00000000 ;# "
70 mww 0xD0020204 0x00000000 ;# "
71 mww 0xD0020204 0x00000000 ;# "
72 mww 0xD0020204 0x00000000 ;# "
73 mww 0xD0020204 0x00000000 ;# "
74 mww 0xD0020204 0x00000000 ;# "
75 mww 0xD0020204 0x00000000 ;# "
76 mww 0xD0020204 0x00000000 ;# "
77 mww 0xD0020204 0x00000000 ;# "
78 mww 0xD0020204 0x00000000 ;# "
79 mww 0xD0020204 0x00000000 ;# "
80 mww 0xD0020204 0x00000000 ;# "
81 mww 0xD0020204 0x00000000 ;# "
82 mww 0xD0020204 0x00000000 ;# "
83 mww 0xD0020204 0x00000000 ;# "
84 mww 0xD0020204 0x00000000 ;# "
85 mww 0xD0020204 0x00000000 ;# "
86 mww 0xD0020204 0x00000000 ;# "
87 mww 0xD0020204 0x00000000 ;# "
88 mww 0xD0020204 0x00000000 ;# "
89 mww 0xD0020204 0x00000000 ;# "
90 mww 0xD0020204 0x00000000 ;# "
91 mww 0xD0020204 0x00000000 ;# "
92 mww 0xD0020204 0x00000000 ;# "
93 mww 0xD0020204 0x00000000 ;# "
95 mww 0xD0010000 0x01111111 ;# MPP 0 to 7
96 mww 0xD0010004 0x11113322 ;# MPP 8 to 15
97 mww 0xD0010008 0x00001111 ;# MPP 16 to 23
99 mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
100 mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
101 mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
105 proc sheevaplug_reflash_uboot { } {
107 # reflash the u-Boot binary and reboot into it
110 nand erase 0 0x0 0xa0000
111 nand write 0 uboot.bin 0 oob_softecc_kw
116 proc sheevaplug_reflash_uboot_env { } {
118 # reflash the u-Boot environment variables area
121 nand erase 0 0xa0000 0x40000
122 nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw
127 proc sheevaplug_load_uboot { } {
129 # load u-Boot into RAM and execute it
132 verify_image uboot.elf