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Change return value on error.
[openocd.git] / src / flash / nand / lpc3180.c
blob9d8cbae176bd379891b0aa58f2ed6d0b8b8e2398
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 *
5 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
6 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "lpc3180.h"
29 #include <target/target.h>
30
31
32 static int lpc3180_reset(struct nand_device *nand);
33 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
34 static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
35
36
37 #define ECC_OFFS 0x120
38 #define SPARE_OFFS 0x140
39 #define DATA_OFFS 0x200
40
41
42 /* nand device lpc3180 <target#> <oscillator_frequency>
43 */
44 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
45 {
46 if (CMD_ARGC < 3)
47 {
48 return ERROR_COMMAND_SYNTAX_ERROR;
49 }
50
51 uint32_t osc_freq;
52 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
53
54 struct lpc3180_nand_controller *lpc3180_info;
55 lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
56 nand->controller_priv = lpc3180_info;
57
58 lpc3180_info->osc_freq = osc_freq;
59
60 if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
61 {
62 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
63 }
64 lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
65 lpc3180_info->sw_write_protection = 0;
66 lpc3180_info->sw_wp_lower_bound = 0x0;
67 lpc3180_info->sw_wp_upper_bound = 0x0;
68
69 return ERROR_OK;
70 }
71
72 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
73 {
74 int bypass = (pll_ctrl & 0x8000) >> 15;
75 int direct = (pll_ctrl & 0x4000) >> 14;
76 int feedback = (pll_ctrl & 0x2000) >> 13;
77 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
78 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
79 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
80 int lock = (pll_ctrl & 0x1);
81
82 if (!lock)
83 LOG_WARNING("PLL is not locked");
84
85 if (!bypass && direct) /* direct mode */
86 return (m * fclkin) / n;
87
88 if (bypass && !direct) /* bypass mode */
89 return fclkin / (2 * p);
90
91 if (bypass & direct) /* direct bypass mode */
92 return fclkin;
93
94 if (feedback) /* integer mode */
95 return m * (fclkin / n);
96 else /* non-integer mode */
97 return (m / (2 * p)) * (fclkin / n);
98 }
99
100 static float lpc3180_cycle_time(struct nand_device *nand)
101 {
102 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
103 struct target *target = nand->target;
104 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
105 int sysclk;
106 int hclk;
107 int hclk_pll;
108 float cycle;
109
110 /* calculate timings */
111
112 /* determine current SYSCLK (13'MHz or main oscillator) */
113 target_read_u32(target, 0x40004050, &sysclk_ctrl);
114
115 if ((sysclk_ctrl & 1) == 0)
116 sysclk = lpc3180_info->osc_freq;
117 else
118 sysclk = 13000;
119
120 /* determine selected HCLK source */
121 target_read_u32(target, 0x40004044, &pwr_ctrl);
122
123 if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
124 {
125 hclk = sysclk;
126 }
127 else
128 {
129 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
130 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
131
132 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
133
134 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
135 {
136 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
137 }
138 else /* HCLK uses HCLK_PLL */
139 {
140 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
141 }
142 }
143
144 LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
145
146 cycle = (1.0 / hclk) * 1000000.0;
147
148 return cycle;
149 }
150
151 static int lpc3180_init(struct nand_device *nand)
152 {
153 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
154 struct target *target = nand->target;
155 int bus_width = nand->bus_width ? : 8;
156 int address_cycles = nand->address_cycles ? : 3;
157 int page_size = nand->page_size ? : 512;
158
159 if (target->state != TARGET_HALTED)
160 {
161 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
162 return ERROR_NAND_OPERATION_FAILED;
163 }
164
165 /* sanitize arguments */
166 if ((bus_width != 8) && (bus_width != 16))
167 {
168 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
169 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
170 }
171
172 /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
173 * would support 16 bit, too, so we just warn about this for now
174 */
175 if (bus_width == 16)
176 {
177 LOG_WARNING("LPC3180 only supports 8 bit bus width");
178 }
179
180 /* inform calling code about selected bus width */
181 nand->bus_width = bus_width;
182
183 if ((address_cycles != 3) && (address_cycles != 4))
184 {
185 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
186 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
187 }
188
189 if ((page_size != 512) && (page_size != 2048))
190 {
191 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
192 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
193 }
194
195 /* select MLC controller if none is currently selected */
196 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
197 {
198 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
199 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
200 }
201
202 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
203 {
204 uint32_t mlc_icr_value = 0x0;
205 float cycle;
206 int twp, twh, trp, treh, trhz, trbwb, tcea;
207
208 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
209 target_write_u32(target, 0x400040c8, 0x22);
210
211 /* MLC_CEH = 0x0 (Force nCE assert) */
212 target_write_u32(target, 0x200b804c, 0x0);
213
214 /* MLC_LOCK = 0xa25e (unlock protected registers) */
215 target_write_u32(target, 0x200b8044, 0xa25e);
216
217 /* MLC_ICR = configuration */
218 if (lpc3180_info->sw_write_protection)
219 mlc_icr_value |= 0x8;
220 if (page_size == 2048)
221 mlc_icr_value |= 0x4;
222 if (address_cycles == 4)
223 mlc_icr_value |= 0x2;
224 if (bus_width == 16)
225 mlc_icr_value |= 0x1;
226 target_write_u32(target, 0x200b8030, mlc_icr_value);
227
228 /* calculate NAND controller timings */
229 cycle = lpc3180_cycle_time(nand);
230
231 twp = ((40 / cycle) + 1);
232 twh = ((20 / cycle) + 1);
233 trp = ((30 / cycle) + 1);
234 treh = ((15 / cycle) + 1);
235 trhz = ((30 / cycle) + 1);
236 trbwb = ((100 / cycle) + 1);
237 tcea = ((45 / cycle) + 1);
238
239 /* MLC_LOCK = 0xa25e (unlock protected registers) */
240 target_write_u32(target, 0x200b8044, 0xa25e);
241
242 /* MLC_TIME_REG */
243 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
244 ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
245 ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
246
247 lpc3180_reset(nand);
248 }
249 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
250 {
251 float cycle;
252 int r_setup, r_hold, r_width, r_rdy;
253 int w_setup, w_hold, w_width, w_rdy;
254
255 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
256 target_write_u32(target, 0x400040c8, 0x05);
257
258 /* after reset set other registers of SLC so reset calling is here at the begining*/
259 lpc3180_reset(nand);
260
261 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
262 target_write_u32(target, 0x20020014, 0x3e | (bus_width == 16) ? 1 : 0);
263
264 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
265 target_write_u32(target, 0x20020020, 0x03);
266
267 /* DMA configuration */
268 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
269 target_write_u32(target, 0x400040e8, 0x01);
270 /* DMACConfig = DMA enabled*/
271 target_write_u32(target, 0x31000030, 0x01);
272
273
274 /* calculate NAND controller timings */
275 cycle = lpc3180_cycle_time(nand);
276
277 r_setup = w_setup = 0;
278 r_hold = w_hold = 10 / cycle;
279 r_width = 30 / cycle;
280 w_width = 40 / cycle;
281 r_rdy = w_rdy = 100 / cycle;
282
283 /* SLC_TAC: SLC timing arcs register */
284 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
285 ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
286 ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
287
288 }
289
290 return ERROR_OK;
291 }
292
293 static int lpc3180_reset(struct nand_device *nand)
294 {
295 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
296 struct target *target = nand->target;
297
298 if (target->state != TARGET_HALTED)
299 {
300 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
301 return ERROR_NAND_OPERATION_FAILED;
302 }
303
304 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
305 {
306 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
307 return ERROR_NAND_OPERATION_FAILED;
308 }
309 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
310 {
311 /* MLC_CMD = 0xff (reset controller and NAND device) */
312 target_write_u32(target, 0x200b8000, 0xff);
313
314 if (!lpc3180_controller_ready(nand, 100))
315 {
316 LOG_ERROR("LPC3180 NAND controller timed out after reset");
317 return ERROR_NAND_OPERATION_TIMEOUT;
318 }
319 }
320 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
321 {
322 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
323 target_write_u32(target, 0x20020010, 0x6);
324
325 if (!lpc3180_controller_ready(nand, 100))
326 {
327 LOG_ERROR("LPC3180 NAND controller timed out after reset");
328 return ERROR_NAND_OPERATION_TIMEOUT;
329 }
330 }
331
332 return ERROR_OK;
333 }
334
335 static int lpc3180_command(struct nand_device *nand, uint8_t command)
336 {
337 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
338 struct target *target = nand->target;
339
340 if (target->state != TARGET_HALTED)
341 {
342 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
343 return ERROR_NAND_OPERATION_FAILED;
344 }
345
346 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
347 {
348 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
349 return ERROR_NAND_OPERATION_FAILED;
350 }
351 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
352 {
353 /* MLC_CMD = command */
354 target_write_u32(target, 0x200b8000, command);
355 }
356 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
357 {
358 /* SLC_CMD = command */
359 target_write_u32(target, 0x20020008, command);
360 }
361
362 return ERROR_OK;
363 }
364
365 static int lpc3180_address(struct nand_device *nand, uint8_t address)
366 {
367 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
368 struct target *target = nand->target;
369
370 if (target->state != TARGET_HALTED)
371 {
372 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
373 return ERROR_NAND_OPERATION_FAILED;
374 }
375
376 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
377 {
378 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
379 return ERROR_NAND_OPERATION_FAILED;
380 }
381 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
382 {
383 /* MLC_ADDR = address */
384 target_write_u32(target, 0x200b8004, address);
385 }
386 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
387 {
388 /* SLC_ADDR = address */
389 target_write_u32(target, 0x20020004, address);
390 }
391
392 return ERROR_OK;
393 }
394
395 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
396 {
397 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
398 struct target *target = nand->target;
399
400 if (target->state != TARGET_HALTED)
401 {
402 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
403 return ERROR_NAND_OPERATION_FAILED;
404 }
405
406 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
407 {
408 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
409 return ERROR_NAND_OPERATION_FAILED;
410 }
411 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
412 {
413 /* MLC_DATA = data */
414 target_write_u32(target, 0x200b0000, data);
415 }
416 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
417 {
418 /* SLC_DATA = data */
419 target_write_u32(target, 0x20020000, data);
420 }
421
422 return ERROR_OK;
423 }
424
425 static int lpc3180_read_data(struct nand_device *nand, void *data)
426 {
427 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
428 struct target *target = nand->target;
429
430 if (target->state != TARGET_HALTED)
431 {
432 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
433 return ERROR_NAND_OPERATION_FAILED;
434 }
435
436 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
437 {
438 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
439 return ERROR_NAND_OPERATION_FAILED;
440 }
441 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
442 {
443 /* data = MLC_DATA, use sized access */
444 if (nand->bus_width == 8)
445 {
446 uint8_t *data8 = data;
447 target_read_u8(target, 0x200b0000, data8);
448 }
449 else if (nand->bus_width == 16)
450 {
451 uint16_t *data16 = data;
452 target_read_u16(target, 0x200b0000, data16);
453 }
454 else
455 {
456 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
457 return ERROR_NAND_OPERATION_FAILED;
458 }
459 }
460 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
461 {
462 uint32_t data32;
463
464 /* data = SLC_DATA, must use 32-bit access */
465 target_read_u32(target, 0x20020000, &data32);
466
467 if (nand->bus_width == 8)
468 {
469 uint8_t *data8 = data;
470 *data8 = data32 & 0xff;
471 }
472 else if (nand->bus_width == 16)
473 {
474 uint16_t *data16 = data;
475 *data16 = data32 & 0xffff;
476 }
477 else
478 {
479 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
480 return ERROR_NAND_OPERATION_FAILED;
481 }
482 }
483
484 return ERROR_OK;
485 }
486
487 static int lpc3180_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
488 {
489 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
490 struct target *target = nand->target;
491 int retval;
492 uint8_t status;
493 uint8_t *page_buffer;
494
495 if (target->state != TARGET_HALTED)
496 {
497 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
498 return ERROR_NAND_OPERATION_FAILED;
499 }
500
501 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
502 {
503 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
504 return ERROR_NAND_OPERATION_FAILED;
505 }
506 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
507 {
508 uint8_t *oob_buffer;
509 int quarter, num_quarters;
510
511 if (!data && oob)
512 {
513 LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
514 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
515 }
516
517 if (oob && (oob_size > 24))
518 {
519 LOG_ERROR("LPC3180 MLC controller can't write more "
520 "than 6 bytes for each quarter's OOB data");
521 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
522 }
523
524 if (data_size > (uint32_t)nand->page_size)
525 {
526 LOG_ERROR("data size exceeds page size");
527 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
528 }
529
530 /* MLC_CMD = sequential input */
531 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
532
533 page_buffer = malloc(512);
534 oob_buffer = malloc(6);
535
536 if (nand->page_size == 512)
537 {
538 /* MLC_ADDR = 0x0 (one column cycle) */
539 target_write_u32(target, 0x200b8004, 0x0);
540
541 /* MLC_ADDR = row */
542 target_write_u32(target, 0x200b8004, page & 0xff);
543 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
544
545 if (nand->address_cycles == 4)
546 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
547 }
548 else
549 {
550 /* MLC_ADDR = 0x0 (two column cycles) */
551 target_write_u32(target, 0x200b8004, 0x0);
552 target_write_u32(target, 0x200b8004, 0x0);
553
554 /* MLC_ADDR = row */
555 target_write_u32(target, 0x200b8004, page & 0xff);
556 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
557 }
558
559 /* when using the MLC controller, we have to treat a large page device
560 * as being made out of four quarters, each the size of a small page device
561 */
562 num_quarters = (nand->page_size == 2048) ? 4 : 1;
563
564 for (quarter = 0; quarter < num_quarters; quarter++)
565 {
566 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
567 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
568
569 memset(page_buffer, 0xff, 512);
570 if (data)
571 {
572 memcpy(page_buffer, data, thisrun_data_size);
573 data_size -= thisrun_data_size;
574 data += thisrun_data_size;
575 }
576
577 memset(oob_buffer, 0xff, 6);
578 if (oob)
579 {
580 memcpy(oob_buffer, oob, thisrun_oob_size);
581 oob_size -= thisrun_oob_size;
582 oob += thisrun_oob_size;
583 }
584
585 /* write MLC_ECC_ENC_REG to start encode cycle */
586 target_write_u32(target, 0x200b8008, 0x0);
587
588 target_write_memory(target, 0x200a8000,
589 4, 128, page_buffer);
590 target_write_memory(target, 0x200a8000,
591 1, 6, oob_buffer);
592
593 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
594 target_write_u32(target, 0x200b8010, 0x0);
595
596 if (!lpc3180_controller_ready(nand, 1000))
597 {
598 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
599 return ERROR_NAND_OPERATION_FAILED;
600 }
601 }
602
603 /* MLC_CMD = auto program command */
604 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
605
606 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
607 {
608 LOG_ERROR("couldn't read status");
609 return ERROR_NAND_OPERATION_FAILED;
610 }
611
612 if (status & NAND_STATUS_FAIL)
613 {
614 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
615 return ERROR_NAND_OPERATION_FAILED;
616 }
617
618 free(page_buffer);
619 free(oob_buffer);
620 }
621 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
622 {
623
624 /**********************************************************************
625 * Write both SLC NAND flash page main area and spare area.
626 * Small page -
627 * ------------------------------------------
628 * | 512 bytes main | 16 bytes spare |
629 * ------------------------------------------
630 * Large page -
631 * ------------------------------------------
632 * | 2048 bytes main | 64 bytes spare |
633 * ------------------------------------------
634 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
635 * data is written to the 3rd word of the spare area. The ECC
636 * generated for the 2nd 256-byte data is written to the 4th word
637 * of the spare area. The ECC generated for the 3rd 256-byte data is
638 * written to the 7th word of the spare area. The ECC generated
639 * for the 4th 256-byte data is written to the 8th word of the
640 * spare area and so on.
641 *
642 **********************************************************************/
643
644 int i=0,target_mem_base;
645 uint8_t *ecc_flash_buffer;
646 struct working_area *pworking_area;
647
648
649 if(lpc3180_info->is_bulk){
650
651 if (!data && oob){
652 /*if oob only mode is active original method is used as SLC controller hangs during DMA interworking. Anyway the code supports the oob only mode below. */
653 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
654 }
655 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
656 if (ERROR_OK != retval)
657 return retval;
658
659 /* allocate a working area */
660 if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
661 LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
662 return ERROR_FLASH_OPERATION_FAILED;
663 }
664 if (target->working_area_phys%4){
665 LOG_ERROR("Reserve the physical target working area at word boundary");
666 return ERROR_FLASH_OPERATION_FAILED;
667 }
668 if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
669 {
670 LOG_ERROR("no working area specified, can't read LPC internal flash");
671 return ERROR_FLASH_OPERATION_FAILED;
672 }
673 target_mem_base = target->working_area_phys;
674
675
676 if (nand->page_size == 2048)
677 {
678 page_buffer = malloc(2048);
679 }
680 else
681 {
682 page_buffer = malloc(512);
683 }
684
685 ecc_flash_buffer = malloc(64);
686
687 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA write to SLC, WIDTH = bus_width) */
688 target_write_u32(target, 0x20020014, 0x3c);
689
690 if( data && !oob){
691 /* set DMA LLI-s in target memory and in DMA*/
692 for(i=0;i<nand->page_size/0x100;i++){
693
694 int tmp;
695 /* -------LLI for 256 byte block---------*/
696 /* DMACC0SrcAddr = SRAM */
697 target_write_u32(target,target_mem_base+0+i*32,target_mem_base+DATA_OFFS+i*256 );
698 if(i==0) target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
699 /* DMACCxDestAddr = SLC_DMA_DATA */
700 target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
701 if(i==0) target_write_u32(target,0x31000104,0x20020038 );
702 /* DMACCxLLI = next element */
703 tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
704 target_write_u32(target,target_mem_base+8+i*32, tmp );
705 if(i==0) target_write_u32(target,0x31000108, tmp );
706 /* DMACCxControl = TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
707 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
708 Destination increment = 0, Terminal count interrupt enable bit = 0*/
709 target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
710 if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
711
712 /* -------LLI for 3 byte ECC---------*/
713 /* DMACC0SrcAddr = SLC_ECC*/
714 target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
715 /* DMACCxDestAddr = SRAM */
716 target_write_u32(target,target_mem_base+20+i*32,target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4 );
717 /* DMACCxLLI = next element */
718 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
719 target_write_u32(target,target_mem_base+24+i*32, tmp );
720 /* DMACCxControl = TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
721 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
722 Destination increment = 1, Terminal count interrupt enable bit = 0*/
723 target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
724 }
725 }
726 else if (data && oob){
727 /* -------LLI for 512 or 2048 bytes page---------*/
728 /* DMACC0SrcAddr = SRAM */
729 target_write_u32(target,target_mem_base,target_mem_base+DATA_OFFS );
730 target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
731 /* DMACCxDestAddr = SLC_DMA_DATA */
732 target_write_u32(target,target_mem_base+4,0x20020038 );
733 target_write_u32(target,0x31000104,0x20020038 );
734 /* DMACCxLLI = next element */
735 target_write_u32(target,target_mem_base+8, (target_mem_base+32)&0xfffffffc );
736 target_write_u32(target,0x31000108, (target_mem_base+32)&0xfffffffc );
737 /* DMACCxControl = TransferSize =512 or 128, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
738 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
739 Destination increment = 0, Terminal count interrupt enable bit = 0*/
740 target_write_u32(target,target_mem_base+12,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
741 target_write_u32(target,0x3100010c,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
742 i = 1;
743 }
744 else if (!data && oob){
745 i = 0;
746 }
747
748 /* -------LLI for spare area---------*/
749 /* DMACC0SrcAddr = SRAM*/
750 target_write_u32(target,target_mem_base+0+i*32,target_mem_base+SPARE_OFFS );
751 if(i==0) target_write_u32(target,0x31000100,target_mem_base+SPARE_OFFS );
752 /* DMACCxDestAddr = SLC_DMA_DATA */
753 target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
754 if(i==0) target_write_u32(target,0x31000104,0x20020038 );
755 /* DMACCxLLI = next element = NULL */
756 target_write_u32(target,target_mem_base+8+i*32, 0 );
757 if(i==0) target_write_u32(target,0x31000108,0 );
758 /* DMACCxControl = TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
759 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
760 Destination increment = 0, Terminal count interrupt enable bit = 0*/
761 target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
762 if(i==0) target_write_u32(target,0x3100010c,(nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31 );
763
764
765
766 memset(ecc_flash_buffer, 0xff, 64);
767 if( oob ){
768 memcpy(ecc_flash_buffer,oob, oob_size);
769 }
770 target_write_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
771
772 if (data){
773 memset(page_buffer, 0xff, nand->page_size == 2048?2048:512);
774 memcpy(page_buffer,data, data_size);
775 target_write_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
776 }
777
778 free(page_buffer);
779 free(ecc_flash_buffer);
780
781 /* Enable DMA after channel set up !
782 LLI only works when DMA is the flow controller!
783 */
784 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
785 target_write_u32(target,0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
786
787
788
789 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
790 target_write_u32(target, 0x20020010, 0x3);
791
792 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
793 target_write_u32(target, 0x20020028, 2);
794
795 /* SLC_TC */
796 if (!data && oob)
797 target_write_u32(target, 0x20020030, (nand->page_size==2048?0x10:0x04));
798 else
799 target_write_u32(target, 0x20020030, (nand->page_size==2048?0x840:0x210));
800
801 nand_write_finish(nand);
802
803
804 if (!lpc3180_tc_ready(nand, 1000))
805 {
806 LOG_ERROR("timeout while waiting for completion of DMA");
807 return ERROR_NAND_OPERATION_FAILED;
808 }
809
810 target_free_working_area(target,pworking_area);
811
812 LOG_INFO("Page = 0x%" PRIx32 " was written.",page);
813
814 }
815 else
816 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
817 }
818
819
820 return ERROR_OK;
821 }
822
823 static int lpc3180_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
824 {
825 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
826 struct target *target = nand->target;
827 uint8_t *page_buffer;
828
829 if (target->state != TARGET_HALTED)
830 {
831 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
832 return ERROR_NAND_OPERATION_FAILED;
833 }
834
835 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
836 {
837 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
838 return ERROR_NAND_OPERATION_FAILED;
839 }
840 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
841 {
842 uint8_t *oob_buffer;
843 uint32_t page_bytes_done = 0;
844 uint32_t oob_bytes_done = 0;
845 uint32_t mlc_isr;
846
847 #if 0
848 if (oob && (oob_size > 6))
849 {
850 LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
851 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
852 }
853 #endif
854
855 if (data_size > (uint32_t)nand->page_size)
856 {
857 LOG_ERROR("data size exceeds page size");
858 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
859 }
860
861 if (nand->page_size == 2048)
862 {
863 page_buffer = malloc(2048);
864 oob_buffer = malloc(64);
865 }
866 else
867 {
868 page_buffer = malloc(512);
869 oob_buffer = malloc(16);
870 }
871
872 if (!data && oob)
873 {
874 /* MLC_CMD = Read OOB
875 * we can use the READOOB command on both small and large page devices,
876 * as the controller translates the 0x50 command to a 0x0 with appropriate
877 * positioning of the serial buffer read pointer
878 */
879 target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
880 }
881 else
882 {
883 /* MLC_CMD = Read0 */
884 target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
885 }
886
887 if (nand->page_size == 512)
888 {
889 /* small page device */
890 /* MLC_ADDR = 0x0 (one column cycle) */
891 target_write_u32(target, 0x200b8004, 0x0);
892
893 /* MLC_ADDR = row */
894 target_write_u32(target, 0x200b8004, page & 0xff);
895 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
896
897 if (nand->address_cycles == 4)
898 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
899 }
900 else
901 {
902 /* large page device */
903 /* MLC_ADDR = 0x0 (two column cycles) */
904 target_write_u32(target, 0x200b8004, 0x0);
905 target_write_u32(target, 0x200b8004, 0x0);
906
907 /* MLC_ADDR = row */
908 target_write_u32(target, 0x200b8004, page & 0xff);
909 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
910
911 /* MLC_CMD = Read Start */
912 target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
913 }
914
915 while (page_bytes_done < (uint32_t)nand->page_size)
916 {
917 /* MLC_ECC_AUTO_DEC_REG = dummy */
918 target_write_u32(target, 0x200b8014, 0xaa55aa55);
919
920 if (!lpc3180_controller_ready(nand, 1000))
921 {
922 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
923 return ERROR_NAND_OPERATION_FAILED;
924 }
925
926 target_read_u32(target, 0x200b8048, &mlc_isr);
927
928 if (mlc_isr & 0x8)
929 {
930 if (mlc_isr & 0x40)
931 {
932 LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr);
933 return ERROR_NAND_OPERATION_FAILED;
934 }
935
936 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr & 0x30) >> 4) + 1)));
937 }
938
939 if (data)
940 {
941 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
942 }
943
944 if (oob)
945 {
946 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
947 }
948
949 page_bytes_done += 512;
950 oob_bytes_done += 16;
951 }
952
953 if (data)
954 memcpy(data, page_buffer, data_size);
955
956 if (oob)
957 memcpy(oob, oob_buffer, oob_size);
958
959 free(page_buffer);
960 free(oob_buffer);
961 }
962 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
963 {
964
965 /**********************************************************************
966 * Read both SLC NAND flash page main area and spare area.
967 * Small page -
968 * ------------------------------------------
969 * | 512 bytes main | 16 bytes spare |
970 * ------------------------------------------
971 * Large page -
972 * ------------------------------------------
973 * | 2048 bytes main | 64 bytes spare |
974 * ------------------------------------------
975 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
976 * data is compared with the 3rd word of the spare area. The ECC
977 * generated for the 2nd 256-byte data is compared with the 4th word
978 * of the spare area. The ECC generated for the 3rd 256-byte data is
979 * compared with the 7th word of the spare area. The ECC generated
980 * for the 4th 256-byte data is compared with the 8th word of the
981 * spare area and so on.
982 *
983 **********************************************************************/
984
985 int retval,i,target_mem_base;
986 uint8_t *ecc_hw_buffer;
987 uint8_t *ecc_flash_buffer;
988 struct working_area *pworking_area;
989
990 if(lpc3180_info->is_bulk){
991
992 /* read always the data and also oob areas*/
993
994 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
995 if (ERROR_OK != retval)
996 return retval;
997
998 /* allocate a working area */
999 if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
1000 LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
1001 return ERROR_FLASH_OPERATION_FAILED;
1002 }
1003 if (target->working_area_phys%4){
1004 LOG_ERROR("Reserve the physical target working area at word boundary");
1005 return ERROR_FLASH_OPERATION_FAILED;
1006 }
1007 if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
1008 {
1009 LOG_ERROR("no working area specified, can't read LPC internal flash");
1010 return ERROR_FLASH_OPERATION_FAILED;
1011 }
1012 target_mem_base = target->working_area_phys;
1013
1014 if (nand->page_size == 2048)
1015 {
1016 page_buffer = malloc(2048);
1017 }
1018 else
1019 {
1020 page_buffer = malloc(512);
1021 }
1022
1023 ecc_hw_buffer = malloc(32);
1024 ecc_flash_buffer = malloc(64);
1025
1026 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
1027 target_write_u32(target, 0x20020014, 0x3e);
1028
1029 /* set DMA LLI-s in target memory and in DMA*/
1030 for(i=0;i<nand->page_size/0x100;i++){
1031 int tmp;
1032 /* -------LLI for 256 byte block---------*/
1033 /* DMACC0SrcAddr = SLC_DMA_DATA*/
1034 target_write_u32(target,target_mem_base+0+i*32,0x20020038 );
1035 if(i==0) target_write_u32(target,0x31000100,0x20020038 );
1036 /* DMACCxDestAddr = SRAM */
1037 target_write_u32(target,target_mem_base+4+i*32,target_mem_base+DATA_OFFS+i*256 );
1038 if(i==0) target_write_u32(target,0x31000104,target_mem_base+DATA_OFFS );
1039 /* DMACCxLLI = next element */
1040 tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
1041 target_write_u32(target,target_mem_base+8+i*32, tmp );
1042 if(i==0) target_write_u32(target,0x31000108, tmp );
1043 /* DMACCxControl = TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1044 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1045 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1046 target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1047 if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1048
1049 /* -------LLI for 3 byte ECC---------*/
1050 /* DMACC0SrcAddr = SLC_ECC*/
1051 target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
1052 /* DMACCxDestAddr = SRAM */
1053 target_write_u32(target,target_mem_base+20+i*32,target_mem_base+ECC_OFFS+i*4 );
1054 /* DMACCxLLI = next element */
1055 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
1056 target_write_u32(target,target_mem_base+24+i*32, tmp );
1057 /* DMACCxControl = TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
1058 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1059 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1060 target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1061
1062
1063 }
1064
1065 /* -------LLI for spare area---------*/
1066 /* DMACC0SrcAddr = SLC_DMA_DATA*/
1067 target_write_u32(target,target_mem_base+0+i*32,0x20020038 );
1068 /* DMACCxDestAddr = SRAM */
1069 target_write_u32(target,target_mem_base+4+i*32,target_mem_base+SPARE_OFFS );
1070 /* DMACCxLLI = next element = NULL */
1071 target_write_u32(target,target_mem_base+8+i*32, 0 );
1072 /* DMACCxControl = TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1073 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1074 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1075 target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1076
1077 /* Enable DMA after channel set up !
1078 LLI only works when DMA is the flow controller!
1079 */
1080 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1081 target_write_u32(target,0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1082
1083
1084 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1085 target_write_u32(target, 0x20020010, 0x3);
1086
1087 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1088 target_write_u32(target, 0x20020028, 2);
1089
1090 /* SLC_TC */
1091 target_write_u32(target, 0x20020030, (nand->page_size==2048?0x840:0x210));
1092
1093 if (!lpc3180_tc_ready(nand, 1000))
1094 {
1095 LOG_ERROR("timeout while waiting for completion of DMA");
1096 free(page_buffer);
1097 free(ecc_hw_buffer);
1098 free(ecc_flash_buffer);
1099 target_free_working_area(target,pworking_area);
1100 return ERROR_NAND_OPERATION_FAILED;
1101 }
1102
1103 if (data){
1104 target_read_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
1105 memcpy(data, page_buffer, data_size);
1106
1107 LOG_INFO("Page = 0x%" PRIx32 " was read.",page);
1108
1109 /* check hw generated ECC for each 256 bytes block with the saved ECC in flash spare area*/
1110 int idx = nand->page_size/0x200 ;
1111 target_read_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
1112 target_read_memory(target, target_mem_base+ECC_OFFS, 4, 8, ecc_hw_buffer);
1113 for(i=0;i<idx;i++){
1114 if( (0x00ffffff&*(uint32_t *)(void *)(ecc_hw_buffer+i*8)) != (0x00ffffff&*(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)) )
1115 LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+1,page);
1116 if( (0x00ffffff&*(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) != (0x00ffffff&*(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)) )
1117 LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+2,page);
1118 }
1119 }
1120
1121 if (oob)
1122 memcpy(oob, ecc_flash_buffer, oob_size);
1123
1124 free(page_buffer);
1125 free(ecc_hw_buffer);
1126 free(ecc_flash_buffer);
1127
1128 target_free_working_area(target,pworking_area);
1129
1130 }
1131 else
1132 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
1133 }
1134
1135 return ERROR_OK;
1136 }
1137
1138 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
1139 {
1140 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1141 struct target *target = nand->target;
1142
1143 if (target->state != TARGET_HALTED)
1144 {
1145 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1146 return ERROR_NAND_OPERATION_FAILED;
1147 }
1148
1149 LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
1150
1151 do
1152 {
1153 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1154 {
1155 uint8_t status;
1156
1157 /* Read MLC_ISR, wait for controller to become ready */
1158 target_read_u8(target, 0x200b8048, &status);
1159
1160 if (status & 2) {
1161 LOG_DEBUG("lpc3180_controller_ready count=%d",
1162 timeout);
1163 return 1;
1164 }
1165 }
1166 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1167 {
1168 uint32_t status;
1169
1170 /* Read SLC_STAT and check READY bit */
1171 target_read_u32(target, 0x20020018, &status);
1172
1173 if (status & 1) {
1174 LOG_DEBUG("lpc3180_controller_ready count=%d",
1175 timeout);
1176 return 1;
1177 }
1178 }
1179
1180 alive_sleep(1);
1181 } while (timeout-- > 0);
1182
1183 return 0;
1184 }
1185
1186 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
1187 {
1188 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1189 struct target *target = nand->target;
1190
1191 if (target->state != TARGET_HALTED)
1192 {
1193 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1194 return ERROR_NAND_OPERATION_FAILED;
1195 }
1196
1197 LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
1198
1199 do
1200 {
1201 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1202 {
1203 uint8_t status = 0x0;
1204
1205 /* Read MLC_ISR, wait for NAND flash device to become ready */
1206 target_read_u8(target, 0x200b8048, &status);
1207
1208 if (status & 1) {
1209 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1210 timeout);
1211 return 1;
1212 }
1213 }
1214 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1215 {
1216 uint32_t status = 0x0;
1217
1218 /* Read SLC_STAT and check READY bit */
1219 target_read_u32(target, 0x20020018, &status);
1220
1221 if (status & 1) {
1222 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1223 timeout);
1224 return 1;
1225 }
1226 }
1227
1228 alive_sleep(1);
1229 } while (timeout-- > 0);
1230
1231 return 0;
1232 }
1233
1234 static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
1235 {
1236 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1237 struct target *target = nand->target;
1238
1239 if (target->state != TARGET_HALTED)
1240 {
1241 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1242 return ERROR_NAND_OPERATION_FAILED;
1243 }
1244
1245 LOG_DEBUG("lpc3180_tc_ready count start=%d",
1246 timeout);
1247
1248 do
1249 {
1250 if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1251 {
1252 uint32_t status = 0x0;
1253 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1254 target_read_u32(target, 0x2002001c, &status);
1255
1256 if (status & 2){
1257 LOG_DEBUG("lpc3180_tc_ready count=%d",
1258 timeout);
1259 return 1;
1260 }
1261 }
1262
1263 alive_sleep(1);
1264 } while (timeout-- > 0);
1265
1266 return 0;
1267 }
1268
1269
1270 COMMAND_HANDLER(handle_lpc3180_select_command)
1271 {
1272 struct lpc3180_nand_controller *lpc3180_info = NULL;
1273 char *selected[] =
1274 {
1275 "no", "mlc", "slc"
1276 };
1277
1278 if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1279 {
1280 return ERROR_COMMAND_SYNTAX_ERROR;
1281 }
1282
1283 unsigned num;
1284 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1285 struct nand_device *nand = get_nand_device_by_num(num);
1286 if (!nand)
1287 {
1288 command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
1289 return ERROR_OK;
1290 }
1291
1292 lpc3180_info = nand->controller_priv;
1293
1294 if (CMD_ARGC >= 2)
1295 {
1296 if (strcmp(CMD_ARGV[1], "mlc") == 0)
1297 {
1298 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
1299 }
1300 else if (strcmp(CMD_ARGV[1], "slc") == 0)
1301 {
1302 lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
1303 if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0){
1304 lpc3180_info->is_bulk = 1;
1305 }
1306 else{
1307 lpc3180_info->is_bulk = 0;
1308 }
1309 }
1310 else
1311 {
1312 return ERROR_COMMAND_SYNTAX_ERROR;
1313 }
1314 }
1315
1316 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1317 command_print(CMD_CTX, "%s controller selected", selected[lpc3180_info->selected_controller]);
1318 else{
1319 command_print(CMD_CTX, lpc3180_info->is_bulk?"%s controller selected bulk mode is available":"%s controller selected bulk mode is not available", selected[lpc3180_info->selected_controller]);
1320 }
1321
1322
1323 return ERROR_OK;
1324 }
1325
1326 static const struct command_registration lpc3180_exec_command_handlers[] = {
1327 {
1328 .name = "select",
1329 .handler = handle_lpc3180_select_command,
1330 .mode = COMMAND_EXEC,
1331 .help = "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1332 .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
1333 },
1334 COMMAND_REGISTRATION_DONE
1335 };
1336 static const struct command_registration lpc3180_command_handler[] = {
1337 {
1338 .name = "lpc3180",
1339 .mode = COMMAND_ANY,
1340 .help = "LPC3180 NAND flash controller commands",
1341 .chain = lpc3180_exec_command_handlers,
1342 },
1343 COMMAND_REGISTRATION_DONE
1344 };
1345
1346 struct nand_flash_controller lpc3180_nand_controller = {
1347 .name = "lpc3180",
1348 .commands = lpc3180_command_handler,
1349 .nand_device_command = lpc3180_nand_device_command,
1350 .init = lpc3180_init,
1351 .reset = lpc3180_reset,
1352 .command = lpc3180_command,
1353 .address = lpc3180_address,
1354 .write_data = lpc3180_write_data,
1355 .read_data = lpc3180_read_data,
1356 .write_page = lpc3180_write_page,
1357 .read_page = lpc3180_read_page,
1358 .nand_ready = lpc3180_nand_ready,
1359 };
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