1 /***************************************************************************
2 * Copyright (C) 2005, 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef EMBEDDED_ICE_H
27 #define EMBEDDED_ICE_H
29 #include "arm7_9_common.h"
37 EICE_W0_ADDR_VALUE
= 4,
38 EICE_W0_ADDR_MASK
= 5,
39 EICE_W0_DATA_VALUE
= 6,
40 EICE_W0_DATA_MASK
= 7,
41 EICE_W0_CONTROL_VALUE
= 8,
42 EICE_W0_CONTROL_MASK
= 9,
43 EICE_W1_ADDR_VALUE
= 10,
44 EICE_W1_ADDR_MASK
= 11,
45 EICE_W1_DATA_VALUE
= 12,
46 EICE_W1_DATA_MASK
= 13,
47 EICE_W1_CONTROL_VALUE
= 14,
48 EICE_W1_CONTROL_MASK
= 15,
54 EICE_DBG_CONTROL_ICEDIS
= 5,
55 EICE_DBG_CONTROL_MONEN
= 4,
56 EICE_DBG_CONTROL_INTDIS
= 2,
57 EICE_DBG_CONTROL_DBGRQ
= 1,
58 EICE_DBG_CONTROL_DBGACK
= 0,
63 EICE_DBG_STATUS_IJBIT
= 5,
64 EICE_DBG_STATUS_ITBIT
= 4,
65 EICE_DBG_STATUS_SYSCOMP
= 3,
66 EICE_DBG_STATUS_IFEN
= 2,
67 EICE_DBG_STATUS_DBGRQ
= 1,
68 EICE_DBG_STATUS_DBGACK
= 0
73 EICE_W_CTRL_ENABLE
= 0x100,
74 EICE_W_CTRL_RANGE
= 0x80,
75 EICE_W_CTRL_CHAIN
= 0x40,
76 EICE_W_CTRL_EXTERN
= 0x20,
77 EICE_W_CTRL_nTRANS
= 0x10,
78 EICE_W_CTRL_nOPC
= 0x8,
79 EICE_W_CTRL_MAS
= 0x6,
80 EICE_W_CTRL_ITBIT
= 0x2,
86 EICE_COMM_CTRL_WBIT
= 1,
87 EICE_COMM_CTRL_RBIT
= 0
90 typedef struct embeddedice_reg_s
93 arm_jtag_t
*jtag_info
;
96 extern reg_cache_t
* embeddedice_build_reg_cache(target_t
*target
, arm7_9_common_t
*arm7_9
);
97 extern int embeddedice_setup(target_t
*target
);
98 extern int embeddedice_read_reg(reg_t
*reg
);
99 extern void embeddedice_write_reg(reg_t
*reg
, uint32_t value
);
100 extern int embeddedice_read_reg_w_check(reg_t
*reg
, uint8_t* check_value
, uint8_t* check_mask
);
101 extern void embeddedice_store_reg(reg_t
*reg
);
102 extern void embeddedice_set_reg(reg_t
*reg
, uint32_t value
);
103 extern int embeddedice_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
);
104 extern int embeddedice_receive(arm_jtag_t
*jtag_info
, uint32_t *data
, uint32_t size
);
105 extern int embeddedice_send(arm_jtag_t
*jtag_info
, uint32_t *data
, uint32_t size
);
106 extern int embeddedice_handshake(arm_jtag_t
*jtag_info
, int hsbit
, uint32_t timeout
);
108 /* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
109 * embeddedice_write_reg
111 static __inline__
void embeddedice_write_reg_inner( jtag_tap_t
*tap
, int reg_addr
, uint32_t value
)
113 static const int embeddedice_num_bits
[]={32,5,1};
120 jtag_add_dr_out( tap
,
122 embeddedice_num_bits
,
124 jtag_get_end_state());
127 void embeddedice_write_dcc(jtag_tap_t
*tap
, int reg_addr
, uint8_t *buffer
, int little
, int count
);
129 #endif /* EMBEDDED_ICE_H */