1 # script for stm32wbx family
4 # stm32wb devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32wbx
17 # Work-area is a space in RAM used for flash programming
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x10000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 set _CPUTAPID 0x6ba00477
32 # SWD IDCODE (single drop, arm)
33 set _CPUTAPID 0x6ba02477
37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
38 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
41 jtag newtap $_CHIPNAME bs -irlen 5
44 set _TARGETNAME $_CHIPNAME.cpu
45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
49 set _FLASHNAME $_CHIPNAME.flash
50 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
52 # Common knowledges tells JTAG speed should be <= F_CPU/6.
53 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
56 # Note that there is a pretty wide band where things are
57 # more or less stable, see http://openocd.zylin.com/#/c/3366/
60 adapter srst delay 100
65 reset_config srst_nogate
68 # if srst is not fitted use SYSRESETREQ to
69 # perform a soft reset
70 cortex_m reset_config sysresetreq
73 $_TARGETNAME configure -event reset-init {
74 # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
75 # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
76 # 2 WS compliant with VOS=Range1 and 24 MHz.
77 mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
78 mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
79 # Boost JTAG frequency
83 $_TARGETNAME configure -event reset-start {
84 # Reset clock is MSI (4 MHz)
88 $_TARGETNAME configure -event examine-end {
89 # Enable debug during low power modes (uses more power)
90 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
91 mmw 0xE0042004 0x00000007 0
93 # Stop watchdog counters during halt
94 # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
95 mmw 0xE004203C 0x00001800 0
98 $_TARGETNAME configure -event trace-config {
99 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
100 # change this value accordingly to configure trace pins
102 mmw 0xE0042004 0x00000020 0