src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include "time_support.h"
  29 #include "target_type.h"
  30
  31
  32 /*
  33  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  34  * ARM DDI 0229C especially Chapter 9 about debug support.
  35  */
  36
  37 #if 0
  38 #define _DEBUG_INSTRUCTION_EXECUTION_
  39 #endif
  40
  41 static int arm720t_scan_cp15(target_t *target,
  42                 uint32_t out, uint32_t *in, int instruction, int clock)
  43 {
  44         int retval;
  45         struct arm720t_common_s *arm720t = target_to_arm720(target);
  46         arm_jtag_t *jtag_info;
  47         scan_field_t fields[2];
  48         uint8_t out_buf[4];
  49         uint8_t instruction_buf = instruction;
  50
  51         jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
  52
  53         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  54
  55         jtag_set_end_state(TAP_DRPAUSE);
  56         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  57         {
  58                 return retval;
  59         }
  60         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
  61         {
  62                 return retval;
  63         }
  64
  65         fields[0].tap = jtag_info->tap;
  66         fields[0].num_bits = 1;
  67         fields[0].out_value = &instruction_buf;
  68         fields[0].in_value = NULL;
  69
  70         fields[1].tap = jtag_info->tap;
  71         fields[1].num_bits = 32;
  72         fields[1].out_value = out_buf;
  73         fields[1].in_value = NULL;
  74
  75         if (in)
  76         {
  77                 fields[1].in_value = (uint8_t *)in;
  78                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  79                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  80         } else
  81         {
  82                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  83         }
  84
  85         if (clock)
  86                 jtag_add_runtest(0, jtag_get_end_state());
  87
  88 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  89         if ((retval = jtag_execute_queue()) != ERROR_OK)
  90         {
  91                 return retval;
  92         }
  93
  94         if (in)
  95                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  96         else
  97                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  98 #else
  99                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 100 #endif
 101
 102         return ERROR_OK;
 103 }
 104
 105 static int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
 106 {
 107         /* fetch CP15 opcode */
 108         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 109         /* "DECODE" stage */
 110         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 111         /* "EXECUTE" stage (1) */
 112         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 113         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 114         /* "EXECUTE" stage (2) */
 115         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 116         /* "EXECUTE" stage (3), CDATA is read */
 117         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 118
 119         return ERROR_OK;
 120 }
 121
 122 static int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
 123 {
 124         /* fetch CP15 opcode */
 125         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 126         /* "DECODE" stage */
 127         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 128         /* "EXECUTE" stage (1) */
 129         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 130         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 131         /* "EXECUTE" stage (2) */
 132         arm720t_scan_cp15(target, value, NULL, 0, 1);
 133         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 134
 135         return ERROR_OK;
 136 }
 137
 138 static uint32_t arm720t_get_ttb(target_t *target)
 139 {
 140         uint32_t ttb = 0x0;
 141
 142         arm720t_read_cp15(target, 0xee120f10, &ttb);
 143         jtag_execute_queue();
 144
 145         ttb &= 0xffffc000;
 146
 147         return ttb;
 148 }
 149
 150 static void arm720t_disable_mmu_caches(target_t *target,
 151                 int mmu, int d_u_cache, int i_cache)
 152 {
 153         uint32_t cp15_control;
 154
 155         /* read cp15 control register */
 156         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 157         jtag_execute_queue();
 158
 159         if (mmu)
 160                 cp15_control &= ~0x1U;
 161
 162         if (d_u_cache || i_cache)
 163                 cp15_control &= ~0x4U;
 164
 165         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 166 }
 167
 168 static void arm720t_enable_mmu_caches(target_t *target,
 169                 int mmu, int d_u_cache, int i_cache)
 170 {
 171         uint32_t cp15_control;
 172
 173         /* read cp15 control register */
 174         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 175         jtag_execute_queue();
 176
 177         if (mmu)
 178                 cp15_control |= 0x1U;
 179
 180         if (d_u_cache || i_cache)
 181                 cp15_control |= 0x4U;
 182
 183         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 184 }
 185
 186 static void arm720t_post_debug_entry(target_t *target)
 187 {
 188         struct arm720t_common_s *arm720t = target_to_arm720(target);
 189
 190         /* examine cp15 control reg */
 191         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 192         jtag_execute_queue();
 193         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 194
 195         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 196         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 197         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 198
 199         /* save i/d fault status and address register */
 200         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 201         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 202         jtag_execute_queue();
 203 }
 204
 205 static void arm720t_pre_restore_context(target_t *target)
 206 {
 207         struct arm720t_common_s *arm720t = target_to_arm720(target);
 208
 209         /* restore i/d fault status and address register */
 210         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 211         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 212 }
 213
 214 static int arm720t_verify_pointer(struct command_context_s *cmd_ctx,
 215                 struct arm720t_common_s *arm720t)
 216 {
 217         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 218                 command_print(cmd_ctx, "target is not an ARM720");
 219                 return ERROR_TARGET_INVALID;
 220         }
 221         return ERROR_OK;
 222 }
 223
 224 static int arm720t_arch_state(struct target_s *target)
 225 {
 226         struct arm720t_common_s *arm720t = target_to_arm720(target);
 227         struct armv4_5_common_s *armv4_5;
 228
 229         static const char *state[] =
 230         {
 231                 "disabled", "enabled"
 232         };
 233
 234         armv4_5 = &arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common;
 235
 236         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 237                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 238                         "MMU: %s, Cache: %s",
 239                          armv4_5_state_strings[armv4_5->core_state],
 240                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 241                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 242                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 243                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 244                          state[arm720t->armv4_5_mmu.mmu_enabled],
 245                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 246
 247         return ERROR_OK;
 248 }
 249
 250 static int arm720t_read_memory(struct target_s *target,
 251                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 252 {
 253         int retval;
 254         struct arm720t_common_s *arm720t = target_to_arm720(target);
 255
 256         /* disable cache, but leave MMU enabled */
 257         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 258                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 259
 260         retval = arm7_9_read_memory(target, address, size, count, buffer);
 261
 262         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 263                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 264
 265         return retval;
 266 }
 267
 268 static int arm720t_read_phys_memory(struct target_s *target,
 269                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 270 {
 271         struct arm720t_common_s *arm720t = target_to_arm720(target);
 272
 273         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 274 }
 275
 276 static int arm720t_write_phys_memory(struct target_s *target,
 277                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 278 {
 279         struct arm720t_common_s *arm720t = target_to_arm720(target);
 280
 281         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 282 }
 283
 284 static int arm720t_soft_reset_halt(struct target_s *target)
 285 {
 286         int retval = ERROR_OK;
 287         struct arm720t_common_s *arm720t = target_to_arm720(target);
 288         reg_t *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
 289                         .eice_cache->reg_list[EICE_DBG_STAT];
 290         struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
 291                         .arm7_9_common.armv4_5_common;
 292
 293         if ((retval = target_halt(target)) != ERROR_OK)
 294         {
 295                 return retval;
 296         }
 297
 298         long long then = timeval_ms();
 299         int timeout;
 300         while (!(timeout = ((timeval_ms()-then) > 1000)))
 301         {
 302                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 303                 {
 304                         embeddedice_read_reg(dbg_stat);
 305                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 306                         {
 307                                 return retval;
 308                         }
 309                 } else
 310                 {
 311                         break;
 312                 }
 313                 if (debug_level >= 3)
 314                 {
 315                         alive_sleep(100);
 316                 } else
 317                 {
 318                         keep_alive();
 319                 }
 320         }
 321         if (timeout)
 322         {
 323                 LOG_ERROR("Failed to halt CPU after 1 sec");
 324                 return ERROR_TARGET_TIMEOUT;
 325         }
 326
 327         target->state = TARGET_HALTED;
 328
 329         /* SVC, ARM state, IRQ and FIQ disabled */
 330         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 331         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 332         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 333
 334         /* start fetching from 0x0 */
 335         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 336         armv4_5->core_cache->reg_list[15].dirty = 1;
 337         armv4_5->core_cache->reg_list[15].valid = 1;
 338
 339         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 340         armv4_5->core_state = ARMV4_5_STATE_ARM;
 341
 342         arm720t_disable_mmu_caches(target, 1, 1, 1);
 343         arm720t->armv4_5_mmu.mmu_enabled = 0;
 344         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 345         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 346
 347         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 348         {
 349                 return retval;
 350         }
 351
 352         return ERROR_OK;
 353 }
 354
 355 static int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 356 {
 357         return arm7tdmi_init_target(cmd_ctx, target);
 358 }
 359
 360 static int arm720t_init_arch_info(target_t *target,
 361                 arm720t_common_t *arm720t, jtag_tap_t *tap)
 362 {
 363         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 364         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 365
 366         arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 367
 368         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 369
 370         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 371         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 372
 373         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 374         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 375         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 376         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 377         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 378         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 379         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 380         arm720t->armv4_5_mmu.mmu_enabled = 0;
 381
 382         return ERROR_OK;
 383 }
 384
 385 static int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
 386 {
 387         struct arm720t_common_s *arm720t = target_to_arm720(target);
 388
 389         return arm720t_init_arch_info(target, arm720t, target->tap);
 390 }
 391
 392 static int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx,
 393                 char *cmd, char **args, int argc)
 394 {
 395         int retval;
 396         target_t *target = get_current_target(cmd_ctx);
 397         struct arm720t_common_s *arm720t = target_to_arm720(target);
 398         arm_jtag_t *jtag_info;
 399
 400         retval = arm720t_verify_pointer(cmd_ctx, arm720t);
 401         if (retval != ERROR_OK)
 402                 return retval;
 403
 404         jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
 405
 406         if (target->state != TARGET_HALTED)
 407         {
 408                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 409                 return ERROR_OK;
 410         }
 411
 412         /* one or more argument, access a single register (write if second argument is given */
 413         if (argc >= 1)
 414         {
 415                 uint32_t opcode;
 416                 COMMAND_PARSE_NUMBER(u32, args[0], opcode);
 417
 418                 if (argc == 1)
 419                 {
 420                         uint32_t value;
 421                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 422                         {
 423                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 424                                 return ERROR_OK;
 425                         }
 426
 427                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 428                         {
 429                                 return retval;
 430                         }
 431
 432                         command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 433                 }
 434                 else if (argc == 2)
 435                 {
 436                         uint32_t value;
 437                         COMMAND_PARSE_NUMBER(u32, args[1], value);
 438
 439                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 440                         {
 441                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 442                                 return ERROR_OK;
 443                         }
 444                         command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 445                 }
 446         }
 447
 448         return ERROR_OK;
 449 }
 450
 451 static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 452 {
 453         if (cpnum!=15)
 454         {
 455                 LOG_ERROR("Only cp15 is supported");
 456                 return ERROR_FAIL;
 457         }
 458
 459         return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
 460
 461 }
 462
 463 static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 464 {
 465         if (cpnum!=15)
 466         {
 467                 LOG_ERROR("Only cp15 is supported");
 468                 return ERROR_FAIL;
 469         }
 470
 471         return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
 472 }
 473
 474 static int arm720t_register_commands(struct command_context_s *cmd_ctx)
 475 {
 476         int retval;
 477         command_t *arm720t_cmd;
 478
 479
 480         retval = arm7_9_register_commands(cmd_ctx);
 481
 482         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t",
 483                         NULL, COMMAND_ANY,
 484                         "arm720t specific commands");
 485
 486         register_command(cmd_ctx, arm720t_cmd, "cp15",
 487                         arm720t_handle_cp15_command, COMMAND_EXEC,
 488                         "display/modify cp15 register <opcode> [value]");
 489
 490         return ERROR_OK;
 491 }
 492
 493 /** Holds methods for ARM720 targets. */
 494 target_type_t arm720t_target =
 495 {
 496         .name = "arm720t",
 497
 498         .poll = arm7_9_poll,
 499         .arch_state = arm720t_arch_state,
 500
 501         .halt = arm7_9_halt,
 502         .resume = arm7_9_resume,
 503         .step = arm7_9_step,
 504
 505         .assert_reset = arm7_9_assert_reset,
 506         .deassert_reset = arm7_9_deassert_reset,
 507         .soft_reset_halt = arm720t_soft_reset_halt,
 508
 509         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 510
 511         .read_memory = arm720t_read_memory,
 512         .write_memory = arm7_9_write_memory,
 513         .read_phys_memory = arm720t_read_phys_memory,
 514         .write_phys_memory = arm720t_write_phys_memory,
 515         .bulk_write_memory = arm7_9_bulk_write_memory,
 516         .checksum_memory = arm7_9_checksum_memory,
 517         .blank_check_memory = arm7_9_blank_check_memory,
 518
 519         .run_algorithm = armv4_5_run_algorithm,
 520
 521         .add_breakpoint = arm7_9_add_breakpoint,
 522         .remove_breakpoint = arm7_9_remove_breakpoint,
 523         .add_watchpoint = arm7_9_add_watchpoint,
 524         .remove_watchpoint = arm7_9_remove_watchpoint,
 525
 526         .register_commands = arm720t_register_commands,
 527         .target_create = arm720t_target_create,
 528         .init_target = arm720t_init_target,
 529         .examine = arm7tdmi_examine,
 530         .mrc = arm720t_mrc,
 531         .mcr = arm720t_mcr,
 532
 533 };