1 # Main file for NXP LPC1xxx series Cortex-M0/0+/3 parts
5 # This file should not be included directly, rather by the lpc11xx.cfg,
6 # lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
11 # LPC11xx chips support only SWD transport.
12 # LPC12xx chips support only SWD transport.
13 # LPC11Uxx chips support both JTAG and SWD transports.
14 # LPC13xx chips support both JTAG and SWD transports.
15 # LPC17xx chips support both JTAG and SWD transports.
16 # Adapt based on what transport is active.
17 source [find target/swj-dp.tcl]
19 if { [info exists CHIPNAME] } {
20 set _CHIPNAME $CHIPNAME
22 error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
25 if { [info exists CHIPSERIES] } {
26 # Validate chip series is supported
27 if { $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" } {
28 error "Unsupported LPC1xxx chip series specified."
30 set _CHIPSERIES $CHIPSERIES
32 error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
35 # After reset, the chip is clocked by an internal RC oscillator.
36 # When board-specific code (reset-init handler or device firmware)
37 # configures another oscillator and/or PLL0, set CCLK to match; if
38 # you don't, then flash erase and write operations may misbehave.
39 # (The ROM code doing those updates cares about core clock speed...)
40 # CCLK is the core clock frequency in KHz
41 if { [info exists CCLK] } {
45 # LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one
46 if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
48 } elseif { $_CHIPSERIES == "lpc1700" } {
53 if { [info exists CPUTAPID] } {
55 set _CPUTAPID $CPUTAPID
57 # LPC11xx/LPC12xx uses a Cortex M0 core, LPC13xx/LPC17xx use a Cortex M3 core
58 if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
59 set _CPUTAPID 0x0bb11477
60 } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" } {
62 set _CPUTAPID 0x4ba00477
64 set _CPUTAPID 0x2ba01477
69 if { [info exists WORKAREASIZE] } {
70 set _WORKAREASIZE $WORKAREASIZE
72 error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
75 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
77 set _TARGETNAME $_CHIPNAME.cpu
78 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
80 # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
81 # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
82 # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
83 # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
84 # The LPC17xx devices have 8/16/32kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
85 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
87 # The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
88 # The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
89 # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
90 # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
91 # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
93 # All are compatible with the "lpc1700" variant of the LPC2000 flash driver
94 # (same cmd51 destination boundary alignment, and all three support 256 byte
97 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
98 set _FLASHNAME $_CHIPNAME.flash
99 flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
100 auto $_CCLK calc_checksum
102 if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
103 # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
104 # "User Flash Mode" where interrupt vectors are _not_ remapped,
105 # and reside in flash instead).
107 # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
108 # Bit Symbol Value Description
109 # 1:0 MAP System memory remap
110 # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
111 # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
112 # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
114 $_TARGETNAME configure -event reset-init {
117 } elseif { $_CHIPSERIES == "lpc1700" } {
118 # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
119 # "User Flash Mode" where interrupt vectors are _not_ remapped,
120 # and reside in flash instead).
122 # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
123 # Bit Symbol Value Description Reset
125 # 0 MAP Memory map control. 0
126 # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
127 # 1 User mode. The on-chip Flash memory is mapped to address 0.
128 # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
130 # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
131 $_TARGETNAME configure -event reset-init {
136 # Run with *real slow* clock by default since the
137 # boot rom could have been playing with the PLL, so
138 # we have no idea what clock the target is running at.
141 # delays on reset lines
142 adapter_nsrst_delay 200
147 # LPC11xx/LPC12xx (Cortex M0 core) supports SYSRESETREQ
148 # LPC13xx/LPC17xx (Cortex M3 core) supports SYSRESETREQ
150 # if srst is not fitted use SYSRESETREQ to
151 # perform a soft reset
152 cortex_m reset_config sysresetreq