src/target/embeddedice.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005, 2006 by Dominic Rath                              *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   8  *   oyvind.harboe@zylin.com                                               *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  ***************************************************************************/
  13
  14 #ifndef OPENOCD_TARGET_EMBEDDEDICE_H
  15 #define OPENOCD_TARGET_EMBEDDEDICE_H
  16
  17 #include "arm7_9_common.h"
  18
  19 enum {
  20         EICE_DBG_CTRL = 0,
  21         EICE_DBG_STAT = 1,
  22         EICE_COMMS_CTRL = 2,
  23         EICE_COMMS_DATA = 3,
  24         EICE_W0_ADDR_VALUE = 4,
  25         EICE_W0_ADDR_MASK = 5,
  26         EICE_W0_DATA_VALUE  = 6,
  27         EICE_W0_DATA_MASK = 7,
  28         EICE_W0_CONTROL_VALUE = 8,
  29         EICE_W0_CONTROL_MASK = 9,
  30         EICE_W1_ADDR_VALUE = 10,
  31         EICE_W1_ADDR_MASK = 11,
  32         EICE_W1_DATA_VALUE = 12,
  33         EICE_W1_DATA_MASK = 13,
  34         EICE_W1_CONTROL_VALUE = 14,
  35         EICE_W1_CONTROL_MASK = 15,
  36         EICE_VEC_CATCH = 16
  37 };
  38
  39 enum {
  40         EICE_DBG_CONTROL_ICEDIS = 5,
  41         EICE_DBG_CONTROL_MONEN = 4,
  42         EICE_DBG_CONTROL_INTDIS = 2,
  43         EICE_DBG_CONTROL_DBGRQ = 1,
  44         EICE_DBG_CONTROL_DBGACK = 0,
  45 };
  46
  47 enum {
  48         EICE_DBG_STATUS_IJBIT = 5,
  49         EICE_DBG_STATUS_ITBIT = 4,
  50         EICE_DBG_STATUS_SYSCOMP = 3,
  51         EICE_DBG_STATUS_IFEN = 2,
  52         EICE_DBG_STATUS_DBGRQ = 1,
  53         EICE_DBG_STATUS_DBGACK = 0
  54 };
  55
  56 enum {
  57         EICE_W_CTRL_ENABLE = 0x100,
  58         EICE_W_CTRL_RANGE = 0x80,
  59         EICE_W_CTRL_CHAIN = 0x40,
  60         EICE_W_CTRL_EXTERN = 0x20,
  61         EICE_W_CTRL_NTRANS = 0x10,
  62         EICE_W_CTRL_NOPC = 0x8,
  63         EICE_W_CTRL_MAS = 0x6,
  64         EICE_W_CTRL_ITBIT = 0x2,
  65         EICE_W_CTRL_NRW = 0x1
  66 };
  67
  68 enum {
  69         EICE_COMM_CTRL_WBIT = 1,
  70         EICE_COMM_CTRL_RBIT = 0
  71 };
  72
  73 struct embeddedice_reg {
  74         int addr;
  75         struct arm_jtag *jtag_info;
  76 };
  77
  78 struct reg_cache *embeddedice_build_reg_cache(struct target *target,
  79                 struct arm7_9_common *arm7_9);
  80 void embeddedice_free_reg_cache(struct reg_cache *reg_cache);
  81
  82 int embeddedice_setup(struct target *target);
  83
  84 int embeddedice_read_reg(struct reg *reg);
  85 int embeddedice_read_reg_w_check(struct reg *reg,
  86                 uint8_t *check_value, uint8_t *check_mask);
  87
  88 void embeddedice_write_reg(struct reg *reg, uint32_t value);
  89 void embeddedice_store_reg(struct reg *reg);
  90
  91 void embeddedice_set_reg(struct reg *reg, uint32_t value);
  92
  93 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
  94 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
  95
  96 int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout);
  97
  98 /* If many embeddedice_write_reg() follow each other, then the >1 invocations can be
  99  * this faster version of embeddedice_write_reg
 100  */
 101 static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value)
 102 {
 103         uint8_t out_reg_addr = (1 << 5) | reg_addr;
 104         uint8_t out_value[4];
 105         buf_set_u32(out_value, 0, 32, value);
 106
 107         struct scan_field fields[2] = {
 108                         { .num_bits = 32, .out_value = out_value },
 109                         { .num_bits = 6, .out_value = &out_reg_addr },
 110         };
 111
 112         jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 113 }
 114
 115 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer,
 116                 int little, int count);
 117
 118 #endif /* OPENOCD_TARGET_EMBEDDEDICE_H */