2 * Copyright (C) 2015 by Matthias Welwarsky <matthias.welwarsky@sysgo.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
24 #include "armv8_opcodes.h"
26 static const uint32_t a64_opcodes
[ARMV8_OPC_NUM
] = {
27 [READ_REG_CTR
] = ARMV8_MRS(SYSTEM_CTR
, 0),
28 [READ_REG_CLIDR
] = ARMV8_MRS(SYSTEM_CLIDR
, 0),
29 [READ_REG_CSSELR
] = ARMV8_MRS(SYSTEM_CSSELR
, 0),
30 [READ_REG_CCSIDR
] = ARMV8_MRS(SYSTEM_CCSIDR
, 0),
31 [WRITE_REG_CSSELR
] = ARMV8_MSR_GP(SYSTEM_CSSELR
, 0),
32 [READ_REG_MPIDR
] = ARMV8_MRS(SYSTEM_MPIDR
, 0),
33 [READ_REG_DTRRX
] = ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0
, 0),
34 [WRITE_REG_DTRTX
] = ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0
, 0),
35 [WRITE_REG_DSPSR
] = ARMV8_MSR_DSPSR(0),
36 [READ_REG_DSPSR
] = ARMV8_MRS_DSPSR(0),
37 [ARMV8_OPC_DSB_SY
] = ARMV8_DSB_SY
,
38 [ARMV8_OPC_DCPS
] = ARMV8_DCPS(0, 11),
39 [ARMV8_OPC_DRPS
] = ARMV8_DRPS
,
40 [ARMV8_OPC_ISB_SY
] = ARMV8_ISB
,
41 [ARMV8_OPC_DCCISW
] = ARMV8_SYS(SYSTEM_DCCISW
, 0),
42 [ARMV8_OPC_DCCIVAC
] = ARMV8_SYS(SYSTEM_DCCIVAC
, 0),
43 [ARMV8_OPC_ICIVAU
] = ARMV8_SYS(SYSTEM_ICIVAU
, 0),
44 [ARMV8_OPC_HLT
] = ARMV8_HLT(11),
47 static const uint32_t t32_opcodes
[ARMV8_OPC_NUM
] = {
48 [READ_REG_CTR
] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
49 [READ_REG_CLIDR
] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
50 [READ_REG_CSSELR
] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
51 [READ_REG_CCSIDR
] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
52 [WRITE_REG_CSSELR
] = ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
53 [READ_REG_MPIDR
] = ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
54 [READ_REG_DTRRX
] = ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
55 [WRITE_REG_DTRTX
] = ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
56 [WRITE_REG_DSPSR
] = ARMV8_MCR_DSPSR(0),
57 [READ_REG_DSPSR
] = ARMV8_MRC_DSPSR(0),
58 [ARMV8_OPC_DSB_SY
] = ARMV8_DSB_SY_T1
,
59 [ARMV8_OPC_DCPS
] = ARMV8_DCPS_T1(0),
60 [ARMV8_OPC_DRPS
] = ARMV8_ERET_T1
,
61 [ARMV8_OPC_ISB_SY
] = ARMV8_ISB_SY_T1
,
62 [ARMV8_OPC_DCCISW
] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
63 [ARMV8_OPC_DCCIVAC
] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
64 [ARMV8_OPC_ICIVAU
] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
65 [ARMV8_OPC_HLT
] = ARMV8_HLT_A1(11),
68 void armv8_select_opcodes(struct armv8_common
*armv8
, bool state_is_aarch64
)
71 armv8
->opcodes
= &a64_opcodes
[0];
73 armv8
->opcodes
= &t32_opcodes
[0];
76 uint32_t armv8_opcode(struct armv8_common
*armv8
, enum armv8_opcode code
)
78 if ((int)code
>= ARMV8_OPC_NUM
)
81 return *(armv8
->opcodes
+ code
);