1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
32 char* mips32_core_reg_list
[] =
34 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
35 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
36 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
37 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
38 "status", "lo", "hi", "badvaddr", "cause", "pc"
41 mips32_core_reg_t mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
84 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
85 * we also add 18 unknown registers to handle gdb requests */
87 #define MIPS32NUMFPREGS 34 + 18
89 uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
91 reg_t mips32_gdb_dummy_fp_reg
=
93 "GDB dummy floating-point register", mips32_gdb_dummy_fp_value
, 0, 1, 32, NULL
, 0, NULL
, 0
96 int mips32_core_reg_arch_type
= -1;
98 int mips32_get_core_reg(reg_t
*reg
)
101 mips32_core_reg_t
*mips32_reg
= reg
->arch_info
;
102 target_t
*target
= mips32_reg
->target
;
103 mips32_common_t
*mips32_target
= target
->arch_info
;
105 if (target
->state
!= TARGET_HALTED
)
107 return ERROR_TARGET_NOT_HALTED
;
110 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
115 int mips32_set_core_reg(reg_t
*reg
, uint8_t *buf
)
117 mips32_core_reg_t
*mips32_reg
= reg
->arch_info
;
118 target_t
*target
= mips32_reg
->target
;
119 uint32_t value
= buf_get_u32(buf
, 0, 32);
121 if (target
->state
!= TARGET_HALTED
)
123 return ERROR_TARGET_NOT_HALTED
;
126 buf_set_u32(reg
->value
, 0, 32, value
);
133 int mips32_read_core_reg(struct target_s
*target
, int num
)
136 mips32_core_reg_t
*mips_core_reg
;
138 /* get pointers to arch-specific information */
139 mips32_common_t
*mips32
= target
->arch_info
;
141 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
142 return ERROR_INVALID_ARGUMENTS
;
144 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
145 reg_value
= mips32
->core_regs
[num
];
146 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
147 mips32
->core_cache
->reg_list
[num
].valid
= 1;
148 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
153 int mips32_write_core_reg(struct target_s
*target
, int num
)
156 mips32_core_reg_t
*mips_core_reg
;
158 /* get pointers to arch-specific information */
159 mips32_common_t
*mips32
= target
->arch_info
;
161 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
162 return ERROR_INVALID_ARGUMENTS
;
164 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
165 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
166 mips32
->core_regs
[num
] = reg_value
;
167 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
168 mips32
->core_cache
->reg_list
[num
].valid
= 1;
169 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
174 int mips32_invalidate_core_regs(target_t
*target
)
176 /* get pointers to arch-specific information */
177 mips32_common_t
*mips32
= target
->arch_info
;
180 for (i
= 0; i
< mips32
->core_cache
->num_regs
; i
++)
182 mips32
->core_cache
->reg_list
[i
].valid
= 0;
183 mips32
->core_cache
->reg_list
[i
].dirty
= 0;
189 int mips32_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
191 /* get pointers to arch-specific information */
192 mips32_common_t
*mips32
= target
->arch_info
;
195 /* include floating point registers */
196 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
197 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
199 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
201 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
204 /* add dummy floating points regs */
205 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
207 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
213 int mips32_save_context(target_t
*target
)
217 /* get pointers to arch-specific information */
218 mips32_common_t
*mips32
= target
->arch_info
;
219 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
221 /* read core registers */
222 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
224 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
226 if (!mips32
->core_cache
->reg_list
[i
].valid
)
228 mips32
->read_core_reg(target
, i
);
235 int mips32_restore_context(target_t
*target
)
239 /* get pointers to arch-specific information */
240 mips32_common_t
*mips32
= target
->arch_info
;
241 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
243 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
245 if (mips32
->core_cache
->reg_list
[i
].dirty
)
247 mips32
->write_core_reg(target
, i
);
251 /* write core regs */
252 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
257 int mips32_arch_state(struct target_s
*target
)
259 mips32_common_t
*mips32
= target
->arch_info
;
261 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
263 LOG_ERROR("BUG: called for a non-MIPS32 target");
267 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32
"",
268 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
269 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
274 reg_cache_t
*mips32_build_reg_cache(target_t
*target
)
276 /* get pointers to arch-specific information */
277 mips32_common_t
*mips32
= target
->arch_info
;
279 int num_regs
= MIPS32NUMCOREREGS
;
280 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
281 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
282 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
283 mips32_core_reg_t
*arch_info
= malloc(sizeof(mips32_core_reg_t
) * num_regs
);
286 if (mips32_core_reg_arch_type
== -1)
287 mips32_core_reg_arch_type
= register_reg_arch_type(mips32_get_core_reg
, mips32_set_core_reg
);
289 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
291 /* Build the process context cache */
292 cache
->name
= "mips32 registers";
294 cache
->reg_list
= reg_list
;
295 cache
->num_regs
= num_regs
;
297 mips32
->core_cache
= cache
;
299 for (i
= 0; i
< num_regs
; i
++)
301 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
302 arch_info
[i
].target
= target
;
303 arch_info
[i
].mips32_common
= mips32
;
304 reg_list
[i
].name
= mips32_core_reg_list
[i
];
305 reg_list
[i
].size
= 32;
306 reg_list
[i
].value
= calloc(1, 4);
307 reg_list
[i
].dirty
= 0;
308 reg_list
[i
].valid
= 0;
309 reg_list
[i
].bitfield_desc
= NULL
;
310 reg_list
[i
].num_bitfields
= 0;
311 reg_list
[i
].arch_type
= mips32_core_reg_arch_type
;
312 reg_list
[i
].arch_info
= &arch_info
[i
];
318 int mips32_init_arch_info(target_t
*target
, mips32_common_t
*mips32
, jtag_tap_t
*tap
)
320 target
->arch_info
= mips32
;
321 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
323 /* has breakpoint/watchpint unit been scanned */
324 mips32
->bp_scanned
= 0;
325 mips32
->data_break_list
= NULL
;
327 mips32
->ejtag_info
.tap
= tap
;
328 mips32
->read_core_reg
= mips32_read_core_reg
;
329 mips32
->write_core_reg
= mips32_write_core_reg
;
334 int mips32_register_commands(struct command_context_s
*cmd_ctx
)
339 int mips32_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
345 int mips32_examine(struct target_s
*target
)
347 mips32_common_t
*mips32
= target
->arch_info
;
349 if (!target_was_examined(target
))
351 target_set_examined(target
);
353 /* we will configure later */
354 mips32
->bp_scanned
= 0;
355 mips32
->num_inst_bpoints
= 0;
356 mips32
->num_data_bpoints
= 0;
357 mips32
->num_inst_bpoints_avail
= 0;
358 mips32
->num_data_bpoints_avail
= 0;
364 int mips32_configure_break_unit(struct target_s
*target
)
366 /* get pointers to arch-specific information */
367 mips32_common_t
*mips32
= target
->arch_info
;
369 uint32_t dcr
, bpinfo
;
372 if (mips32
->bp_scanned
)
375 /* get info about breakpoint support */
376 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
381 /* get number of inst breakpoints */
382 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
385 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
386 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
387 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(mips32_comparator_t
));
388 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
390 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
394 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
400 /* get number of data breakpoints */
401 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
404 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
405 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
406 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(mips32_comparator_t
));
407 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
409 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
413 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
417 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
, mips32
->num_data_bpoints
);
419 mips32
->bp_scanned
= 1;
424 int mips32_enable_interrupts(struct target_s
*target
, int enable
)
430 /* read debug control register */
431 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
436 if (!(dcr
& (1 << 4)))
438 /* enable interrupts */
447 /* disable interrupts */
455 if ((retval
= target_write_u32(target
, EJTAG_DCR
, dcr
)) != ERROR_OK
)