src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include <helper/log.h>
  26 #include "target.h"
  27 #include "armv4_5_mmu.h"
  28
  29 int armv4_5_mmu_translate_va(struct target *target,
  30                 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
  31 {
  32         uint32_t first_lvl_descriptor = 0x0;
  33         uint32_t second_lvl_descriptor = 0x0;
  34         uint32_t ttb;
  35         int retval;
  36         retval = armv4_5_mmu->get_ttb(target, &ttb);
  37         if (retval != ERROR_OK)
  38                 return retval;
  39
  40         retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  41                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  42                 4, 1, (uint8_t *)&first_lvl_descriptor);
  43         if (retval != ERROR_OK)
  44                 return retval;
  45         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
  46
  47         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  48
  49         if ((first_lvl_descriptor & 0x3) == 0) {
  50                 LOG_ERROR("Address translation failure");
  51                 return ERROR_TARGET_TRANSLATION_FAULT;
  52         }
  53
  54         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) {
  55                 LOG_ERROR("Address translation failure");
  56                 return ERROR_TARGET_TRANSLATION_FAULT;
  57         }
  58
  59         if ((first_lvl_descriptor & 0x3) == 2) {
  60                 /* section descriptor */
  61                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  62                 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  63                 return ERROR_OK;
  64         }
  65
  66         if ((first_lvl_descriptor & 0x3) == 1) {
  67                 /* coarse page table */
  68                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  69                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  70                         4, 1, (uint8_t *)&second_lvl_descriptor);
  71                 if (retval != ERROR_OK)
  72                         return retval;
  73         } else if ((first_lvl_descriptor & 0x3) == 3) {
  74                 /* fine page table */
  75                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  76                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  77                         4, 1, (uint8_t *)&second_lvl_descriptor);
  78                 if (retval != ERROR_OK)
  79                         return retval;
  80         }
  81
  82         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
  83
  84         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  85
  86         if ((second_lvl_descriptor & 0x3) == 0) {
  87                 LOG_ERROR("Address translation failure");
  88                 return ERROR_TARGET_TRANSLATION_FAULT;
  89         }
  90
  91         /* cacheable/bufferable is always specified in bits 3-2 */
  92         *cb = (second_lvl_descriptor & 0xc) >> 2;
  93
  94         if ((second_lvl_descriptor & 0x3) == 1) {
  95                 /* large page descriptor */
  96                 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
  97                 return ERROR_OK;
  98         }
  99
 100         if ((second_lvl_descriptor & 0x3) == 2) {
 101                 /* small page descriptor */
 102                 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 103                 return ERROR_OK;
 104         }
 105
 106         if ((second_lvl_descriptor & 0x3) == 3) {
 107                 /* tiny page descriptor */
 108                 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 109                 return ERROR_OK;
 110         }
 111
 112         /* should not happen */
 113         LOG_ERROR("Address translation failure");
 114         return ERROR_TARGET_TRANSLATION_FAULT;
 115 }
 116
 117 int armv4_5_mmu_read_physical(struct target *target,
 118                 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
 119                 uint32_t size, uint32_t count, uint8_t *buffer)
 120 {
 121         int retval;
 122
 123         if (target->state != TARGET_HALTED)
 124                 return ERROR_TARGET_NOT_HALTED;
 125
 126         /* disable MMU and data (or unified) cache */
 127         retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 128         if (retval != ERROR_OK)
 129                 return retval;
 130
 131         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 132         if (retval != ERROR_OK)
 133                 return retval;
 134
 135         /* reenable MMU / cache */
 136         retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 137                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 138                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 139         if (retval != ERROR_OK)
 140                 return retval;
 141
 142         return retval;
 143 }
 144
 145 int armv4_5_mmu_write_physical(struct target *target,
 146                 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
 147                 uint32_t size, uint32_t count, const uint8_t *buffer)
 148 {
 149         int retval;
 150
 151         if (target->state != TARGET_HALTED)
 152                 return ERROR_TARGET_NOT_HALTED;
 153
 154         /* disable MMU and data (or unified) cache */
 155         retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 156         if (retval != ERROR_OK)
 157                 return retval;
 158
 159         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 160         if (retval != ERROR_OK)
 161                 return retval;
 162
 163         /* reenable MMU / cache */
 164         retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 165                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 166                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 167         if (retval != ERROR_OK)
 168                 return retval;
 169
 170         return retval;
 171 }