Add comments and tiny improvements to STM32 flash loader algorithm
[openocd.git] / contrib / loaders / flash / stm32x.s
blob6cf9f5791cbb6dcf6bfba476830e4493af9cfc0e
1 /***************************************************************************
2 * Copyright (C) 2010 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 .text
22 .syntax unified
23 .thumb
24 .thumb_func
25 .global write
28 r0 - source address
29 r1 - target address
30 r2 - count (halfword-16bit)
31 r3 - result
32 r4 - temp
35 #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
36 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of CR register in FLASH struct */
38 write:
39 ldr r4, STM32_FLASH_BASE
40 write_half_word:
41 movs r3, #0x01
42 str r3, [r4, #STM32_FLASH_CR_OFFSET] /* PG (bit0) == 1 => flash programming enabled */
43 ldrh r3, [r0], #0x02 /* read one half-word from src, increment ptr */
44 strh r3, [r1], #0x02 /* write one half-word from src, increment ptr */
45 busy:
46 ldr r3, [r4, #STM32_FLASH_SR_OFFSET]
47 tst r3, #0x01 /* BSY (bit0) == 1 => operation in progress */
48 beq busy /* wait more... */
49 tst r3, #0x14 /* PGERR (bit2) == 1 or WRPRTERR (bit4) == 1 => error */
50 bne exit /* fail... */
51 subs r2, r2, #0x01 /* decrement counter */
52 bne write_half_word /* write next half-word if anything left */
53 exit:
54 bkpt #0x00
56 STM32_FLASH_BASE: .word 0x40022000 /* base address of FLASH struct */