| blob | f46a8f1dd82a095fe4d466407c84ceb98d37f124 |
1 From nobody Mon Sep 17 00:00:00 2001
2 From: Håvard Skinnemoen <hskinnemoen@atmel.com>
3 Date: Fri Nov 18 18:13:25 2005 +0100
4 Subject: [PATCH] Driver for the Atmel HUSB2 Device Controller
6 This adds the driver for the Atmel HUSB2 Device Controller.
8 ---
10 drivers/usb/gadget/Kconfig | 10
11 drivers/usb/gadget/Makefile | 1
12 drivers/usb/gadget/gadget_chips.h | 8
13 drivers/usb/gadget/husb2_udc.c | 1998 ++++++++++++++++++++++++++++++++++++++
14 drivers/usb/gadget/husb2_udc.h | 406 +++++++
15 5 files changed, 2423 insertions(+)
17 Index: linux-2.6.18-avr32/drivers/usb/gadget/Kconfig
18 ===================================================================
19 --- linux-2.6.18-avr32.orig/drivers/usb/gadget/Kconfig 2006-11-02 15:54:18.000000000 +0100
20 +++ linux-2.6.18-avr32/drivers/usb/gadget/Kconfig 2006-11-02 15:56:20.000000000 +0100
21 @@ -154,6 +154,16 @@ config USB_LH7A40X
22 default USB_GADGET
23 select USB_GADGET_SELECTED
25 +config USB_GADGET_HUSB2DEV
26 + boolean "Atmel HUSB2DEVICE"
27 + select USB_GADGET_DUALSPEED
28 + depends on AVR32
29 +
30 +config USB_HUSB2DEV
31 + tristate
32 + depends on USB_GADGET_HUSB2DEV
33 + default USB_GADGET
34 + select USB_GADGET_SELECTED
36 config USB_GADGET_OMAP
37 boolean "OMAP USB Device Controller"
38 Index: linux-2.6.18-avr32/drivers/usb/gadget/Makefile
39 ===================================================================
40 --- linux-2.6.18-avr32.orig/drivers/usb/gadget/Makefile 2006-11-02 15:54:18.000000000 +0100
41 +++ linux-2.6.18-avr32/drivers/usb/gadget/Makefile 2006-11-02 15:56:20.000000000 +0100
42 @@ -8,6 +8,7 @@ obj-$(CONFIG_USB_GOKU) += goku_udc.o
43 obj-$(CONFIG_USB_OMAP) += omap_udc.o
44 obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
45 obj-$(CONFIG_USB_AT91) += at91_udc.o
46 +obj-$(CONFIG_USB_HUSB2DEV) += husb2_udc.o
48 #
49 # USB gadget drivers
50 Index: linux-2.6.18-avr32/drivers/usb/gadget/gadget_chips.h
51 ===================================================================
52 --- linux-2.6.18-avr32.orig/drivers/usb/gadget/gadget_chips.h 2006-11-02 15:54:18.000000000 +0100
53 +++ linux-2.6.18-avr32/drivers/usb/gadget/gadget_chips.h 2006-11-02 15:56:20.000000000 +0100
54 @@ -75,6 +75,12 @@
55 #define gadget_is_pxa27x(g) 0
56 #endif
58 +#ifdef CONFIG_USB_GADGET_HUSB2DEV
59 +#define gadget_is_husb2dev(g) !strcmp("husb2_udc", (g)->name)
60 +#else
61 +#define gadget_is_husb2dev(g) 0
62 +#endif
63 +
64 #ifdef CONFIG_USB_GADGET_S3C2410
65 #define gadget_is_s3c2410(g) !strcmp("s3c2410_udc", (g)->name)
66 #else
67 @@ -169,5 +175,7 @@ static inline int usb_gadget_controller_
68 return 0x16;
69 else if (gadget_is_mpc8272(gadget))
70 return 0x17;
71 + else if (gadget_is_husb2dev(gadget))
72 + return 0x80;
73 return -ENOENT;
74 }
75 Index: linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.c
76 ===================================================================
77 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
78 +++ linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.c 2006-11-02 16:06:40.000000000 +0100
79 @@ -0,0 +1,1998 @@
80 +/*
81 + * Driver for the Atmel HUSB2device high speed USB device controller
82 + *
83 + * Copyright (C) 2005-2006 Atmel Corporation
84 + *
85 + * This program is free software; you can redistribute it and/or modify
86 + * it under the terms of the GNU General Public License version 2 as
87 + * published by the Free Software Foundation.
88 + */
89 +#undef DEBUG
90 +
91 +#include <linux/config.h>
92 +#include <linux/clk.h>
93 +#include <linux/module.h>
94 +#include <linux/init.h>
95 +#include <linux/interrupt.h>
96 +#include <linux/device.h>
97 +#include <linux/dma-mapping.h>
98 +#include <linux/list.h>
99 +#include <linux/platform_device.h>
100 +#include <linux/usb_ch9.h>
101 +#include <linux/usb_gadget.h>
102 +#include <linux/dmapool.h>
103 +#include <linux/delay.h>
104 +
105 +#include <asm/io.h>
106 +
107 +#include "husb2_udc.h"
108 +
109 +#define DRIVER_VERSION "0.9"
110 +
111 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
112 +
113 +#define FIFO_IOMEM_ID 0
114 +#define CTRL_IOMEM_ID 1
115 +
116 +#ifdef DEBUG
117 +#define DBG_ERR 0x0001 /* report all error returns */
118 +#define DBG_HW 0x0002 /* debug hardware initialization */
119 +#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
120 +#define DBG_INT 0x0008 /* interrupts */
121 +#define DBG_BUS 0x0010 /* report changes in bus state */
122 +#define DBG_QUEUE 0x0020 /* debug request queue processing */
123 +#define DBG_FIFO 0x0040 /* debug FIFO contents */
124 +#define DBG_DMA 0x0080 /* debug DMA handling */
125 +#define DBG_REQ 0x0100 /* print out queued request length */
126 +#define DBG_ALL 0xffff
127 +#define DBG_NONE 0x0000
128 +
129 +#define DEBUG_LEVEL (DBG_ERR|DBG_REQ)
130 +#define DBG(level, fmt, ...) \
131 + do { \
132 + if ((level) & DEBUG_LEVEL) \
133 + printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__); \
134 + } while (0)
135 +#else
136 +#define DBG(level, fmt...)
137 +#endif
138 +
139 +static struct husb2_udc the_udc;
140 +
141 +#ifdef CONFIG_DEBUG_FS
142 +#include <linux/debugfs.h>
143 +#include <asm/uaccess.h>
144 +
145 +static int queue_dbg_open(struct inode *inode, struct file *file)
146 +{
147 + struct husb2_ep *ep = inode->u.generic_ip;
148 + struct husb2_request *req, *req_copy;
149 + struct list_head *queue_data;
150 +
151 + queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
152 + if (!queue_data)
153 + return -ENOMEM;
154 + INIT_LIST_HEAD(queue_data);
155 +
156 + spin_lock_irq(&ep->udc->lock);
157 + list_for_each_entry(req, &ep->queue, queue) {
158 + req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
159 + if (!req_copy)
160 + goto fail;
161 + memcpy(req_copy, req, sizeof(*req_copy));
162 + list_add_tail(&req_copy->queue, queue_data);
163 + }
164 + spin_unlock_irq(&ep->udc->lock);
165 +
166 + file->private_data = queue_data;
167 + return 0;
168 +
169 +fail:
170 + spin_unlock_irq(&ep->udc->lock);
171 + list_for_each_entry_safe(req, req_copy, queue_data, queue) {
172 + list_del(&req->queue);
173 + kfree(req);
174 + }
175 + kfree(queue_data);
176 + return -ENOMEM;
177 +}
178 +
179 +/*
180 + * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
181 + *
182 + * b: buffer address
183 + * l: buffer length
184 + * I/i: interrupt/no interrupt
185 + * Z/z: zero/no zero
186 + * S/s: short ok/short not ok
187 + * s: status
188 + * n: nr_packets
189 + * F/f: submitted/not submitted to FIFO
190 + * D/d: using/not using DMA
191 + * L/l: last transaction/not last transaction
192 + */
193 +static ssize_t queue_dbg_read(struct file *file, char __user *buf,
194 + size_t nbytes, loff_t *ppos)
195 +{
196 + struct list_head *queue = file->private_data;
197 + struct husb2_request *req, *tmp_req;
198 + size_t len, remaining, actual = 0;
199 + char tmpbuf[38];
200 +
201 + if (!access_ok(VERIFY_WRITE, buf, nbytes))
202 + return -EFAULT;
203 +
204 + mutex_lock(&file->f_dentry->d_inode->i_mutex);
205 + list_for_each_entry_safe(req, tmp_req, queue, queue) {
206 + len = snprintf(tmpbuf, sizeof(tmpbuf),
207 + "%8p %08x %c%c%c %5d %4u %c%c%c\n",
208 + req->req.buf, req->req.length,
209 + req->req.no_interrupt ? 'i' : 'I',
210 + req->req.zero ? 'Z' : 'z',
211 + req->req.short_not_ok ? 's' : 'S',
212 + req->req.status,
213 + req->nr_pkts,
214 + req->submitted ? 'F' : 'f',
215 + req->using_dma ? 'D' : 'd',
216 + req->last_transaction ? 'L' : 'l');
217 + len = min(len, sizeof(tmpbuf));
218 + if (len > nbytes)
219 + break;
220 +
221 + list_del(&req->queue);
222 + kfree(req);
223 +
224 + remaining = __copy_to_user(buf, tmpbuf, len);
225 + actual += len - remaining;
226 + if (remaining)
227 + break;
228 +
229 + nbytes -= len;
230 + buf += len;
231 + }
232 + mutex_unlock(&file->f_dentry->d_inode->i_mutex);
233 +
234 + return actual;
235 +}
236 +
237 +static int queue_dbg_release(struct inode *inode, struct file *file)
238 +{
239 + struct list_head *queue_data = file->private_data;
240 + struct husb2_request *req, *tmp_req;
241 +
242 + list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
243 + list_del(&req->queue);
244 + kfree(req);
245 + }
246 + kfree(queue_data);
247 + return 0;
248 +}
249 +
250 +static int regs_dbg_open(struct inode *inode, struct file *file)
251 +{
252 + struct husb2_udc *udc;
253 + unsigned int i;
254 + u32 *data;
255 + int ret = -ENOMEM;
256 +
257 + mutex_lock(&inode->i_mutex);
258 + udc = inode->u.generic_ip;
259 + data = kmalloc(inode->i_size, GFP_KERNEL);
260 + if (!data)
261 + goto out;
262 +
263 + spin_lock_irq(&udc->lock);
264 + for (i = 0; i < inode->i_size / 4; i++)
265 + data[i] = __raw_readl(udc->regs + i * 4);
266 + spin_unlock_irq(&udc->lock);
267 +
268 + file->private_data = data;
269 + ret = 0;
270 +
271 +out:
272 + mutex_unlock(&inode->i_mutex);
273 +
274 + return ret;
275 +}
276 +
277 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
278 + size_t nbytes, loff_t *ppos)
279 +{
280 + struct inode *inode = file->f_dentry->d_inode;
281 + int ret;
282 +
283 + mutex_lock(&inode->i_mutex);
284 + ret = simple_read_from_buffer(buf, nbytes, ppos,
285 + file->private_data,
286 + file->f_dentry->d_inode->i_size);
287 + mutex_unlock(&inode->i_mutex);
288 +
289 + return ret;
290 +}
291 +
292 +static int regs_dbg_release(struct inode *inode, struct file *file)
293 +{
294 + kfree(file->private_data);
295 + return 0;
296 +}
297 +
298 +const struct file_operations queue_dbg_fops = {
299 + .owner = THIS_MODULE,
300 + .open = queue_dbg_open,
301 + .llseek = no_llseek,
302 + .read = queue_dbg_read,
303 + .release = queue_dbg_release,
304 +};
305 +
306 +const struct file_operations regs_dbg_fops = {
307 + .owner = THIS_MODULE,
308 + .open = regs_dbg_open,
309 + .llseek = generic_file_llseek,
310 + .read = regs_dbg_read,
311 + .release = regs_dbg_release,
312 +};
313 +
314 +static void husb2_ep_init_debugfs(struct husb2_udc *udc,
315 + struct husb2_ep *ep)
316 +{
317 + struct dentry *ep_root;
318 +
319 + ep_root = debugfs_create_dir(ep_name(ep), udc->debugfs_root);
320 + if (!ep_root)
321 + goto err_root;
322 + ep->debugfs_dir = ep_root;
323 +
324 + ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
325 + ep, &queue_dbg_fops);
326 + if (!ep->debugfs_queue)
327 + goto err_queue;
328 +
329 + if (ep_can_dma(ep)) {
330 + ep->debugfs_dma_status
331 + = debugfs_create_u32("dma_status", 0400, ep_root,
332 + &ep->last_dma_status);
333 + if (!ep->debugfs_dma_status)
334 + goto err_dma_status;
335 + }
336 +
337 + return;
338 +
339 +err_dma_status:
340 + debugfs_remove(ep->debugfs_queue);
341 +err_queue:
342 + debugfs_remove(ep_root);
343 +err_root:
344 + dev_err(&ep->udc->pdev->dev,
345 + "failed to create debugfs directory for %s\n", ep_name(ep));
346 +}
347 +
348 +static void husb2_ep_cleanup_debugfs(struct husb2_ep *ep)
349 +{
350 + debugfs_remove(ep->debugfs_queue);
351 + debugfs_remove(ep->debugfs_dma_status);
352 + debugfs_remove(ep->debugfs_dir);
353 + ep->debugfs_dma_status = NULL;
354 + ep->debugfs_dir = NULL;
355 +}
356 +
357 +static void husb2_init_debugfs(struct husb2_udc *udc)
358 +{
359 + struct dentry *root, *regs;
360 + struct resource *regs_resource;
361 +
362 + root = debugfs_create_dir(udc->gadget.name, NULL);
363 + if (IS_ERR(root) || !root)
364 + goto err_root;
365 + udc->debugfs_root = root;
366 +
367 + regs = debugfs_create_file("regs", 0400, root, udc, ®s_dbg_fops);
368 + if (!regs)
369 + goto err_regs;
370 +
371 + regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
372 + CTRL_IOMEM_ID);
373 + regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
374 + udc->debugfs_regs = regs;
375 +
376 + husb2_ep_init_debugfs(udc, to_husb2_ep(udc->gadget.ep0));
377 +
378 + return;
379 +
380 +err_regs:
381 + debugfs_remove(root);
382 +err_root:
383 + udc->debugfs_root = NULL;
384 + dev_err(&udc->pdev->dev, "debugfs is not available\n");
385 +}
386 +
387 +static void husb2_cleanup_debugfs(struct husb2_udc *udc)
388 +{
389 + husb2_ep_cleanup_debugfs(to_husb2_ep(udc->gadget.ep0));
390 + debugfs_remove(udc->debugfs_regs);
391 + debugfs_remove(udc->debugfs_root);
392 + udc->debugfs_regs = NULL;
393 + udc->debugfs_root = NULL;
394 +}
395 +#else
396 +static inline void husb2_ep_init_debugfs(struct husb2_udc *udc,
397 + struct husb2_ep *ep)
398 +{
399 +
400 +}
401 +
402 +static inline void husb2_ep_cleanup_debugfs(struct husb2_ep *ep)
403 +{
404 +
405 +}
406 +
407 +static inline void husb2_init_debugfs(struct husb2_udc *udc)
408 +{
409 +
410 +}
411 +
412 +static inline void husb2_cleanup_debugfs(struct husb2_udc *udc)
413 +{
414 +
415 +}
416 +#endif
417 +
418 +static void copy_to_fifo(void __iomem *fifo, void *buf, int len)
419 +{
420 + unsigned long tmp;
421 +
422 + DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
423 + for (; len > 0; len -= 4, buf += 4, fifo += 4) {
424 + tmp = *(unsigned long *)buf;
425 + if (len >= 4) {
426 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
427 + __raw_writel(tmp, fifo);
428 + } else {
429 + do {
430 + DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
431 + __raw_writeb(tmp >> 24, fifo);
432 + fifo++;
433 + tmp <<= 8;
434 + } while (--len);
435 + break;
436 + }
437 + }
438 +}
439 +
440 +static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
441 +{
442 + union {
443 + unsigned long *w;
444 + unsigned char *b;
445 + } p;
446 + unsigned long tmp;
447 +
448 + DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
449 + for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
450 + if (len >= 4) {
451 + tmp = __raw_readl(fifo);
452 + *p.w = tmp;
453 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
454 + } else {
455 + do {
456 + tmp = __raw_readb(fifo);
457 + *p.b = tmp;
458 + DBG(DBG_FIFO, " -> %02lx\n", tmp);
459 + fifo++, p.b++;
460 + } while (--len);
461 + }
462 + }
463 +}
464 +
465 +static void next_fifo_transaction(struct husb2_ep *ep,
466 + struct husb2_request *req)
467 +{
468 + unsigned int transaction_len;
469 +
470 + transaction_len = req->req.length - req->req.actual;
471 + req->last_transaction = 1;
472 + if (transaction_len > ep->ep.maxpacket) {
473 + transaction_len = ep->ep.maxpacket;
474 + req->last_transaction = 0;
475 + } else if (transaction_len == ep->ep.maxpacket
476 + && req->req.zero) {
477 + req->last_transaction = 0;
478 + }
479 + DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
480 + ep_name(ep), req, transaction_len,
481 + req->last_transaction ? ", done" : "");
482 +
483 + copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
484 + husb2_ep_writel(ep, SET_STA, HUSB2_BIT(TX_PK_RDY));
485 + req->req.actual += transaction_len;
486 +}
487 +
488 +static void submit_request(struct husb2_ep *ep, struct husb2_request *req)
489 +{
490 + DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
491 + ep_name(ep), req, req->req.length);
492 +
493 + req->req.actual = 0;
494 + req->submitted = 1;
495 +
496 + if (req->using_dma) {
497 + if (req->req.length == 0) {
498 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
499 + } else {
500 + husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(TX_PK_RDY));
501 + husb2_dma_writel(ep, NXT_DSC,
502 + req->packet[0].desc_dma);
503 + husb2_dma_writel(ep, CONTROL, HUSB2_BIT(DMA_LINK));
504 + }
505 + } else {
506 + next_fifo_transaction(ep, req);
507 + if (req->last_transaction)
508 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_COMPLETE));
509 + else
510 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
511 + }
512 +}
513 +
514 +static void submit_next_request(struct husb2_ep *ep)
515 +{
516 + struct husb2_request *req;
517 +
518 + if (list_empty(&ep->queue)) {
519 + husb2_ep_writel(ep, CTL_DIS, (HUSB2_BIT(TX_PK_RDY)
520 + | HUSB2_BIT(RX_BK_RDY)));
521 + return;
522 + }
523 +
524 + req = list_entry(ep->queue.next, struct husb2_request, queue);
525 + if (!req->submitted)
526 + submit_request(ep, req);
527 +}
528 +
529 +static void send_status(struct husb2_udc *udc, struct husb2_ep *ep)
530 +{
531 + ep->state = STATUS_STAGE_IN;
532 + husb2_ep_writel(ep, SET_STA, HUSB2_BIT(TX_PK_RDY));
533 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_COMPLETE));
534 +}
535 +
536 +static void receive_data(struct husb2_ep *ep)
537 +{
538 + struct husb2_udc *udc = ep->udc;
539 + struct husb2_request *req;
540 + unsigned long status;
541 + unsigned int bytecount, nr_busy;
542 + int is_complete = 0;
543 +
544 + status = husb2_ep_readl(ep, STA);
545 + nr_busy = HUSB2_BFEXT(BUSY_BANKS, status);
546 +
547 + DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
548 +
549 + while (nr_busy > 0) {
550 + if (list_empty(&ep->queue)) {
551 + husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(RX_BK_RDY));
552 + break;
553 + }
554 + req = list_entry(ep->queue.next,
555 + struct husb2_request, queue);
556 +
557 + bytecount = HUSB2_BFEXT(BYTE_COUNT, status);
558 +
559 + if (status & (1 << 31))
560 + is_complete = 1;
561 + if (req->req.actual + bytecount >= req->req.length) {
562 + is_complete = 1;
563 + bytecount = req->req.length - req->req.actual;
564 + }
565 +
566 + copy_from_fifo(req->req.buf + req->req.actual,
567 + ep->fifo, bytecount);
568 + req->req.actual += bytecount;
569 +
570 + husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
571 +
572 + if (is_complete) {
573 + DBG(DBG_QUEUE, "%s: request done\n", ep_name(ep));
574 + req->req.status = 0;
575 + list_del_init(&req->queue);
576 + req->req.complete(&ep->ep, &req->req);
577 + }
578 +
579 + status = husb2_ep_readl(ep, STA);
580 + nr_busy = HUSB2_BFEXT(BUSY_BANKS, status);
581 +
582 + if (is_complete && ep_is_control(ep)) {
583 + BUG_ON(nr_busy != 0);
584 + send_status(udc, ep);
585 + break;
586 + }
587 + }
588 +}
589 +
590 +static void request_complete(struct husb2_ep *ep,
591 + struct husb2_request *req,
592 + int status)
593 +{
594 + struct husb2_udc *udc = ep->udc;
595 + int i;
596 +
597 + BUG_ON(!list_empty(&req->queue));
598 +
599 + if (req->req.status == -EINPROGRESS)
600 + req->req.status = status;
601 +
602 + if (req->packet) {
603 + for (i = 0; i < req->nr_pkts; i++)
604 + dma_pool_free(udc->desc_pool, req->packet[i].desc,
605 + req->packet[i].desc_dma);
606 + kfree(req->packet);
607 + req->packet = NULL;
608 + dma_unmap_single(&udc->pdev->dev,
609 + req->req.dma, req->req.length,
610 + (ep_is_in(ep)
611 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
612 + req->req.dma = DMA_ADDR_INVALID;
613 + }
614 +
615 + DBG(DBG_GADGET | DBG_REQ,
616 + "%s: req %p complete: status %d, actual %u\n",
617 + ep_name(ep), req, req->req.status, req->req.actual);
618 + req->req.complete(&ep->ep, &req->req);
619 +}
620 +
621 +static void request_complete_list(struct husb2_ep *ep,
622 + struct list_head *list,
623 + int status)
624 +{
625 + struct husb2_request *req, *tmp_req;
626 +
627 + list_for_each_entry_safe(req, tmp_req, list, queue) {
628 + list_del_init(&req->queue);
629 + request_complete(ep, req, status);
630 + }
631 +}
632 +
633 +static int husb2_ep_enable(struct usb_ep *_ep,
634 + const struct usb_endpoint_descriptor *desc)
635 +{
636 + struct husb2_ep *ep = to_husb2_ep(_ep);
637 + struct husb2_udc *udc = ep->udc;
638 + unsigned long flags, ept_cfg, maxpacket;
639 +
640 + DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep_name(ep), desc);
641 +
642 + maxpacket = le16_to_cpu(desc->wMaxPacketSize);
643 +
644 + if (ep->index == 0
645 + || desc->bDescriptorType != USB_DT_ENDPOINT
646 + || ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
647 + != ep->index)
648 + || maxpacket == 0
649 + || maxpacket > ep->fifo_size) {
650 + DBG(DBG_ERR, "ep_enable: Invalid argument");
651 + return -EINVAL;
652 + }
653 +
654 + if (((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
655 + == USB_ENDPOINT_XFER_ISOC)
656 + && !(ep->capabilities & HUSB2_EP_CAP_ISOC)) {
657 + DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
658 + ep_name(ep));
659 + return -EINVAL;
660 + }
661 +
662 + if (maxpacket <= 8)
663 + ept_cfg = HUSB2_BF(EPT_SIZE, HUSB2_EPT_SIZE_8);
664 + else
665 + /* LSB is bit 1, not 0 */
666 + ept_cfg = HUSB2_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
667 + DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
668 + ep_name(ep), ept_cfg, maxpacket);
669 +
670 + if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
671 + ept_cfg |= HUSB2_BIT(EPT_DIR);
672 +
673 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
674 + case USB_ENDPOINT_XFER_CONTROL:
675 + ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_CONTROL);
676 + break;
677 + case USB_ENDPOINT_XFER_ISOC:
678 + ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_ISO);
679 + break;
680 + case USB_ENDPOINT_XFER_BULK:
681 + ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_BULK);
682 + break;
683 + case USB_ENDPOINT_XFER_INT:
684 + ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_INT);
685 + break;
686 + }
687 + ept_cfg |= HUSB2_BF(BK_NUMBER, ep->nr_banks);
688 +
689 + spin_lock_irqsave(&ep->udc->lock, flags);
690 +
691 + if (ep->desc) {
692 + spin_unlock_irqrestore(&ep->udc->lock, flags);
693 + DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
694 + return -EBUSY;
695 + }
696 +
697 + ep->desc = desc;
698 + ep->ep.maxpacket = maxpacket;
699 +
700 + husb2_ep_writel(ep, CFG, ept_cfg);
701 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(EPT_ENABLE));
702 +
703 + if (ep_can_dma(ep)) {
704 + husb2_writel(udc, INT_ENB,
705 + (husb2_readl(udc, INT_ENB)
706 + | HUSB2_BF(EPT_INT, 1 << ep->index)
707 + | HUSB2_BF(DMA_INT, 1 << ep->index)));
708 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(AUTO_VALID));
709 + } else {
710 + husb2_writel(udc, INT_ENB,
711 + (husb2_readl(udc, INT_ENB)
712 + | HUSB2_BF(EPT_INT, 1 << ep->index)));
713 + }
714 +
715 + spin_unlock_irqrestore(&udc->lock, flags);
716 +
717 + DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
718 + (unsigned long)husb2_ep_readl(ep, CFG));
719 + DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
720 + (unsigned long)husb2_readl(udc, INT_ENB));
721 +
722 + husb2_ep_init_debugfs(udc, ep);
723 +
724 + return 0;
725 +}
726 +
727 +static int husb2_ep_disable(struct usb_ep *_ep)
728 +{
729 + struct husb2_ep *ep = to_husb2_ep(_ep);
730 + struct husb2_udc *udc = ep->udc;
731 + LIST_HEAD(req_list);
732 + unsigned long flags;
733 +
734 + DBG(DBG_GADGET, "ep_disable: %s\n", ep_name(ep));
735 +
736 + husb2_ep_cleanup_debugfs(ep);
737 +
738 + spin_lock_irqsave(&udc->lock, flags);
739 +
740 + if (!ep->desc) {
741 + spin_unlock_irqrestore(&udc->lock, flags);
742 + DBG(DBG_ERR, "ep_disable: %s not enabled\n",
743 + ep_name(ep));
744 + return -EINVAL;
745 + }
746 + ep->desc = NULL;
747 +
748 + list_splice_init(&ep->queue, &req_list);
749 + if (ep_can_dma(ep)) {
750 + husb2_dma_writel(ep, CONTROL, 0);
751 + husb2_dma_writel(ep, ADDRESS, 0);
752 + husb2_dma_readl(ep, STATUS);
753 + }
754 + husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(EPT_ENABLE));
755 + husb2_writel(udc, INT_ENB, (husb2_readl(udc, INT_ENB)
756 + & ~HUSB2_BF(EPT_INT, 1 << ep->index)));
757 +
758 + spin_unlock_irqrestore(&udc->lock, flags);
759 +
760 + request_complete_list(ep, &req_list, -ESHUTDOWN);
761 +
762 + return 0;
763 +}
764 +
765 +static struct usb_request *
766 +husb2_ep_alloc_request(struct usb_ep *_ep, unsigned gfp_flags)
767 +{
768 + struct husb2_request *req;
769 +
770 + DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
771 +
772 + req = kzalloc(sizeof(*req), gfp_flags);
773 + if (!req)
774 + return NULL;
775 +
776 + INIT_LIST_HEAD(&req->queue);
777 + req->req.dma = DMA_ADDR_INVALID;
778 +
779 + return &req->req;
780 +}
781 +
782 +static void
783 +husb2_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
784 +{
785 + struct husb2_request *req = to_husb2_req(_req);
786 +
787 + DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
788 +
789 + kfree(req);
790 +}
791 +
792 +static void *husb2_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
793 + dma_addr_t *dma, unsigned gfp_flags)
794 +{
795 + struct husb2_ep *ep = to_husb2_ep(_ep);
796 + void *buf;
797 +
798 + /*
799 + * We depend on kmalloc() returning cache-aligned memory. This
800 + * is normally guaranteed as long as we allocate a whole
801 + * cacheline or more.
802 + *
803 + * When CONFIG_DEBUG_SLAB is enabled, however, the slab
804 + * allocator inserts red zones and ownership information,
805 + * causing the slab objects to be misaligned.
806 + *
807 + * One alternative would be to use dma_alloc_coherent, but
808 + * that would make us unable to allocate anything less than a
809 + * page at a time.
810 + */
811 +#ifdef CONFIG_DEBUG_SLAB
812 +# error The HUSB2 UDC driver breaks with SLAB debugging enabled
813 +#endif
814 +
815 + if (bytes < L1_CACHE_BYTES)
816 + bytes = L1_CACHE_BYTES;
817 +
818 + buf = kmalloc(bytes, gfp_flags);
819 +
820 + /*
821 + * Seems like we have to map the buffer any chance we get.
822 + * ether.c wants us to initialize the dma member of a
823 + * different request than the one receiving the buffer, so one
824 + * never knows...
825 + *
826 + * Ah, screw it. The ether driver is probably wrong, and this
827 + * is not the right place to do the mapping. The driver
828 + * shouldn't mess with our DMA mappings anyway.
829 + */
830 + *dma = DMA_ADDR_INVALID;
831 +
832 + DBG(DBG_GADGET, "ep_alloc_buffer: %s, %u, 0x%x -> %p\n",
833 + ep_name(ep), bytes, gfp_flags, buf);
834 +
835 + return buf;
836 +}
837 +
838 +static void husb2_ep_free_buffer(struct usb_ep *_ep, void *buf,
839 + dma_addr_t dma, unsigned bytes)
840 +{
841 + DBG(DBG_GADGET, "ep_free_buffer: %s, buf %p (size %u)\n",
842 + _ep->name, buf, bytes);
843 + kfree(buf);
844 +}
845 +
846 +static int queue_dma(struct husb2_udc *udc, struct husb2_ep *ep,
847 + struct husb2_request *req, unsigned int direction,
848 + gfp_t gfp_flags)
849 +{
850 + struct husb2_packet *pkt, *prev_pkt;
851 + unsigned int pkt_size, nr_pkts, i;
852 + unsigned int residue;
853 + dma_addr_t addr;
854 + unsigned long flags;
855 + u32 ctrl;
856 +
857 + req->using_dma = 1;
858 +
859 + if (req->req.length == 0) {
860 + if (!req->req.zero)
861 + return -EINVAL;
862 + req->send_zlp = 1;
863 +
864 + spin_lock_irqsave(&udc->lock, flags);
865 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
866 + list_add_tail(&req->queue, &ep->queue);
867 + spin_unlock_irqrestore(&udc->lock, flags);
868 +
869 + return 0;
870 + }
871 +
872 + if (req->req.dma == DMA_ADDR_INVALID)
873 + req->req.dma = dma_map_single(&udc->pdev->dev,
874 + req->req.buf,
875 + req->req.length,
876 + direction);
877 + else
878 + dma_sync_single_for_device(&udc->pdev->dev,
879 + req->req.dma,
880 + req->req.length,
881 + direction);
882 +
883 + pkt_size = ep->ep.maxpacket;
884 + nr_pkts = req->req.length / pkt_size;
885 + residue = req->req.length % pkt_size;
886 + if (residue != 0)
887 + nr_pkts++;
888 + else if (req->req.zero && ep_is_in(ep))
889 + /* ensure last packet is short */
890 + req->send_zlp = 1;
891 +
892 + req->nr_pkts = nr_pkts;
893 +
894 + req->packet = kzalloc(sizeof(*req->packet) * nr_pkts, gfp_flags);
895 + if (!req->packet)
896 + goto out_of_memory;
897 +
898 + addr = req->req.dma;
899 + ctrl = (HUSB2_BF(DMA_BUF_LEN, pkt_size)
900 + | HUSB2_BIT(DMA_CH_EN) | HUSB2_BIT(DMA_LINK)
901 + | HUSB2_BIT(DMA_END_TR_EN) | HUSB2_BIT(DMA_END_TR_IE));
902 + prev_pkt = NULL;
903 + pkt = NULL;
904 + DBG(DBG_DMA, "DMA descriptors:\n");
905 + for (i = 0; i < nr_pkts; i++) {
906 + pkt = &req->packet[i];
907 + pkt->desc = dma_pool_alloc(udc->desc_pool, gfp_flags,
908 + &pkt->desc_dma);
909 + if (!pkt->desc)
910 + goto out_of_memory;
911 +
912 + if (prev_pkt) {
913 + prev_pkt->desc->next = pkt->desc_dma;
914 + DBG(DBG_DMA, "[%d] n%08x a%08x c%08x\n",
915 + i - 1, prev_pkt->desc->next, prev_pkt->desc->addr,
916 + prev_pkt->desc->ctrl);
917 + }
918 + prev_pkt = pkt;
919 +
920 + pkt->desc->addr = addr;
921 + pkt->desc->ctrl = ctrl;
922 + addr += pkt_size;
923 + }
924 +
925 + /* special care is needed for the last packet... */
926 + ctrl = (HUSB2_BIT(DMA_CH_EN)
927 + | HUSB2_BIT(DMA_END_TR_EN) | HUSB2_BIT(DMA_END_TR_IE)
928 + | HUSB2_BIT(DMA_END_BUF_IE));
929 + if (ep_is_in(ep))
930 + ctrl |= HUSB2_BIT(DMA_END_BUF_EN);
931 + if (req->req.zero || residue)
932 + ctrl |= HUSB2_BF(DMA_BUF_LEN, residue);
933 + else
934 + ctrl |= HUSB2_BF(DMA_BUF_LEN, pkt_size);
935 + pkt->desc->ctrl = ctrl;
936 +
937 + DBG(DBG_DMA, "[%d] n%08x a%08x c%08x\n",
938 + i - 1, prev_pkt->desc->next, prev_pkt->desc->addr,
939 + prev_pkt->desc->ctrl);
940 +
941 + /* Add this request to the queue and try to chain the DMA descriptors */
942 + spin_lock_irqsave(&udc->lock, flags);
943 +
944 + /* If the DMA controller is idle, start it */
945 + if (list_empty(&ep->queue)) {
946 + husb2_dma_writel(ep, NXT_DSC, req->packet[0].desc_dma);
947 + husb2_dma_writel(ep, CONTROL, HUSB2_BIT(DMA_LINK));
948 + }
949 +
950 + list_add_tail(&req->queue, &ep->queue);
951 +
952 + spin_unlock_irqrestore(&udc->lock, flags);
953 +
954 + return 0;
955 +
956 +out_of_memory:
957 + printk(KERN_ERR "ERROR: Could not allocate DMA memory for endpoint %s\n",
958 + ep_name(ep));
959 + if (req->packet) {
960 + for (i = 0; i < nr_pkts; i++)
961 + if (req->packet[i].desc)
962 + dma_pool_free(udc->desc_pool,
963 + req->packet[i].desc,
964 + req->packet[i].desc_dma);
965 + kfree(req->packet);
966 + }
967 +
968 + return -ENOMEM;
969 +}
970 +
971 +static int husb2_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
972 + gfp_t gfp_flags)
973 +{
974 + struct husb2_request *req = to_husb2_req(_req);
975 + struct husb2_ep *ep = to_husb2_ep(_ep);
976 + struct husb2_udc *udc = ep->udc;
977 + unsigned long flags;
978 + int direction_in = 0;
979 +
980 + DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ,
981 + "%s: queue req %p, len %u\n", ep_name(ep), req, _req->length);
982 +
983 + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
984 + return -ESHUTDOWN;
985 + if (!ep->desc)
986 + return -ENODEV;
987 +
988 + req->nr_pkts = 0;
989 + req->submitted = 0;
990 + req->using_dma = 0;
991 + req->last_transaction = 0;
992 + req->send_zlp = 0;
993 +
994 + BUG_ON(req->packet);
995 +
996 + if (ep_is_in(ep)
997 + || (ep_is_control(ep) && (ep->state == DATA_STAGE_IN
998 + || ep->state == STATUS_STAGE_IN)))
999 + direction_in = 1;
1000 +
1001 + _req->status = -EINPROGRESS;
1002 + _req->actual = 0;
1003 +
1004 + if (ep_can_dma(ep)) {
1005 + return queue_dma(udc, ep, req, (direction_in
1006 + ? DMA_TO_DEVICE
1007 + : DMA_FROM_DEVICE),
1008 + gfp_flags);
1009 + } else {
1010 + spin_lock_irqsave(&udc->lock, flags);
1011 + list_add_tail(&req->queue, &ep->queue);
1012 +
1013 + if (direction_in)
1014 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
1015 + else
1016 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(RX_BK_RDY));
1017 + spin_unlock_irqrestore(&udc->lock, flags);
1018 + }
1019 +
1020 + return 0;
1021 +}
1022 +
1023 +static void husb2_update_req(struct husb2_ep *ep, struct husb2_request *req,
1024 + u32 status)
1025 +{
1026 + struct husb2_dma_desc *desc;
1027 + dma_addr_t from;
1028 + dma_addr_t addr;
1029 + size_t size;
1030 + unsigned int i;
1031 +
1032 + addr = husb2_dma_readl(ep, ADDRESS);
1033 + req->req.actual = 0;
1034 +
1035 + for (i = 0; i < req->nr_pkts; i++) {
1036 + desc = req->packet[i].desc;
1037 + from = desc->addr;
1038 + size = HUSB2_BFEXT(DMA_BUF_LEN, desc->ctrl);
1039 +
1040 + req->req.actual += size;
1041 +
1042 + DBG(DBG_DMA, " from=%#08x, size=%#zx\n", from, size);
1043 +
1044 + if (from <= addr && (from + size) >= addr)
1045 + break;
1046 + }
1047 +
1048 + req->req.actual -= HUSB2_BFEXT(DMA_BUF_LEN, status);
1049 +}
1050 +
1051 +static int stop_dma(struct husb2_ep *ep, u32 *pstatus)
1052 +{
1053 + unsigned int timeout;
1054 + u32 status;
1055 +
1056 + /*
1057 + * Stop the DMA controller. When writing both CH_EN
1058 + * and LINK to 0, the other bits are not affected.
1059 + */
1060 + husb2_dma_writel(ep, CONTROL, 0);
1061 +
1062 + /* Wait for the FIFO to empty */
1063 + for (timeout = 40; timeout; --timeout) {
1064 + status = husb2_dma_readl(ep, STATUS);
1065 + if (!(status & HUSB2_BIT(DMA_CH_EN)))
1066 + break;
1067 + udelay(1);
1068 + }
1069 +
1070 + if (pstatus)
1071 + *pstatus = status;
1072 +
1073 + if (timeout == 0) {
1074 + dev_err(&ep->udc->pdev->dev,
1075 + "%s: timed out waiting for DMA FIFO to empty\n",
1076 + ep_name(ep));
1077 + return -ETIMEDOUT;
1078 + }
1079 +
1080 + return 0;
1081 +}
1082 +
1083 +static int husb2_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1084 +{
1085 + struct husb2_ep *ep = to_husb2_ep(_ep);
1086 + struct husb2_udc *udc = ep->udc;
1087 + struct husb2_request *req = to_husb2_req(_req);
1088 + unsigned long flags;
1089 + u32 status;
1090 +
1091 + DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n", ep_name(ep), req);
1092 +
1093 + spin_lock_irqsave(&udc->lock, flags);
1094 +
1095 + if (req->using_dma) {
1096 + /*
1097 + * If this request is currently being transferred,
1098 + * stop the DMA controller and reset the FIFO.
1099 + */
1100 + if (ep->queue.next == &req->queue) {
1101 + status = husb2_dma_readl(ep, STATUS);
1102 + if (status & HUSB2_BIT(DMA_CH_EN))
1103 + stop_dma(ep, &status);
1104 +
1105 +#ifdef CONFIG_DEBUG_FS
1106 + ep->last_dma_status = status;
1107 +#endif
1108 +
1109 + husb2_writel(udc, EPT_RST,
1110 + 1 << ep_index(ep));
1111 +
1112 + husb2_update_req(ep, req, status);
1113 + }
1114 + }
1115 +
1116 + /*
1117 + * Errors should stop the queue from advancing until the
1118 + * completion function returns.
1119 + */
1120 + list_del_init(&req->queue);
1121 + spin_unlock_irqrestore(&udc->lock, flags);
1122 +
1123 + request_complete(ep, req, -ECONNRESET);
1124 +
1125 + /* Process the next request if any */
1126 + spin_lock_irqsave(&udc->lock, flags);
1127 + submit_next_request(ep);
1128 + spin_unlock_irqrestore(&udc->lock, flags);
1129 +
1130 + return 0;
1131 +}
1132 +
1133 +static int husb2_ep_set_halt(struct usb_ep *_ep, int value)
1134 +{
1135 + struct husb2_ep *ep = to_husb2_ep(_ep);
1136 + struct husb2_udc *udc = ep->udc;
1137 + unsigned long flags;
1138 + int ret = 0;
1139 +
1140 + DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep_name(ep),
1141 + value ? "set" : "clear");
1142 +
1143 + if (!ep->desc) {
1144 + DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
1145 + ep_name(ep));
1146 + return -ENODEV;
1147 + }
1148 + if (ep_is_isochronous(ep)) {
1149 + DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
1150 + ep_name(ep));
1151 + return -ENOTTY;
1152 + }
1153 +
1154 + spin_lock_irqsave(&udc->lock, flags);
1155 +
1156 + /*
1157 + * We can't halt IN endpoints while there are still data to be
1158 + * transferred
1159 + */
1160 + if (!list_empty(&ep->queue)
1161 + || ((value && ep_is_in(ep)
1162 + && (husb2_ep_readl(ep, STA)
1163 + & HUSB2_BF(BUSY_BANKS, -1L))))) {
1164 + ret = -EAGAIN;
1165 + } else {
1166 + if (value)
1167 + husb2_ep_writel(ep, SET_STA, HUSB2_BIT(FORCE_STALL));
1168 + else
1169 + husb2_ep_writel(ep, CLR_STA, (HUSB2_BIT(FORCE_STALL)
1170 + | HUSB2_BIT(TOGGLE_SEQ)));
1171 + husb2_ep_readl(ep, STA);
1172 + }
1173 +
1174 + spin_unlock_irqrestore(&udc->lock, flags);
1175 +
1176 + return ret;
1177 +}
1178 +
1179 +static int husb2_ep_fifo_status(struct usb_ep *_ep)
1180 +{
1181 + struct husb2_ep *ep = to_husb2_ep(_ep);
1182 +
1183 + return HUSB2_BFEXT(BYTE_COUNT, husb2_ep_readl(ep, STA));
1184 +}
1185 +
1186 +static void husb2_ep_fifo_flush(struct usb_ep *_ep)
1187 +{
1188 + struct husb2_ep *ep = to_husb2_ep(_ep);
1189 + struct husb2_udc *udc = ep->udc;
1190 +
1191 + husb2_writel(udc, EPT_RST, 1 << ep->index);
1192 +}
1193 +
1194 +struct usb_ep_ops husb2_ep_ops = {
1195 + .enable = husb2_ep_enable,
1196 + .disable = husb2_ep_disable,
1197 + .alloc_request = husb2_ep_alloc_request,
1198 + .free_request = husb2_ep_free_request,
1199 + .alloc_buffer = husb2_ep_alloc_buffer,
1200 + .free_buffer = husb2_ep_free_buffer,
1201 + .queue = husb2_ep_queue,
1202 + .dequeue = husb2_ep_dequeue,
1203 + .set_halt = husb2_ep_set_halt,
1204 + .fifo_status = husb2_ep_fifo_status,
1205 + .fifo_flush = husb2_ep_fifo_flush,
1206 +};
1207 +
1208 +static int husb2_udc_get_frame(struct usb_gadget *gadget)
1209 +{
1210 + struct husb2_udc *udc = to_husb2_udc(gadget);
1211 +
1212 + return HUSB2_BFEXT(FRAME_NUMBER, husb2_readl(udc, FNUM));
1213 +}
1214 +
1215 +struct usb_gadget_ops husb2_udc_ops = {
1216 + .get_frame = husb2_udc_get_frame,
1217 +};
1218 +
1219 +#define EP(nam, type, idx, caps) { \
1220 + .ep = { \
1221 + .ops = &husb2_ep_ops, \
1222 + .name = nam, \
1223 + .maxpacket = type##_FIFO_SIZE, \
1224 + }, \
1225 + .udc = &the_udc, \
1226 + .queue = LIST_HEAD_INIT(husb2_ep[idx].queue), \
1227 + .fifo_size = type##_FIFO_SIZE, \
1228 + .nr_banks = type##_NR_BANKS, \
1229 + .index = idx, \
1230 + .capabilities = caps, \
1231 +}
1232 +
1233 +static struct husb2_ep husb2_ep[] = {
1234 + EP("ep0", EP0, 0, 0),
1235 + EP("ep1in-bulk", BULK, 1, HUSB2_EP_CAP_DMA),
1236 + EP("ep2out-bulk", BULK, 2, HUSB2_EP_CAP_DMA),
1237 + EP("ep3in-iso", ISO, 3, HUSB2_EP_CAP_DMA | HUSB2_EP_CAP_ISOC),
1238 + EP("ep4out-iso", ISO, 4, HUSB2_EP_CAP_DMA | HUSB2_EP_CAP_ISOC),
1239 + EP("ep5in-int", INT, 5, HUSB2_EP_CAP_DMA),
1240 + EP("ep6out-int", INT, 6, HUSB2_EP_CAP_DMA),
1241 +};
1242 +#undef EP
1243 +
1244 +static struct usb_endpoint_descriptor husb2_ep0_desc = {
1245 + .bLength = USB_DT_ENDPOINT_SIZE,
1246 + .bDescriptorType = USB_DT_ENDPOINT,
1247 + .bEndpointAddress = 0,
1248 + .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1249 + .wMaxPacketSize = __constant_cpu_to_le16(64),
1250 + /* FIXME: I have no idea what to put here */
1251 + .bInterval = 1,
1252 +};
1253 +
1254 +static void nop_release(struct device *dev)
1255 +{
1256 +
1257 +}
1258 +
1259 +static struct husb2_udc the_udc = {
1260 + .gadget = {
1261 + .ops = &husb2_udc_ops,
1262 + .ep0 = &husb2_ep[0].ep,
1263 + .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
1264 + .is_dualspeed = 1,
1265 + .name = "husb2_udc",
1266 + .dev = {
1267 + .bus_id = "gadget",
1268 + .release = nop_release,
1269 + },
1270 + },
1271 +
1272 + .lock = SPIN_LOCK_UNLOCKED,
1273 +};
1274 +
1275 +static void udc_enable(struct husb2_udc *udc)
1276 +{
1277 + struct husb2_ep *ep0 = &husb2_ep[0];
1278 +
1279 + /* Enable the controller */
1280 + husb2_writel(udc, CTRL, HUSB2_BIT(EN_HUSB2));
1281 +
1282 + /* Reset all endpoints and enable basic interrupts */
1283 + husb2_writel(udc, EPT_RST, ~0UL);
1284 + husb2_writel(udc, INT_ENB, (HUSB2_BIT(DET_SUSPEND)
1285 + | HUSB2_BIT(END_OF_RESET)
1286 + | HUSB2_BIT(END_OF_RESUME)));
1287 +
1288 + /* Configure endpoint 0 */
1289 + ep0->desc = &husb2_ep0_desc;
1290 +
1291 + husb2_writel(udc, EPT_RST, 1 << 0);
1292 + husb2_ep_writel(ep0, CTL_ENB, HUSB2_BIT(EPT_ENABLE));
1293 + husb2_ep_writel(ep0, CFG, (HUSB2_BF(EPT_SIZE, EP0_EPT_SIZE)
1294 + | HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_CONTROL)
1295 + | HUSB2_BF(BK_NUMBER, HUSB2_BK_NUMBER_ONE)));
1296 +
1297 + husb2_ep_writel(ep0, CTL_ENB, HUSB2_BIT(RX_SETUP));
1298 + husb2_writel(udc, INT_ENB, (husb2_readl(udc, INT_ENB)
1299 + | HUSB2_BF(EPT_INT, 1)));
1300 +
1301 + if (!(husb2_ep_readl(ep0, CFG) & HUSB2_BIT(EPT_MAPPED)))
1302 + dev_warn(&udc->pdev->dev,
1303 + "WARNING: EP0 configuration is invalid!\n");
1304 +}
1305 +
1306 +static void udc_disable(struct husb2_udc *udc)
1307 +{
1308 + udc->gadget.speed = USB_SPEED_UNKNOWN;
1309 +
1310 + husb2_writel(udc, CTRL, 0);
1311 +}
1312 +
1313 +/*
1314 + * Called with interrupts disabled and udc->lock held.
1315 + */
1316 +static void reset_all_endpoints(struct husb2_udc *udc)
1317 +{
1318 + struct husb2_ep *ep;
1319 + struct husb2_request *req, *tmp_req;
1320 +
1321 + husb2_writel(udc, EPT_RST, ~0UL);
1322 +
1323 + ep = to_husb2_ep(udc->gadget.ep0);
1324 + list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
1325 + list_del_init(&req->queue);
1326 + request_complete(ep, req, -ECONNRESET);
1327 + }
1328 + BUG_ON(!list_empty(&ep->queue));
1329 +
1330 + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1331 + if (ep->desc)
1332 + husb2_ep_disable(&ep->ep);
1333 + }
1334 +}
1335 +
1336 +static struct husb2_ep *get_ep_by_addr(struct husb2_udc *udc, u16 wIndex)
1337 +{
1338 + struct husb2_ep *ep;
1339 +
1340 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
1341 + return to_husb2_ep(udc->gadget.ep0);
1342 +
1343 + list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
1344 + u8 bEndpointAddress;
1345 +
1346 + if (!ep->desc)
1347 + continue;
1348 + bEndpointAddress = ep->desc->bEndpointAddress;
1349 + if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
1350 + continue;
1351 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
1352 + == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
1353 + return ep;
1354 + }
1355 +
1356 + return NULL;
1357 +}
1358 +
1359 +/* Called with interrupts disabled and udc->lock held */
1360 +static inline void set_protocol_stall(struct husb2_udc *udc,
1361 + struct husb2_ep *ep)
1362 +{
1363 + husb2_ep_writel(ep, SET_STA, HUSB2_BIT(FORCE_STALL));
1364 + ep->state = WAIT_FOR_SETUP;
1365 +}
1366 +
1367 +static inline int is_stalled(struct husb2_udc *udc, struct husb2_ep *ep)
1368 +{
1369 + if (husb2_ep_readl(ep, STA) & HUSB2_BIT(FORCE_STALL))
1370 + return 1;
1371 + return 0;
1372 +}
1373 +
1374 +static inline void set_address(struct husb2_udc *udc, unsigned int addr)
1375 +{
1376 + u32 regval;
1377 +
1378 + DBG(DBG_BUS, "setting address %u...\n", addr);
1379 + regval = husb2_readl(udc, CTRL);
1380 + regval = HUSB2_BFINS(DEV_ADDR, addr, regval);
1381 + husb2_writel(udc, CTRL, regval);
1382 +}
1383 +
1384 +static int handle_ep0_setup(struct husb2_udc *udc, struct husb2_ep *ep,
1385 + struct usb_ctrlrequest *crq)
1386 +{
1387 + switch (crq->bRequest) {
1388 + case USB_REQ_GET_STATUS: {
1389 + u16 status;
1390 +
1391 + if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
1392 + /* Self-powered, no remote wakeup */
1393 + status = __constant_cpu_to_le16(1 << 0);
1394 + } else if (crq->bRequestType
1395 + == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
1396 + status = __constant_cpu_to_le16(0);
1397 + } else if (crq->bRequestType
1398 + == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
1399 + struct husb2_ep *target;
1400 +
1401 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1402 + if (!target)
1403 + goto stall;
1404 +
1405 + status = 0;
1406 + if (is_stalled(udc, target))
1407 + status |= __constant_cpu_to_le16(1);
1408 + } else {
1409 + goto delegate;
1410 + }
1411 +
1412 + /* Write directly to the FIFO. No queueing is done. */
1413 + if(crq->wLength != __constant_cpu_to_le16(sizeof(status)))
1414 + goto stall;
1415 + ep->state = DATA_STAGE_IN;
1416 + __raw_writew(status, ep->fifo);
1417 + husb2_ep_writel(ep, SET_STA, HUSB2_BIT(TX_PK_RDY));
1418 + break;
1419 + }
1420 +
1421 + case USB_REQ_CLEAR_FEATURE: {
1422 + if (crq->bRequestType == USB_RECIP_DEVICE) {
1423 + /* We don't support TEST_MODE */
1424 + goto stall;
1425 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1426 + struct husb2_ep *target;
1427 +
1428 + if (crq->wValue != __constant_cpu_to_le16(USB_ENDPOINT_HALT)
1429 + || crq->wLength != __constant_cpu_to_le16(0))
1430 + goto stall;
1431 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1432 + if (!target)
1433 + goto stall;
1434 +
1435 + husb2_ep_writel(target, CLR_STA, (HUSB2_BIT(FORCE_STALL)
1436 + | HUSB2_BIT(TOGGLE_SEQ)));
1437 + } else {
1438 + goto delegate;
1439 + }
1440 +
1441 + send_status(udc, ep);
1442 + break;
1443 + }
1444 +
1445 + case USB_REQ_SET_FEATURE: {
1446 + if (crq->bRequestType == USB_RECIP_DEVICE) {
1447 + /* We don't support TEST_MODE */
1448 + goto stall;
1449 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1450 + struct husb2_ep *target;
1451 +
1452 + if (crq->wValue != __constant_cpu_to_le16(USB_ENDPOINT_HALT)
1453 + || crq->wLength != __constant_cpu_to_le16(0))
1454 + goto stall;
1455 +
1456 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1457 + if (!target)
1458 + goto stall;
1459 +
1460 + husb2_ep_writel(target, SET_STA, HUSB2_BIT(FORCE_STALL));
1461 + } else
1462 + goto delegate;
1463 +
1464 + send_status(udc, ep);
1465 + break;
1466 + }
1467 +
1468 + case USB_REQ_SET_ADDRESS:
1469 + if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
1470 + goto delegate;
1471 +
1472 + set_address(udc, le16_to_cpu(crq->wValue));
1473 + send_status(udc, ep);
1474 + ep->state = STATUS_STAGE_ADDR;
1475 + break;
1476 +
1477 + default:
1478 + delegate:
1479 + return udc->driver->setup(&udc->gadget, crq);
1480 + }
1481 +
1482 + return 0;
1483 +
1484 +stall:
1485 + printk(KERN_ERR
1486 + "udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
1487 + "halting endpoint...\n",
1488 + ep_name(ep), crq->bRequestType, crq->bRequest,
1489 + le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
1490 + le16_to_cpu(crq->wLength));
1491 + set_protocol_stall(udc, ep);
1492 + return -1;
1493 +}
1494 +
1495 +static void husb2_control_irq(struct husb2_udc *udc, struct husb2_ep *ep)
1496 +{
1497 + struct husb2_request *req;
1498 + u32 epstatus;
1499 + u32 epctrl;
1500 +
1501 +restart:
1502 + epstatus = husb2_ep_readl(ep, STA);
1503 + epctrl = husb2_ep_readl(ep, CTL);
1504 +
1505 + DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n",
1506 + ep_name(ep), epstatus);
1507 +
1508 + req = NULL;
1509 + if (!list_empty(&ep->queue))
1510 + req = list_entry(ep->queue.next,
1511 + struct husb2_request, queue);
1512 +
1513 + if ((epctrl & HUSB2_BIT(TX_PK_RDY))
1514 + && !(epstatus & HUSB2_BIT(TX_PK_RDY))) {
1515 + DBG(DBG_BUS, "tx pk rdy: %d\n", ep->state);
1516 +
1517 + if (req->submitted)
1518 + next_fifo_transaction(ep, req);
1519 + else
1520 + submit_request(ep, req);
1521 +
1522 + if (req->last_transaction) {
1523 + husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(TX_PK_RDY));
1524 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_COMPLETE));
1525 + }
1526 + goto restart;
1527 + }
1528 + if ((epstatus & epctrl) & HUSB2_BIT(TX_COMPLETE)) {
1529 + husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(TX_COMPLETE));
1530 + DBG(DBG_BUS, "txc: %d\n", ep->state);
1531 +
1532 + switch (ep->state) {
1533 + case DATA_STAGE_IN:
1534 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(RX_BK_RDY));
1535 + husb2_ep_writel(ep, CTL_DIS,
1536 + HUSB2_BIT(TX_COMPLETE));
1537 + ep->state = STATUS_STAGE_OUT;
1538 + break;
1539 + case STATUS_STAGE_ADDR:
1540 + /* Activate our new address */
1541 + husb2_writel(udc, CTRL, (husb2_readl(udc, CTRL)
1542 + | HUSB2_BIT(FADDR_EN)));
1543 + husb2_ep_writel(ep, CTL_DIS,
1544 + HUSB2_BIT(TX_COMPLETE));
1545 + ep->state = WAIT_FOR_SETUP;
1546 + break;
1547 + case STATUS_STAGE_IN:
1548 + if (req) {
1549 + list_del_init(&req->queue);
1550 + request_complete(ep, req, 0);
1551 + submit_next_request(ep);
1552 + }
1553 + BUG_ON(!list_empty(&ep->queue));
1554 + husb2_ep_writel(ep, CTL_DIS,
1555 + HUSB2_BIT(TX_COMPLETE));
1556 + ep->state = WAIT_FOR_SETUP;
1557 + break;
1558 + default:
1559 + printk(KERN_ERR
1560 + "udc: %s: TXCOMP: Invalid endpoint state %d, "
1561 + "halting endpoint...\n",
1562 + ep_name(ep), ep->state);
1563 + set_protocol_stall(udc, ep);
1564 + break;
1565 + }
1566 +
1567 + goto restart;
1568 + }
1569 + if ((epstatus & epctrl) & HUSB2_BIT(RX_BK_RDY)) {
1570 + DBG(DBG_BUS, "rxc: %d\n", ep->state);
1571 +
1572 + switch (ep->state) {
1573 + case STATUS_STAGE_OUT:
1574 + husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
1575 +
1576 + if (req) {
1577 + list_del_init(&req->queue);
1578 + request_complete(ep, req, 0);
1579 + }
1580 + husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(RX_BK_RDY));
1581 + ep->state = WAIT_FOR_SETUP;
1582 + break;
1583 +
1584 + case DATA_STAGE_OUT:
1585 + receive_data(ep);
1586 + break;
1587 +
1588 + default:
1589 + husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
1590 + set_protocol_stall(udc, ep);
1591 + printk(KERN_ERR
1592 + "udc: %s: RXRDY: Invalid endpoint state %d, "
1593 + "halting endpoint...\n",
1594 + ep_name(ep), ep->state);
1595 + break;
1596 + }
1597 +
1598 + goto restart;
1599 + }
1600 + if (epstatus & HUSB2_BIT(RX_SETUP)) {
1601 + union {
1602 + struct usb_ctrlrequest crq;
1603 + unsigned long data[2];
1604 + } crq;
1605 + unsigned int pkt_len;
1606 + int ret;
1607 +
1608 + if (ep->state != WAIT_FOR_SETUP) {
1609 + /*
1610 + * Didn't expect a SETUP packet at this
1611 + * point. Clean up any pending requests (which
1612 + * may be successful).
1613 + */
1614 + int status = -EPROTO;
1615 +
1616 + /*
1617 + * RXRDY is dropped when SETUP packets arrive.
1618 + * Just pretend we received the status packet.
1619 + */
1620 + if (ep->state == STATUS_STAGE_OUT)
1621 + status = 0;
1622 +
1623 + if (req) {
1624 + list_del_init(&req->queue);
1625 + request_complete(ep, req, status);
1626 + }
1627 + BUG_ON(!list_empty(&ep->queue));
1628 + }
1629 +
1630 + pkt_len = HUSB2_BFEXT(BYTE_COUNT, husb2_ep_readl(ep, STA));
1631 + DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1632 + BUG_ON(pkt_len != sizeof(crq));
1633 +
1634 + DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
1635 + copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
1636 +
1637 + /* Free up one bank in the FIFO so that we can
1638 + * generate or receive a reply right away. */
1639 + husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_SETUP));
1640 +
1641 + /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
1642 + ep->state, crq.crq.bRequestType,
1643 + crq.crq.bRequest); */
1644 +
1645 + if (crq.crq.bRequestType & USB_DIR_IN) {
1646 + /*
1647 + * The USB 2.0 spec states that "if wLength is
1648 + * zero, there is no data transfer phase."
1649 + * However, testusb #14 seems to actually
1650 + * expect a data phase even if wLength = 0...
1651 + */
1652 + ep->state = DATA_STAGE_IN;
1653 + } else {
1654 + if (crq.crq.wLength != __constant_cpu_to_le16(0))
1655 + ep->state = DATA_STAGE_OUT;
1656 + else
1657 + ep->state = STATUS_STAGE_IN;
1658 + }
1659 +
1660 + ret = -1;
1661 + if (ep->index == 0)
1662 + ret = handle_ep0_setup(udc, ep, &crq.crq);
1663 + else
1664 + ret = udc->driver->setup(&udc->gadget, &crq.crq);
1665 +
1666 + DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
1667 + crq.crq.bRequestType, crq.crq.bRequest,
1668 + le16_to_cpu(crq.crq.wLength), ep->state, ret);
1669 +
1670 + if (ret < 0) {
1671 + /* Let the host know that we failed */
1672 + set_protocol_stall(udc, ep);
1673 + }
1674 + }
1675 +}
1676 +
1677 +static void husb2_ep_irq(struct husb2_udc *udc, struct husb2_ep *ep)
1678 +{
1679 + struct husb2_request *req;
1680 + u32 epstatus;
1681 + u32 epctrl;
1682 +
1683 + epstatus = husb2_ep_readl(ep, STA);
1684 + epctrl = husb2_ep_readl(ep, CTL);
1685 +
1686 + DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n",
1687 + ep_name(ep), epstatus);
1688 +
1689 + while ((epctrl & HUSB2_BIT(TX_PK_RDY))
1690 + && !(epstatus & HUSB2_BIT(TX_PK_RDY))) {
1691 + BUG_ON(!ep_is_in(ep));
1692 +
1693 + DBG(DBG_BUS, "%s: TX PK ready\n", ep_name(ep));
1694 +
1695 + if (list_empty(&ep->queue)) {
1696 + dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
1697 + husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(TX_PK_RDY));
1698 + return;
1699 + }
1700 +
1701 + req = list_entry(ep->queue.next, struct husb2_request, queue);
1702 +
1703 + if (req->using_dma) {
1704 + BUG_ON(!req->send_zlp);
1705 +
1706 + /* Send a zero-length packet */
1707 + husb2_ep_writel(ep, SET_STA,
1708 + HUSB2_BIT(TX_PK_RDY));
1709 + husb2_ep_writel(ep, CTL_DIS,
1710 + HUSB2_BIT(TX_PK_RDY));
1711 + list_del_init(&req->queue);
1712 + submit_next_request(ep);
1713 + request_complete(ep, req, 0);
1714 + } else {
1715 + if (req->submitted)
1716 + next_fifo_transaction(ep, req);
1717 + else
1718 + submit_request(ep, req);
1719 +
1720 + if (req->last_transaction) {
1721 + list_del_init(&req->queue);
1722 + submit_next_request(ep);
1723 + request_complete(ep, req, 0);
1724 + }
1725 + }
1726 +
1727 + epstatus = husb2_ep_readl(ep, STA);
1728 + epctrl = husb2_ep_readl(ep, CTL);
1729 + }
1730 + if ((epstatus & epctrl) & HUSB2_BIT(RX_BK_RDY)) {
1731 + BUG_ON(ep_is_in(ep));
1732 +
1733 + DBG(DBG_BUS, "%s: RX data ready\n", ep_name(ep));
1734 + receive_data(ep);
1735 + husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
1736 + }
1737 +}
1738 +
1739 +static void husb2_dma_irq(struct husb2_udc *udc, struct husb2_ep *ep)
1740 +{
1741 + struct husb2_request *req;
1742 + u32 status, control, pending;
1743 +
1744 + status = husb2_dma_readl(ep, STATUS);
1745 + control = husb2_dma_readl(ep, CONTROL);
1746 +#ifdef CONFIG_DEBUG_FS
1747 + ep->last_dma_status = status;
1748 +#endif
1749 + pending = status & control;
1750 + DBG(DBG_INT, "dma irq, status=%#08x, pending=%#08x, control=%#08x\n",
1751 + status, pending, control);
1752 +
1753 + BUG_ON(status & HUSB2_BIT(DMA_CH_EN));
1754 +
1755 + if (list_empty(&ep->queue))
1756 + /* Might happen if a reset comes along at the right moment */
1757 + return;
1758 +
1759 + if (pending & (HUSB2_BIT(DMA_END_TR_ST) | HUSB2_BIT(DMA_END_BUF_ST))) {
1760 + req = list_entry(ep->queue.next, struct husb2_request, queue);
1761 + husb2_update_req(ep, req, status);
1762 +
1763 + if (req->send_zlp) {
1764 + husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
1765 + } else {
1766 + list_del_init(&req->queue);
1767 + submit_next_request(ep);
1768 + request_complete(ep, req, 0);
1769 + }
1770 + }
1771 +}
1772 +
1773 +static irqreturn_t husb2_udc_irq(int irq, void *devid, struct pt_regs *regs)
1774 +{
1775 + struct husb2_udc *udc = devid;
1776 + u32 status;
1777 + u32 dma_status;
1778 + u32 ep_status;
1779 +
1780 + spin_lock(&udc->lock);
1781 +
1782 + status = husb2_readl(udc, INT_STA);
1783 + DBG(DBG_INT, "irq, status=%#08x\n", status);
1784 +
1785 + if (status & HUSB2_BIT(DET_SUSPEND)) {
1786 + husb2_writel(udc, INT_CLR, HUSB2_BIT(DET_SUSPEND));
1787 + //DBG(DBG_BUS, "Suspend detected\n");
1788 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
1789 + && udc->driver && udc->driver->suspend)
1790 + udc->driver->suspend(&udc->gadget);
1791 + }
1792 +
1793 + if (status & HUSB2_BIT(WAKE_UP)) {
1794 + husb2_writel(udc, INT_CLR, HUSB2_BIT(WAKE_UP));
1795 + //DBG(DBG_BUS, "Wake Up CPU detected\n");
1796 + }
1797 +
1798 + if (status & HUSB2_BIT(END_OF_RESUME)) {
1799 + husb2_writel(udc, INT_CLR, HUSB2_BIT(END_OF_RESUME));
1800 + DBG(DBG_BUS, "Resume detected\n");
1801 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
1802 + && udc->driver && udc->driver->resume)
1803 + udc->driver->resume(&udc->gadget);
1804 + }
1805 +
1806 + dma_status = HUSB2_BFEXT(DMA_INT, status);
1807 + if (dma_status) {
1808 + int i;
1809 +
1810 + for (i = 1; i < HUSB2_NR_ENDPOINTS; i++)
1811 + if (dma_status & (1 << i))
1812 + husb2_dma_irq(udc, &husb2_ep[i]);
1813 + }
1814 +
1815 + ep_status = HUSB2_BFEXT(EPT_INT, status);
1816 + if (ep_status) {
1817 + int i;
1818 +
1819 + for (i = 0; i < HUSB2_NR_ENDPOINTS; i++)
1820 + if (ep_status & (1 << i)) {
1821 + if (ep_is_control(&husb2_ep[i]))
1822 + husb2_control_irq(udc, &husb2_ep[i]);
1823 + else
1824 + husb2_ep_irq(udc, &husb2_ep[i]);
1825 + }
1826 + }
1827 +
1828 + if (status & HUSB2_BIT(END_OF_RESET)) {
1829 + husb2_writel(udc, INT_CLR, HUSB2_BIT(END_OF_RESET));
1830 + if (status & HUSB2_BIT(HIGH_SPEED)) {
1831 + DBG(DBG_BUS, "High-speed bus reset detected\n");
1832 + udc->gadget.speed = USB_SPEED_HIGH;
1833 + } else {
1834 + DBG(DBG_BUS, "Full-speed bus reset detected\n");
1835 + udc->gadget.speed = USB_SPEED_FULL;
1836 + }
1837 + /* Better start from scratch... */
1838 + reset_all_endpoints(udc);
1839 + husb2_ep[0].state = WAIT_FOR_SETUP;
1840 + udc_enable(udc);
1841 + }
1842 +
1843 + spin_unlock(&udc->lock);
1844 +
1845 + return IRQ_HANDLED;
1846 +}
1847 +
1848 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1849 +{
1850 + struct husb2_udc *udc = &the_udc;
1851 + int ret;
1852 +
1853 + spin_lock(&udc->lock);
1854 +
1855 + ret = -ENODEV;
1856 + if (!udc->pdev)
1857 + goto out;
1858 + ret = -EBUSY;
1859 + if (udc->driver)
1860 + goto out;
1861 +
1862 + udc->driver = driver;
1863 + udc->gadget.dev.driver = &driver->driver;
1864 +
1865 + device_add(&udc->gadget.dev);
1866 + ret = driver->bind(&udc->gadget);
1867 + if (ret) {
1868 + DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
1869 + driver->driver.name, ret);
1870 + device_del(&udc->gadget.dev);
1871 +
1872 + udc->driver = NULL;
1873 + udc->gadget.dev.driver = NULL;
1874 + goto out;
1875 + }
1876 +
1877 + /* TODO: Create sysfs files */
1878 +
1879 + DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
1880 + udc_enable(udc);
1881 +
1882 +out:
1883 + spin_unlock(&udc->lock);
1884 + return ret;
1885 +}
1886 +EXPORT_SYMBOL(usb_gadget_register_driver);
1887 +
1888 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1889 +{
1890 + struct husb2_udc *udc = &the_udc;
1891 + int ret;
1892 +
1893 + spin_lock(&udc->lock);
1894 +
1895 + ret = -ENODEV;
1896 + if (!udc->pdev)
1897 + goto out;
1898 + ret = -EINVAL;
1899 + if (driver != udc->driver)
1900 + goto out;
1901 +
1902 + local_irq_disable();
1903 + udc_disable(udc);
1904 + local_irq_enable();
1905 +
1906 + driver->unbind(&udc->gadget);
1907 + udc->driver = NULL;
1908 +
1909 + device_del(&udc->gadget.dev);
1910 +
1911 + /* TODO: Remove sysfs files */
1912 +
1913 + DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
1914 +
1915 +out:
1916 + spin_unlock(&udc->lock);
1917 + return ret;
1918 +}
1919 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
1920 +
1921 +static int __devinit husb2_udc_probe(struct platform_device *pdev)
1922 +{
1923 + struct resource *regs, *fifo;
1924 + struct clk *pclk, *hclk;
1925 + struct husb2_udc *udc = &the_udc;
1926 + int irq, ret, i;
1927 +
1928 + regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
1929 + fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
1930 + if (!regs || !fifo)
1931 + return -ENXIO;
1932 +
1933 + irq = platform_get_irq(pdev, 0);
1934 + if (irq < 0)
1935 + return irq;
1936 +
1937 + pclk = clk_get(&pdev->dev, "pclk");
1938 + if (IS_ERR(pclk))
1939 + return PTR_ERR(pclk);
1940 + hclk = clk_get(&pdev->dev, "hclk");
1941 + if (IS_ERR(hclk)) {
1942 + ret = PTR_ERR(hclk);
1943 + goto out_put_pclk;
1944 + }
1945 +
1946 + clk_enable(pclk);
1947 + clk_enable(hclk);
1948 +
1949 + udc->pdev = pdev;
1950 + udc->pclk = pclk;
1951 + udc->hclk = hclk;
1952 +
1953 + ret = -ENOMEM;
1954 + udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
1955 + if (!udc->regs) {
1956 + dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
1957 + goto out_disable_clocks;
1958 + }
1959 + dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
1960 + (unsigned long)regs->start, udc->regs);
1961 + udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
1962 + if (!udc->fifo) {
1963 + dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
1964 + goto out_unmap_regs;
1965 + }
1966 + dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
1967 + (unsigned long)fifo->start, udc->fifo);
1968 +
1969 + device_initialize(&udc->gadget.dev);
1970 + udc->gadget.dev.parent = &pdev->dev;
1971 + udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
1972 +
1973 + /* The 3-word descriptors must be 4-word aligned... */
1974 + udc->desc_pool = dma_pool_create("husb2-desc", &pdev->dev,
1975 + sizeof(struct husb2_dma_desc),
1976 + 16, 0);
1977 + if (!udc->desc_pool) {
1978 + dev_err(&pdev->dev, "Cannot create descriptor DMA pool\n");
1979 + goto out_unmap_fifo;
1980 + }
1981 +
1982 + platform_set_drvdata(pdev, udc);
1983 +
1984 + udc_disable(udc);
1985 +
1986 + INIT_LIST_HEAD(&husb2_ep[0].ep.ep_list);
1987 + husb2_ep[0].ep_regs = udc->regs + HUSB2_EPT_BASE(0);
1988 + husb2_ep[0].dma_regs = udc->regs + HUSB2_DMA_BASE(0);
1989 + husb2_ep[0].fifo = udc->fifo + HUSB2_FIFO_BASE(0);
1990 + for (i = 1; i < ARRAY_SIZE(husb2_ep); i++) {
1991 + struct husb2_ep *ep = &husb2_ep[i];
1992 +
1993 + ep->ep_regs = udc->regs + HUSB2_EPT_BASE(i);
1994 + ep->dma_regs = udc->regs + HUSB2_DMA_BASE(i);
1995 + ep->fifo = udc->fifo + HUSB2_FIFO_BASE(i);
1996 +
1997 + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1998 + }
1999 +
2000 + ret = request_irq(irq, husb2_udc_irq, SA_SAMPLE_RANDOM,
2001 + "husb2_udc", udc);
2002 + if (ret) {
2003 + dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
2004 + irq, ret);
2005 + goto out_free_pool;
2006 + }
2007 + udc->irq = irq;
2008 +
2009 + husb2_init_debugfs(udc);
2010 +
2011 + return 0;
2012 +
2013 +out_free_pool:
2014 + dma_pool_destroy(udc->desc_pool);
2015 +out_unmap_fifo:
2016 + iounmap(udc->fifo);
2017 +out_unmap_regs:
2018 + iounmap(udc->regs);
2019 +out_disable_clocks:
2020 + clk_disable(hclk);
2021 + clk_disable(pclk);
2022 + clk_put(hclk);
2023 +out_put_pclk:
2024 + clk_put(pclk);
2025 +
2026 + platform_set_drvdata(pdev, NULL);
2027 +
2028 + return ret;
2029 +}
2030 +
2031 +static int __devexit husb2_udc_remove(struct platform_device *pdev)
2032 +{
2033 + struct husb2_udc *udc;
2034 +
2035 + udc = platform_get_drvdata(pdev);
2036 + if (!udc)
2037 + return 0;
2038 +
2039 + husb2_cleanup_debugfs(udc);
2040 +
2041 + free_irq(udc->irq, udc);
2042 + dma_pool_destroy(udc->desc_pool);
2043 + iounmap(udc->fifo);
2044 + iounmap(udc->regs);
2045 + clk_disable(udc->hclk);
2046 + clk_disable(udc->pclk);
2047 + clk_put(udc->hclk);
2048 + clk_put(udc->pclk);
2049 + platform_set_drvdata(pdev, NULL);
2050 +
2051 + return 0;
2052 +}
2053 +
2054 +static struct platform_driver udc_driver = {
2055 + .probe = husb2_udc_probe,
2056 + .remove = __devexit_p(husb2_udc_remove),
2057 + .driver = {
2058 + .name = "usb",
2059 + },
2060 +};
2061 +
2062 +static int __init udc_init(void)
2063 +{
2064 + printk(KERN_INFO "husb2device: Driver version %s\n", DRIVER_VERSION);
2065 + return platform_driver_register(&udc_driver);
2066 +}
2067 +module_init(udc_init);
2068 +
2069 +static void __exit udc_exit(void)
2070 +{
2071 + platform_driver_unregister(&udc_driver);
2072 +}
2073 +module_exit(udc_exit);
2074 +
2075 +MODULE_DESCRIPTION("Atmel HUSB2 Device Controller driver");
2076 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
2077 +MODULE_LICENSE("GPL");
2078 Index: linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.h
2079 ===================================================================
2080 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2081 +++ linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.h 2006-11-02 16:03:44.000000000 +0100
2082 @@ -0,0 +1,406 @@
2083 +/*
2084 + * Driver for the Atmel HUSB2device high speed USB device controller
2085 + *
2086 + * Copyright (C) 2005-2006 Atmel Corporation
2087 + *
2088 + * This program is free software; you can redistribute it and/or modify
2089 + * it under the terms of the GNU General Public License version 2 as
2090 + * published by the Free Software Foundation.
2091 + */
2092 +#ifndef __LINUX_USB_GADGET_HUSB2_UDC_H__
2093 +#define __LINUX_USB_GADGET_HUSB2_UDC_H__
2094 +
2095 +/* USB register offsets */
2096 +#define HUSB2_CTRL 0x0000
2097 +#define HUSB2_FNUM 0x0004
2098 +#define HUSB2_INT_ENB 0x0010
2099 +#define HUSB2_INT_STA 0x0014
2100 +#define HUSB2_INT_CLR 0x0018
2101 +#define HUSB2_EPT_RST 0x001c
2102 +#define HUSB2_TST_SOF_CNT 0x00d0
2103 +#define HUSB2_TST_CNT_A 0x00d4
2104 +#define HUSB2_TST_CNT_B 0x00d8
2105 +#define HUSB2_TST_MODE_REG 0x00dc
2106 +#define HUSB2_TST 0x00f0
2107 +
2108 +/* USB endpoint register offsets */
2109 +#define HUSB2_EPT_CFG 0x0000
2110 +#define HUSB2_EPT_CTL_ENB 0x0004
2111 +#define HUSB2_EPT_CTL_DIS 0x0008
2112 +#define HUSB2_EPT_CTL 0x000c
2113 +#define HUSB2_EPT_SET_STA 0x0014
2114 +#define HUSB2_EPT_CLR_STA 0x0018
2115 +#define HUSB2_EPT_STA 0x001c
2116 +
2117 +/* USB DMA register offsets */
2118 +#define HUSB2_DMA_NXT_DSC 0x0000
2119 +#define HUSB2_DMA_ADDRESS 0x0004
2120 +#define HUSB2_DMA_CONTROL 0x0008
2121 +#define HUSB2_DMA_STATUS 0x000c
2122 +
2123 +/* Bitfields in CTRL */
2124 +#define HUSB2_DEV_ADDR_OFFSET 0
2125 +#define HUSB2_DEV_ADDR_SIZE 7
2126 +#define HUSB2_FADDR_EN_OFFSET 7
2127 +#define HUSB2_FADDR_EN_SIZE 1
2128 +#define HUSB2_EN_HUSB2_OFFSET 8
2129 +#define HUSB2_EN_HUSB2_SIZE 1
2130 +#define HUSB2_DETACH_OFFSET 9
2131 +#define HUSB2_DETACH_SIZE 1
2132 +#define HUSB2_REMOTE_WAKE_UP_OFFSET 10
2133 +#define HUSB2_REMOTE_WAKE_UP_SIZE 1
2134 +
2135 +/* Bitfields in FNUM */
2136 +#define HUSB2_MICRO_FRAME_NUM_OFFSET 0
2137 +#define HUSB2_MICRO_FRAME_NUM_SIZE 3
2138 +#define HUSB2_FRAME_NUMBER_OFFSET 3
2139 +#define HUSB2_FRAME_NUMBER_SIZE 11
2140 +#define HUSB2_FRAME_NUM_ERROR_OFFSET 31
2141 +#define HUSB2_FRAME_NUM_ERROR_SIZE 1
2142 +
2143 +/* Bitfields in INT_ENB/INT_STA/INT_CLR */
2144 +#define HUSB2_HIGH_SPEED_OFFSET 0
2145 +#define HUSB2_HIGH_SPEED_SIZE 1
2146 +#define HUSB2_DET_SUSPEND_OFFSET 1
2147 +#define HUSB2_DET_SUSPEND_SIZE 1
2148 +#define HUSB2_MICRO_SOF_OFFSET 2
2149 +#define HUSB2_MICRO_SOF_SIZE 1
2150 +#define HUSB2_SOF_OFFSET 3
2151 +#define HUSB2_SOF_SIZE 1
2152 +#define HUSB2_END_OF_RESET_OFFSET 4
2153 +#define HUSB2_END_OF_RESET_SIZE 1
2154 +#define HUSB2_WAKE_UP_OFFSET 5
2155 +#define HUSB2_WAKE_UP_SIZE 1
2156 +#define HUSB2_END_OF_RESUME_OFFSET 6
2157 +#define HUSB2_END_OF_RESUME_SIZE 1
2158 +#define HUSB2_UPSTREAM_RESUME_OFFSET 7
2159 +#define HUSB2_UPSTREAM_RESUME_SIZE 1
2160 +#define HUSB2_EPT_INT_OFFSET 8
2161 +#define HUSB2_EPT_INT_SIZE 16
2162 +#define HUSB2_DMA_INT_OFFSET 24
2163 +#define HUSB2_DMA_INT_SIZE 8
2164 +
2165 +/* Bitfields in EPT_RST */
2166 +#define HUSB2_RST_OFFSET 0
2167 +#define HUSB2_RST_SIZE 16
2168 +
2169 +/* Bitfields in TST_SOF_CNT */
2170 +#define HUSB2_SOF_CNT_MAX_OFFSET 0
2171 +#define HUSB2_SOF_CNT_MAX_SIZE 7
2172 +#define HUSB2_SOF_CNT_LOAD_OFFSET 7
2173 +#define HUSB2_SOF_CNT_LOAD_SIZE 1
2174 +
2175 +/* Bitfields in TST_CNT_A */
2176 +#define HUSB2_CNT_A_MAX_OFFSET 0
2177 +#define HUSB2_CNT_A_MAX_SIZE 7
2178 +#define HUSB2_CNT_A_LOAD_OFFSET 7
2179 +#define HUSB2_CNT_A_LOAD_SIZE 1
2180 +
2181 +/* Bitfields in TST_CNT_B */
2182 +#define HUSB2_CNT_B_MAX_OFFSET 0
2183 +#define HUSB2_CNT_B_MAX_SIZE 7
2184 +#define HUSB2_CNT_B_LOAD_OFFSET 7
2185 +#define HUSB2_CNT_B_LOAD_SIZE 1
2186 +
2187 +/* Bitfields in TST_MODE_REG */
2188 +#define HUSB2_TST_MODE_OFFSET 0
2189 +#define HUSB2_TST_MODE_SIZE 6
2190 +
2191 +/* Bitfields in HUSB2_TST */
2192 +#define HUSB2_SPEED_CFG_OFFSET 0
2193 +#define HUSB2_SPEED_CFG_SIZE 2
2194 +#define HUSB2_TST_J_MODE_OFFSET 2
2195 +#define HUSB2_TST_J_MODE_SIZE 1
2196 +#define HUSB2_TST_K_MODE_OFFSET 3
2197 +#define HUSB2_TST_K_MODE_SIZE 1
2198 +#define HUSB2_TST_PKT_MODE_OFFSE 4
2199 +#define HUSB2_TST_PKT_MODE_SIZE 1
2200 +#define HUSB2_OPMODE2_OFFSET 5
2201 +#define HUSB2_OPMODE2_SIZE 1
2202 +
2203 +/* Bitfields in EPT_CFG */
2204 +#define HUSB2_EPT_SIZE_OFFSET 0
2205 +#define HUSB2_EPT_SIZE_SIZE 3
2206 +#define HUSB2_EPT_DIR_OFFSET 3
2207 +#define HUSB2_EPT_DIR_SIZE 1
2208 +#define HUSB2_EPT_TYPE_OFFSET 4
2209 +#define HUSB2_EPT_TYPE_SIZE 2
2210 +#define HUSB2_BK_NUMBER_OFFSET 6
2211 +#define HUSB2_BK_NUMBER_SIZE 2
2212 +#define HUSB2_NB_TRANS_OFFSET 8
2213 +#define HUSB2_NB_TRANS_SIZE 2
2214 +#define HUSB2_EPT_MAPPED_OFFSET 31
2215 +#define HUSB2_EPT_MAPPED_SIZE 1
2216 +
2217 +/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
2218 +#define HUSB2_EPT_ENABLE_OFFSET 0
2219 +#define HUSB2_EPT_ENABLE_SIZE 1
2220 +#define HUSB2_AUTO_VALID_OFFSET 1
2221 +#define HUSB2_AUTO_VALID_SIZE 1
2222 +#define HUSB2_INT_DIS_DMA_OFFSET 3
2223 +#define HUSB2_INT_DIS_DMA_SIZE 1
2224 +#define HUSB2_NYET_DIS_OFFSET 4
2225 +#define HUSB2_NYET_DIS_SIZE 1
2226 +#define HUSB2_DATAX_RX_OFFSET 6
2227 +#define HUSB2_DATAX_RX_SIZE 1
2228 +#define HUSB2_MDATA_RX_OFFSET 7
2229 +#define HUSB2_MDATA_RX_SIZE 1
2230 +/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
2231 +#define HUSB2_BUSY_BANK_IE_OFFSET 18
2232 +#define HUSB2_BUSY_BANK_IE_SIZE 1
2233 +
2234 +/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
2235 +#define HUSB2_FORCE_STALL_OFFSET 5
2236 +#define HUSB2_FORCE_STALL_SIZE 1
2237 +#define HUSB2_TOGGLE_SEQ_OFFSET 6
2238 +#define HUSB2_TOGGLE_SEQ_SIZE 2
2239 +#define HUSB2_ERR_OVFLW_OFFSET 8
2240 +#define HUSB2_ERR_OVFLW_SIZE 1
2241 +#define HUSB2_RX_BK_RDY_OFFSET 9
2242 +#define HUSB2_RX_BK_RDY_SIZE 1
2243 +#define HUSB2_KILL_BANK_OFFSET 9
2244 +#define HUSB2_KILL_BANK_SIZE 1
2245 +#define HUSB2_TX_COMPLETE_OFFSET 10
2246 +#define HUSB2_TX_COMPLETE_SIZE 1
2247 +#define HUSB2_TX_PK_RDY_OFFSET 11
2248 +#define HUSB2_TX_PK_RDY_SIZE 1
2249 +#define HUSB2_ISO_ERR_TRANS_OFFSET 11
2250 +#define HUSB2_ISO_ERR_TRANS_SIZE 1
2251 +#define HUSB2_RX_SETUP_OFFSET 12
2252 +#define HUSB2_RX_SETUP_SIZE 1
2253 +#define HUSB2_ISO_ERR_FLOW_OFFSET 12
2254 +#define HUSB2_ISO_ERR_FLOW_SIZE 1
2255 +#define HUSB2_STALL_SENT_OFFSET 13
2256 +#define HUSB2_STALL_SENT_SIZE 1
2257 +#define HUSB2_ISO_ERR_CRC_OFFSET 13
2258 +#define HUSB2_ISO_ERR_CRC_SIZE 1
2259 +#define HUSB2_ISO_ERR_NBTRANS_OFFSET 13
2260 +#define HUSB2_ISO_ERR_NBTRANS_SIZE 1
2261 +#define HUSB2_NAK_IN_OFFSET 14
2262 +#define HUSB2_NAK_IN_SIZE 1
2263 +#define HUSB2_ISO_ERR_FLUSH_OFFSET 14
2264 +#define HUSB2_ISO_ERR_FLUSH_SIZE 1
2265 +#define HUSB2_NAK_OUT_OFFSET 15
2266 +#define HUSB2_NAK_OUT_SIZE 1
2267 +#define HUSB2_CURRENT_BANK_OFFSET 16
2268 +#define HUSB2_CURRENT_BANK_SIZE 2
2269 +#define HUSB2_BUSY_BANKS_OFFSET 18
2270 +#define HUSB2_BUSY_BANKS_SIZE 2
2271 +#define HUSB2_BYTE_COUNT_OFFSET 20
2272 +#define HUSB2_BYTE_COUNT_SIZE 11
2273 +#define HUSB2_SHORT_PACKET_OFFSET 31
2274 +#define HUSB2_SHORT_PACKET_SIZE 1
2275 +
2276 +/* Bitfields in DMA_CONTROL */
2277 +#define HUSB2_DMA_CH_EN_OFFSET 0
2278 +#define HUSB2_DMA_CH_EN_SIZE 1
2279 +#define HUSB2_DMA_LINK_OFFSET 1
2280 +#define HUSB2_DMA_LINK_SIZE 1
2281 +#define HUSB2_DMA_END_TR_EN_OFFSET 2
2282 +#define HUSB2_DMA_END_TR_EN_SIZE 1
2283 +#define HUSB2_DMA_END_BUF_EN_OFFSET 3
2284 +#define HUSB2_DMA_END_BUF_EN_SIZE 1
2285 +#define HUSB2_DMA_END_TR_IE_OFFSET 4
2286 +#define HUSB2_DMA_END_TR_IE_SIZE 1
2287 +#define HUSB2_DMA_END_BUF_IE_OFFSET 5
2288 +#define HUSB2_DMA_END_BUF_IE_SIZE 1
2289 +#define HUSB2_DMA_DESC_LOAD_IE_OFFSET 6
2290 +#define HUSB2_DMA_DESC_LOAD_IE_SIZE 1
2291 +#define HUSB2_DMA_BURST_LOCK_OFFSET 7
2292 +#define HUSB2_DMA_BURST_LOCK_SIZE 1
2293 +#define HUSB2_DMA_BUF_LEN_OFFSET 16
2294 +#define HUSB2_DMA_BUF_LEN_SIZE 16
2295 +
2296 +/* Bitfields in DMA_STATUS */
2297 +#define HUSB2_DMA_CH_ACTIVE_OFFSET 1
2298 +#define HUSB2_DMA_CH_ACTIVE_SIZE 1
2299 +#define HUSB2_DMA_END_TR_ST_OFFSET 4
2300 +#define HUSB2_DMA_END_TR_ST_SIZE 1
2301 +#define HUSB2_DMA_END_BUF_ST_OFFSET 5
2302 +#define HUSB2_DMA_END_BUF_ST_SIZE 1
2303 +#define HUSB2_DMA_DESC_LOAD_ST_OFFSET 6
2304 +#define HUSB2_DMA_DESC_LOAD_ST_SIZE 1
2305 +
2306 +/* Constants for SPEED_CFG */
2307 +#define HUSB2_SPEED_CFG_NORMAL 0
2308 +#define HUSB2_SPEED_CFG_FORCE_HIGH 2
2309 +#define HUSB2_SPEED_CFG_FORCE_FULL 3
2310 +
2311 +/* Constants for EPT_SIZE */
2312 +#define HUSB2_EPT_SIZE_8 0
2313 +#define HUSB2_EPT_SIZE_16 1
2314 +#define HUSB2_EPT_SIZE_32 2
2315 +#define HUSB2_EPT_SIZE_64 3
2316 +#define HUSB2_EPT_SIZE_128 4
2317 +#define HUSB2_EPT_SIZE_256 5
2318 +#define HUSB2_EPT_SIZE_512 6
2319 +#define HUSB2_EPT_SIZE_1024 7
2320 +
2321 +/* Constants for EPT_TYPE */
2322 +#define HUSB2_EPT_TYPE_CONTROL 0
2323 +#define HUSB2_EPT_TYPE_ISO 1
2324 +#define HUSB2_EPT_TYPE_BULK 2
2325 +#define HUSB2_EPT_TYPE_INT 3
2326 +
2327 +/* Constants for BK_NUMBER */
2328 +#define HUSB2_BK_NUMBER_ZERO 0
2329 +#define HUSB2_BK_NUMBER_ONE 1
2330 +#define HUSB2_BK_NUMBER_DOUBLE 2
2331 +#define HUSB2_BK_NUMBER_TRIPLE 3
2332 +
2333 +/* Bit manipulation macros */
2334 +#define HUSB2_BIT(name) \
2335 + (1 << HUSB2_##name##_OFFSET)
2336 +#define HUSB2_BF(name,value) \
2337 + (((value) & ((1 << HUSB2_##name##_SIZE) - 1)) \
2338 + << HUSB2_##name##_OFFSET)
2339 +#define HUSB2_BFEXT(name,value) \
2340 + (((value) >> HUSB2_##name##_OFFSET) \
2341 + & ((1 << HUSB2_##name##_SIZE) - 1))
2342 +#define HUSB2_BFINS(name,value,old) \
2343 + (((old) & ~(((1 << HUSB2_##name##_SIZE) - 1) \
2344 + << HUSB2_##name##_OFFSET)) \
2345 + | HUSB2_BF(name,value))
2346 +
2347 +/* Register access macros */
2348 +#define husb2_readl(udc,reg) \
2349 + __raw_readl((udc)->regs + HUSB2_##reg)
2350 +#define husb2_writel(udc,reg,value) \
2351 + __raw_writel((value), (udc)->regs + HUSB2_##reg)
2352 +#define husb2_ep_readl(ep,reg) \
2353 + __raw_readl((ep)->ep_regs + HUSB2_EPT_##reg)
2354 +#define husb2_ep_writel(ep,reg,value) \
2355 + __raw_writel((value), (ep)->ep_regs + HUSB2_EPT_##reg)
2356 +#define husb2_dma_readl(ep,reg) \
2357 + __raw_readl((ep)->dma_regs + HUSB2_DMA_##reg)
2358 +#define husb2_dma_writel(ep,reg,value) \
2359 + __raw_writel((value), (ep)->dma_regs + HUSB2_DMA_##reg)
2360 +
2361 +/* Calculate base address for a given endpoint or DMA controller */
2362 +#define HUSB2_EPT_BASE(x) (0x100 + (x) * 0x20)
2363 +#define HUSB2_DMA_BASE(x) (0x300 + (x) * 0x10)
2364 +#define HUSB2_FIFO_BASE(x) ((x) << 16)
2365 +
2366 +/* Synth parameters */
2367 +#define HUSB2_NR_ENDPOINTS 7
2368 +
2369 +#define EP0_FIFO_SIZE 64
2370 +#define EP0_EPT_SIZE HUSB2_EPT_SIZE_64
2371 +#define EP0_NR_BANKS 1
2372 +#define BULK_FIFO_SIZE 512
2373 +#define BULK_EPT_SIZE HUSB2_EPT_SIZE_512
2374 +#define BULK_NR_BANKS 2
2375 +#define ISO_FIFO_SIZE 1024
2376 +#define ISO_EPT_SIZE HUSB2_EPT_SIZE_1024
2377 +#define ISO_NR_BANKS 3
2378 +#define INT_FIFO_SIZE 64
2379 +#define INT_EPT_SIZE HUSB2_EPT_SIZE_64
2380 +#define INT_NR_BANKS 3
2381 +
2382 +enum husb2_ctrl_state {
2383 + WAIT_FOR_SETUP,
2384 + DATA_STAGE_IN,
2385 + DATA_STAGE_OUT,
2386 + STATUS_STAGE_IN,
2387 + STATUS_STAGE_OUT,
2388 + STATUS_STAGE_ADDR,
2389 +};
2390 +/*
2391 + EP_STATE_IDLE,
2392 + EP_STATE_SETUP,
2393 + EP_STATE_IN_DATA,
2394 + EP_STATE_OUT_DATA,
2395 + EP_STATE_SET_ADDR_STATUS,
2396 + EP_STATE_RX_STATUS,
2397 + EP_STATE_TX_STATUS,
2398 + EP_STATE_HALT,
2399 +*/
2400 +
2401 +struct husb2_dma_desc {
2402 + dma_addr_t next;
2403 + dma_addr_t addr;
2404 + u32 ctrl;
2405 +};
2406 +
2407 +struct husb2_ep {
2408 + int state;
2409 + void __iomem *ep_regs;
2410 + void __iomem *dma_regs;
2411 + void __iomem *fifo;
2412 + struct usb_ep ep;
2413 + struct husb2_udc *udc;
2414 +
2415 + struct list_head queue;
2416 + const struct usb_endpoint_descriptor *desc;
2417 +
2418 + u16 fifo_size;
2419 + u8 nr_banks;
2420 + u8 index;
2421 + u8 capabilities;
2422 +
2423 +#ifdef CONFIG_DEBUG_FS
2424 + u32 last_dma_status;
2425 + struct dentry *debugfs_dir;
2426 + struct dentry *debugfs_queue;
2427 + struct dentry *debugfs_dma_status;
2428 +#endif
2429 +};
2430 +#define HUSB2_EP_CAP_ISOC 0x0001
2431 +#define HUSB2_EP_CAP_DMA 0x0002
2432 +
2433 +struct husb2_packet {
2434 + struct husb2_dma_desc *desc;
2435 + dma_addr_t desc_dma;
2436 +};
2437 +
2438 +struct husb2_request {
2439 + struct usb_request req;
2440 + struct list_head queue;
2441 +
2442 + struct husb2_packet *packet;
2443 + unsigned int nr_pkts;
2444 +
2445 + unsigned int submitted:1;
2446 + unsigned int using_dma:1;
2447 + unsigned int last_transaction:1;
2448 + unsigned int send_zlp:1;
2449 +};
2450 +
2451 +struct husb2_udc {
2452 + spinlock_t lock;
2453 +
2454 + void __iomem *regs;
2455 + void __iomem *fifo;
2456 +
2457 + struct dma_pool *desc_pool;
2458 +
2459 + struct usb_gadget gadget;
2460 + struct usb_gadget_driver *driver;
2461 + struct platform_device *pdev;
2462 + int irq;
2463 + struct clk *pclk;
2464 + struct clk *hclk;
2465 +
2466 +#ifdef CONFIG_DEBUG_FS
2467 + struct dentry *debugfs_root;
2468 + struct dentry *debugfs_regs;
2469 +#endif
2470 +};
2471 +
2472 +#define to_husb2_ep(x) container_of((x), struct husb2_ep, ep)
2473 +#define to_husb2_req(x) container_of((x), struct husb2_request, req)
2474 +#define to_husb2_udc(x) container_of((x), struct husb2_udc, gadget)
2475 +
2476 +#define ep_index(ep) ((ep)->index)
2477 +#define ep_can_dma(ep) ((ep)->capabilities & HUSB2_EP_CAP_DMA)
2478 +#define ep_is_in(ep) (((ep)->desc->bEndpointAddress \
2479 + & USB_ENDPOINT_DIR_MASK) \
2480 + == USB_DIR_IN)
2481 +#define ep_is_isochronous(ep) \
2482 + (((ep)->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) \
2483 + == USB_ENDPOINT_XFER_ISOC)
2484 +#define ep_is_control(ep) (ep_index(ep) == 0)
2485 +#define ep_name(ep) ((ep)->ep.name)
2486 +#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
2487 +
2488 +#endif /* __LINUX_USB_GADGET_HUSB2_H */