| blob | 736ac4b6b6b78b1e465cd84b9a9af14bc80d6b2f |
1 Adds support for Freescale Power architecture e300c2 and e300c3 cores.
2 http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
4 Leon Woestenberg <leonw@mailcan.com>
6 Index: gcc-4.1.2/gcc/config/rs6000/e300c2c3.md
7 ===================================================================
8 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9 +++ gcc-4.1.2/gcc/config/rs6000/e300c2c3.md 2007-10-18 15:32:51.000000000 +0200
10 @@ -0,0 +1,189 @@
11 +;; Pipeline description for Motorola PowerPC e300c3 core.
12 +;; Copyright (C) 2003 Free Software Foundation, Inc.
13 +;;
14 +;; This file is part of GCC.
15 +
16 +;; GCC is free software; you can redistribute it and/or modify it
17 +;; under the terms of the GNU General Public License as published
18 +;; by the Free Software Foundation; either version 2, or (at your
19 +;; option) any later version.
20 +
21 +;; GCC is distributed in the hope that it will be useful, but WITHOUT
22 +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
24 +;; License for more details.
25 +
26 +;; You should have received a copy of the GNU General Public License
27 +;; along with GCC; see the file COPYING. If not, write to the
28 +;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
29 +;; MA 02111-1307, USA.
30 +
31 +(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
32 +(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
33 +
34 +;; We don't simulate general issue queue (GIC). If we have SU insn
35 +;; and then SU1 insn, they can not be issued on the same cycle
36 +;; (although SU1 insn and then SU insn can be issued) because the SU
37 +;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
38 +;; multipass insn scheduling will find the situation and issue the SU1
39 +;; insn and then the SU insn.
40 +(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
41 +
42 +;; We could describe completion buffers slots in combination with the
43 +;; retirement units and the order of completion but the result
44 +;; automaton would behave in the same way because we can not describe
45 +;; real latency time with taking in order completion into account.
46 +;; Actually we could define the real latency time by querying reserved
47 +;; automaton units but the current scheduler uses latency time before
48 +;; issuing insns and making any reservations.
49 +;;
50 +;; So our description is aimed to achieve a insn schedule in which the
51 +;; insns would not wait in the completion buffer.
52 +(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
53 +
54 +;; Branch unit:
55 +(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
56 +
57 +;; IU:
58 +(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
59 +
60 +;; IU: This used to describe non-pipelined division.
61 +(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
62 +
63 +;; SRU:
64 +(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
65 +
66 +;; Here we simplified LSU unit description not describing the stages.
67 +(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
68 +
69 +;; FPU:
70 +(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
71 +
72 +;; The following units are used to make automata deterministic
73 +(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
74 +(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
75 +(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
76 +(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
77 +
78 +;; The following sets to make automata deterministic when option ndfa is used.
79 +(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
80 +(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
81 +(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
82 +(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
83 +
84 +;; Some useful abbreviations.
85 +(define_reservation "ppce300c3_decode"
86 + "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
87 +(define_reservation "ppce300c3_issue"
88 + "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
89 +(define_reservation "ppce300c3_retire"
90 + "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
91 +(define_reservation "ppce300c3_iu_stage0"
92 + "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
93 +
94 +;; Compares can be executed either one of the IU or SRU
95 +(define_insn_reservation "ppce300c3_cmp" 1
96 + (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
97 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
98 + "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
99 + +ppce300c3_retire")
100 +
101 +;; Other one cycle IU insns
102 +(define_insn_reservation "ppce300c3_iu" 1
103 + (and (eq_attr "type" "integer,insert_word")
104 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
105 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
106 +
107 +;; Branch. Actually this latency time is not used by the scheduler.
108 +(define_insn_reservation "ppce300c3_branch" 1
109 + (and (eq_attr "type" "jmpreg,branch")
110 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
111 + "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
112 +
113 +;; Multiply is non-pipelined but can be executed in any IU
114 +(define_insn_reservation "ppce300c3_multiply" 2
115 + (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
116 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
117 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
118 + ppce300c3_iu_stage0+ppce300c3_retire")
119 +
120 +;; Divide. We use the average latency time here. We omit reserving a
121 +;; retire unit because of the result automata will be huge.
122 +(define_insn_reservation "ppce300c3_divide" 20
123 + (and (eq_attr "type" "idiv")
124 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
125 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
126 + ppce300c3_mu_div*19")
127 +
128 +;; CR logical
129 +(define_insn_reservation "ppce300c3_cr_logical" 1
130 + (and (eq_attr "type" "cr_logical,delayed_cr")
131 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
132 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
133 +
134 +;; Mfcr
135 +(define_insn_reservation "ppce300c3_mfcr" 1
136 + (and (eq_attr "type" "mfcr")
137 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
138 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
139 +
140 +;; Mtcrf
141 +(define_insn_reservation "ppce300c3_mtcrf" 1
142 + (and (eq_attr "type" "mtcr")
143 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
144 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
145 +
146 +;; Mtjmpr
147 +(define_insn_reservation "ppce300c3_mtjmpr" 1
148 + (and (eq_attr "type" "mtjmpr,mfjmpr")
149 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
150 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
151 +
152 +;; Float point instructions
153 +(define_insn_reservation "ppce300c3_fpcompare" 3
154 + (and (eq_attr "type" "fpcompare")
155 + (eq_attr "cpu" "ppce300c3"))
156 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
157 +
158 +(define_insn_reservation "ppce300c3_fp" 3
159 + (and (eq_attr "type" "fp")
160 + (eq_attr "cpu" "ppce300c3"))
161 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
162 +
163 +(define_insn_reservation "ppce300c3_dmul" 4
164 + (and (eq_attr "type" "dmul")
165 + (eq_attr "cpu" "ppce300c3"))
166 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
167 +
168 +; Divides are not pipelined
169 +(define_insn_reservation "ppce300c3_sdiv" 18
170 + (and (eq_attr "type" "sdiv")
171 + (eq_attr "cpu" "ppce300c3"))
172 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
173 +
174 +(define_insn_reservation "ppce300c3_ddiv" 33
175 + (and (eq_attr "type" "ddiv")
176 + (eq_attr "cpu" "ppce300c3"))
177 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
178 +
179 +;; Loads
180 +(define_insn_reservation "ppce300c3_load" 2
181 + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
182 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
183 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
184 +
185 +(define_insn_reservation "ppce300c3_fpload" 2
186 + (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
187 + (eq_attr "cpu" "ppce300c3"))
188 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
189 +
190 +;; Stores.
191 +(define_insn_reservation "ppce300c3_store" 2
192 + (and (eq_attr "type" "store,store_ux,store_u")
193 + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
194 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
195 +
196 +(define_insn_reservation "ppce300c3_fpstore" 2
197 + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
198 + (eq_attr "cpu" "ppce300c3"))
199 + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
200 Index: gcc-4.1.2/gcc/config/rs6000/rs6000.c
201 ===================================================================
202 --- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.c 2006-12-16 20:24:56.000000000 +0100
203 +++ gcc-4.1.2/gcc/config/rs6000/rs6000.c 2007-10-18 15:34:26.000000000 +0200
204 @@ -557,6 +557,21 @@
205 COSTS_N_INSNS (29), /* ddiv */
206 };
208 +/* Instruction costs on E300C2 and E300C3 cores. */
209 +static const
210 +struct processor_costs ppce300c2c3_cost = {
211 + COSTS_N_INSNS (4), /* mulsi */
212 + COSTS_N_INSNS (4), /* mulsi_const */
213 + COSTS_N_INSNS (4), /* mulsi_const9 */
214 + COSTS_N_INSNS (4), /* muldi */
215 + COSTS_N_INSNS (19), /* divsi */
216 + COSTS_N_INSNS (19), /* divdi */
217 + COSTS_N_INSNS (3), /* fp */
218 + COSTS_N_INSNS (4), /* dmul */
219 + COSTS_N_INSNS (18), /* sdiv */
220 + COSTS_N_INSNS (33), /* ddiv */
221 +};
222 +
223 /* Instruction costs on POWER4 and POWER5 processors. */
224 static const
225 struct processor_costs power4_cost = {
226 @@ -1140,6 +1155,8 @@
227 /* 8548 has a dummy entry for now. */
228 {"8548", PROCESSOR_PPC8540,
229 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
230 + {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
231 + {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
232 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
233 {"970", PROCESSOR_POWER4,
234 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
235 @@ -1529,6 +1546,11 @@
236 rs6000_cost = &ppc8540_cost;
237 break;
239 + case PROCESSOR_PPCE300C2:
240 + case PROCESSOR_PPCE300C3:
241 + rs6000_cost = &ppce300c2c3_cost;
242 + break;
243 +
244 case PROCESSOR_POWER4:
245 case PROCESSOR_POWER5:
246 rs6000_cost = &power4_cost;
247 @@ -16647,6 +16669,8 @@
248 case CPU_PPC750:
249 case CPU_PPC7400:
250 case CPU_PPC8540:
251 + case CPU_PPCE300C2:
252 + case CPU_PPCE300C3:
253 return 2;
254 case CPU_RIOS2:
255 case CPU_PPC604:
256 Index: gcc-4.1.2/gcc/config/rs6000/rs6000.h
257 ===================================================================
258 --- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.h 2006-11-18 01:25:49.000000000 +0100
259 +++ gcc-4.1.2/gcc/config/rs6000/rs6000.h 2007-10-18 15:32:51.000000000 +0200
260 @@ -111,6 +111,8 @@
261 %{mcpu=970: -mpower4 -maltivec} \
262 %{mcpu=G5: -mpower4 -maltivec} \
263 %{mcpu=8540: -me500} \
264 +%{mcpu=e300c2: -mppc} \
265 +%{mcpu=e300c3: -mppc -mpmr} \
266 %{maltivec: -maltivec} \
267 -many"
269 @@ -211,6 +213,8 @@
270 PROCESSOR_PPC7400,
271 PROCESSOR_PPC7450,
272 PROCESSOR_PPC8540,
273 + PROCESSOR_PPCE300C2,
274 + PROCESSOR_PPCE300C3,
275 PROCESSOR_POWER4,
276 PROCESSOR_POWER5
277 };
278 Index: gcc-4.1.2/gcc/config/rs6000/rs6000.md
279 ===================================================================
280 --- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.md 2006-12-16 20:24:56.000000000 +0100
281 +++ gcc-4.1.2/gcc/config/rs6000/rs6000.md 2007-10-18 15:32:51.000000000 +0200
282 @@ -103,7 +103,7 @@
283 ;; Processor type -- this attribute must exactly match the processor_type
284 ;; enumeration in rs6000.h.
286 -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
287 +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5"
288 (const (symbol_ref "rs6000_cpu_attr")))
290 (automata_option "ndfa")
291 @@ -119,6 +119,7 @@
292 (include "7xx.md")
293 (include "7450.md")
294 (include "8540.md")
295 +(include "e300c2c3.md")
296 (include "power4.md")
297 (include "power5.md")
299 Index: gcc-4.1.2/gcc/config.gcc
300 ===================================================================
301 --- gcc-4.1.2.orig/gcc/config.gcc 2007-10-18 15:26:23.000000000 +0200
302 +++ gcc-4.1.2/gcc/config.gcc 2007-10-18 15:32:51.000000000 +0200
303 @@ -2710,7 +2710,7 @@
304 | rios | rios1 | rios2 | rsc | rsc1 | rs64a \
305 | 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
306 | 601 | 602 | 603 | 603e | ec603e | 604 \
307 - | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
308 + | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
309 | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5)
310 # OK
311 ;;