| blob | dcee3fad0ab4455c192752eb9296ac003eb499da |
1 diff -urN glibc-2.5/ports/sysdeps/arm/eabi/fraiseexcpt.c glibc-2.5/ports/sysdeps/arm/eabi-new/fraiseexcpt.c
2 --- glibc-2.5/ports/sysdeps/arm/eabi/fraiseexcpt.c 2005-10-11 01:29:32.000000000 +1000
3 +++ glibc-2.5/ports/sysdeps/arm/eabi-new/fraiseexcpt.c 2008-04-14 17:21:09.000000000 +1000
4 @@ -25,6 +25,7 @@
5 #include <ldsodefs.h>
6 #include <dl-procinfo.h>
7 #include <sysdep.h>
8 +#include <math.h>
10 int
11 feraiseexcept (int excepts)
12 @@ -105,8 +105,74 @@
14 if (GLRO (dl_hwcap) & HWCAP_ARM_CRUNCH)
15 {
16 - /* Unsupported, for now. */
17 - return 1;
18 + unsigned int dspsc;
19 + const float fp_zero = 0.0, fp_one = 1.0, fp_max = FLT_MAX,
20 + fp_min = FLT_MIN, fp_1e32 = 1.0e32f, fp_two = 2.0,
21 + fp_three = 3.0, fp_inf = HUGE_VALF;
22 +
23 + /* Raise exceptions represented by EXPECTS. But we must raise only
24 + one signal at a time. It is important that if the overflow/underflow
25 + exception and the inexact exception are given at the same time,
26 + the overflow/underflow exception follows the inexact exception. After
27 + each exception we read from the dspsc, to force the exception to be
28 + raised immediately. */
29 +
30 + /* There are additional complications because this file may be compiled
31 + without CRUNCH support enabled, and we also can't assume that the
32 + assembler has CRUNCH instructions enabled. To get around this we use the
33 + generic coprocessor mnemonics and avoid asking GCC to put float values
34 + in CRUNCH registers. */
35 +
36 + /* First: invalid exception. */
37 + if (FE_CRUNCH_INVALID & excepts)
38 + /* (ZERO * INFINITY) */
39 + __asm__ __volatile__ (
40 + "ldc p4, cr0, %1\n\t" /* cflds mvf0, %1 */
41 + "ldc p4, cr1, %2\n\t" /* cflds mvf1, %2 */
42 + "cdp p4, 1, cr0, cr0, cr1, 0\n\t" /* cfmuls mvf0, mvf0, mvf1 */
43 + "cdp p4, 0, cr0, cr0, cr0, 7\n\t" /* cfmv32sc mvdx0, dspsc */
44 + "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
45 + : "m" (fp_zero), "m" (fp_inf)
46 + : "s0", "s1");
47 +
48 + /* Next: overflow. */
49 + if (FE_CRUNCH_OVERFLOW & excepts)
50 + /* There's no way to raise overflow without also raising inexact. */
51 + __asm__ __volatile__ (
52 + "ldc p4, cr0, %1\n\t" /* cflds mvf0, %1 */
53 + "ldc p4, cr1, %2\n\t" /* cflds mvf1, %2 */
54 + "cdp p4, 3, cr0, cr0, cr1, 4\n\t" /* cfadds mvf0, mvf0, mvf1 */
55 + "cdp p4, 0, cr0, cr0, cr0, 7\n\t" /* cfmv32sc mvdx0, dspsc */
56 + "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
57 + : "m" (fp_max), "m" (fp_1e32)
58 + : "s0", "s1");
59 +
60 + /* Next: underflow. */
61 + if (FE_CRUNCH_UNDERFLOW & excepts)
62 + /* (FLT_MIN * FLT_MIN) */
63 + __asm__ __volatile__ (
64 + "ldc p4, cr0, %1\n\t" /* cflds mvf0, %1 */
65 + "ldc p4, cr1, %2\n\t" /* cflds mvf1, %2 */
66 + "cdp p4, 1, cr0, cr0, cr1, 0\n\t" /* cfmul mvf0, mvf0, mvf1 */
67 + "cdp p4, 0, cr0, cr0, cr0, 7\n\t" /* cfmv32sc mvdx0, dspsc */
68 + "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
69 + : "m" (fp_min), "m" (fp_min)
70 + : "s0", "s1");
71 +
72 + /* Last: inexact. */
73 + if (FE_CRUNCH_INEXACT & excepts)
74 + /* There's no way to raise inexact without also raising overflow. */
75 + __asm__ __volatile__ (
76 + "ldc p4, cr0, %1\n\t" /* cflds mvf0, %1 */
77 + "ldc p4, cr1, %2\n\t" /* cflds mvf1, %2 */
78 + "cdp p4, 3, cr0, cr0, cr1, 4\n\t" /* cfadds mvf0, mvf0, mvf1 */
79 + "cdp p4, 0, cr0, cr0, cr0, 7\n\t" /* cfmv32sc mvdx0, dspsc */
80 + "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
81 + : "m" (fp_max), "m" (fp_1e32)
82 + : "s0", "s1");
83 +
84 + /* Success. */
85 + return 0;
86 }
88 /* Unsupported, so fail. */