| blob | 2b2a17da7fcf0b9cfa6ad1a5c41f39b240502a70 |
1 --- u-boot-1.2.0.vanilla/board/qnap/config.mk 1970-01-01 01:00:00.000000000 +0100
2 +++ u-boot-1.2.0/board/qnap/config.mk 2007-02-26 01:55:37.000000000 +0100
3 @@ -0,0 +1,35 @@
4 +#
5 +# (C) Copyright 2000, 2001
6 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 +#
8 +# See file CREDITS for list of people who contributed to this
9 +# project.
10 +#
11 +# This program is free software; you can redistribute it and/or
12 +# modify it under the terms of the GNU General Public License as
13 +# published by the Free Software Foundation; either version 2 of
14 +# the License, or (at your option) any later version.
15 +#
16 +# This program is distributed in the hope that it will be useful,
17 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
18 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 +# GNU General Public License for more details.
20 +#
21 +# You should have received a copy of the GNU General Public License
22 +# along with this program; if not, write to the Free Software
23 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 +# MA 02111-1307 USA
25 +#
26 +# Valid values for TEXT_BASE are:
27 +#
28 +# Standard configuration
29 +# 0xFFF00000 boot from flash
30 +#
31 +# Standard configuration
32 +# 0xFFE60000 chain boot from flash
33 +#
34 +
35 +
36 +TEXT_BASE = 0xFFE60000
37 +
38 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
39 --- u-boot-1.2.0.vanilla/board/qnap/ide.c 1970-01-01 01:00:00.000000000 +0100
40 +++ u-boot-1.2.0/board/qnap/ide.c 2007-02-26 01:55:37.000000000 +0100
41 @@ -0,0 +1,67 @@
42 +/*
43 + * (C) Copyright 2000
44 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
45 + *
46 + * See file CREDITS for list of people who contributed to this
47 + * project.
48 + *
49 + * This program is free software; you can redistribute it and/or
50 + * modify it under the terms of the GNU General Public License as
51 + * published by the Free Software Foundation; either version 2 of
52 + * the License, or (at your option) any later version.
53 + *
54 + * This program is distributed in the hope that it will be useful,
55 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
56 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57 + * GNU General Public License for more details.
58 + *
59 + * You should have received a copy of the GNU General Public License
60 + * along with this program; if not, write to the Free Software
61 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
62 + * MA 02111-1307 USA
63 + */
64 +
65 + #include <common.h>
66 +
67 +#ifdef CFG_CMD_IDE
68 +#include <ata.h>
69 +#include <ide.h>
70 +#include <pci.h>
71 +
72 +extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
73 +extern struct pci_controller hose;
74 +
75 +int ide_preinit (void)
76 +{
77 + int status;
78 + pci_dev_t devbusfn;
79 + int l;
80 +
81 + status = 1;
82 + for (l = 0; l < CFG_IDE_MAXBUS; l++) {
83 + ide_bus_offset[l] = -ATA_STATUS;
84 + }
85 + devbusfn = pci_find_device (0x1095, 0x3512, 0);
86 +
87 + if (devbusfn != -1) {
88 +
89 + status = 0;
90 +
91 + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
92 + (u32 *) &ide_bus_offset[0]);
93 + ide_bus_offset[0] &= 0xfffffffe;
94 + ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
95 + ide_bus_offset[0] & 0xfffffffe,
96 + PCI_REGION_IO);
97 +
98 + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
99 + (u32 *) &ide_bus_offset[1]);
100 + ide_bus_offset[1] &= 0xfffffffe;
101 + ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
102 + ide_bus_offset[1] & 0xfffffffe,
103 + PCI_REGION_IO);
104 + }
105 + return (status);
106 +}
107 +
108 +#endif /* of CONFIG_CMDS_IDE */
109 --- u-boot-1.2.0.vanilla/board/qnap/Makefile 1970-01-01 01:00:00.000000000 +0100
110 +++ u-boot-1.2.0/board/qnap/Makefile 2007-02-26 01:55:37.000000000 +0100
111 @@ -0,0 +1,40 @@
112 +#
113 +# (C) Copyright 2000
114 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
115 +#
116 +# See file CREDITS for list of people who contributed to this
117 +# project.
118 +#
119 +# This program is free software; you can redistribute it and/or
120 +# modify it under the terms of the GNU General Public License as
121 +# published by the Free Software Foundation; either version 2 of
122 +# the License, or (at your option) any later version.
123 +#
124 +# This program is distributed in the hope that it will be useful,
125 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
126 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
127 +# GNU General Public License for more details.
128 +#
129 +# You should have received a copy of the GNU General Public License
130 +# along with this program; if not, write to the Free Software
131 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
132 +# MA 02111-1307 USA
133 +#
134 +
135 +include $(TOPDIR)/config.mk
136 +
137 +LIB = lib$(BOARD).a
138 +
139 +OBJS = $(BOARD).o ide.o
140 +
141 +$(LIB): .depend $(OBJS)
142 + $(AR) crv $@ $(OBJS)
143 +
144 +#########################################################################
145 +
146 +.depend: Makefile $(OBJS:.o=.c)
147 + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
148 +
149 +sinclude .depend
150 +
151 +#########################################################################
152 --- u-boot-1.2.0.vanilla/board/qnap/qnap.c 1970-01-01 01:00:00.000000000 +0100
153 +++ u-boot-1.2.0/board/qnap/qnap.c 2007-02-26 01:55:37.000000000 +0100
154 @@ -0,0 +1,126 @@
155 +/*
156 + * Copyright (C) 2006 Andrew Luyten <u-boot@luyten.org.uk>
157 + *
158 + * Copyright (C) 2000
159 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
160 + *
161 + * See file CREDITS for list of people who contributed to this
162 + * project.
163 + *
164 + * This program is free software; you can redistribute it and/or
165 + * modify it under the terms of the GNU General Public License as
166 + * published by the Free Software Foundation; either version 2 of
167 + * the License, or (at your option) any later version.
168 + *
169 + * This program is distributed in the hope that it will be useful,
170 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
171 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
172 + * GNU General Public License for more details.
173 + *
174 + * You should have received a copy of the GNU General Public License
175 + * along with this program; if not, write to the Free Software
176 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
177 + * MA 02111-1307 USA
178 + *
179 + */
180 +
181 +#include <common.h>
182 +#include <mpc824x.h>
183 +#include <pci.h>
184 +
185 +int checkboard (void)
186 +{
187 + ulong busfreq = get_bus_freq(0);
188 + char buf[32];
189 +
190 + printf("Board: QNAP TS-101/TS-201 local bus at %s MHz\n", strmhz(buf, busfreq));
191 + return 0;
192 +}
193 +
194 +
195 +long int initdram (int board_type)
196 +{
197 + long size;
198 + long new_bank0_end;
199 + long mear1;
200 + long emear1;
201 +
202 + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
203 +
204 + new_bank0_end = size - 1;
205 + mear1 = mpc824x_mpc107_getreg(MEAR1);
206 + emear1 = mpc824x_mpc107_getreg(EMEAR1);
207 + mear1 = (mear1 & 0xFFFFFF00) |
208 + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
209 + emear1 = (emear1 & 0xFFFFFF00) |
210 + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
211 + mpc824x_mpc107_setreg(MEAR1, mear1);
212 + mpc824x_mpc107_setreg(EMEAR1, emear1);
213 +
214 + return (size);
215 +}
216 +
217 +/*
218 + * Initialize PCI Devices, report devices found.
219 + */
220 +#ifndef CONFIG_PCI_PNP
221 +
222 +static struct pci_config_table pci_qnap_config_table[] = {
223 + /* vendor, device, class */
224 + /* bus, dev, func */
225 +
226 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
227 + PCI_ANY_ID, 0x0f, 0, /* RTL8110SC or Intel 82540EM */
228 + /* Gigabit ethernet controller */
229 + pci_cfgfunc_config_device, { PCI_ETH_IOADDR,
230 + PCI_ETH_MEMADDR,
231 + PCI_COMMAND_IO |
232 + PCI_COMMAND_MEMORY |
233 + PCI_COMMAND_MASTER }},
234 +
235 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
236 + PCI_ANY_ID, 0x0d, 0, /* SII3512 */
237 + /* SATA controller */
238 + pci_cfgfunc_config_device, { PCI_IDE_IOADDR,
239 + PCI_IDE_MEMADDR,
240 + PCI_COMMAND_IO |
241 + PCI_COMMAND_MEMORY |
242 + PCI_COMMAND_MASTER }},
243 +
244 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
245 + PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */
246 + pci_cfgfunc_config_device, { PCI_USB0_IOADDR,
247 + PCI_USB0_MEMADDR,
248 + PCI_COMMAND_MEMORY |
249 + PCI_COMMAND_MASTER }},
250 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
251 + PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */
252 + pci_cfgfunc_config_device, { PCI_USB1_IOADDR,
253 + PCI_USB1_MEMADDR,
254 + PCI_COMMAND_MEMORY |
255 + PCI_COMMAND_MASTER }},
256 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
257 + PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */
258 + pci_cfgfunc_config_device, { PCI_USB2_IOADDR,
259 + PCI_USB2_MEMADDR,
260 + PCI_COMMAND_MEMORY |
261 + PCI_COMMAND_MASTER }},
262 + { }
263 +};
264 +#endif
265 +
266 +struct pci_controller hose = {
267 +#ifndef CONFIG_PCI_PNP
268 + config_table: pci_qnap_config_table,
269 +#endif
270 +};
271 +
272 +void pci_init_board(void)
273 +{
274 + pci_mpc824x_init(&hose);
275 +
276 + /* Reset USB 1.1 !/
277 + out_le32(PCI_USB0_MEMADDR+8, 1);
278 + out_le32(PCI_USB1_MEMADDR+8, 1);
279 + */
280 +}
281 --- u-boot-1.2.0.vanilla/board/qnap/README 1970-01-01 01:00:00.000000000 +0100
282 +++ u-boot-1.2.0/board/qnap/README 2007-02-26 01:55:37.000000000 +0100
283 @@ -0,0 +1,10 @@
284 +*This port of U-Boot will run on a QNAP TS-101/TS-201 NAS*
285 +Andrew Luyten (u-boot@luyten.org.uk)
286 +
287 +Adapted from a Linkstation port by Mihai Georgian
288 +http://http://www.linuxnotincluded.org.uk/
289 +
290 +Adapted from Motorola Sandpoint 3 development system equipped with
291 +a Unity X4 PPMC card (MPC8240 CPU) only. It is a snapshot of work
292 +in progress and far from being completed.
293 +Thomas Koeller
294 --- u-boot-1.2.0.vanilla/board/qnap/u-boot.lds 1970-01-01 01:00:00.000000000 +0100
295 +++ u-boot-1.2.0/board/qnap/u-boot.lds 2007-02-26 01:55:37.000000000 +0100
296 @@ -0,0 +1,136 @@
297 +/*
298 + * (C) Copyright 2001
299 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
300 + *
301 + * See file CREDITS for list of people who contributed to this
302 + * project.
303 + *
304 + * This program is free software; you can redistribute it and/or
305 + * modify it under the terms of the GNU General Public License as
306 + * published by the Free Software Foundation; either version 2 of
307 + * the License, or (at your option) any later version.
308 + *
309 + * This program is distributed in the hope that it will be useful,
310 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
311 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
312 + * GNU General Public License for more details.
313 + *
314 + * You should have received a copy of the GNU General Public License
315 + * along with this program; if not, write to the Free Software
316 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
317 + * MA 02111-1307 USA
318 + */
319 +
320 +OUTPUT_ARCH(powerpc)
321 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
322 +/* Do we need any of these for elf?
323 + __DYNAMIC = 0; */
324 +SECTIONS
325 +{
326 + /* Read-only sections, merged into text segment: */
327 + . = + SIZEOF_HEADERS;
328 + .interp : { *(.interp) }
329 + .hash : { *(.hash) }
330 + .dynsym : { *(.dynsym) }
331 + .dynstr : { *(.dynstr) }
332 + .rel.text : { *(.rel.text) }
333 + .rela.text : { *(.rela.text) }
334 + .rel.data : { *(.rel.data) }
335 + .rela.data : { *(.rela.data) }
336 + .rel.rodata : { *(.rel.rodata) }
337 + .rela.rodata : { *(.rela.rodata) }
338 + .rel.got : { *(.rel.got) }
339 + .rela.got : { *(.rela.got) }
340 + .rel.ctors : { *(.rel.ctors) }
341 + .rela.ctors : { *(.rela.ctors) }
342 + .rel.dtors : { *(.rel.dtors) }
343 + .rela.dtors : { *(.rela.dtors) }
344 + .rel.bss : { *(.rel.bss) }
345 + .rela.bss : { *(.rela.bss) }
346 + .rel.plt : { *(.rel.plt) }
347 + .rela.plt : { *(.rela.plt) }
348 + .init : { *(.init) }
349 + .plt : { *(.plt) }
350 + .text :
351 + {
352 + cpu/mpc824x/start.o (.text)
353 + lib_ppc/board.o (.text)
354 + lib_ppc/ppcstring.o (.text)
355 + lib_generic/vsprintf.o (.text)
356 + lib_generic/crc32.o (.text)
357 + lib_generic/zlib.o (.text)
358 +
359 + . = DEFINED(env_offset) ? env_offset : .;
360 + common/environment.o (.text)
361 +
362 + *(.text)
363 +
364 + *(.fixup)
365 + *(.got1)
366 + . = ALIGN(16);
367 + *(.rodata)
368 + *(.rodata1)
369 + *(.rodata.str1.4)
370 + *(.eh_frame)
371 + }
372 + .fini : { *(.fini) } =0
373 + .ctors : { *(.ctors) }
374 + .dtors : { *(.dtors) }
375 +
376 + /* Read-write section, merged into data segment: */
377 + . = (. + 0x0FFF) & 0xFFFFF000;
378 + _erotext = .;
379 + PROVIDE (erotext = .);
380 + .reloc :
381 + {
382 + *(.got)
383 + _GOT2_TABLE_ = .;
384 + *(.got2)
385 + _FIXUP_TABLE_ = .;
386 + *(.fixup)
387 + }
388 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
389 + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
390 +
391 + .data :
392 + {
393 + *(.data)
394 + *(.data1)
395 + *(.sdata)
396 + *(.sdata2)
397 + *(.dynamic)
398 + CONSTRUCTORS
399 + }
400 + _edata = .;
401 + PROVIDE (edata = .);
402 +
403 + . = .;
404 + __u_boot_cmd_start = .;
405 + .u_boot_cmd : { *(.u_boot_cmd) }
406 + __u_boot_cmd_end = .;
407 +
408 +
409 + . = .;
410 + __start___ex_table = .;
411 + __ex_table : { *(__ex_table) }
412 + __stop___ex_table = .;
413 +
414 + . = ALIGN(4096);
415 + __init_begin = .;
416 + .text.init : { *(.text.init) }
417 + .data.init : { *(.data.init) }
418 + . = ALIGN(4096);
419 + __init_end = .;
420 +
421 + __bss_start = .;
422 + .bss :
423 + {
424 + *(.sbss) *(.scommon)
425 + *(.dynbss)
426 + *(.bss)
427 + *(COMMON)
428 + }
429 +
430 + _end = . ;
431 + PROVIDE (end = .);
432 +}
433 --- u-boot-1.2.0.vanilla/cpu/mpc824x/cpu.c 2007-01-07 00:13:11.000000000 +0100
434 +++ u-boot-1.2.0/cpu/mpc824x/cpu.c 2007-02-26 01:55:37.000000000 +0100
435 @@ -44,7 +44,11 @@
436 break;
438 case CPU_TYPE_8245:
439 +#ifdef CONFIG_MPC8241
440 + puts ("MPC8241"); /* impossible to distinguish using chip registers */
441 +#else
442 puts ("MPC8245");
443 +#endif
444 break;
446 default:
447 --- u-boot-1.2.0.vanilla/drivers/rtl8169.c 2007-01-07 00:13:11.000000000 +0100
448 +++ u-boot-1.2.0/drivers/rtl8169.c 2007-02-26 01:55:37.000000000 +0100
449 @@ -48,7 +48,10 @@
450 *
451 * Indent Options: indent -kr -i8
452 ***************************************************************************/
453 -
454 +/*
455 + * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
456 + * Modified to use le32_to_cpu and cpu_to_le32 properly
457 + */
458 #include <common.h>
459 #include <malloc.h>
460 #include <net.h>
461 @@ -68,6 +71,7 @@
462 static u32 ioaddr;
464 /* Condensed operations for readability. */
465 +#define virt_to_bus(addr) cpu_to_le32(addr)
466 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
467 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
469 @@ -247,8 +251,15 @@
470 u8 version; /* depend on RTL8169 docs */
471 u32 RxConfigMask; /* should clear the bits supported by this chip */
472 } rtl_chip_info[] = {
473 - {"RTL-8169", 0x00, 0xff7e1880,},
474 - {"RTL-8169", 0x04, 0xff7e1880,},
475 + {"RTL8169", 0x00, 0xff7e1880,},
476 + {"RTL8169s/8110s", 0x02, 0xff7e1880,},
477 + {"RTL8169s/8110s", 0x04, 0xff7e1880,},
478 + {"RTL8169sb/8110sb", 0x10, 0xff7e1880,},
479 + {"RTL8169sc/8110sc", 0x18, 0xff7e1880,},
480 + {"RTL8168b/8111sb", 0x30, 0xff7e1880,},
481 + {"RTL8168b/8111sb", 0x38, 0xff7e1880,},
482 + {"RTL8101e", 0x34, 0xff7e1880,},
483 + {"RTL8100e", 0x32, 0xff7e1880,},
484 };
486 enum _DescStatusBit {
487 @@ -315,6 +326,7 @@
489 static struct pci_device_id supported[] = {
490 {PCI_VENDOR_ID_REALTEK, 0x8169},
491 + {PCI_VENDOR_ID_REALTEK, 0x8167},
492 {}
493 };
495 @@ -383,13 +395,15 @@
496 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
497 if (tmp == rtl_chip_info[i].version) {
498 tpc->chipset = i;
499 + printf ("%s... ", rtl_chip_info[i].name);
500 goto match;
501 }
502 }
504 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
505 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
506 - printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig));
507 + printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
508 +
509 tpc->chipset = 0;
511 match:
512 @@ -413,23 +427,23 @@
513 ioaddr = dev->iobase;
515 cur_rx = tpc->cur_rx;
516 - if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
517 - if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
518 + if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
519 + if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
520 unsigned char rxdata[RX_BUF_LEN];
521 - length = (int) (tpc->RxDescArray[cur_rx].
522 - status & 0x00001FFF) - 4;
523 + length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
524 + status) & 0x00001FFF) - 4;
526 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
527 NetReceive(rxdata, length);
529 if (cur_rx == NUM_RX_DESC - 1)
530 tpc->RxDescArray[cur_rx].status =
531 - (OWNbit | EORbit) + RX_BUF_SIZE;
532 + cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
533 else
534 tpc->RxDescArray[cur_rx].status =
535 - OWNbit + RX_BUF_SIZE;
536 + cpu_to_le32(OWNbit + RX_BUF_SIZE);
537 tpc->RxDescArray[cur_rx].buf_addr =
538 - virt_to_bus(tpc->RxBufferRing[cur_rx]);
539 + cpu_to_le32((u32)tpc->RxBufferRing[cur_rx]);
540 } else {
541 puts("Error Rx");
542 }
543 @@ -454,6 +468,7 @@
544 u8 *ptxb;
545 int entry = tpc->cur_tx % NUM_TX_DESC;
546 u32 len = length;
547 + int ret;
549 #ifdef DEBUG_RTL8169_TX
550 int stime = currticks();
551 @@ -465,39 +480,46 @@
553 /* point to the current txb incase multiple tx_rings are used */
554 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
555 +#ifdef DEBUG_RTL8169_TX
556 + printf("ptxb: %08X, length: %d\n", ptxb, (int)length);
557 +#endif
558 memcpy(ptxb, (char *)packet, (int)length);
560 while (len < ETH_ZLEN)
561 ptxb[len++] = '\0';
563 - tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
564 + tpc->TxDescArray[entry].buf_addr = cpu_to_le32((u32)ptxb);
565 if (entry != (NUM_TX_DESC - 1)) {
566 tpc->TxDescArray[entry].status =
567 - (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ?
568 - len : ETH_ZLEN);
569 + cpu_to_le32((OWNbit | FSbit | LSbit) |
570 + ((len > ETH_ZLEN) ? len : ETH_ZLEN));
571 } else {
572 tpc->TxDescArray[entry].status =
573 - (OWNbit | EORbit | FSbit | LSbit) |
574 - ((len > ETH_ZLEN) ? length : ETH_ZLEN);
575 + cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
576 + ((len > ETH_ZLEN) ? len : ETH_ZLEN));
577 }
578 RTL_W8(TxPoll, 0x40); /* set polling bit */
580 tpc->cur_tx++;
581 to = currticks() + TX_TIMEOUT;
582 - while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */
583 + while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
584 + && (currticks() < to)); /* wait */
586 if (currticks() >= to) {
587 #ifdef DEBUG_RTL8169_TX
588 puts ("tx timeout/error\n");
589 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
590 #endif
591 - return 0;
592 + ret = 0;
593 } else {
594 #ifdef DEBUG_RTL8169_TX
595 puts("tx done\n");
596 #endif
597 - return length;
598 + ret = length;
599 }
600 + /* Delay to make net console (nc) work properly */
601 + udelay(20);
602 + return ret;
603 }
605 static void rtl8169_set_rx_mode(struct eth_device *dev)
606 @@ -564,8 +586,8 @@
608 tpc->cur_rx = 0;
610 - RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
611 - RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
612 + RTL_W32(TxDescStartAddr, virt_to_le32desc((u32)tpc->TxDescArray));
613 + RTL_W32(RxDescStartAddr, virt_to_le32desc((u32)tpc->RxDescArray));
614 RTL_W8(Cfg9346, Cfg9346_Lock);
615 udelay(10);
617 @@ -603,13 +625,14 @@
618 for (i = 0; i < NUM_RX_DESC; i++) {
619 if (i == (NUM_RX_DESC - 1))
620 tpc->RxDescArray[i].status =
621 - (OWNbit | EORbit) + RX_BUF_SIZE;
622 + cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
623 else
624 - tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
625 + tpc->RxDescArray[i].status =
626 + cpu_to_le32(OWNbit + RX_BUF_SIZE);
628 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
629 tpc->RxDescArray[i].buf_addr =
630 - virt_to_bus(tpc->RxBufferRing[i]);
631 + cpu_to_le32((u32)tpc->RxBufferRing[i]);
632 }
634 #ifdef DEBUG_RTL8169
635 @@ -620,7 +643,7 @@
636 /**************************************************************************
637 RESET - Finish setting up the ethernet interface
638 ***************************************************************************/
639 -static void rtl_reset(struct eth_device *dev, bd_t *bis)
640 +static int rtl_reset(struct eth_device *dev, bd_t *bis)
641 {
642 int i;
643 u8 diff;
644 @@ -635,21 +658,27 @@
645 if (tpc->TxDescArrays == 0)
646 puts("Allot Error");
647 /* Tx Desscriptor needs 256 bytes alignment; */
648 - TxPhyAddr = virt_to_bus(tpc->TxDescArrays);
649 + TxPhyAddr = (u32)tpc->TxDescArrays;
650 diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
651 TxPhyAddr += diff;
652 tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff);
653 +#ifdef DEBUG_RTL8169
654 + printf("tpc->TxDescArray: %08X\n", tpc->TxDescArray);
655 +#endif
657 tpc->RxDescArrays = rx_ring;
658 /* Rx Desscriptor needs 256 bytes alignment; */
659 - RxPhyAddr = virt_to_bus(tpc->RxDescArrays);
660 + RxPhyAddr = (u32)tpc->RxDescArrays;
661 diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
662 RxPhyAddr += diff;
663 tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff);
664 +#ifdef DEBUG_RTL8169
665 + printf("tpc->RxDescArray: %08X\n", tpc->RxDescArray);
666 +#endif
668 if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) {
669 puts("Allocate RxDescArray or TxDescArray failed\n");
670 - return;
671 + return 0;
672 }
674 rtl8169_init_ring(dev);
675 @@ -669,6 +698,7 @@
676 #ifdef DEBUG_RTL8169
677 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
678 #endif
679 + return 1;
680 }
682 /**************************************************************************
683 @@ -733,7 +763,7 @@
685 /* Get MAC address. FIXME: read EEPROM */
686 for (i = 0; i < MAC_ADDR_LEN; i++)
687 - dev->enetaddr[i] = RTL_R8(MAC0 + i);
688 + bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i);
690 #ifdef DEBUG_RTL8169
691 printf("MAC Address");
692 @@ -814,17 +844,14 @@
693 if (option & _1000bpsF) {
694 #ifdef DEBUG_RTL8169
695 printf("%s: 1000Mbps Full-duplex operation.\n",
696 - dev->name);
697 + dev->name);
698 #endif
699 } else {
700 #ifdef DEBUG_RTL8169
701 - printf
702 - ("%s: %sMbps %s-duplex operation.\n",
703 - dev->name,
704 - (option & _100bps) ? "100" :
705 - "10",
706 - (option & FullDup) ? "Full" :
707 - "Half");
708 + printf("%s: %sMbps %s-duplex operation.\n",
709 + dev->name,
710 + (option & _100bps) ? "100" : "10",
711 + (option & FullDup) ? "Full" : "Half");
712 #endif
713 }
714 break;
715 @@ -886,3 +913,5 @@
716 }
718 #endif
719 +
720 +/* vim: set ts=4: */
721 Index: u-boot-1.2.0/include/configs/qnap.h
722 ===================================================================
723 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
724 +++ u-boot-1.2.0/include/configs/qnap.h 2007-04-07 21:56:55.376393000 +0200
725 @@ -0,0 +1,363 @@
726 +/*
727 + * Copyright (C) 2006 Andrew Luyten <u-boot@luyten.org.uk>
728 + *
729 + * See file CREDITS for list of people who contributed to this
730 + * project.
731 + *
732 + * This program is free software; you can redistribute it and/or
733 + * modify it under the terms of the GNU General Public License as
734 + * published by the Free Software Foundation; either version 2 of
735 + * the License, or (at your option) any later version.
736 + *
737 + * This program is distributed in the hope that it will be useful,
738 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
739 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
740 + * GNU General Public License for more details.
741 + *
742 + * You should have received a copy of the GNU General Public License
743 + * along with this program; if not, write to the Free Software
744 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
745 + * MA 02111-1307 USA
746 + */
747 +
748 +/* ------------------------------------------------------------------------- */
749 +
750 +/*
751 + * board/config.h - configuration options, board specific
752 + */
753 +
754 +#ifndef __CONFIG_H
755 +#define __CONFIG_H
756 +
757 +/*
758 + * High Level Configuration Options
759 + * (easy to change)
760 + */
761 +
762 +#define CONFIG_MPC824X 1
763 +#define CONFIG_MPC8245 1
764 +#define CONFIG_MPC8241 1
765 +
766 +#define CONFIG_IDENT_STRING " OpenTS(c)"
767 +#define CONFIG_TIMESTAMP
768 +#define CFG_HUSH_PARSER 1
769 +#define CFG_PROMPT_HUSH_PS2 "turbostation> "
770 +#define CONFIG_BOOTDELAY 3
771 +
772 +
773 +/*----------------------------------------------------------------------
774 + * Define supported commands
775 + */
776 +
777 +#define CONFIG_COMMANDS ( \
778 + CONFIG_CMD_DFL | \
779 + CFG_CMD_ELF | \
780 + CFG_CMD_I2C | \
781 + CFG_CMD_PING | \
782 + CFG_CMD_DHCP | \
783 + CFG_CMD_IDE | \
784 + CFG_CMD_EXT2 | \
785 + CFG_CMD_DATE | \
786 + CFG_CMD_PCI )
787 +
788 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
789 +#include <cmd_confdefs.h>
790 +
791 +
792 +/*-----------------------------------------------------------------------
793 + * Miscellaneous configurable options
794 + */
795 +
796 +#define CFG_LONGHELP 1 /* undef to save memory */
797 +#define CFG_PROMPT "=> " /* Monitor Command Prompt*/
798 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/
799 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size*/
800 +#define CFG_MAXARGS 16 /* max number of command args*/
801 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/
802 +#define CFG_LOAD_ADDR 0x00100000 /* default load address */
803 +#define CFG_HZ 1000 /* decrementer freq:1 ms ticks*/
804 +
805 +
806 +/*-----------------------------------------------------------------------
807 + * PCI
808 + *
809 + */
810 +
811 +#define CONFIG_PCI
812 +#undef CONFIG_PCI_PNP
813 +
814 +#define PCI_ETH_IOADDR 0xbffe00
815 +#define PCI_ETH_MEMADDR 0xbfffce00
816 +
817 +#define PCI_IDE_IOADDR 0xbfffd0
818 +#define PCI_IDE_MEMADDR 0xbffffe00
819 +
820 +#define PCI_USB0_IOADDR 0
821 +#define PCI_USB0_MEMADDR 0xbfffe000
822 +#define PCI_USB1_IOADDR 0
823 +#define PCI_USB1_MEMADDR 0xbfffd000
824 +#define PCI_USB2_IOADDR 0
825 +#define PCI_USB2_MEMADDR 0xbfffcf00
826 +
827 +
828 +/*-----------------------------------------------------------------------
829 + * Start addresses for the final memory configuration
830 + * (Set up by the startup code)
831 + */
832 +
833 +#define CFG_SDRAM_BASE 0x00000000
834 +#define CFG_MONITOR_BASE TEXT_BASE
835 +#undef CFG_RAMBOOT
836 +
837 +#define CFG_PCI_MEM_ADDR 0xB0000000
838 +#define CFG_EUMB_ADDR 0xFC000000
839 +#define CFG_FLASH_BASE 0xFF000000
840 +
841 +#define CFG_RESET_ADDRESS 0xFFF00100
842 +
843 +#define CFG_MONITOR_LEN (256 << 10)
844 +#define CFG_MALLOC_LEN (512 << 10)
845 +
846 +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
847 +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
848 +#define CFG_MAX_RAM_SIZE 0x10000000 /* up to 256M of SDRAM */
849 +
850 +
851 +/*-----------------------------------------------------------------------
852 + * Definitions for initial stack pointer and data area
853 + */
854 +
855 +#define CFG_INIT_RAM_ADDR 0x40000000
856 +#define CFG_INIT_RAM_END 0x1000
857 +#define CFG_GBL_DATA_SIZE 128
858 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
859 +
860 +
861 +/*-----------------------------------------------------------------------
862 + * FLASH organization
863 + */
864 +
865 +#define CFG_FLASH_CFI 1
866 +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
867 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
868 +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip*/
869 +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
870 +#define CFG_FLASH_USE_BUFFER_WRITE /* faster writes */
871 +
872 +#define CFG_ENV_IS_IN_FLASH 1
873 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00EA0000)
874 +#define CFG_ENV_SECT_SIZE 0x00020000 /* Total Size of Environment Sector*/
875 +
876 +
877 +/*-----------------------------------------------------------------------
878 + * Gigabit Ethernet
879 + */
880 +
881 +#define CONFIG_NET_MULTI
882 +#define CONFIG_RTL8169
883 +
884 +
885 +/*-----------------------------------------------------------------------
886 + * Filesystems
887 + */
888 +
889 +#define CONFIG_MAC_PARTITION
890 +#define CONFIG_DOS_PARTITION
891 +//#define CONFIG_ISO_PARTITION
892 +
893 +
894 +/*-----------------------------------------------------------------------
895 + * IDE/ATA
896 + */
897 +
898 +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
899 +#undef CONFIG_IDE_LED /* no led for ide supported */
900 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
901 +#undef CONFIG_ATAPI /* no ATAPI support */
902 +
903 +#define CONFIG_IDE_PREINIT /* To set up MMIO adresses */
904 +#define CONFIG_LBA48 /* Large disk support */
905 +
906 +#define CFG_IDE_MAXBUS 2 /* Two channels x 1 device each */
907 +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1)
908 +
909 +#define CFG_ATA_BASE_ADDR 0x0000 /* Set up in board specific code */
910 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
911 +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
912 +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
913 +
914 +
915 +/*----------------------------------------------------------------------
916 + * On Chip Serial configuration
917 + */
918 +
919 +#define CONFIG_CONS_INDEX 1
920 +#define CONFIG_BAUDRATE 115200
921 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
922 +
923 +#define CFG_NS16550
924 +#define CFG_NS16550_SERIAL
925 +
926 +#define CFG_NS16550_REG_SIZE 1
927 +#define CFG_NS16550_CLK get_bus_freq(0)
928 +
929 +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) /* Console port */
930 +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) /* PIC ? */
931 +
932 +
933 +/*----------------------------------------------------------------------
934 + * i2c support configuration
935 + */
936 +
937 +#define CONFIG_HARD_I2C 1 /* To enable I2C support */
938 +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
939 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
940 +#define CFG_I2C_SLAVE 0x7F
941 +
942 +#define CONFIG_RTC_RS5C372A /* Real-time clock chip */
943 +
944 +
945 +/*----------------------------------------------------------------------
946 + * Low Level Configuration Settings
947 + * (address mappings, register initial values, etc.)
948 + * You should know what you are doing if you make changes here.
949 + */
950 +
951 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
952 +
953 +#define CFG_ROMNAL 7 /*rom/flash next access time */
954 +#define CFG_ROMFAL 11 /*rom/flash access time */
955 +
956 +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
957 +
958 +/* the following are for SDRAM only*/
959 +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
960 +#define CFG_REFREC 8 /* Refresh to activate interval */
961 +#define CFG_RDLAT 4 /* data latency from read command */
962 +#define CFG_PRETOACT 3 /* Precharge to activate interval */
963 +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
964 +#define CFG_ACTORW 3 /* Activate to R/W */
965 +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
966 +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
967 +
968 +#define CFG_REGISTERD_TYPE_BUFFER 1
969 +#define CFG_EXTROM 1
970 +#define CFG_REGDIMM 0
971 +
972 +
973 +/*----------------------------------------------------------------------
974 + * memory bank settings
975 + *
976 + * only bits 20-29 are actually used from these vales to set the
977 + * start/end address the upper two bits will be 0, and the lower 20
978 + * bits will be set to 0x00000 for a start address, or 0xfffff for an
979 + * end address
980 + */
981 +
982 +#define CFG_BANK0_START 0x00000000
983 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
984 +#define CFG_BANK0_ENABLE 1
985 +#define CFG_BANK1_START 0x3ff00000
986 +#define CFG_BANK1_END 0x3fffffff
987 +#define CFG_BANK1_ENABLE 0
988 +#define CFG_BANK2_START 0x3ff00000
989 +#define CFG_BANK2_END 0x3fffffff
990 +#define CFG_BANK2_ENABLE 0
991 +#define CFG_BANK3_START 0x3ff00000
992 +#define CFG_BANK3_END 0x3fffffff
993 +#define CFG_BANK3_ENABLE 0
994 +#define CFG_BANK4_START 0x00000000
995 +#define CFG_BANK4_END 0x00000000
996 +#define CFG_BANK4_ENABLE 0
997 +#define CFG_BANK5_START 0x00000000
998 +#define CFG_BANK5_END 0x00000000
999 +#define CFG_BANK5_ENABLE 0
1000 +#define CFG_BANK6_START 0x00000000
1001 +#define CFG_BANK6_END 0x00000000
1002 +#define CFG_BANK6_ENABLE 0
1003 +#define CFG_BANK7_START 0x00000000
1004 +#define CFG_BANK7_END 0x00000000
1005 +#define CFG_BANK7_ENABLE 0
1006 +
1007 +
1008 +/*
1009 + * Memory bank enable bitmask, specifying which of the banks defined above
1010 + are actually present. MSB is for bank #7, LSB is for bank #0.
1011 + */
1012 +#define CFG_BANK_ENABLE 0x01
1013 +
1014 +#define CFG_ODCR 0xff /* configures line driver impedances, */
1015 + /* see 8240 book for bit definitions */
1016 +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
1017 + /* currently accessed page in memory */
1018 + /* see 8240 book for details */
1019 +#define CFG_DBUS_SIZE2 1
1020 +#define CFG_BANK0_ROW 2
1021 +
1022 +
1023 +/*----------------------------------------------------------------------
1024 + * Initial BAT mappings
1025 + */
1026 +
1027 +/* SDRAM 0 - 256MB */
1028 +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
1029 +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
1030 +
1031 +/* stack in DCACHE @ 1GB (no backing mem) */
1032 +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
1033 +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
1034 +
1035 +/* PCI memory */
1036 +#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
1037 +#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)
1038 +
1039 +/* Flash, config addrs, etc */
1040 +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
1041 +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
1042 +
1043 +#define CFG_DBAT0L CFG_IBAT0L
1044 +#define CFG_DBAT0U CFG_IBAT0U
1045 +#define CFG_DBAT1L CFG_IBAT1L
1046 +#define CFG_DBAT1U CFG_IBAT1U
1047 +#define CFG_DBAT2L CFG_IBAT2L
1048 +#define CFG_DBAT2U CFG_IBAT2U
1049 +#define CFG_DBAT3L CFG_IBAT3L
1050 +#define CFG_DBAT3U CFG_IBAT3U
1051 +
1052 +/*
1053 + * For booting Linux, the board info and command line data
1054 + * have to be in the first 8 MB of memory, since this is
1055 + * the maximum mapped by the Linux kernel during initialization.
1056 + */
1057 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
1058 +
1059 +
1060 +/*-----------------------------------------------------------------------
1061 + * Cache Configuration
1062 + */
1063 +
1064 +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
1065 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
1066 +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
1067 +#endif
1068 +
1069 +
1070 +/*-----------------------------------------------------------------------
1071 + * Internal Definitions
1072 + *
1073 + * Boot Flags
1074 + */
1075 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1076 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
1077 +
1078 +/* pass open firmware flat tree */
1079 +#define CONFIG_OF_FLAT_TREE 1
1080 +
1081 +/* maximum size of the flat tree (8K) */
1082 +#define OF_FLAT_TREE_MAX_SIZE 8192
1083 +
1084 +#define OF_CPU "PowerPC,603e"
1085 +#define OF_STDOUT_PATH "/soc10x/serial@fc004500"
1086 +
1087 +#endif /* __CONFIG_H */
1088 +
1089 --- u-boot-1.2.0.vanilla/Makefile 2007-01-07 00:13:11.000000000 +0100
1090 +++ u-boot-1.2.0/Makefile 2007-02-26 01:55:37.000000000 +0100
1091 @@ -1296,6 +1296,9 @@
1092 PN62_config: unconfig
1093 @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62
1095 +qnap_config: unconfig
1096 + @$(MKCONFIG) $(@:_config=) ppc mpc824x qnap
1097 +
1098 Sandpoint8240_config: unconfig
1099 @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint