1 From e7665ffb72cbc890b8494c687b335e3e242231d9 Mon Sep 17 00:00:00 2001
2 From: Tomi Valkeinen <tomi.valkeinen@ti.com>
3 Date: Fri, 15 Apr 2011 10:42:59 +0300
4 Subject: [PATCH 04/31] OMAP: DSS: DSI: Fix DSI PLL power bug
6 OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3)
7 to not work properly. The bug prevents us from enabling DSI PLL power
8 only to HS divider block.
10 This patch adds a dss feature for the bug and converts POWER_ON_DIV
11 requests to POWER_ON_ALL (0x2).
13 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
15 drivers/video/omap2/dss/dsi.c | 5 +++++
16 drivers/video/omap2/dss/dss_features.c | 2 +-
17 drivers/video/omap2/dss/dss_features.h | 2 ++
18 3 files changed, 8 insertions(+), 1 deletions(-)
20 diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
21 index 1464ac4..cbd9ca4 100644
22 --- a/drivers/video/omap2/dss/dsi.c
23 +++ b/drivers/video/omap2/dss/dsi.c
24 @@ -1059,6 +1059,11 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
28 + /* DSI-PLL power command 0x3 is not working */
29 + if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
30 + state == DSI_PLL_POWER_ON_DIV)
31 + state = DSI_PLL_POWER_ON_ALL;
33 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
36 diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
37 index aa16222..8c50e18 100644
38 --- a/drivers/video/omap2/dss/dss_features.c
39 +++ b/drivers/video/omap2/dss/dss_features.c
40 @@ -271,7 +271,7 @@ static struct omap_dss_features omap3630_dss_features = {
41 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
42 FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
43 FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
45 + FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG,
49 diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
50 index 12e9c4e..37922ce 100644
51 --- a/drivers/video/omap2/dss/dss_features.h
52 +++ b/drivers/video/omap2/dss/dss_features.h
53 @@ -40,6 +40,8 @@ enum dss_feat_id {
54 /* Independent core clk divider */
55 FEAT_CORE_CLK_DIV = 1 << 11,
56 FEAT_LCD_CLK_SRC = 1 << 12,
57 + /* DSI-PLL power command 0x3 is not working */
58 + FEAT_DSI_PLL_PWR_BUG = 1 << 13,
61 /* DSS register field id */