1 /* mips16 floating point support code
2 Copyright (C) 1996, 1997, 1998, 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Cygnus Support
5 This file is free software; you can redistribute it and/or modify it
6 under the terms of the GNU General Public License as published by the
7 Free Software Foundation; either version 3, or (at your option) any
10 This file is distributed in the hope that it will be useful, but
11 WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 General Public License for more details.
15 Under Section 7 of GPL version 3, you are granted additional
16 permissions described in the GCC Runtime Library Exception, version
17 3.1, as published by the Free Software Foundation.
19 You should have received a copy of the GNU General Public License and
20 a copy of the GCC Runtime Library Exception along with this program;
21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
22 <http://www.gnu.org/licenses/>. */
24 /* This file contains mips16 floating point support functions. These
25 functions are called by mips16 code to handle floating point when
26 -msoft-float is not used. They accept the arguments and return
27 values using the soft-float calling convention, but do the actual
28 operation using the hard floating point instructions. */
30 #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64)
32 /* This file contains 32-bit assembly code. */
35 /* Start a function. */
37 #define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
39 /* Finish a function. */
41 #define ENDFN(NAME) .end NAME
44 The FPR that holds the first floating-point argument.
47 The FPR that holds the second floating-point argument.
50 The FPR that holds a floating-point return value. */
60 /* Set 64-bit register GPR so that its high 32 bits contain HIGH_FPR
61 and so that its low 32 bits contain LOW_FPR. */
62 #define MERGE_GPRf(GPR, HIGH_FPR, LOW_FPR) \
72 /* Move the high 32 bits of GPR to HIGH_FPR and the low 32 bits of
74 #define MERGE_GPRt(GPR, HIGH_FPR, LOW_FPR) \
81 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
82 #define DELAYt(T, OPCODE, OP2) \
88 /* Use "OPCODE. OP2" and jump to T. */
89 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
92 Move the first single-precision floating-point argument between
96 Likewise the first single-precision integer argument.
99 Move the second single-precision floating-point argument between
100 GPRs and FPRs, given that the first argument occupies 4 bytes.
103 Move the second single-precision floating-point argument between
104 GPRs and FPRs, given that the first argument occupies 8 bytes.
107 Move the first double-precision floating-point argument between
111 Likewise the second double-precision floating-point argument.
114 Likewise a single-precision floating-point return value,
118 Likewise a complex single-precision floating-point return value.
121 Likewise a double-precision floating-point return value.
124 Likewise a complex double-precision floating-point return value.
127 Likewise a single-precision integer return value.
129 The D argument is "t" to move to FPRs and "f" to move from FPRs.
130 The return macros may assume that the target of the jump does not
131 use a floating-point register. */
133 #define MOVE_SF_RET(D, T) DELAY##D (T, m##D##c1 $2,$f0)
134 #define MOVE_SI_RET(D, T) DELAY##D (T, m##D##c1 $2,$f0)
136 #if defined(__mips64) && defined(__MIPSEB__)
137 #define MOVE_SC_RET(D, T) MERGE_GPR##D ($2, $f0, $f1); jr T
138 #elif defined(__mips64)
139 /* The high 32 bits of $2 correspond to the second word in memory;
140 i.e. the imaginary part. */
141 #define MOVE_SC_RET(D, T) MERGE_GPR##D ($2, $f1, $f0); jr T
142 #elif __mips_fpr == 64
143 #define MOVE_SC_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f1)
145 #define MOVE_SC_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f2)
148 #if defined(__mips64)
149 #define MOVE_SF_BYTE0(D) m##D##c1 $4,$f12
150 #define MOVE_SF_BYTE4(D) m##D##c1 $5,$f13
151 #define MOVE_SF_BYTE8(D) m##D##c1 $5,$f13
153 #define MOVE_SF_BYTE0(D) m##D##c1 $4,$f12
154 #define MOVE_SF_BYTE4(D) m##D##c1 $5,$f14
155 #define MOVE_SF_BYTE8(D) m##D##c1 $6,$f14
157 #define MOVE_SI_BYTE0(D) MOVE_SF_BYTE0(D)
159 #if defined(__mips64)
160 #define MOVE_DF_BYTE0(D) dm##D##c1 $4,$f12
161 #define MOVE_DF_BYTE8(D) dm##D##c1 $5,$f13
162 #define MOVE_DF_RET(D, T) DELAY##D (T, dm##D##c1 $2,$f0)
163 #define MOVE_DC_RET(D, T) dm##D##c1 $3,$f1; MOVE_DF_RET (D, T)
164 #elif __mips_fpr == 64 && defined(__MIPSEB__)
165 #define MOVE_DF_BYTE0(D) m##D##c1 $5,$f12; m##D##hc1 $4,$f12
166 #define MOVE_DF_BYTE8(D) m##D##c1 $7,$f14; m##D##hc1 $6,$f14
167 #define MOVE_DF_RET(D, T) m##D##c1 $3,$f0; DELAY##D (T, m##D##hc1 $2,$f0)
168 #define MOVE_DC_RET(D, T) m##D##c1 $5,$f1; m##D##hc1 $4,$f1; MOVE_DF_RET (D, T)
169 #elif __mips_fpr == 64
170 #define MOVE_DF_BYTE0(D) m##D##c1 $4,$f12; m##D##hc1 $5,$f12
171 #define MOVE_DF_BYTE8(D) m##D##c1 $6,$f14; m##D##hc1 $7,$f14
172 #define MOVE_DF_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##hc1 $3,$f0)
173 #define MOVE_DC_RET(D, T) m##D##c1 $4,$f1; m##D##hc1 $5,$f1; MOVE_DF_RET (D, T)
174 #elif defined(__MIPSEB__)
175 /* FPRs are little-endian. */
176 #define MOVE_DF_BYTE0(D) m##D##c1 $4,$f13; m##D##c1 $5,$f12
177 #define MOVE_DF_BYTE8(D) m##D##c1 $6,$f15; m##D##c1 $7,$f14
178 #define MOVE_DF_RET(D, T) m##D##c1 $2,$f1; DELAY##D (T, m##D##c1 $3,$f0)
179 #define MOVE_DC_RET(D, T) m##D##c1 $4,$f3; m##D##c1 $5,$f2; MOVE_DF_RET (D, T)
181 #define MOVE_DF_BYTE0(D) m##D##c1 $4,$f12; m##D##c1 $5,$f13
182 #define MOVE_DF_BYTE8(D) m##D##c1 $6,$f14; m##D##c1 $7,$f15
183 #define MOVE_DF_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f1)
184 #define MOVE_DC_RET(D, T) m##D##c1 $4,$f2; m##D##c1 $5,$f3; MOVE_DF_RET (D, T)
187 /* Single-precision math. */
189 /* Define a function NAME that loads two single-precision values,
190 performs FPU operation OPCODE on them, and returns the single-
193 #define OPSF3(NAME, OPCODE) \
197 OPCODE RET,ARG1,ARG2; \
198 MOVE_SF_RET (f, $31); \
202 OPSF3 (__mips16_addsf3, add.s)
205 OPSF3 (__mips16_subsf3, sub.s)
208 OPSF3 (__mips16_mulsf3, mul.s)
211 OPSF3 (__mips16_divsf3, div.s)
214 /* Define a function NAME that loads a single-precision value,
215 performs FPU operation OPCODE on it, and returns the single-
218 #define OPSF2(NAME, OPCODE) \
222 MOVE_SF_RET (f, $31); \
226 OPSF2 (__mips16_negsf2, neg.s)
229 OPSF2 (__mips16_abssf2, abs.s)
232 /* Single-precision comparisons. */
234 /* Define a function NAME that loads two single-precision values,
235 performs floating point comparison OPCODE, and returns TRUE or
236 FALSE depending on the result. */
238 #define CMPSF(NAME, OPCODE, TRUE, FALSE) \
250 /* Like CMPSF, but reverse the comparison operands. */
252 #define REVCMPSF(NAME, OPCODE, TRUE, FALSE) \
265 CMPSF (__mips16_eqsf2, c.eq.s, 0, 1)
268 CMPSF (__mips16_nesf2, c.eq.s, 0, 1)
271 REVCMPSF (__mips16_gtsf2, c.lt.s, 1, 0)
274 REVCMPSF (__mips16_gesf2, c.le.s, 0, -1)
277 CMPSF (__mips16_lesf2, c.le.s, 0, 1)
280 CMPSF (__mips16_ltsf2, c.lt.s, -1, 0)
283 CMPSF(__mips16_unordsf2, c.un.s, 1, 0)
287 /* Single-precision conversions. */
290 STARTFN (__mips16_floatsisf)
294 ENDFN (__mips16_floatsisf)
297 #ifdef L_m16fltunsisf
298 STARTFN (__mips16_floatunsisf)
313 ENDFN (__mips16_floatunsisf)
316 #ifdef L_m16fix_truncsfsi
317 STARTFN (__mips16_fix_truncsfsi)
319 trunc.w.s RET,ARG1,$4
321 ENDFN (__mips16_fix_truncsfsi)
324 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
326 /* Double-precision math. */
328 /* Define a function NAME that loads two double-precision values,
329 performs FPU operation OPCODE on them, and returns the double-
332 #define OPDF3(NAME, OPCODE) \
336 OPCODE RET,ARG1,ARG2; \
337 MOVE_DF_RET (f, $31); \
341 OPDF3 (__mips16_adddf3, add.d)
344 OPDF3 (__mips16_subdf3, sub.d)
347 OPDF3 (__mips16_muldf3, mul.d)
350 OPDF3 (__mips16_divdf3, div.d)
353 /* Define a function NAME that loads a double-precision value,
354 performs FPU operation OPCODE on it, and returns the double-
357 #define OPDF2(NAME, OPCODE) \
361 MOVE_DF_RET (f, $31); \
365 OPDF2 (__mips16_negdf2, neg.d)
368 OPDF2 (__mips16_absdf2, abs.d)
371 /* Conversions between single and double precision. */
374 STARTFN (__mips16_extendsfdf2)
378 ENDFN (__mips16_extendsfdf2)
382 STARTFN (__mips16_truncdfsf2)
386 ENDFN (__mips16_truncdfsf2)
389 /* Double-precision comparisons. */
391 /* Define a function NAME that loads two double-precision values,
392 performs floating point comparison OPCODE, and returns TRUE or
393 FALSE depending on the result. */
395 #define CMPDF(NAME, OPCODE, TRUE, FALSE) \
407 /* Like CMPDF, but reverse the comparison operands. */
409 #define REVCMPDF(NAME, OPCODE, TRUE, FALSE) \
422 CMPDF (__mips16_eqdf2, c.eq.d, 0, 1)
425 CMPDF (__mips16_nedf2, c.eq.d, 0, 1)
428 REVCMPDF (__mips16_gtdf2, c.lt.d, 1, 0)
431 REVCMPDF (__mips16_gedf2, c.le.d, 0, -1)
434 CMPDF (__mips16_ledf2, c.le.d, 0, 1)
437 CMPDF (__mips16_ltdf2, c.lt.d, -1, 0)
440 CMPDF(__mips16_unorddf2, c.un.d, 1, 0)
443 /* Double-precision conversions. */
446 STARTFN (__mips16_floatsidf)
450 ENDFN (__mips16_floatsidf)
453 #ifdef L_m16fltunsidf
454 STARTFN (__mips16_floatunsidf)
458 li.d ARG1, 4.294967296e+9
460 1: MOVE_DF_RET (f, $31)
461 ENDFN (__mips16_floatunsidf)
464 #ifdef L_m16fix_truncdfsi
465 STARTFN (__mips16_fix_truncdfsi)
467 trunc.w.d RET,ARG1,$4
469 ENDFN (__mips16_fix_truncdfsi)
471 #endif /* !__mips_single_float */
473 /* Define a function NAME that moves a return value of mode MODE from
476 #define RET_FUNCTION(NAME, MODE) \
478 MOVE_##MODE##_RET (t, $31); \
482 RET_FUNCTION (__mips16_ret_sf, SF)
486 RET_FUNCTION (__mips16_ret_sc, SC)
489 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
491 RET_FUNCTION (__mips16_ret_df, DF)
495 RET_FUNCTION (__mips16_ret_dc, DC)
497 #endif /* !__mips_single_float */
499 /* STUB_ARGS_X copies the arguments from GPRs to FPRs for argument
500 code X. X is calculated as ARG1 + ARG2 * 4, where ARG1 and ARG2
501 classify the first and second arguments as follows:
503 1: a single-precision argument
504 2: a double-precision argument
505 0: no argument, or not one of the above. */
507 #define STUB_ARGS_0 /* () */
508 #define STUB_ARGS_1 MOVE_SF_BYTE0 (t) /* (sf) */
509 #define STUB_ARGS_5 MOVE_SF_BYTE0 (t); MOVE_SF_BYTE4 (t) /* (sf, sf) */
510 #define STUB_ARGS_9 MOVE_SF_BYTE0 (t); MOVE_DF_BYTE8 (t) /* (sf, df) */
511 #define STUB_ARGS_2 MOVE_DF_BYTE0 (t) /* (df) */
512 #define STUB_ARGS_6 MOVE_DF_BYTE0 (t); MOVE_SF_BYTE8 (t) /* (df, sf) */
513 #define STUB_ARGS_10 MOVE_DF_BYTE0 (t); MOVE_DF_BYTE8 (t) /* (df, df) */
515 /* These functions are used by 16-bit code when calling via a function
516 pointer. They must copy the floating point arguments from the GPRs
517 to FPRs and then call function $2. */
519 #define CALL_STUB_NO_RET(NAME, CODE) \
529 CALL_STUB_NO_RET (__mips16_call_stub_1, 1)
533 CALL_STUB_NO_RET (__mips16_call_stub_5, 5)
536 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
539 CALL_STUB_NO_RET (__mips16_call_stub_2, 2)
543 CALL_STUB_NO_RET (__mips16_call_stub_6, 6)
547 CALL_STUB_NO_RET (__mips16_call_stub_9, 9)
551 CALL_STUB_NO_RET (__mips16_call_stub_10, 10)
553 #endif /* !__mips_single_float */
555 /* Now we have the same set of functions, except that this time the
556 function being called returns an SFmode, SCmode, DFmode or DCmode
557 value; we need to instantiate a set for each case. The calling
558 function will arrange to preserve $18, so these functions are free
559 to use it to hold the return address.
561 Note that we do not know whether the function we are calling is 16
562 bit or 32 bit. However, it does not matter, because 16-bit
563 functions always return floating point values in both the gp and
564 the fp regs. It would be possible to check whether the function
565 being called is 16 bits, in which case the copy is unnecessary;
566 however, it's faster to always do the copy. */
568 #define CALL_STUB_RET(NAME, CODE, MODE) \
576 MOVE_##MODE##_RET (f, $18); \
579 /* First, instantiate the single-float set. */
582 CALL_STUB_RET (__mips16_call_stub_sf_0, 0, SF)
586 CALL_STUB_RET (__mips16_call_stub_sf_1, 1, SF)
590 CALL_STUB_RET (__mips16_call_stub_sf_5, 5, SF)
593 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
595 CALL_STUB_RET (__mips16_call_stub_sf_2, 2, SF)
599 CALL_STUB_RET (__mips16_call_stub_sf_6, 6, SF)
603 CALL_STUB_RET (__mips16_call_stub_sf_9, 9, SF)
607 CALL_STUB_RET (__mips16_call_stub_sf_10, 10, SF)
609 #endif /* !__mips_single_float */
612 /* Now we have the same set of functions again, except that this time
613 the function being called returns an DFmode value. */
615 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
617 CALL_STUB_RET (__mips16_call_stub_df_0, 0, DF)
621 CALL_STUB_RET (__mips16_call_stub_df_1, 1, DF)
625 CALL_STUB_RET (__mips16_call_stub_df_5, 5, DF)
629 CALL_STUB_RET (__mips16_call_stub_df_2, 2, DF)
633 CALL_STUB_RET (__mips16_call_stub_df_6, 6, DF)
637 CALL_STUB_RET (__mips16_call_stub_df_9, 9, DF)
641 CALL_STUB_RET (__mips16_call_stub_df_10, 10, DF)
643 #endif /* !__mips_single_float */
646 /* Ho hum. Here we have the same set of functions again, this time
647 for when the function being called returns an SCmode value. */
650 CALL_STUB_RET (__mips16_call_stub_sc_0, 0, SC)
654 CALL_STUB_RET (__mips16_call_stub_sc_1, 1, SC)
658 CALL_STUB_RET (__mips16_call_stub_sc_5, 5, SC)
661 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
663 CALL_STUB_RET (__mips16_call_stub_sc_2, 2, SC)
667 CALL_STUB_RET (__mips16_call_stub_sc_6, 6, SC)
671 CALL_STUB_RET (__mips16_call_stub_sc_9, 9, SC)
675 CALL_STUB_RET (__mips16_call_stub_sc_10, 10, SC)
677 #endif /* !__mips_single_float */
680 /* Finally, another set of functions for DCmode. */
682 #if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
684 CALL_STUB_RET (__mips16_call_stub_dc_0, 0, DC)
688 CALL_STUB_RET (__mips16_call_stub_dc_1, 1, DC)
692 CALL_STUB_RET (__mips16_call_stub_dc_5, 5, DC)
696 CALL_STUB_RET (__mips16_call_stub_dc_2, 2, DC)
700 CALL_STUB_RET (__mips16_call_stub_dc_6, 6, DC)
704 CALL_STUB_RET (__mips16_call_stub_dc_9, 9, DC)
708 CALL_STUB_RET (__mips16_call_stub_dc_10, 10, DC)
710 #endif /* !__mips_single_float */