gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 /* Driver configuration.  */
  23
  24 /* A generic LIB_SPEC with -leval and --*group tacked on.  */
  25 #undef  LIB_SPEC
  26 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  27
  28 #undef STARTFILE_SPEC
  29 #undef ENDFILE_SPEC
  30
  31 #undef  LINK_SPEC
  32 #define LINK_SPEC "%{h*} %{v:-V} \
  33                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  34
  35 \f
  36 /* Run-time target specifications.  */
  37
  38 #define TARGET_CPU_CPP_BUILTINS()               \
  39   do                                            \
  40     {                                           \
  41       builtin_define ("__iq2000__");            \
  42       builtin_assert ("cpu=iq2000");            \
  43       builtin_assert ("machine=iq2000");        \
  44     }                                           \
  45   while (0)
  46
  47 /* Macros used in the machine description to test the flags.  */
  48
  49 #define TARGET_STATS            0
  50
  51 #define TARGET_DEBUG_MODE       0
  52 #define TARGET_DEBUG_A_MODE     0
  53 #define TARGET_DEBUG_B_MODE     0
  54 #define TARGET_DEBUG_C_MODE     0
  55 #define TARGET_DEBUG_D_MODE     0
  56
  57 #ifndef IQ2000_ISA_DEFAULT
  58 #define IQ2000_ISA_DEFAULT 1
  59 #endif
  60
  61 #define IQ2000_VERSION "[1.0]"
  62
  63 #ifndef MACHINE_TYPE
  64 #define MACHINE_TYPE "IQ2000"
  65 #endif
  66
  67 #ifndef TARGET_VERSION_INTERNAL
  68 #define TARGET_VERSION_INTERNAL(STREAM)                                 \
  69   fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
  70 #endif
  71
  72 #ifndef TARGET_VERSION
  73 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
  74 #endif
  75 \f
  76 /* Storage Layout.  */
  77
  78 #define BITS_BIG_ENDIAN                 0
  79 #define BYTES_BIG_ENDIAN                1
  80 #define WORDS_BIG_ENDIAN                1
  81 #define BITS_PER_WORD                   32
  82 #define MAX_BITS_PER_WORD               64
  83 #define UNITS_PER_WORD                  4
  84 #define MIN_UNITS_PER_WORD              4
  85 #define POINTER_SIZE                    32
  86
  87 /* Define this macro if it is advisable to hold scalars in registers
  88    in a wider mode than that declared by the program.  In such cases,
  89    the value is constrained to be within the bounds of the declared
  90    type, but kept valid in the wider mode.  The signedness of the
  91    extension may differ from that of the type.
  92
  93    We promote any value smaller than SImode up to SImode.  */
  94
  95 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  96   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  97       && GET_MODE_SIZE (MODE) < 4)              \
  98     (MODE) = SImode;
  99
 100 #define PARM_BOUNDARY 32
 101
 102 #define STACK_BOUNDARY 64
 103
 104 #define FUNCTION_BOUNDARY 32
 105
 106 #define BIGGEST_ALIGNMENT 64
 107
 108 #undef  DATA_ALIGNMENT
 109 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 110   ((((ALIGN) < BITS_PER_WORD)                                           \
 111     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 112         || TREE_CODE (TYPE) == UNION_TYPE                               \
 113         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 114
 115 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 116   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 117    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 118
 119 #define EMPTY_FIELD_BOUNDARY 32
 120
 121 #define STRUCTURE_SIZE_BOUNDARY 8
 122
 123 #define STRICT_ALIGNMENT 1
 124
 125 #define PCC_BITFIELD_TYPE_MATTERS 1
 126
 127 \f
 128 /* Layout of Source Language Data Types.  */
 129
 130 #define INT_TYPE_SIZE           32
 131 #define SHORT_TYPE_SIZE         16
 132 #define LONG_TYPE_SIZE          32
 133 #define LONG_LONG_TYPE_SIZE     64
 134 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 135 #define FLOAT_TYPE_SIZE         32
 136 #define DOUBLE_TYPE_SIZE        64
 137 #define LONG_DOUBLE_TYPE_SIZE   64
 138 #define DEFAULT_SIGNED_CHAR     1
 139
 140 #undef  SIZE_TYPE
 141 #define SIZE_TYPE "unsigned int"
 142
 143 #undef  PTRDIFF_TYPE
 144 #define PTRDIFF_TYPE "int"
 145
 146 #undef  WCHAR_TYPE
 147 #define WCHAR_TYPE "long int"
 148
 149 #undef  WCHAR_TYPE_SIZE
 150 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 151
 152 \f
 153 /* Register Basics.  */
 154
 155 /* On the IQ2000, we have 32 integer registers.  */
 156 #define FIRST_PSEUDO_REGISTER 33
 157
 158 #define FIXED_REGISTERS                                                 \
 159 {                                                                       \
 160   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 161   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 162 }
 163
 164 #define CALL_USED_REGISTERS                                             \
 165 {                                                                       \
 166   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 167   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 168 }
 169
 170 \f
 171 /* Order of allocation of registers.  */
 172
 173 #define REG_ALLOC_ORDER                                                 \
 174 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 175   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 176 }
 177
 178 \f
 179 /* How Values Fit in Registers.  */
 180
 181 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 182   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 183
 184 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 185  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 186   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 187   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 188
 189 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 190   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 191     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 192    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 193        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 194
 195 #define AVOID_CCMODE_COPIES
 196
 197 \f
 198 /* Register Classes.  */
 199
 200 enum reg_class
 201 {
 202   NO_REGS,                      /* No registers in set.  */
 203   GR_REGS,                      /* Integer registers.  */
 204   ALL_REGS,                     /* All registers.  */
 205   LIM_REG_CLASSES               /* Max value + 1.  */
 206 };
 207
 208 #define GENERAL_REGS GR_REGS
 209
 210 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 211
 212 #define IRA_COVER_CLASSES       \
 213 {                               \
 214   GR_REGS, LIM_REG_CLASSES      \
 215 }
 216
 217 #define REG_CLASS_NAMES                                         \
 218 {                                                               \
 219   "NO_REGS",                                                    \
 220   "GR_REGS",                                                    \
 221   "ALL_REGS"                                                    \
 222 }
 223
 224 #define REG_CLASS_CONTENTS                                      \
 225 {                                                               \
 226   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 227   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 228   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 229 }
 230
 231 #define REGNO_REG_CLASS(REGNO) \
 232 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 233
 234 #define BASE_REG_CLASS  (GR_REGS)
 235
 236 #define INDEX_REG_CLASS NO_REGS
 237
 238 #define REG_CLASS_FROM_LETTER(C) \
 239   ((C) == 'd' ? GR_REGS :        \
 240    (C) == 'b' ? ALL_REGS :       \
 241    (C) == 'y' ? GR_REGS :        \
 242    NO_REGS)
 243
 244 #define REGNO_OK_FOR_INDEX_P(regno)     0
 245
 246 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 247   ((CLASS) != ALL_REGS                                          \
 248    ? (CLASS)                                                    \
 249    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 250        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 251       ? (GR_REGS)                                               \
 252       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 253           || GET_MODE (X) == VOIDmode)                          \
 254          ? (GR_REGS)                                            \
 255          : (CLASS))))
 256
 257 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 258   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 259
 260 /* For IQ2000:
 261
 262    `I'  is used for the range of constants an arithmetic insn can
 263         actually contain (16-bits signed integers).
 264
 265    `J'  is used for the range which is just zero (i.e., $r0).
 266
 267    `K'  is used for the range of constants a logical insn can actually
 268         contain (16-bit zero-extended integers).
 269
 270    `L'  is used for the range of constants that be loaded with lui
 271         (i.e., the bottom 16 bits are zero).
 272
 273    `M'  is used for the range of constants that take two words to load
 274         (i.e., not matched by `I', `K', and `L').
 275
 276    `N'  is used for constants 0xffffnnnn or 0xnnnnffff
 277
 278    `O'  is a 5-bit zero-extended integer.  */
 279
 280 #define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
 281   ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
 282    : (C) == 'J' ? ((VALUE) == 0)                                        \
 283    : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
 284    : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                          \
 285                    && (((VALUE) & ~2147483647) == 0                     \
 286                        || ((VALUE) & ~2147483647) == ~2147483647))      \
 287    : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                       \
 288                    && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
 289                    && (((VALUE) & 0x0000ffff) != 0                      \
 290                        || (((VALUE) & ~2147483647) != 0                 \
 291                            && ((VALUE) & ~2147483647) != ~2147483647))) \
 292    : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff)                       \
 293                    || (((VALUE) & 0xffff0000) == 0xffff0000))           \
 294    : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40)    \
 295    : 0)
 296
 297 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
 298   ((C) == 'G'                                                           \
 299    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
 300
 301 /* `R' is for memory references which take 1 word for the instruction.  */
 302
 303 #define EXTRA_CONSTRAINT(OP,CODE)                                       \
 304   (((CODE) == 'R')        ? simple_memory_operand (OP, GET_MODE (OP))   \
 305    : FALSE)
 306
 307 \f
 308 /* Basic Stack Layout.  */
 309
 310 #define STACK_GROWS_DOWNWARD
 311
 312 #define FRAME_GROWS_DOWNWARD 0
 313
 314 #define STARTING_FRAME_OFFSET                                           \
 315   (crtl->outgoing_args_size)
 316
 317 /* Use the default value zero.  */
 318 /* #define STACK_POINTER_OFFSET 0 */
 319
 320 #define FIRST_PARM_OFFSET(FNDECL) 0
 321
 322 /* The return address for the current frame is in r31 if this is a leaf
 323    function.  Otherwise, it is on the stack.  It is at a variable offset
 324    from sp/fp/ap, so we define a fake hard register rap which is a
 325    pointer to the return address on the stack.  This always gets eliminated
 326    during reload to be either the frame pointer or the stack pointer plus
 327    an offset.  */
 328
 329 #define RETURN_ADDR_RTX(count, frame)                                   \
 330   (((count) == 0)                                                       \
 331    ? (leaf_function_p ()                                                \
 332       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 333       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 334                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 335     : (rtx) 0)
 336
 337 /* Before the prologue, RA lives in r31.  */
 338 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 339
 340 \f
 341 /* Register That Address the Stack Frame.  */
 342
 343 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 344 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 345 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 346 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 347 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 348 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 349
 350 \f
 351 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 352
 353 #define ELIMINABLE_REGS                                                 \
 354 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 355  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 356  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 357  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 358  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 359  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 360  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 361
 362 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 363         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 364 \f
 365 /* Passing Function Arguments on the Stack.  */
 366
 367 /* #define PUSH_ROUNDING(BYTES) 0 */
 368
 369 #define ACCUMULATE_OUTGOING_ARGS 1
 370
 371 #define REG_PARM_STACK_SPACE(FNDECL) 0
 372
 373 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 374
 375 \f
 376 /* Function Arguments in Registers.  */
 377
 378 #define MAX_ARGS_IN_REGISTERS 8
 379
 380 typedef struct iq2000_args
 381 {
 382   int gp_reg_found;             /* Whether a gp register was found yet.  */
 383   unsigned int arg_number;      /* Argument number.  */
 384   unsigned int arg_words;       /* # total words the arguments take.  */
 385   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 386   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 387   int fp_code;                  /* Mode of FP arguments.  */
 388   unsigned int num_adjusts;     /* Number of adjustments made.  */
 389                                 /* Adjustments made to args pass in regs.  */
 390   struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
 391 } CUMULATIVE_ARGS;
 392
 393 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 394    for a call to a function whose data type is FNTYPE.
 395    For a library call, FNTYPE is 0.  */
 396 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 397   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 398
 399 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 400   (! BYTES_BIG_ENDIAN                                                   \
 401    ? upward                                                             \
 402    : (((MODE) == BLKmode                                                \
 403        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 404           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 405        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 406           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 407       ? downward : upward))
 408
 409 #define FUNCTION_ARG_REGNO_P(N)                                         \
 410   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 411
 412 \f
 413 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 414
 415 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N)
 416
 417 \f
 418 /* How Large Values are Returned.  */
 419
 420 #define DEFAULT_PCC_STRUCT_RETURN 0
 421 \f
 422 /* Function Entry and Exit.  */
 423
 424 #define EXIT_IGNORE_STACK 1
 425
 426 \f
 427 /* Generating Code for Profiling.  */
 428
 429 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 430 {                                                                       \
 431   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 432   fprintf (FILE, "\t.set\tnoat\n");                                     \
 433   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 434            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 435   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 436   fprintf (FILE,                                                        \
 437            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 438            "subu",                                                      \
 439            reg_names[STACK_POINTER_REGNUM],                             \
 440            reg_names[STACK_POINTER_REGNUM],                             \
 441            Pmode == DImode ? 16 : 8);                                   \
 442   fprintf (FILE, "\t.set\treorder\n");                                  \
 443   fprintf (FILE, "\t.set\tat\n");                                       \
 444 }
 445
 446 \f
 447 /* Trampolines for Nested Functions.  */
 448
 449 #define TRAMPOLINE_CODE_SIZE  (8*4)
 450 #define TRAMPOLINE_SIZE       (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode))
 451 #define TRAMPOLINE_ALIGNMENT  GET_MODE_ALIGNMENT (Pmode)
 452
 453 \f
 454 /* Addressing Modes.  */
 455
 456 #define CONSTANT_ADDRESS_P(X)                                           \
 457   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 458     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 459     || (GET_CODE (X) == CONST)))
 460
 461 #define MAX_REGS_PER_ADDRESS 1
 462
 463 #define REG_OK_FOR_INDEX_P(X) 0
 464
 465 #define LEGITIMATE_CONSTANT_P(X) (1)
 466
 467 \f
 468 /* Describing Relative Costs of Operations.  */
 469
 470 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 471
 472 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 473   (TO_P ? 2 : 16)
 474
 475 #define BRANCH_COST(speed_p, predictable_p) 2
 476
 477 #define SLOW_BYTE_ACCESS 1
 478
 479 #define NO_FUNCTION_CSE 1
 480
 481 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 482   if (REG_NOTE_KIND (LINK) != 0)                                        \
 483     (COST) = 0; /* Anti or output dependence.  */
 484
 485 \f
 486 /* Dividing the output into sections.  */
 487
 488 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 489
 490 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 491
 492 \f
 493 /* The Overall Framework of an Assembler File.  */
 494
 495 #define ASM_COMMENT_START " #"
 496
 497 #define ASM_APP_ON "#APP\n"
 498
 499 #define ASM_APP_OFF "#NO_APP\n"
 500
 501 \f
 502 /* Output and Generation of Labels.  */
 503
 504 #undef ASM_GENERATE_INTERNAL_LABEL
 505 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 506   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 507
 508 #define GLOBAL_ASM_OP "\t.globl\t"
 509
 510 \f
 511 /* Output of Assembler Instructions.  */
 512
 513 #define REGISTER_NAMES                                                  \
 514 {                                                                       \
 515  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 516  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 517  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 518  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 519 }
 520
 521 #define ADDITIONAL_REGISTER_NAMES                                       \
 522 {                                                                       \
 523   { "%0",        0 + GP_REG_FIRST },                                    \
 524   { "%1",        1 + GP_REG_FIRST },                                    \
 525   { "%2",        2 + GP_REG_FIRST },                                    \
 526   { "%3",        3 + GP_REG_FIRST },                                    \
 527   { "%4",        4 + GP_REG_FIRST },                                    \
 528   { "%5",        5 + GP_REG_FIRST },                                    \
 529   { "%6",        6 + GP_REG_FIRST },                                    \
 530   { "%7",        7 + GP_REG_FIRST },                                    \
 531   { "%8",        8 + GP_REG_FIRST },                                    \
 532   { "%9",        9 + GP_REG_FIRST },                                    \
 533   { "%10",      10 + GP_REG_FIRST },                                    \
 534   { "%11",      11 + GP_REG_FIRST },                                    \
 535   { "%12",      12 + GP_REG_FIRST },                                    \
 536   { "%13",      13 + GP_REG_FIRST },                                    \
 537   { "%14",      14 + GP_REG_FIRST },                                    \
 538   { "%15",      15 + GP_REG_FIRST },                                    \
 539   { "%16",      16 + GP_REG_FIRST },                                    \
 540   { "%17",      17 + GP_REG_FIRST },                                    \
 541   { "%18",      18 + GP_REG_FIRST },                                    \
 542   { "%19",      19 + GP_REG_FIRST },                                    \
 543   { "%20",      20 + GP_REG_FIRST },                                    \
 544   { "%21",      21 + GP_REG_FIRST },                                    \
 545   { "%22",      22 + GP_REG_FIRST },                                    \
 546   { "%23",      23 + GP_REG_FIRST },                                    \
 547   { "%24",      24 + GP_REG_FIRST },                                    \
 548   { "%25",      25 + GP_REG_FIRST },                                    \
 549   { "%26",      26 + GP_REG_FIRST },                                    \
 550   { "%27",      27 + GP_REG_FIRST },                                    \
 551   { "%28",      28 + GP_REG_FIRST },                                    \
 552   { "%29",      29 + GP_REG_FIRST },                                    \
 553   { "%30",      27 + GP_REG_FIRST },                                    \
 554   { "%31",      31 + GP_REG_FIRST },                                    \
 555   { "%rap",     32 + GP_REG_FIRST },                                    \
 556 }
 557
 558 /* Check if the current insn needs a nop in front of it
 559    because of load delays, and also update the delay slot statistics.  */
 560
 561 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 562   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 563
 564 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 565 do                                                                      \
 566   {                                                                     \
 567     fputs ("\n", STREAM);                                               \
 568   }                                                                     \
 569 while (0)
 570
 571 #define LOCAL_LABEL_PREFIX      "$"
 572
 573 #define USER_LABEL_PREFIX       ""
 574
 575 \f
 576 /* Output of dispatch tables.  */
 577
 578 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 579   do                                                                    \
 580     {                                                                   \
 581       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 582                Pmode == DImode ? ".dword" : ".word",                    \
 583                LOCAL_LABEL_PREFIX, VALUE);                              \
 584     }                                                                   \
 585   while (0)
 586
 587 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 588   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 589            Pmode == DImode ? ".dword" : ".word",                        \
 590            LOCAL_LABEL_PREFIX,                                          \
 591            VALUE)
 592
 593 \f
 594 /* Assembler Commands for Alignment.  */
 595
 596 #undef ASM_OUTPUT_SKIP
 597 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 598   fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",      \
 599            (unsigned HOST_WIDE_INT)(SIZE))
 600
 601 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 602   if ((LOG) != 0)                                                       \
 603     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 604
 605 \f
 606 /* Macros Affecting all Debug Formats.  */
 607
 608 #define DEBUGGER_AUTO_OFFSET(X)  \
 609   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 610
 611 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 612   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 613
 614 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 615
 616 #define DWARF2_DEBUGGING_INFO 1
 617
 618 \f
 619 /* Miscellaneous Parameters.  */
 620
 621 #define CASE_VECTOR_MODE SImode
 622
 623 #define WORD_REGISTER_OPERATIONS
 624
 625 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 626
 627 #define MOVE_MAX 4
 628
 629 #define MAX_MOVE_MAX 8
 630
 631 #define SHIFT_COUNT_TRUNCATED 1
 632
 633 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 634
 635 #define STORE_FLAG_VALUE 1
 636
 637 #define Pmode SImode
 638
 639 #define FUNCTION_MODE SImode
 640
 641 /* Standard GCC variables that we reference.  */
 642
 643 extern char     call_used_regs[];
 644
 645 /* IQ2000 external variables defined in iq2000.c.  */
 646
 647 /* Comparison type.  */
 648 enum cmp_type
 649 {
 650   CMP_SI,                               /* Compare four byte integers.  */
 651   CMP_DI,                               /* Compare eight byte integers.  */
 652   CMP_SF,                               /* Compare single precision floats.  */
 653   CMP_DF,                               /* Compare double precision floats.  */
 654   CMP_MAX                               /* Max comparison type.  */
 655 };
 656
 657 /* Types of delay slot.  */
 658 enum delay_type
 659 {
 660   DELAY_NONE,                           /* No delay slot.  */
 661   DELAY_LOAD,                           /* Load from memory delay.  */
 662   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 663 };
 664
 665 /* Which processor to schedule for.  */
 666
 667 enum processor_type
 668 {
 669   PROCESSOR_DEFAULT,
 670   PROCESSOR_IQ2000,
 671   PROCESSOR_IQ10
 672 };
 673
 674 /* Recast the cpu class to be the cpu attribute.  */
 675 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 676
 677 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 678 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 679
 680 \f
 681 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 682
 683 /* Macros to decide whether certain features are available or not,
 684    depending on the instruction set architecture level.  */
 685
 686 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 687
 688 /* ISA has branch likely instructions.  */
 689 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 690
 691 \f
 692 #undef ASM_SPEC
 693
 694 \f
 695 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 696 #define DWARF_FRAME_REGNUM(REG)        (REG)
 697
 698 /* The DWARF 2 CFA column which tracks the return address.  */
 699 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 700
 701 /* Describe how we implement __builtin_eh_return.  */
 702 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 703
 704 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 705    location used to store the amount to adjust the stack.  This is
 706    usually a register that is available from end of the function's body
 707    to the end of the epilogue. Thus, this cannot be a register used as a
 708    temporary by the epilogue.
 709
 710    This must be an integer register.  */
 711 #define EH_RETURN_STACKADJ_REGNO        3
 712 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 713
 714 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 715    location used to store the address the processor should jump to
 716    catch exception.  This is usually a registers that is available from
 717    end of the function's body to the end of the epilogue. Thus, this
 718    cannot be a register used as a temporary by the epilogue.
 719
 720    This must be an address register.  */
 721 #define EH_RETURN_HANDLER_REGNO         26
 722 #define EH_RETURN_HANDLER_RTX           \
 723         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 724
 725 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 726 #define DWARF_CIE_DATA_ALIGNMENT 4
 727
 728 /* For IQ2000, width of a floating point register.  */
 729 #define UNITS_PER_FPREG 4
 730
 731 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 732
 733 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 734
 735 /* Internal macros to classify a register number as to whether it's a
 736    general purpose register, a floating point register, a
 737    multiply/divide register, or a status register.  */
 738
 739 #define GP_REG_FIRST 0
 740 #define GP_REG_LAST  31
 741 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 742
 743 #define RAP_REG_NUM   32
 744 #define AT_REGNUM       (GP_REG_FIRST + 1)
 745
 746 #define GP_REG_P(REGNO) \
 747   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 748
 749 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 750    is larger than 32K bytes.  These registers must come from the
 751    scratch register set, and not used for passing and returning
 752    arguments and any other information used in the calling sequence.  */
 753
 754 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 755 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 756
 757 /* This macro is used later on in the file.  */
 758 #define GR_REG_CLASS_P(CLASS)                                           \
 759   ((CLASS) == GR_REGS)
 760
 761 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 762 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 763
 764 /* Certain machines have the property that some registers cannot be
 765    copied to some other registers without using memory.  Define this
 766    macro on those machines to be a C expression that is nonzero if
 767    objects of mode MODE in registers of CLASS1 can only be copied to
 768    registers of class CLASS2 by storing a register of CLASS1 into
 769    memory and loading that memory location into a register of CLASS2.
 770
 771    Do not define this macro if its value would always be zero.  */
 772
 773 /* Return the maximum number of consecutive registers
 774    needed to represent mode MODE in a register of class CLASS.  */
 775
 776 #define CLASS_UNITS(mode, size)                                         \
 777   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
 778
 779 /* If defined, gives a class of registers that cannot be used as the
 780    operand of a SUBREG that changes the mode of the object illegally.  */
 781
 782 #define CLASS_CANNOT_CHANGE_MODE 0
 783
 784 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
 785
 786 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
 787   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 788
 789 /* Make sure 4 words are always allocated on the stack.  */
 790
 791 #ifndef STACK_ARGS_ADJUST
 792 #define STACK_ARGS_ADJUST(SIZE)                                         \
 793   {                                                                     \
 794     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
 795       SIZE.constant = 4 * UNITS_PER_WORD;                               \
 796   }
 797 #endif
 798
 799 \f
 800 /* Symbolic macros for the registers used to return integer and floating
 801    point values.  */
 802
 803 #define GP_RETURN (GP_REG_FIRST + 2)
 804
 805 /* Symbolic macros for the first/last argument registers.  */
 806
 807 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
 808 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
 809
 810 #define MAX_ARGS_IN_REGISTERS   8
 811
 812 \f
 813 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
 814
 815 #define MUST_SAVE_REGISTER(regno) \
 816   ((df_regs_ever_live_p (regno) && !call_used_regs[regno])              \
 817   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
 818    || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
 819
 820 /* ALIGN FRAMES on double word boundaries */
 821 #ifndef IQ2000_STACK_ALIGN
 822 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
 823 #endif
 824
 825 \f
 826 /* These assume that REGNO is a hard or pseudo reg number.
 827    They give nonzero only if REGNO is a hard reg of the suitable class
 828    or a pseudo reg currently allocated to a suitable hard reg.
 829    These definitions are NOT overridden anywhere.  */
 830
 831 #define BASE_REG_P(regno, mode)                                 \
 832   (GP_REG_P (regno))
 833
 834 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
 835   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
 836              (mode))
 837
 838 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
 839   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
 840
 841 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
 842   GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode))
 843
 844 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 845    and check its validity for a certain class.
 846    We have two alternate definitions for each of them.
 847    The usual definition accepts all pseudo regs; the other rejects them all.
 848    The symbol REG_OK_STRICT causes the latter definition to be used.
 849
 850    Most source files want to accept pseudo regs in the hope that
 851    they will get allocated to the class that the insn wants them to be in.
 852    Some source files that are used after register allocation
 853    need to be strict.  */
 854
 855 #ifndef REG_OK_STRICT
 856 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 857   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
 858 #else
 859 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 860   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
 861 #endif
 862
 863 #if 1
 864 #define GO_PRINTF(x)    fprintf (stderr, (x))
 865 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
 866 #define GO_DEBUG_RTX(x) debug_rtx (x)
 867
 868 #else
 869 #define GO_PRINTF(x)
 870 #define GO_PRINTF2(x,y)
 871 #define GO_DEBUG_RTX(x)
 872 #endif
 873
 874 /* If defined, modifies the length assigned to instruction INSN as a
 875    function of the context in which it is used.  LENGTH is an lvalue
 876    that contains the initially computed length of the insn and should
 877    be updated with the correct length of the insn.  */
 878 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
 879   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
 880
 881 \f
 882
 883
 884 /* How to tell the debugger about changes of source files.  */
 885
 886 #ifndef SET_FILE_NUMBER
 887 #define SET_FILE_NUMBER() ++ num_source_filenames
 888 #endif
 889
 890 /* This is how to output a note the debugger telling it the line number
 891    to which the following sequence of instructions corresponds.  */
 892
 893 #ifndef LABEL_AFTER_LOC
 894 #define LABEL_AFTER_LOC(STREAM)
 895 #endif
 896
 897 \f
 898 /* Default to -G 8 */
 899 #ifndef IQ2000_DEFAULT_GVALUE
 900 #define IQ2000_DEFAULT_GVALUE 8
 901 #endif
 902
 903 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
 904
 905 \f
 906 /* The target cpu for optimization and scheduling.  */
 907 extern enum processor_type iq2000_tune;
 908
 909 /* Which instruction set architecture to use.  */
 910 extern int iq2000_isa;
 911
 912 enum iq2000_builtins
 913 {
 914   IQ2000_BUILTIN_ADO16,
 915   IQ2000_BUILTIN_CFC0,
 916   IQ2000_BUILTIN_CFC1,
 917   IQ2000_BUILTIN_CFC2,
 918   IQ2000_BUILTIN_CFC3,
 919   IQ2000_BUILTIN_CHKHDR,
 920   IQ2000_BUILTIN_CTC0,
 921   IQ2000_BUILTIN_CTC1,
 922   IQ2000_BUILTIN_CTC2,
 923   IQ2000_BUILTIN_CTC3,
 924   IQ2000_BUILTIN_LU,
 925   IQ2000_BUILTIN_LUC32L,
 926   IQ2000_BUILTIN_LUC64,
 927   IQ2000_BUILTIN_LUC64L,
 928   IQ2000_BUILTIN_LUK,
 929   IQ2000_BUILTIN_LULCK,
 930   IQ2000_BUILTIN_LUM32,
 931   IQ2000_BUILTIN_LUM32L,
 932   IQ2000_BUILTIN_LUM64,
 933   IQ2000_BUILTIN_LUM64L,
 934   IQ2000_BUILTIN_LUR,
 935   IQ2000_BUILTIN_LURL,
 936   IQ2000_BUILTIN_MFC0,
 937   IQ2000_BUILTIN_MFC1,
 938   IQ2000_BUILTIN_MFC2,
 939   IQ2000_BUILTIN_MFC3,
 940   IQ2000_BUILTIN_MRGB,
 941   IQ2000_BUILTIN_MTC0,
 942   IQ2000_BUILTIN_MTC1,
 943   IQ2000_BUILTIN_MTC2,
 944   IQ2000_BUILTIN_MTC3,
 945   IQ2000_BUILTIN_PKRL,
 946   IQ2000_BUILTIN_RAM,
 947   IQ2000_BUILTIN_RB,
 948   IQ2000_BUILTIN_RX,
 949   IQ2000_BUILTIN_SRRD,
 950   IQ2000_BUILTIN_SRRDL,
 951   IQ2000_BUILTIN_SRULC,
 952   IQ2000_BUILTIN_SRULCK,
 953   IQ2000_BUILTIN_SRWR,
 954   IQ2000_BUILTIN_SRWRU,
 955   IQ2000_BUILTIN_TRAPQF,
 956   IQ2000_BUILTIN_TRAPQFL,
 957   IQ2000_BUILTIN_TRAPQN,
 958   IQ2000_BUILTIN_TRAPQNE,
 959   IQ2000_BUILTIN_TRAPRE,
 960   IQ2000_BUILTIN_TRAPREL,
 961   IQ2000_BUILTIN_WB,
 962   IQ2000_BUILTIN_WBR,
 963   IQ2000_BUILTIN_WBU,
 964   IQ2000_BUILTIN_WX,
 965   IQ2000_BUILTIN_SYSCALL
 966 };