| blob | 36e9c12408e652e17e202c18fdce4883bad6b6e5 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
101 /* Include output.h for dump_file. */
109 /* Number of attempts to combine instructions in this function. */
113 /* Number of attempts that got as far as substitution in this function. */
117 /* Number of instructions combined with added SETs in this function. */
121 /* Number of instructions combined in this function. */
125 /* Totals over entire compilation. */
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 \f
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
151 rtx last_set;
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
198 rtx last_set_value;
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
235 If an entry is zero, it means that we don't know anything special. */
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
294 that location. */
298 /* Basic block in which we are performing combines. */
302 \f
303 /* Length of the currently allocated uid_insn_cost array. */
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
324 /* Reset to label_tick for each extended basic block in scanning order. */
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
337 in a loop. */
341 \f
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
347 struct undo
348 {
353 };
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
361 struct undobuf
362 {
365 rtx other_insn;
366 };
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
451 \f
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
473 \f
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
478 register. */
480 static rtx
482 {
483 rtx ret;
491 }
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
501 {
510 {
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
544 }
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
551 {
553 {
558 else
564 /* Duplicate usage. */
566 }
568 {
572 {
578 else
585 }
586 }
587 }
590 }
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
595 it is used.
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
609 {
610 basic_block bb;
611 rtx next;
613 rtx link;
615 #ifdef HAVE_cc0
617 {
627 }
628 #endif
638 {
644 {
649 }
650 }
653 }
654 \f
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
659 the undo table. */
661 static void
663 {
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
677 {
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
693 }
697 else
706 }
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
712 not safe. */
714 static void
716 {
725 else
734 }
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
741 well. */
743 static void
745 {
754 else
763 }
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 \f
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
774 sequence. */
776 static bool
778 rtx newotherpat)
779 {
784 /* Lookup the original insn_rtx_costs. */
789 {
793 }
794 else
795 {
798 }
800 /* Calculate the replacement insn_rtx_costs. */
803 {
807 }
808 else
809 {
812 }
815 {
821 {
824 }
825 else
827 }
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
833 {
835 {
837 {
843 }
844 else
845 {
851 }
854 {
857 }
858 else
860 }
863 }
865 /* Update the uid_insn_cost array with the replacement costs. */
872 }
875 /* Delete any insns that copy a register to itself. */
877 static void
879 {
881 basic_block bb;
884 {
886 {
889 {
894 }
895 }
896 }
897 }
899 \f
900 /* Fill in log links field for all insns. */
902 static void
904 {
905 basic_block bb;
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
921 {
923 {
927 /* Log links are created only once. */
931 {
934 rtx use_insn;
939 /* Do not consider if it is pre/post modification in MEM. */
943 /* Do not make the log link for frame pointer. */
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
949 #endif
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
952 #endif
953 )
958 {
959 /* flow.c claimed:
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
968 {
969 /* Don't add duplicate links between instructions. */
970 rtx links;
979 }
980 }
982 }
985 {
989 /* Do not consider the usage of the stack pointer
990 by function call. */
995 }
996 }
997 }
1000 }
1002 /* Clear LOG_LINKS fields of insns. */
1004 static void
1006 {
1007 rtx insn;
1012 }
1013 \f
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1019 static int
1021 {
1023 #ifdef HAVE_cc0
1024 rtx prev;
1025 #endif
1027 rtx first;
1028 basic_block last_bb;
1048 /* Allocate array for insn info. */
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1075 {
1080 label_tick++;
1088 {
1093 insn);
1096 #ifdef AUTO_INC_DEC
1100 insn);
1101 #endif
1103 /* Record the current insn_rtx_cost of this instruction. */
1106 optimize_this_for_speed_p);
1110 }
1111 }
1115 /* Now scan all the insns in forward order. */
1122 {
1127 label_tick++;
1137 {
1140 {
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1147 into SUBREGs. */
1150 /* Try this insn with each insn it links back to. */
1157 /* Try each sequence of three linked insns ending with this one. */
1160 {
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1169 nextlinks;
1175 }
1177 #ifdef HAVE_cc0
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1189 {
1200 }
1202 /* Do the same for an insn that explicitly references CC0. */
1209 {
1220 }
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1235 #endif
1237 /* Try combining an insn with two different insns whose results it
1238 uses. */
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1249 {
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1261 {
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1276 }
1277 }
1282 retry:
1283 ;
1284 }
1285 }
1286 }
1294 /* Clean up. */
1299 {
1302 {
1305 }
1307 }
1317 /* Make recognizer allow volatile MEMs again. */
1321 }
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1325 static void
1327 {
1333 }
1334 \f
1335 /* Set up any promoted values for incoming argument registers. */
1337 static void
1339 {
1340 tree arg;
1345 {
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1375 /* The mode of the register in which the argument is being passed. */
1378 /* Eliminate sign extensions in the callee when:
1379 (a) A mode promotion has occurred; */
1382 /* (b) The mode of the register is the same as the mode of
1383 the argument as it is passed; */
1386 /* (c) There's no language level extension; */
1388 ;
1389 /* (c.1) All callers are from the current compilation unit. If that's
1390 the case we don't have to rely on an ABI, we only have to know
1391 what we're generating right now, and we know that we will do the
1392 mode1 to mode2 promotion with the given sign. */
1395 /* (c.2) The combination of the two promotions is useful. This is
1396 true when the signs match, or if the first promotion is unsigned.
1397 In the later case, (sign_extend (zero_extend x)) is the same as
1398 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1404 /* Record that the value was promoted from mode1 to mode3,
1405 so that any sign extension at the head of the current
1406 function may be eliminated. */
1410 }
1411 }
1413 /* Called via note_stores. If X is a pseudo that is narrower than
1414 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1416 If we are setting only a portion of X and we can't figure out what
1417 portion, assume all bits will be used since we don't know what will
1418 be happening.
1420 Similarly, set how many bits of X are known to be copies of the sign bit
1421 at all locations in the function. This is the smallest number implied
1422 by any set of X. */
1424 static void
1426 {
1432 /* If this register is undefined at the start of the file, we can't
1433 say what its contents were. */
1434 && ! REGNO_REG_SET_P
1437 {
1441 {
1445 }
1447 /* If this register is being initialized using itself, and the
1448 register is uninitialized in this basic block, and there are
1449 no LOG_LINKS which set the register, then part of the
1450 register is uninitialized. In that case we can't assume
1451 anything about the number of nonzero bits.
1453 ??? We could do better if we checked this in
1454 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1455 could avoid making assumptions about the insn which initially
1456 sets the register, while still using the information in other
1457 insns. We would have to be careful to check every insn
1458 involved in the combination. */
1464 {
1465 rtx link;
1468 {
1471 }
1473 {
1477 }
1478 }
1480 /* If this is a complex assignment, see if we can convert it into a
1481 simple assignment. */
1484 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1485 set what we know about X. */
1492 {
1495 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1496 /* If X is narrower than a word and SRC is a non-negative
1497 constant that would appear negative in the mode of X,
1498 sign-extend it for use in reg_stat[].nonzero_bits because some
1499 machines (maybe most) will actually do the sign-extension
1500 and this is the conservative approach.
1502 ??? For 2.5, try to tighten up the MD files in this regard
1503 instead of this kludge. */
1514 #endif
1516 /* Don't call nonzero_bits if it cannot change anything. */
1523 }
1524 else
1525 {
1528 }
1529 }
1530 }
1531 \f
1532 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1533 insns that were previously combined into I3 or that will be combined
1534 into the merger of INSN and I3.
1536 Return 0 if the combination is not allowed for any reason.
1538 If the combination is allowed, *PDEST will be set to the single
1539 destination of INSN and *PSRC to the single source, and this function
1540 will return 1. */
1542 static int
1545 {
1549 rtx p;
1550 #ifdef AUTO_INC_DEC
1551 rtx link;
1552 #endif
1557 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1558 or a PARALLEL consisting of such a SET and CLOBBERs.
1560 If INSN has CLOBBER parallel parts, ignore them for our processing.
1561 By definition, these happen during the execution of the insn. When it
1562 is merged with another insn, all bets are off. If they are, in fact,
1563 needed and aren't also supplied in I3, they may be added by
1564 recog_for_combine. Otherwise, it won't match.
1566 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1567 note.
1569 Get the source and destination of INSN. If more than one, can't
1570 combine. */
1576 {
1578 {
1582 {
1583 /* This is important to combine floating point insns
1584 for the SH4 port. */
1586 /* Combining an isolated USE doesn't make sense.
1587 We depend here on combinable_i3pat to reject them. */
1588 /* The code below this loop only verifies that the inputs of
1589 the SET in INSN do not change. We call reg_set_between_p
1590 to verify that the REG in the USE does not change between
1591 I3 and INSN.
1592 If the USE in INSN was for a pseudo register, the matching
1593 insn pattern will likely match any register; combining this
1594 with any other USE would only be safe if we knew that the
1595 used registers have identical values, or if there was
1596 something to tell them apart, e.g. different modes. For
1597 now, we forgo such complicated tests and simply disallow
1598 combining of USES of pseudo registers with any other USE. */
1601 {
1606 do
1607 {
1617 }
1619 }
1622 /* We can ignore CLOBBERs. */
1627 /* Ignore SETs whose result isn't used but not those that
1628 have side-effects. */
1634 /* If we have already found a SET, this is a second one and
1635 so we cannot combine with this insn. */
1643 /* Anything else means we can't combine. */
1645 }
1646 }
1649 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1650 so don't do anything with it. */
1653 }
1654 else
1663 /* Don't eliminate a store in the stack pointer. */
1665 /* Don't combine with an insn that sets a register to itself if it has
1666 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1668 /* Can't merge an ASM_OPERANDS. */
1670 /* Can't merge a function call. */
1672 /* Don't eliminate a function call argument. */
1678 /* Don't substitute into an incremented register. */
1681 /* Don't substitute into a non-local goto, this confuses CFG. */
1683 /* Make sure that DEST is not used after SUCC but before I3. */
1686 /* Make sure that the value that is to be substituted for the register
1687 does not use any registers whose values alter in between. However,
1688 If the insns are adjacent, a use can't cross a set even though we
1689 think it might (this can happen for a sequence of insns each setting
1690 the same destination; last_set of that register might point to
1691 a NOTE). If INSN has a REG_EQUIV note, the register is always
1692 equivalent to the memory so the substitution is valid even if there
1693 are intervening stores. Also, don't move a volatile asm or
1694 UNSPEC_VOLATILE across any other insns. */
1695 || (! all_adjacent
1701 /* Don't combine across a CALL_INSN, because that would possibly
1702 change whether the life span of some REGs crosses calls or not,
1703 and it is a pain to update that information.
1704 Exception: if source is a constant, moving it later can't hurt.
1705 Accept that as a special case. */
1709 /* DEST must either be a REG or CC0. */
1711 {
1712 /* If register alignment is being enforced for multi-word items in all
1713 cases except for parameters, it is possible to have a register copy
1714 insn referencing a hard register that is not allowed to contain the
1715 mode being copied and which would not be valid as an operand of most
1716 insns. Eliminate this problem by not combining with such an insn.
1718 Also, on some machines we don't want to extend the life of a hard
1719 register. */
1724 /* Don't extend the life of a hard register unless it is
1725 user variable (if we have few registers) or it can't
1726 fit into the desired register (meaning something special
1727 is going on).
1728 Also avoid substituting a return register into I3, because
1729 reload can't handle a conflict with constraints of other
1730 inputs. */
1734 }
1742 {
1743 /* Don't substitute for a register intended as a clobberable
1744 operand. */
1749 /* If the clobber represents an earlyclobber operand, we must not
1750 substitute an expression containing the clobbered register.
1751 As we do not analyze the constraint strings here, we have to
1752 make the conservative assumption. However, if the register is
1753 a fixed hard reg, the clobber cannot represent any operand;
1754 we leave it up to the machine description to either accept or
1755 reject use-and-clobber patterns. */
1761 }
1763 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1764 or not), reject, unless nothing volatile comes between it and I3 */
1767 {
1768 /* Make sure succ doesn't contain a volatile reference. */
1775 }
1777 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1778 to be an explicit register variable, and was chosen for a reason. */
1784 /* If there are any volatile insns between INSN and I3, reject, because
1785 they might affect machine state. */
1791 /* If INSN contains an autoincrement or autodecrement, make sure that
1792 register is not used between there and I3, and not already used in
1793 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1794 Also insist that I3 not be a jump; if it were one
1795 and the incremented register were spilled, we would lose. */
1797 #ifdef AUTO_INC_DEC
1808 #endif
1810 #ifdef HAVE_cc0
1811 /* Don't combine an insn that follows a CC0-setting insn.
1812 An insn that uses CC0 must not be separated from the one that sets it.
1813 We do, however, allow I2 to follow a CC0-setting insn if that insn
1814 is passed as I1; in that case it will be deleted also.
1815 We also allow combining in this case if all the insns are adjacent
1816 because that would leave the two CC0 insns adjacent as well.
1817 It would be more logical to test whether CC0 occurs inside I1 or I2,
1818 but that would be much slower, and this ought to be equivalent. */
1824 #endif
1826 /* If we get here, we have passed all the tests and the combination is
1827 to be allowed. */
1833 }
1834 \f
1835 /* LOC is the location within I3 that contains its pattern or the component
1836 of a PARALLEL of the pattern. We validate that it is valid for combining.
1838 One problem is if I3 modifies its output, as opposed to replacing it
1839 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1840 so would produce an insn that is not equivalent to the original insns.
1842 Consider:
1844 (set (reg:DI 101) (reg:DI 100))
1845 (set (subreg:SI (reg:DI 101) 0) <foo>)
1847 This is NOT equivalent to:
1849 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1850 (set (reg:DI 101) (reg:DI 100))])
1852 Not only does this modify 100 (in which case it might still be valid
1853 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1855 We can also run into a problem if I2 sets a register that I1
1856 uses and I1 gets directly substituted into I3 (not via I2). In that
1857 case, we would be getting the wrong value of I2DEST into I3, so we
1858 must reject the combination. This case occurs when I2 and I1 both
1859 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1860 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1861 of a SET must prevent combination from occurring.
1863 Before doing the above check, we first try to expand a field assignment
1864 into a set of logical operations.
1866 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1867 we place a register that is both set and used within I3. If more than one
1868 such register is detected, we fail.
1870 Return 1 if the combination is valid, zero otherwise. */
1872 static int
1875 {
1879 {
1884 rtx subdest;
1891 /* Check for the case where I3 modifies its output, as discussed
1892 above. We don't want to prevent pseudos from being combined
1893 into the address of a MEM, so only prevent the combination if
1894 i1 or i2 set the same MEM. */
1902 /* This is the same test done in can_combine_p except we can't test
1903 all_adjacent; we don't have to, since this instruction will stay
1904 in place, thus we are not considering increasing the lifetime of
1905 INNER_DEST.
1907 Also, if this insn sets a function argument, combining it with
1908 something that might need a spill could clobber a previous
1909 function argument; the all_adjacent test in can_combine_p also
1910 checks this; here, we do a more specific test for this case. */
1919 /* If DEST is used in I3, it is being killed in this insn, so
1920 record that for later. We have to consider paradoxical
1921 subregs here, since they kill the whole register, but we
1922 ignore partial subregs, STRICT_LOW_PART, etc.
1923 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1924 STACK_POINTER_REGNUM, since these are always considered to be
1925 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1935 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1937 #endif
1938 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1941 #endif
1943 {
1948 }
1949 }
1952 {
1959 }
1962 }
1963 \f
1964 /* Return 1 if X is an arithmetic expression that contains a multiplication
1965 and division. We don't count multiplications by powers of two here. */
1967 static int
1969 {
1971 {
1987 }
1988 }
1989 \f
1990 /* Determine whether INSN can be used in a combination. Return nonzero if
1991 not. This is used in try_combine to detect early some cases where we
1992 can't perform combinations. */
1994 static int
1996 {
1997 rtx set;
2000 /* If this isn't really an insn, we can't do anything.
2001 This can occur when flow deletes an insn that it has merged into an
2002 auto-increment address. */
2006 /* Never combine loads and stores involving hard regs that are likely
2007 to be spilled. The register allocator can usually handle such
2008 reg-reg moves by tying. If we allow the combiner to make
2009 substitutions of likely-spilled regs, reload might die.
2010 As an exception, we allow combinations involving fixed regs; these are
2011 not available to the register allocator so there's no risk involved. */
2032 }
2034 struct likely_spilled_retval_info
2035 {
2038 };
2040 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2041 hard registers that are known to be written to / clobbered in full. */
2042 static void
2044 {
2061 else
2064 }
2066 /* Return nonzero iff part of the return value is live during INSN, and
2067 it is likely spilled. This can happen when more than one insn is needed
2068 to copy the return value, e.g. when we consider to combine into the
2069 second copy insn for a complex value. */
2071 static int
2073 {
2077 /* We assume here that no machine mode needs more than
2078 32 hard registers when the value overlaps with a register
2079 for which FUNCTION_VALUE_REGNO_P is true. */
2094 /* Disregard parts of the return value that are set later. */
2103 /* Check if any of the (probably) live return value registers is
2104 likely spilled. */
2105 nregs --;
2106 do
2107 {
2113 }
2115 /* Adjust INSN after we made a change to its destination.
2117 Changing the destination can invalidate notes that say something about
2118 the results of the insn and a LOG_LINK pointing to the insn. */
2120 static void
2122 {
2123 /* For notes, be conservative and simply remove them. */
2126 /* The new insn will have a destination that was previously the destination
2127 of an insn just above it. Call distribute_links to make a LOG_LINK from
2128 the next use of that destination. */
2132 }
2134 /* Return TRUE if combine can reuse reg X in mode MODE.
2135 ADDED_SETS is nonzero if the original set is still required. */
2136 static bool
2138 {
2145 /* Allow hard registers if the new mode is legal, and occupies no more
2146 registers than the old mode. */
2152 /* Or a pseudo that is only used once. */
2155 }
2158 /* Check whether X, the destination of a set, refers to part of
2159 the register specified by REG. */
2161 static bool
2163 {
2164 /* Check that reg is an integer mode register. */
2175 }
2177 #ifdef AUTO_INC_DEC
2178 /* Replace auto-increment addressing modes with explicit operations to
2179 access the same addresses without modifying the corresponding
2180 registers. If AFTER holds, SRC is meant to be reused after the
2181 side effect, otherwise it is to be reused before that. */
2183 static rtx
2185 {
2192 {
2203 /* SCRATCH must be shared because they represent distinct values. */
2226 else
2238 else
2244 }
2246 /* Copy the various flags, fields, and other information. We assume
2247 that all fields need copying, and then clear the fields that should
2248 not be copied. That is the sensible default behavior, and forces
2249 us to explicitly document why we are *not* copying a flag. */
2252 /* We do not copy the USED flag, which is used as a mark bit during
2253 walks over the RTL. */
2256 /* We do not copy FRAME_RELATED for INSNs. */
2265 {
2271 }
2274 }
2276 /* Auxiliary data structure for propagate_for_debug_stmt. */
2278 struct rtx_subst_pair
2279 {
2280 rtx to;
2283 };
2285 /* DATA points to an rtx_subst_pair. Return the value that should be
2286 substituted. */
2288 static rtx
2290 {
2294 {
2298 }
2300 }
2301 #endif
2303 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2304 and LAST. If MOVE holds, debug insns must also be moved past
2305 LAST. */
2307 static void
2309 {
2312 #ifdef AUTO_INC_DEC
2317 #endif
2321 {
2325 {
2326 #ifdef AUTO_INC_DEC
2329 #else
2331 #endif
2336 {
2340 }
2341 else
2343 }
2344 }
2345 }
2347 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2348 Note that the INSN should be deleted *after* removing dead edges, so
2349 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2350 but not for a (set (pc) (label_ref FOO)). */
2352 static void
2354 {
2364 }
2367 /* Try to combine the insns I1 and I2 into I3.
2368 Here I1 and I2 appear earlier than I3.
2369 I1 can be zero; then we combine just I2 into I3.
2371 If we are combining three insns and the resulting insn is not recognized,
2372 try splitting it into two insns. If that happens, I2 and I3 are retained
2373 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2374 are pseudo-deleted.
2376 Return 0 if the combination does not work. Then nothing is changed.
2377 If we did the combination, return the insn at which combine should
2378 resume scanning.
2380 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2381 new direct jump instruction. */
2383 static rtx
2385 {
2386 /* New patterns for I3 and I2, respectively. */
2390 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2392 /* Total number of SETs to put into I3. */
2394 /* Nonzero if I2's body now appears in I3. */
2396 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2398 /* Contains I3 if the destination of I3 is used in its source, which means
2399 that the old life of I3 is being killed. If that usage is placed into
2400 I2 and not in I3, a REG_DEAD note must be made. */
2402 /* SET_DEST and SET_SRC of I2 and I1. */
2404 /* Set if I2DEST was reused as a scratch register. */
2406 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2408 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2412 /* Notes that must be added to REG_NOTES in I3 and I2. */
2414 /* Notes that we substituted I3 into I2 instead of the normal case. */
2416 /* Notes that I1, I2 or I3 is a MULT operation. */
2422 rtx temp;
2423 rtx link;
2425 rtx new_other_notes;
2428 /* Exit early if one of the insns involved can't be used for
2429 combinations. */
2436 combine_attempts++;
2439 /* Reset the hard register usage information. */
2443 {
2447 else
2450 }
2452 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2453 code below, set I1 to be the earlier of the two insns. */
2459 /* First check for one important special-case that the code below will
2460 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2461 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2462 we may be able to replace that destination with the destination of I3.
2463 This occurs in the common code where we compute both a quotient and
2464 remainder into a structure, in which case we want to do the computation
2465 directly into the structure to avoid register-register copies.
2467 Note that this case handles both multiple sets in I2 and also
2468 cases where I2 has a number of CLOBBER or PARALLELs.
2470 We make very conservative checks below and only try to handle the
2471 most common cases of this. For example, we only handle the case
2472 where I2 and I3 are adjacent to avoid making difficult register
2473 usage tests. */
2481 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2482 below would need to check what is inside (and reg_overlap_mentioned_p
2483 doesn't support those codes anyway). Don't allow those destinations;
2484 the resulting insn isn't likely to be recognized anyway. */
2490 {
2493 /* Make sure that the destination of I3,
2494 which we are going to substitute into one output of I2,
2495 is not used within another output of I2. We must avoid making this:
2496 (parallel [(set (mem (reg 69)) ...)
2497 (set (reg 69) ...)])
2498 which is not well-defined as to order of actions.
2499 (Besides, reload can't handle output reloads for this.)
2501 The problem can also happen if the dest of I3 is a memory ref,
2502 if another dest in I2 is an indirect memory ref. */
2515 {
2516 combine_merges++;
2526 /* Replace the dest in I2 with our dest and make the resulting
2527 insn the new pattern for I3. Then skip to where we
2528 validate the pattern. Everything was set up above. */
2535 }
2536 }
2538 /* If I2 is setting a pseudo to a constant and I3 is setting some
2539 sub-part of it to another constant, merge them by making a new
2540 constant. */
2549 {
2555 {
2558 {
2564 }
2565 }
2566 else
2567 {
2572 }
2575 {
2576 /* If this is the low part, we're done. */
2578 ;
2579 /* Handle the case where inner is twice the size of outer. */
2583 /* Otherwise give up for now. */
2584 else
2586 }
2591 {
2598 {
2601 }
2602 else
2603 {
2606 }
2609 {
2612 }
2613 else
2614 {
2617 }
2620 {
2623 }
2625 {
2629 }
2630 else
2631 {
2634 }
2640 {
2645 }
2647 {
2654 }
2659 combine_merges++;
2666 /* Replace the source in I2 with the new constant and make the
2667 resulting insn the new pattern for I3. Then skip to where we
2668 validate the pattern. Everything was set up above. */
2674 /* The dest of I3 has been replaced with the dest of I2. */
2677 }
2678 }
2680 #ifndef HAVE_cc0
2681 /* If we have no I1 and I2 looks like:
2682 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2683 (set Y OP)])
2684 make up a dummy I1 that is
2685 (set Y OP)
2686 and change I2 to be
2687 (set (reg:CC X) (compare:CC Y (const_int 0)))
2689 (We can ignore any trailing CLOBBERs.)
2691 This undoes a previous combination and allows us to match a branch-and-
2692 decrement insn. */
2705 {
2711 {
2712 /* We make I1 with the same INSN_UID as I2. This gives it
2713 the same DF_INSN_LUID for value tracking. Our fake I1 will
2714 never appear in the insn stream so giving it the same INSN_UID
2715 as I2 will not cause a problem. */
2724 }
2725 }
2726 #endif
2728 /* Verify that I2 and I1 are valid for combining. */
2731 {
2734 }
2736 /* Record whether I2DEST is used in I2SRC and similarly for the other
2737 cases. Knowing this will help in register status updating below. */
2744 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2745 in I2SRC. */
2748 /* Ensure that I3's pattern can be the destination of combines. */
2752 {
2755 }
2757 /* See if any of the insns is a MULT operation. Unless one is, we will
2758 reject a combination that is, since it must be slower. Be conservative
2759 here. */
2766 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2767 We used to do this EXCEPT in one case: I3 has a post-inc in an
2768 output operand. However, that exception can give rise to insns like
2769 mov r3,(r3)+
2770 which is a famous insn on the PDP-11 where the value of r3 used as the
2771 source was model-dependent. Avoid this sort of thing. */
2773 #if 0
2779 /* It's not the exception. */
2780 #endif
2781 #ifdef AUTO_INC_DEC
2787 {
2790 }
2791 #endif
2793 /* See if the SETs in I1 or I2 need to be kept around in the merged
2794 instruction: whenever the value set there is still needed past I3.
2795 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2797 For the SET in I1, we have two cases: If I1 and I2 independently
2798 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2799 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2800 in I1 needs to be kept around unless I1DEST dies or is set in either
2801 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2802 I1DEST. If so, we know I1 feeds into I2. */
2806 added_sets_1
2810 /* If the set in I2 needs to be kept around, we must make a copy of
2811 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2812 PATTERN (I2), we are only substituting for the original I1DEST, not into
2813 an already-substituted copy. This also prevents making self-referential
2814 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2815 I2DEST. */
2818 {
2821 else
2823 }
2826 {
2829 else
2831 }
2833 combine_merges++;
2835 /* Substitute in the latest insn for the regs set by the earlier ones. */
2841 #ifndef HAVE_cc0
2842 /* Many machines that don't use CC0 have insns that can both perform an
2843 arithmetic operation and set the condition code. These operations will
2844 be represented as a PARALLEL with the first element of the vector
2845 being a COMPARE of an arithmetic operation with the constant zero.
2846 The second element of the vector will set some pseudo to the result
2847 of the same arithmetic operation. If we simplify the COMPARE, we won't
2848 match such a pattern and so will generate an extra insn. Here we test
2849 for this case, where both the comparison and the operation result are
2850 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2851 I2SRC. Later we will make the PARALLEL that contains I2. */
2857 {
2858 #ifdef SELECT_CC_MODE
2861 #endif
2868 #ifdef SELECT_CC_MODE
2869 /* See if a COMPARE with the operand we substituted in should be done
2870 with the mode that is currently being used. If not, do the same
2871 processing we do in `subst' for a SET; namely, if the destination
2872 is used only once, try to replace it with a register of the proper
2873 mode and also replace the COMPARE. */
2880 {
2882 compare_mode))
2883 {
2885 rtx new_dest;
2889 else
2890 {
2893 }
2899 }
2900 else
2902 }
2903 #endif
2904 }
2905 else
2906 #endif
2907 {
2908 /* It is possible that the source of I2 or I1 may be performing
2909 an unneeded operation, such as a ZERO_EXTEND of something
2910 that is known to have the high part zero. Handle that case
2911 by letting subst look at the innermost one of them.
2913 Another way to do this would be to have a function that tries
2914 to simplify a single insn instead of merging two or more
2915 insns. We don't do this because of the potential of infinite
2916 loops and because of the potential extra memory required.
2917 However, doing it the way we are is a bit of a kludge and
2918 doesn't catch all cases.
2920 But only do this if -fexpensive-optimizations since it slows
2921 things down and doesn't usually win.
2923 This is not done in the COMPARE case above because the
2924 unmodified I2PAT is used in the PARALLEL and so a pattern
2925 with a modified I2SRC would not match. */
2928 {
2929 /* Pass pc_rtx so no substitutions are done, just
2930 simplifications. */
2932 {
2935 }
2936 else
2937 {
2940 }
2941 }
2945 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2946 need to make a unique copy of I2SRC each time we substitute it
2947 to avoid self-referential rtl. */
2954 /* Record whether i2's body now appears within i3's body. */
2956 }
2958 /* If we already got a failure, don't try to do more. Otherwise,
2959 try to substitute in I1 if we have it. */
2962 {
2963 /* Check that an autoincrement side-effect on I1 has not been lost.
2964 This happens if I1DEST is mentioned in I2 and dies there, and
2965 has disappeared from the new pattern. */
2967 && !i1_feeds_i3
2970 /* Before we can do this substitution, we must redo the test done
2971 above (see detailed comments there) that ensures that I1DEST
2972 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2974 {
2977 }
2983 }
2985 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2986 to count all the ways that I2SRC and I1SRC can be used. */
2992 /* Fail if we tried to make a new register. */
2994 /* Fail if we couldn't do something and have a CLOBBER. */
2996 /* Fail if this new pattern is a MULT and we didn't have one before
2997 at the outer level. */
3000 {
3003 }
3005 /* If the actions of the earlier insns must be kept
3006 in addition to substituting them into the latest one,
3007 we must make a new PARALLEL for the latest insn
3008 to hold additional the SETs. */
3011 {
3012 combine_extras++;
3015 {
3021 }
3022 else
3023 {
3028 }
3034 {
3035 /* If there is no I1, use I2's body as is. We used to also not do
3036 the subst call below if I2 was substituted into I3,
3037 but that could lose a simplification. */
3040 else
3041 /* See comment where i2pat is assigned. */
3044 }
3045 }
3047 validate_replacement:
3049 /* Note which hard regs this insn has as inputs. */
3052 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3053 consider splitting this pattern, we might need these clobbers. */
3056 {
3062 }
3064 /* Is the result of combination a valid instruction? */
3067 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3068 the second SET's destination is a register that is unused and isn't
3069 marked as an instruction that might trap in an EH region. In that case,
3070 we just need the first SET. This can occur when simplifying a divmod
3071 insn. We *must* test for this case here because the code below that
3072 splits two independent SETs doesn't handle this case correctly when it
3073 updates the register status.
3075 It's pointless doing this if we originally had two sets, one from
3076 i3, and one from i2. Combining then splitting the parallel results
3077 in the original i2 again plus an invalid insn (which we delete).
3078 The net effect is only to move instructions around, which makes
3079 debug info less accurate.
3081 Also check the case where the first SET's destination is unused.
3082 That would not cause incorrect code, but does cause an unneeded
3083 insn to remain. */
3092 {
3102 {
3105 }
3114 {
3120 }
3121 }
3123 /* If we were combining three insns and the result is a simple SET
3124 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3125 insns. There are two ways to do this. It can be split using a
3126 machine-specific method (like when you have an addition of a large
3127 constant) or by combine in the function find_split_point. */
3131 {
3134 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3135 use I2DEST as a scratch register will help. In the latter case,
3136 convert I2DEST to the mode of the source of NEWPAT if we can. */
3140 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3141 inputs of NEWPAT. */
3143 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3144 possible to try that as a scratch reg. This would require adding
3145 more code to make it work though. */
3148 {
3151 /* First try to split using the original register as a
3152 scratch register. */
3156 i2dest)));
3159 /* If that didn't work, try changing the mode of I2DEST if
3160 we can. */
3165 {
3167 rtx ni2dest;
3171 else
3172 {
3175 }
3177 parallel = (gen_rtx_PARALLEL
3181 ni2dest))));
3186 {
3194 }
3195 }
3198 }
3200 /* If recog_for_combine has discarded clobbers, try to use them
3201 again for the split. */
3203 {
3206 }
3209 {
3214 }
3218 {
3228 /* If I2 or I3 has multiple SETs, we won't know how to track
3229 register status, so don't use these insns. If I2's destination
3230 is used between I2 and I3, we also can't use these insns. */
3240 /* It is possible that both insns now set the destination of I3.
3241 If so, we must show an extra use of it. */
3244 {
3262 }
3263 }
3265 /* If we can split it and use I2DEST, go ahead and see if that
3266 helps things be recognized. Verify that none of the registers
3267 are set between I2 and I3. */
3269 #ifdef HAVE_cc0
3271 #endif
3272 /* We need I2DEST in the proper mode. If it is a hard register
3273 or the only use of a pseudo, we can change its mode.
3274 Make sure we don't change a hard register to have a mode that
3275 isn't valid for it, or change the number of registers. */
3282 /* We can't overwrite I2DEST if its value is still used by
3283 NEWPAT. */
3285 {
3294 /* Get NEWDEST as a register in the proper mode. We have already
3295 validated that we can do this. */
3297 {
3300 else
3301 {
3304 }
3305 }
3307 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3308 an ASHIFT. This can occur if it was inside a PLUS and hence
3309 appeared to be a memory address. This is a kludge. */
3314 {
3317 /* Update split_code because we may not have a multiply
3318 anymore. */
3320 }
3322 #ifdef INSN_SCHEDULING
3323 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3324 be written as a ZERO_EXTEND. */
3326 {
3327 #ifdef LOAD_EXTEND_OP
3328 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3329 what it really is. */
3334 else
3335 #endif
3338 }
3339 #endif
3341 /* Attempt to split binary operators using arithmetic identities. */
3345 {
3352 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3354 {
3359 }
3360 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3367 {
3373 /* Split both "((X op Y) op X) op Y" and
3374 "((X op Y) op Y) op X" as "T op T" where T is
3375 "X op Y". */
3378 {
3384 }
3385 /* Split "((X op X) op Y) op Y)" as "T op T" where
3386 T is "X op Y". */
3388 {
3394 }
3395 }
3396 }
3399 {
3402 }
3406 /* recog_for_combine might have added CLOBBERs to newi2pat.
3407 Make sure NEWPAT does not depend on the clobbered regs. */
3411 {
3414 {
3417 }
3418 }
3420 /* If the split point was a MULT and we didn't have one before,
3421 don't use one now. */
3424 }
3425 }
3427 /* Check for a case where we loaded from memory in a narrow mode and
3428 then sign extended it, but we need both registers. In that case,
3429 we have a PARALLEL with both loads from the same memory location.
3430 We can split this into a load from memory followed by a register-register
3431 copy. This saves at least one insn, more if register allocation can
3432 eliminate the copy.
3434 We cannot do this if the destination of the first assignment is a
3435 condition code register or cc0. We eliminate this case by making sure
3436 the SET_DEST and SET_SRC have the same mode.
3438 We cannot do this if the destination of the second assignment is
3439 a register that we have already assumed is zero-extended. Similarly
3440 for a SUBREG of such a register. */
3479 {
3480 rtx ni2dest;
3494 }
3496 /* Similarly, check for a case where we have a PARALLEL of two independent
3497 SETs but we started with three insns. In this case, we can do the sets
3498 as two separate insns. This case occurs when some SET allows two
3499 other insns to combine, but the destination of that SET is still live. */
3518 #ifdef HAVE_cc0
3519 /* We cannot split the parallel into two sets if both sets
3520 reference cc0. */
3523 #endif
3524 )
3525 {
3526 /* Normally, it doesn't matter which of the two is done first,
3527 but it does if one references cc0. In that case, it has to
3528 be first. */
3529 #ifdef HAVE_cc0
3531 {
3534 }
3535 else
3536 #endif
3537 {
3540 }
3546 }
3548 /* If it still isn't recognized, fail and change things back the way they
3549 were. */
3551 /* Is the result a reasonable ASM_OPERANDS? */
3553 {
3556 }
3558 /* If we had to change another insn, make sure it is valid also. */
3560 {
3568 {
3571 }
3572 }
3574 #ifdef HAVE_cc0
3575 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3576 they are adjacent to each other or not. */
3577 {
3581 {
3584 }
3585 }
3586 #endif
3588 /* Only allow this combination if insn_rtx_costs reports that the
3589 replacement instructions are cheaper than the originals. */
3591 {
3594 }
3597 {
3602 {
3607 /* Temporarily revert mode back. */
3611 {
3612 /* If we used i2dest as a scratch register with a
3613 different mode, substitute it for the original
3614 i2src while its original mode is temporarily
3615 restored, and then clear i2scratch so that we don't
3616 do it again later. */
3619 /* Put back the new mode. */
3621 }
3622 else
3623 {
3628 {
3631 }
3632 else
3633 {
3637 }
3639 /* We're dealing with a reg that changed mode but not
3640 meaning, so we want to turn it into a subreg for
3641 the new mode. However, because of REG sharing and
3642 because its mode had already changed, we have to do
3643 it in two steps. First, replace any debug uses of
3644 reg, with its original mode temporarily restored,
3645 with this copy we have created; then, replace the
3646 copy with the SUBREG of the original shared reg,
3647 once again changed to the new mode. */
3653 }
3654 }
3655 }
3657 /* If we will be able to accept this, we have made a
3658 change to the destination of I3. This requires us to
3659 do a few adjustments. */
3662 {
3665 }
3667 /* We now know that we can do this combination. Merge the insns and
3668 update the status of registers and LOG_LINKS. */
3671 {
3676 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3677 are still valid. Then add any non-duplicate notes added by
3678 recog_for_combine. */
3680 {
3686 }
3690 }
3693 {
3694 rtx insn;
3695 rtx link;
3696 rtx ni2dest;
3698 /* I3 now uses what used to be its destination and which is now
3699 I2's destination. This requires us to do a few adjustments. */
3703 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3704 so we still will.
3706 However, some later insn might be using I2's dest and have
3707 a LOG_LINK pointing at I3. We must remove this link.
3708 The simplest way to remove the link is to point it at I1,
3709 which we know will be a NOTE. */
3711 /* newi2pat is usually a SET here; however, recog_for_combine might
3712 have added some clobbers. */
3715 else
3722 {
3724 {
3731 }
3732 }
3733 }
3735 {
3740 /* Compute which registers we expect to eliminate. newi2pat may be setting
3741 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3742 same as i3dest, in which case newi2pat may be setting i1dest. */
3745 || !i2dest_killed
3749 || !i1dest_killed
3752 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3753 clear them. */
3759 /* Ensure that we do not have something that should not be shared but
3760 occurs multiple times in the new insns. Check this by first
3761 resetting all the `used' flags and then copying anything is shared. */
3783 {
3796 }
3801 /* We had one special case above where I2 had more than one set and
3802 we replaced a destination of one of those sets with the destination
3803 of I3. In that case, we have to update LOG_LINKS of insns later
3804 in this basic block. Note that this (expensive) case is rare.
3806 Also, in this case, we must pretend that all REG_NOTEs for I2
3807 actually came from I3, so that REG_UNUSED notes from I2 will be
3808 properly handled. */
3811 {
3829 {
3834 }
3835 else
3838 }
3846 {
3851 }
3852 else
3853 {
3857 }
3860 {
3866 }
3868 /* Get death notes for everything that is now used in either I3 or
3869 I2 and used to die in a previous insn. If we built two new
3870 patterns, move from I1 to I2 then I2 to I3 so that we get the
3871 proper movement on registers that I2 modifies. */
3874 {
3877 }
3878 else
3882 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3896 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3897 know these are REG_UNUSED and want them to go to the desired insn,
3898 so we always pass it as i3. */
3906 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3907 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3908 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3909 in that case, it might delete I2. Similarly for I2 and I1.
3910 Show an additional death due to the REG_DEAD note we make here. If
3911 we discard it in distribute_notes, we will decrement it again. */
3914 {
3917 NULL_RTX),
3919 else
3921 NULL_RTX),
3924 }
3927 {
3931 else
3935 }
3938 {
3942 else
3946 }
3953 {
3954 rtx link;
3957 /* The insn that used to set this register doesn't exist, and
3958 this life of the register may not exist either. See if one of
3959 I3's links points to an insn that sets I2DEST. If it does,
3960 that is now the last known value for I2DEST. If we don't update
3961 this and I2 set the register to a value that depended on its old
3962 contents, we will get confused. If this insn is used, thing
3963 will be set correctly in combine_instructions. */
3972 /* If the reg formerly set in I2 died only once and that was in I3,
3973 zero its use count so it won't make `reload' do any work. */
3977 {
3980 }
3981 }
3984 {
3985 rtx link;
3998 }
4000 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4001 been made to this insn. The order of
4002 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4003 can affect nonzero_bits of newpat */
4007 }
4010 {
4012 {
4015 }
4017 }
4020 {
4022 {
4025 }
4027 }
4030 {
4032 {
4035 }
4037 }
4040 {
4042 {
4045 }
4047 }
4049 /* Set new_direct_jump_p if a new return or simple jump instruction
4050 has been created. Adjust the CFG accordingly. */
4053 {
4057 }
4062 {
4065 }
4067 /* A noop might also need cleaning up of CFG, if it comes from the
4068 simplification of a jump. */
4072 {
4075 }
4077 combine_successes++;
4084 else
4086 }
4087 \f
4088 /* Undo all the modifications recorded in undobuf. */
4090 static void
4092 {
4096 {
4099 {
4111 }
4115 }
4118 }
4120 /* We've committed to accepting the changes we made. Move all
4121 of the undos to the free list. */
4123 static void
4125 {
4129 {
4133 }
4135 }
4136 \f
4137 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4138 where we have an arithmetic expression and return that point. LOC will
4139 be inside INSN.
4141 try_combine will call this function to see if an insn can be split into
4142 two insns. */
4146 {
4155 /* First special-case some codes. */
4157 {
4159 #ifdef INSN_SCHEDULING
4160 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4161 point. */
4164 #endif
4168 #ifdef HAVE_lo_sum
4169 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4170 using LO_SUM and HIGH. */
4173 {
4174 enum machine_mode address_mode
4182 }
4183 #endif
4185 /* If we have a PLUS whose second operand is a constant and the
4186 address is not valid, perhaps will can split it up using
4187 the machine-specific way to split large constants. We use
4188 the first pseudo-reg (one of the virtual regs) as a placeholder;
4189 it will not remain in the result. */
4194 {
4198 subst_insn);
4200 /* This should have produced two insns, each of which sets our
4201 placeholder. If the source of the second is a valid address,
4202 we can make put both sources together and make a split point
4203 in the middle. */
4216 && memory_address_addr_space_p
4219 {
4223 /* Replace the placeholder in SRC2 with SRC1. If we can
4224 find where in SRC2 it was placed, that can become our
4225 split point and we can replace this address with SRC2.
4226 Just try two obvious places. */
4237 {
4240 }
4241 }
4243 /* If that didn't work, perhaps the first operand is complex and
4244 needs to be computed separately, so make a split point there.
4245 This will occur on machines that just support REG + CONST
4246 and have a constant moved through some previous computation. */
4252 }
4254 /* If we have a PLUS whose first operand is complex, try computing it
4255 separately by making a split there. */
4266 #ifdef HAVE_cc0
4267 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4268 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4269 we need to put the operand into a register. So split at that
4270 point. */
4279 #endif
4281 /* See if we can split SET_SRC as it stands. */
4286 /* See if we can split SET_DEST as it stands. */
4291 /* See if this is a bitfield assignment with everything constant. If
4292 so, this is an IOR of an AND, so split it into that. */
4303 {
4310 rtx or_mask;
4319 else
4320 {
4326 or_mask));
4327 }
4334 }
4336 /* Otherwise, see if this is an operation that we can split into two.
4337 If so, try to split that. */
4341 {
4343 /* If we are AND'ing with a large constant that is only a single
4344 bit and the result is only being used in a context where we
4345 need to know if it is zero or nonzero, replace it with a bit
4346 extraction. This will avoid the large constant, which might
4347 have taken more than one insn to make. If the constant were
4348 not a valid argument to the AND but took only one insn to make,
4349 this is no worse, but if it took more than one insn, it will
4350 be better. */
4360 {
4365 {
4368 }
4369 }
4373 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4374 is known to be on, this can be converted into a NEG of a shift. */
4380 {
4392 }
4398 /* We can't optimize if either mode is a partial integer
4399 mode as we don't know how many bits are significant
4400 in those modes. */
4414 {
4422 }
4427 }
4430 {
4433 /* For unsigned, we have a choice of a shift followed by an
4434 AND or two shifts. Use two shifts for field sizes where the
4435 constant might be too large. We assume here that we can
4436 always at least get 8-bit constants in an AND insn, which is
4437 true for every current RISC. */
4440 {
4443 gen_rtx_LSHIFTRT
4451 }
4452 else
4453 {
4455 gen_rtx_fmt_ee
4466 }
4467 }
4469 /* See if this is a simple operation with a constant as the second
4470 operand. It might be that this constant is out of range and hence
4471 could be used as a split point. */
4479 /* Finally, see if this is a simple operation with its first operand
4480 not in a register. The operation might require this operand in a
4481 register, so return it as a split point. We can always do this
4482 because if the first operand were another operation, we would have
4483 already found it as a split point. */
4492 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4493 it is better to write this as (not (ior A B)) so we can split it.
4494 Similarly for IOR. */
4496 {
4504 }
4506 /* Many RISC machines have a large set of logical insns. If the
4507 second operand is a NOT, put it first so we will try to split the
4508 other operand first. */
4510 {
4514 }
4519 }
4521 /* Otherwise, select our actions depending on our rtx class. */
4523 {
4529 /* ... fall through ... */
4537 /* ... fall through ... */
4539 /* Some machines have (and (shift ...) ...) insns. If X is not
4540 an AND, but XEXP (X, 0) is, use it as our split point. */
4550 /* Otherwise, we don't have a split point. */
4552 }
4553 }
4554 \f
4555 /* Throughout X, replace FROM with TO, and return the result.
4556 The result is TO if X is FROM;
4557 otherwise the result is X, but its contents may have been modified.
4558 If they were modified, a record was made in undobuf so that
4559 undo_all will (among other things) return X to its original state.
4561 If the number of changes necessary is too much to record to undo,
4562 the excess changes are not made, so the result is invalid.
4563 The changes already made can still be undone.
4564 undobuf.num_undo is incremented for such changes, so by testing that
4565 the caller can tell whether the result is valid.
4567 `n_occurrences' is incremented each time FROM is replaced.
4569 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4571 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4572 by copying if `n_occurrences' is nonzero. */
4574 static rtx
4576 {
4581 rtx new_rtx;
4583 /* Two expressions are equal if they are identical copies of a shared
4584 RTX or if they are both registers with the same register number
4585 and mode. */
4587 #define COMBINE_RTX_EQUAL_P(X,Y) \
4588 ((X) == (Y) \
4589 || (REG_P (X) && REG_P (Y) \
4590 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4593 {
4594 n_occurrences++;
4596 }
4598 /* If X and FROM are the same register but different modes, they
4599 will not have been seen as equal above. However, the log links code
4600 will make a LOG_LINKS entry for that case. If we do nothing, we
4601 will try to rerecognize our original insn and, when it succeeds,
4602 we will delete the feeding insn, which is incorrect.
4604 So force this insn not to match in this (rare) case. */
4609 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4610 of which may contain things that can be combined. */
4614 /* It is possible to have a subexpression appear twice in the insn.
4615 Suppose that FROM is a register that appears within TO.
4616 Then, after that subexpression has been scanned once by `subst',
4617 the second time it is scanned, TO may be found. If we were
4618 to scan TO here, we would find FROM within it and create a
4619 self-referent rtl structure which is completely wrong. */
4623 /* Parallel asm_operands need special attention because all of the
4624 inputs are shared across the arms. Furthermore, unsharing the
4625 rtl results in recognition failures. Failure to handle this case
4626 specially can result in circular rtl.
4628 Solve this by doing a normal pass across the first entry of the
4629 parallel, and only processing the SET_DESTs of the subsequent
4630 entries. Ug. */
4635 {
4638 /* If this substitution failed, this whole thing fails. */
4646 {
4652 {
4655 /* If this substitution failed, this whole thing fails. */
4661 }
4662 }
4663 }
4664 else
4665 {
4669 /* We don't need to process a SET_DEST that is a register, CC0,
4670 or PC, so set up to skip this common case. All other cases
4671 where we want to suppress replacing something inside a
4672 SET_SRC are handled via the IN_DEST operand. */
4679 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4680 constant. */
4685 {
4687 {
4690 {
4692 {
4695 n_occurrences++;
4696 }
4697 else
4698 {
4700 unique_copy);
4702 /* If this substitution failed, this whole thing
4703 fails. */
4707 }
4710 }
4711 }
4713 {
4714 /* If this is a register being set, ignore it. */
4721 ;
4724 {
4725 /* In general, don't install a subreg involving two
4726 modes not tieable. It can worsen register
4727 allocation, and can even make invalid reload
4728 insns, since the reg inside may need to be copied
4729 from in the outside mode, and that may be invalid
4730 if it is an fp reg copied in integer mode.
4732 We allow two exceptions to this: It is valid if
4733 it is inside another SUBREG and the mode of that
4734 SUBREG and the mode of the inside of TO is
4735 tieable and it is valid if X is a SET that copies
4736 FROM to CC0. */
4744 #ifdef HAVE_cc0
4746 #endif
4747 )
4750 #ifdef CANNOT_CHANGE_MODE_CLASS
4758 #endif
4761 n_occurrences++;
4762 }
4763 else
4764 /* If we are in a SET_DEST, suppress most cases unless we
4765 have gone inside a MEM, in which case we want to
4766 simplify the address. We assume here that things that
4767 are actually part of the destination have their inner
4768 parts in the first expression. This is true for SUBREG,
4769 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4770 things aside from REG and MEM that should appear in a
4771 SET_DEST. */
4773 (((in_dest
4779 /* If we found that we will have to reject this combination,
4780 indicate that by returning the CLOBBER ourselves, rather than
4781 an expression containing it. This will speed things up as
4782 well as prevent accidents where two CLOBBERs are considered
4783 to be equal, thus producing an incorrect simplification. */
4791 {
4799 }
4802 {
4806 }
4807 else
4809 }
4810 }
4811 }
4813 /* Check if we are loading something from the constant pool via float
4814 extension; in this case we would undo compress_float_constant
4815 optimization and degenerate constant load to an immediate value. */
4819 {
4823 }
4825 /* Try to simplify X. If the simplification changed the code, it is likely
4826 that further simplification will help, so loop, but limit the number
4827 of repetitions that will be performed. */
4830 {
4831 /* If X is sufficiently simple, don't bother trying to do anything
4832 with it. */
4841 /* We no longer know the original mode of operand 0 since we
4842 have changed the form of X) */
4844 }
4847 }
4848 \f
4849 /* Simplify X, a piece of RTL. We just operate on the expression at the
4850 outer level; call `subst' to simplify recursively. Return the new
4851 expression.
4853 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4854 if we are inside a SET_DEST. */
4856 static rtx
4858 {
4861 rtx temp;
4864 /* If this is a commutative operation, put a constant last and a complex
4865 expression first. We don't need to do this for comparisons here. */
4868 {
4872 }
4874 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4875 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4876 things. Check for cases where both arms are testing the same
4877 condition.
4879 Don't do anything if all operands are very simple. */
4892 {
4897 /* If everything is a comparison, what we have is highly unlikely
4898 to be simpler, so don't use it. */
4901 {
4908 /* Simplify the alternative arms; this may collapse the true and
4909 false arms to store-flag values. Be careful to use copy_rtx
4910 here since true_rtx or false_rtx might share RTL with x as a
4911 result of the if_then_else_cond call above. */
4915 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4916 is unlikely to be simpler. */
4919 {
4922 /* Restarting if we generate a store-flag expression will cause
4923 us to loop. Just drop through in this case. */
4925 /* If the result values are STORE_FLAG_VALUE and zero, we can
4926 just make the comparison operation. */
4937 /* Likewise, we can make the negate of a comparison operation
4938 if the result values are - STORE_FLAG_VALUE and zero. */
4946 mode);
4957 mode);
4958 else
4961 mode,
4962 VOIDmode,
4963 cond,
4964 cop1),
4969 }
4970 }
4971 }
4973 /* Try to fold this expression in case we have constants that weren't
4974 present before. */
4977 {
4985 {
4988 {
4992 }
4995 }
5008 }
5011 {
5016 }
5018 /* First see if we can apply the inverse distributive law. */
5021 {
5025 }
5027 /* If CODE is an associative operation not otherwise handled, see if we
5028 can associate some operands. This can win if they are constants or
5029 if they are logically related (i.e. (a & b) & a). */
5035 {
5037 {
5041 rtx inner;
5043 /* Make sure we pass the constant operand if any as the second
5044 one if this is a commutative operation. */
5046 {
5050 }
5056 /* For commutative operations, try the other pair if that one
5057 didn't simplify. */
5059 {
5064 }
5068 }
5069 }
5071 /* A little bit of algebraic simplification here. */
5073 {
5075 /* Ensure that our address has any ASHIFTs converted to MULT in case
5076 address-recognizing predicates are called later. */
5085 /* See if this can be moved to simplify_subreg. */
5088 /* Don't call gen_lowpart if the inner mode
5089 is VOIDmode and we cannot simplify it, as SUBREG without
5090 inner mode is invalid. */
5097 {
5098 rtx temp;
5103 }
5105 /* Don't change the mode of the MEM if that would change the meaning
5106 of the address. */
5112 /* Note that we cannot do any narrowing for non-constants since
5113 we might have been counting on using the fact that some bits were
5114 zero. We now do this in the SET. */
5121 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5122 replaced by (lshiftrt X C). This will convert
5123 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5131 /* If X has only a single bit that might be nonzero, say, bit I, convert
5132 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5133 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5134 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5135 or a SUBREG of one since we'd be making the expression more
5136 complex if it was just a register. */
5142 {
5143 rtx temp1 = simplify_shift_const
5149 /* If all we did was surround TEMP with the two shifts, we
5150 haven't improved anything, so don't use it. Otherwise,
5151 we are better off with TEMP1. */
5156 }
5160 /* We can't handle truncation to a partial integer mode here
5161 because we don't know the real bitsize of the partial
5162 integer mode. */
5171 /* We can truncate a constant value and return it. */
5175 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5176 whose value is a comparison can be replaced with a subreg if
5177 STORE_FLAG_VALUE permits. */
5186 /* (const (const X)) can become (const X). Do it this way rather than
5187 returning the inner CONST since CONST can be shared with a
5188 REG_EQUAL note. */
5193 #ifdef HAVE_lo_sum
5195 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5196 can add in an offset. find_split_point will split this address up
5197 again if it doesn't match. */
5202 #endif
5205 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5206 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5207 bit-field and can be replaced by either a sign_extend or a
5208 sign_extract. The `and' may be a zero_extend and the two
5209 <c>, -<c> constants may be reversed. */
5224 return simplify_shift_const
5231 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5232 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5233 the bitsize of the mode - 1. This allows simplification of
5234 "a = (b & 8) == 0;" */
5246 /* If we are adding two things that have no bits in common, convert
5247 the addition into an IOR. This will often be further simplified,
5248 for example in cases like ((a & 1) + (a & 2)), which can
5249 become a & 3. */
5254 {
5255 /* Try to simplify the expression further. */
5259 /* If we could, great. If not, do not go ahead with the IOR
5260 replacement, since PLUS appears in many special purpose
5261 address arithmetic instructions. */
5264 }
5268 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5269 (and <foo> (const_int pow2-1)) */
5279 /* If we have (mult (plus A B) C), apply the distributive law and then
5280 the inverse distributive law to see if things simplify. This
5281 occurs mostly in addresses, often when unrolling loops. */
5284 {
5288 }
5290 /* Try simplify a*(b/c) as (a*b)/c. */
5293 {
5299 }
5303 /* If this is a divide by a power of two, treat it as a shift if
5304 its first operand is a shift. */
5322 /* If the first operand is a condition code, we can't do anything
5323 with it. */
5327 {
5335 /* Simplify our comparison, if possible. */
5338 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5339 if only the low-order bit is possibly nonzero in X (such as when
5340 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5341 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5342 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5343 (plus X 1).
5345 Remove any ZERO_EXTRACT we made when thinking this was a
5346 comparison. It may now be simpler to use, e.g., an AND. If a
5347 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5348 the call to make_compound_operation in the SET case. */
5364 {
5368 mode);
5369 }
5376 {
5380 const1_rtx);
5381 }
5389 {
5392 }
5394 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5395 those above. */
5409 {
5413 mode);
5414 }
5422 {
5426 mode);
5427 }
5429 /* If X is 0/1, (eq X 0) is X-1. */
5435 {
5438 }
5440 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5441 one bit that might be nonzero, we can convert (ne x 0) to
5442 (ashift x c) where C puts the bit in the sign bit. Remove any
5443 AND with STORE_FLAG_VALUE when we are done, since we are only
5444 going to test the sign bit. */
5452 {
5458 else
5460 }
5462 /* If the code changed, return a whole new comparison. */
5466 /* Otherwise, keep this operation, but maybe change its operands.
5467 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5470 }
5480 /* If we are processing SET_DEST, we are done. */
5498 /* If this is a shift by a constant amount, simplify it. */
5514 }
5517 }
5518 \f
5519 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5521 static rtx
5523 {
5530 rtx temp;
5533 rtx reversed;
5535 /* Simplify storing of the truth value. */
5540 /* Also when the truth value has to be reversed. */
5546 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5547 in it is being compared against certain values. Get the true and false
5548 comparisons and see if that says anything about the value of each arm. */
5554 {
5555 HOST_WIDE_INT nzb;
5561 /* If FALSE_CODE is EQ, swap the codes and arms. */
5564 {
5567 }
5569 /* If we are comparing against zero and the expression being tested has
5570 only a single bit that might be nonzero, that is its value when it is
5571 not equal to zero. Similarly if it is known to be -1 or 0. */
5575 {
5578 }
5582 {
5585 }
5587 /* Now simplify an arm if we know the value of the register in the
5588 branch and it is used in the arm. Be careful due to the potential
5589 of locally-shared RTL. */
5606 }
5608 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5609 reversed, do so to avoid needing two sets of patterns for
5610 subtract-and-branch insns. Similarly if we have a constant in the true
5611 arm, the false arm is the same as the first operand of the comparison, or
5612 the false arm is more complicated than the true arm. */
5625 {
5634 /* It is possible that the conditional has been simplified out. */
5637 }
5639 /* If the two arms are identical, we don't need the comparison. */
5644 /* Convert a == b ? b : a to "a". */
5656 /* Look for cases where we have (abs x) or (neg (abs X)). */
5659 && comparison_p
5666 {
5672 return
5675 mode);
5678 }
5680 /* Look for MIN or MAX. */
5683 && comparison_p
5688 {
5703 }
5705 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5706 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5707 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5708 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5709 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5710 neither 1 or -1, but it isn't worth checking for. */
5713 && comparison_p
5716 {
5732 /* If an identity-zero op is commutative, check whether there
5733 would be a match if we swapped the operands. */
5753 {
5757 }
5769 {
5773 }
5789 {
5793 }
5805 {
5809 }
5812 {
5818 const_true_rtx));
5826 }
5827 }
5829 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5830 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5831 negation of a single bit, we can convert this operation to a shift. We
5832 can actually do this more generally, but it doesn't seem worth it. */
5841 return
5845 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5855 }
5856 \f
5857 /* Simplify X, a SET expression. Return the new expression. */
5859 static rtx
5861 {
5864 enum machine_mode mode
5866 rtx other_insn;
5869 /* (set (pc) (return)) gets written as (return). */
5873 /* Now that we know for sure which bits of SRC we are using, see if we can
5874 simplify the expression for the object knowing that we only need the
5875 low-order bits. */
5879 {
5882 }
5884 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5885 the comparison result and try to simplify it unless we already have used
5886 undobuf.other_insn. */
5894 {
5903 else
5911 {
5915 }
5916 else
5917 {
5922 /* Attempt to simplify CC user. */
5924 {
5928 }
5930 /* Convert X into a no-op move. */
5934 }
5936 /* Simplify our comparison, if possible. */
5939 #ifdef SELECT_CC_MODE
5940 /* If this machine has CC modes other than CCmode, check to see if we
5941 need to use a different CC mode here. */
5944 else
5947 #ifndef HAVE_cc0
5948 /* If the mode changed, we have to change SET_DEST, the mode in the
5949 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5950 a hard register, just build new versions with the proper mode. If it
5951 is a pseudo, we lose unless it is only time we set the pseudo, in
5952 which case we can safely change its mode. */
5954 {
5956 {
5958 rtx new_dest;
5962 else
5963 {
5966 }
5973 }
5974 }
5978 /* If the code changed, we have to build a new comparison in
5979 undobuf.other_insn. */
5981 {
5990 /* If the only change we made was to change an EQ into an NE or
5991 vice versa, OP0 has only one bit that might be nonzero, and OP1
5992 is zero, check if changing the user of the condition code will
5993 produce a valid insn. If it won't, we can keep the original code
5994 in that insn by surrounding our operation with an XOR. */
6001 {
6006 {
6012 }
6013 }
6014 }
6019 /* Otherwise, if we didn't previously have a COMPARE in the
6020 correct mode, we need one. */
6022 {
6025 }
6027 {
6030 }
6031 /* Otherwise, update the COMPARE if needed. */
6033 {
6036 }
6037 }
6038 else
6039 {
6040 /* Get SET_SRC in a form where we have placed back any
6041 compound expressions. Then do the checks below. */
6044 }
6046 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6047 and X being a REG or (subreg (reg)), we may be able to convert this to
6048 (set (subreg:m2 x) (op)).
6050 We can always do this if M1 is narrower than M2 because that means that
6051 we only care about the low bits of the result.
6053 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6054 perform a narrower operation than requested since the high-order bits will
6055 be undefined. On machine where it is defined, this transformation is safe
6056 as long as M1 and M2 have the same number of words. */
6064 #ifndef WORD_REGISTER_OPERATIONS
6067 #endif
6068 #ifdef CANNOT_CHANGE_MODE_CLASS
6073 #endif
6077 {
6080 dest));
6084 }
6086 #ifdef HAVE_cc0
6087 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6088 in SRC. */
6094 {
6098 /* Here we make sure that we don't have a sign bit on. */
6103 {
6106 }
6107 }
6108 #endif
6110 #ifdef LOAD_EXTEND_OP
6111 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6112 would require a paradoxical subreg. Replace the subreg with a
6113 zero_extend to avoid the reload that would otherwise be required. */
6122 {
6128 }
6129 #endif
6131 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6132 are comparing an item known to be 0 or -1 against 0, use a logical
6133 operation instead. Check for one of the arms being an IOR of the other
6134 arm with some value. We compute three terms to be IOR'ed together. In
6135 practice, at most two will be nonzero. Then we do the IOR's. */
6143 #ifdef HAVE_conditional_move
6145 #endif
6150 {
6176 false_rtx);
6182 term3));
6185 }
6187 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6188 whole thing fail. */
6193 else
6194 /* Convert this into a field assignment operation, if possible. */
6196 }
6197 \f
6198 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6199 result. */
6201 static rtx
6203 {
6209 {
6211 /* We can call simplify_and_const_int only if we don't lose
6212 any (sign) bits when converting INTVAL (op1) to
6213 "unsigned HOST_WIDE_INT". */
6217 {
6224 }
6226 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6227 apply the distributive law and then the inverse distributive
6228 law to see if things simplify. */
6230 {
6234 }
6236 {
6240 }
6244 /* If we have (ior (and A B) C), apply the distributive law and then
6245 the inverse distributive law to see if things simplify. */
6248 {
6252 }
6255 {
6259 }
6264 }
6267 }
6268 \f
6269 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6270 operations" because they can be replaced with two more basic operations.
6271 ZERO_EXTEND is also considered "compound" because it can be replaced with
6272 an AND operation, which is simpler, though only one operation.
6274 The function expand_compound_operation is called with an rtx expression
6275 and will convert it to the appropriate shifts and AND operations,
6276 simplifying at each stage.
6278 The function make_compound_operation is called to convert an expression
6279 consisting of shifts and ANDs into the equivalent compound expression.
6280 It is the inverse of this function, loosely speaking. */
6282 static rtx
6284 {
6288 rtx tem;
6291 {
6295 /* We can't necessarily use a const_int for a multiword mode;
6296 it depends on implicitly extending the value.
6297 Since we don't know the right way to extend it,
6298 we can't tell whether the implicit way is right.
6300 Even for a mode that is no wider than a const_int,
6301 we can't win, because we need to sign extend one of its bits through
6302 the rest of it, and we don't know which bit. */
6306 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6307 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6308 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6309 reloaded. If not for that, MEM's would very rarely be safe.
6311 Reject MODEs bigger than a word, because we might not be able
6312 to reference a two-register group starting with an arbitrary register
6313 (and currently gen_lowpart might crash for a SUBREG). */
6318 /* Reject MODEs that aren't scalar integers because turning vector
6319 or complex modes into shifts causes problems. */
6325 /* If the inner object has VOIDmode (the only way this can happen
6326 is if it is an ASM_OPERANDS), we can't do anything since we don't
6327 know how much masking to do. */
6336 /* ... fall through ... */
6339 /* If the operand is a CLOBBER, just return it. */
6348 /* Reject MODEs that aren't scalar integers because turning vector
6349 or complex modes into shifts causes problems. */
6357 /* This should stay within the object being extracted, fail otherwise. */
6368 }
6369 /* Convert sign extension to zero extension, if we know that the high
6370 bit is not set, as this is easier to optimize. It will be converted
6371 back to cheaper alternative in make_extraction. */
6379 {
6383 /* Make sure this is a profitable operation. */
6390 else
6392 }
6394 /* We can optimize some special cases of ZERO_EXTEND. */
6396 {
6397 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6398 know that the last value didn't have any inappropriate bits
6399 set. */
6407 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6416 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6417 is a comparison and STORE_FLAG_VALUE permits. This is like
6418 the first case, but it works even when GET_MODE (x) is larger
6419 than HOST_WIDE_INT. */
6429 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6440 }
6442 /* If we reach here, we want to return a pair of shifts. The inner
6443 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6444 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6445 logical depending on the value of UNSIGNEDP.
6447 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6448 converted into an AND of a shift.
6450 We must check for the case where the left shift would have a negative
6451 count. This can happen in a case like (x >> 31) & 255 on machines
6452 that can't shift by a constant. On those machines, we would first
6453 combine the shift with the AND to produce a variable-position
6454 extraction. Then the constant of 31 would be substituted in to produce
6455 a such a position. */
6459 {
6468 }
6475 else
6476 /* Any other cases we can't handle. */
6479 /* If we couldn't do this for some reason, return the original
6480 expression. */
6485 }
6486 \f
6487 /* X is a SET which contains an assignment of one object into
6488 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6489 or certain SUBREGS). If possible, convert it into a series of
6490 logical operations.
6492 We half-heartedly support variable positions, but do not at all
6493 support variable lengths. */
6495 static const_rtx
6497 {
6498 rtx inner;
6504 /* Loop until we find something we can't simplify. */
6506 {
6509 {
6513 }
6516 {
6521 /* A constant position should stay within the width of INNER. */
6527 {
6535 /* If position is ADJUST - X, new position is X. */
6537 else
6542 pos);
6543 }
6544 }
6546 /* A SUBREG between two modes that occupy the same numbers of words
6547 can be done by moving the SUBREG to the source. */
6549 /* We need SUBREGs to compute nonzero_bits properly. */
6550 && nonzero_sign_valid
6555 {
6557 gen_lowpart
6561 }
6562 else
6570 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6572 {
6575 /* Don't do anything for vector or complex integral types. */
6579 /* Try to find an integral mode to pun with. */
6586 }
6588 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6592 /* Now compute the equivalent expression. Make a copy of INNER
6593 for the SET_DEST in case it is a MEM into which we will substitute;
6594 we don't want shared RTL in that case. */
6599 compute_mode,
6601 compute_mode),
6602 inner);
6607 mask),
6608 pos);
6613 }
6616 }
6617 \f
6618 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6619 it is an RTX that represents a variable starting position; otherwise,
6620 POS is the (constant) starting bit position (counted from the LSB).
6622 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6623 signed reference.
6625 IN_DEST is nonzero if this is a reference in the destination of a
6626 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6627 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6628 be used.
6630 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6631 ZERO_EXTRACT should be built even for bits starting at bit 0.
6633 MODE is the desired mode of the result (if IN_DEST == 0).
6635 The result is an RTX for the extraction or NULL_RTX if the target
6636 can't handle it. */
6638 static rtx
6642 {
6643 /* This mode describes the size of the storage area
6644 to fetch the overall value from. Within that, we
6645 ignore the POS lowest bits, etc. */
6655 HOST_WIDE_INT orig_pos;
6658 {
6659 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6660 consider just the QI as the memory to extract from.
6661 The subreg adds or removes high bits; its mode is
6662 irrelevant to the meaning of this extraction,
6663 since POS and LEN count from the lsb. */
6667 }
6672 {
6673 /* We're extracting the least significant bits of an rtx
6674 (ashift X (const_int C)), where LEN > C. Extract the
6675 least significant (LEN - C) bits of X, giving an rtx
6676 whose mode is MODE, then shift it left C times. */
6682 }
6689 /* See if this can be done without an extraction. We never can if the
6690 width of the field is not the same as that of some integer mode. For
6691 registers, we can only avoid the extraction if the position is at the
6692 low-order bit and this is either not in the destination or we have the
6693 appropriate STRICT_LOW_PART operation available.
6695 For MEM, we can avoid an extract if the field starts on an appropriate
6696 boundary and we can change the mode of the memory reference. */
6706 && (! in_dest
6710 && (pos
6713 /* We can't do this if we are widening INNER_MODE (it
6714 may not be aligned, for one thing). */
6719 {
6720 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6721 field. If the original and current mode are the same, we need not
6722 adjust the offset. Otherwise, we do if bytes big endian.
6724 If INNER is not a MEM, get a piece consisting of just the field
6725 of interest (in this case POS % BITS_PER_WORD must be 0). */
6728 {
6729 HOST_WIDE_INT offset;
6731 /* POS counts from lsb, but make OFFSET count in memory order. */
6734 else
6738 }
6740 {
6742 {
6743 /* We can't call gen_lowpart in a DEST since we
6744 always want a SUBREG (see below) and it would sometimes
6745 return a new hard register. */
6747 {
6762 /* Avoid creating invalid subregs, for example when
6763 simplifying (x>>32)&255. */
6768 }
6769 else
6771 }
6772 else
6774 }
6775 else
6777 len >= HOST_BITS_PER_WIDE_INT
6782 /* If this extraction is going into the destination of a SET,
6783 make a STRICT_LOW_PART unless we made a MEM. */
6797 /* If we know that no extraneous bits are set, and that the high
6798 bit is not set, convert the extraction to the cheaper of
6799 sign and zero extension, that are equivalent in these cases. */
6807 {
6811 /* Prefer ZERO_EXTENSION, since it gives more information to
6812 backends. */
6817 }
6819 /* Otherwise, sign- or zero-extend unless we already are in the
6820 proper mode. */
6824 }
6826 /* Unless this is a COMPARE or we have a funny memory reference,
6827 don't do anything with zero-extending field extracts starting at
6828 the low-order bit since they are simple AND operations. */
6833 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6834 if the position is not a constant and the length is not 1. In all
6835 other cases, we would only be going outside our object in cases when
6836 an original shift would have been undefined. */
6842 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6843 and the mode for the result. */
6845 {
6849 }
6853 {
6857 }
6861 {
6865 }
6867 /* Never narrow an object, since that might not be safe. */
6877 /* If this is not from memory, the desired mode is the preferred mode
6878 for an extraction pattern's first input operand, or word_mode if there
6879 is none. */
6882 else
6883 {
6884 /* Be careful not to go beyond the extracted object and maintain the
6885 natural alignment of the memory. */
6889 {
6892 }
6894 /* If we have to change the mode of memory and cannot, the desired mode
6895 is EXTRACTION_MODE. */
6901 }
6906 {
6907 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6908 BITS_BIG_ENDIAN style. If position is constant, compute new
6909 position. Otherwise, build subtraction.
6910 Note that POS is relative to the mode of the original argument.
6911 If it's a MEM we need to recompute POS relative to that.
6912 However, if we're extracting from (or inserting into) a register,
6913 we want to recompute POS relative to wanted_inner_mode. */
6920 else
6921 pos_rtx
6923 /* POS may be less than 0 now, but we check for that below.
6924 Note that it can only be less than 0 if !MEM_P (inner). */
6925 }
6927 /* If INNER has a wider mode, and this is a constant extraction, try to
6928 make it smaller and adjust the byte to point to the byte containing
6929 the value. */
6932 && ! pos_rtx
6937 {
6940 /* The computations below will be correct if the machine is big
6941 endian in both bits and bytes or little endian in bits and bytes.
6942 If it is mixed, we must adjust. */
6944 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6945 adjust OFFSET to compensate. */
6950 /* We can now move to the desired byte. */
6961 }
6963 /* If INNER is not memory, get it into the proper mode. If we are changing
6964 its mode, POS must be a constant and smaller than the size of the new
6965 mode. */
6967 {
6968 /* On the LHS, don't create paradoxical subregs implicitely truncating
6969 the register unless TRULY_NOOP_TRUNCATION. */
6984 pos_rtx
6990 }
6992 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6993 have to zero extend. Otherwise, we can just use a SUBREG. */
6996 {
6999 /* If we know that no extraneous bits are set, and that the high
7000 bit is not set, convert extraction to cheaper one - either
7001 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7002 cases. */
7010 {
7013 /* Prefer ZERO_EXTENSION, since it gives more information to
7014 backends. */
7018 }
7020 }
7025 /* Make POS_RTX unless we already have it and it is correct. If we don't
7026 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7027 be a CONST_INT. */
7034 /* Make the required operation. See if we can use existing rtx. */
7041 }
7042 \f
7043 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7044 with any other operations in X. Return X without that shift if so. */
7046 static rtx
7048 {
7051 rtx tem;
7054 {
7056 /* This is the shift itself. If it is wide enough, we will return
7057 either the value being shifted if the shift count is equal to
7058 COUNT or a shift for the difference. */
7072 /* If we can safely shift this constant and we find the inner shift,
7073 make a new operation. */
7084 }
7087 }
7088 \f
7089 /* Look at the expression rooted at X. Look for expressions
7090 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7091 Form these expressions.
7093 Return the new rtx, usually just X.
7095 Also, for machines like the VAX that don't have logical shift insns,
7096 try to convert logical to arithmetic shift operations in cases where
7097 they are equivalent. This undoes the canonicalizations to logical
7098 shifts done elsewhere.
7100 We try, as much as possible, to re-use rtl expressions to save memory.
7102 IN_CODE says what kind of expression we are processing. Normally, it is
7103 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7104 being kludges), it is MEM. When processing the arguments of a comparison
7105 or a COMPARE against zero, it is COMPARE. */
7107 static rtx
7109 {
7117 rtx tem;
7120 /* Select the code to be used in recursive calls. Once we are inside an
7121 address, we stay there. If we have a comparison, set to COMPARE,
7122 but once inside, go back to our default of SET. */
7129 /* Process depending on the code of this operation. If NEW is set
7130 nonzero, it will be returned. */
7133 {
7135 /* Convert shifts by constants into multiplications if inside
7136 an address. */
7140 {
7145 }
7149 /* If the second operand is not a constant, we can't do anything
7150 with it. */
7154 /* If the constant is a power of two minus one and the first operand
7155 is a logical right shift, make an extraction. */
7158 {
7162 }
7164 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7169 {
7171 next_code);
7175 }
7176 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7182 {
7183 /* Apply the distributive law, and then try to make extractions. */
7190 }
7192 /* If we are have (and (rotate X C) M) and C is larger than the number
7193 of bits in M, this is an extraction. */
7199 {
7205 }
7207 /* On machines without logical shifts, if the operand of the AND is
7208 a logical shift and our mask turns off all the propagated sign
7209 bits, we can replace the logical shift with an arithmetic shift. */
7217 {
7224 make_compound_operation
7227 }
7229 /* If the constant is one less than a power of two, this might be
7230 representable by an extraction even if no shift is present.
7231 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7232 we are in a COMPARE. */
7236 next_code),
7239 /* If we are in a comparison and this is an AND with a power of two,
7240 convert this into the appropriate bit extract. */
7245 next_code),
7251 /* If the sign bit is known to be zero, replace this with an
7252 arithmetic shift. */
7257 {
7260 next_code),
7263 }
7265 /* ... fall through ... */
7271 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7272 this is a SIGN_EXTRACT. */
7278 {
7285 }
7287 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7288 If so, try to merge the shifts into a SIGN_EXTEND. We could
7289 also do this for some cases of SIGN_EXTRACT, but it doesn't
7290 seem worth the effort; the case checked for occurs on Alpha. */
7306 /* Call ourselves recursively on the inner expression. If we are
7307 narrowing the object and it has a different RTL code from
7308 what it originally did, do this SUBREG as a force_to_mode. */
7312 {
7313 rtx simplified;
7323 {
7327 /* If we have something other than a SUBREG, we might have
7328 done an expansion, so rerun ourselves. */
7332 /* force_to_mode can expand compounds. If it just re-expanded the
7333 compound use gen_lowpart instead to convert to the desired
7334 mode. */
7339 }
7343 }
7348 }
7351 {
7354 }
7356 /* Now recursively process each operand of this operation. */
7360 {
7363 }
7366 {
7369 }
7371 /* If this is a commutative operation, the changes to the operands
7372 may have made it noncanonical. */
7375 {
7379 }
7382 }
7383 \f
7384 /* Given M see if it is a value that would select a field of bits
7385 within an item, but not the entire word. Return -1 if not.
7386 Otherwise, return the starting position of the field, where 0 is the
7387 low-order bit.
7389 *PLEN is set to the length of the field. */
7391 static int
7393 {
7394 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7399 /* Now shift off the low-order zero bits and see if we have a
7400 power of two minus 1. */
7408 }
7409 \f
7410 /* If X refers to a register that equals REG in value, replace these
7411 references with REG. */
7412 static rtx
7414 {
7422 {
7458 {
7462 else
7464 }
7466 /* fall through */
7473 {
7476 {
7478 {
7481 }
7483 }
7484 }
7486 {
7489 {
7492 {
7494 {
7497 }
7499 }
7500 }
7501 }
7504 }
7507 }
7509 /* Return X converted to MODE. If the value is already truncated to
7510 MODE we can just return a subreg even though in the general case we
7511 would need an explicit truncation. */
7513 static rtx
7515 {
7521 {
7522 /* Bit-cast X into an integer mode. */
7527 }
7530 }
7532 /* See if X can be simplified knowing that we will only refer to it in
7533 MODE and will only refer to those bits that are nonzero in MASK.
7534 If other bits are being computed or if masking operations are done
7535 that select a superset of the bits in MASK, they can sometimes be
7536 ignored.
7538 Return a possibly simplified expression, but always convert X to
7539 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7541 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7542 are all off in X. This is used when X will be complemented, by either
7543 NOT, NEG, or XOR. */
7545 static rtx
7548 {
7555 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7556 code below will do the wrong thing since the mode of such an
7557 expression is VOIDmode.
7559 Also do nothing if X is a CLOBBER; this can happen if X was
7560 the return value from a call to gen_lowpart. */
7564 /* We want to perform the operation is its present mode unless we know
7565 that the operation is valid in MODE, in which case we do the operation
7566 in MODE. */
7571 /* It is not valid to do a right-shift in a narrower mode
7572 than the one it came in with. */
7577 /* Truncate MASK to fit OP_MODE. */
7581 /* When we have an arithmetic operation, or a shift whose count we
7582 do not know, we need to assume that all bits up to the highest-order
7583 bit in MASK will be needed. This is how we form such a mask. */
7586 else
7590 /* Determine what bits of X are guaranteed to be (non)zero. */
7593 /* If none of the bits in X are needed, return a zero. */
7597 /* If X is a CONST_INT, return a new one. Do this here since the
7598 test below will fail. */
7600 {
7603 else
7604 {
7607 }
7608 }
7610 /* If X is narrower than MODE and we want all the bits in X's mode, just
7611 get X in the proper mode. */
7616 /* We can ignore the effect of a SUBREG if it narrows the mode or
7617 if the constant masks to zero all the bits the mode doesn't have. */
7627 /* The arithmetic simplifications here only work for scalar integer modes. */
7632 {
7634 /* If X is a (clobber (const_int)), return it since we know we are
7635 generating something that won't match. */
7648 /* Similarly for a truncate. */
7652 /* If this is an AND with a constant, convert it into an AND
7653 whose constant is the AND of that constant with MASK. If it
7654 remains an AND of MASK, delete it since it is redundant. */
7657 {
7661 /* If X is still an AND, see if it is an AND with a mask that
7662 is just some low-order bits. If so, and it is MASK, we don't
7663 need it. */
7670 /* If it remains an AND, try making another AND with the bits
7671 in the mode mask that aren't in MASK turned on. If the
7672 constant in the AND is wide enough, this might make a
7673 cheaper constant. */
7678 {
7682 rtx y;
7684 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7685 number, sign extend it. */
7695 }
7698 }
7703 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7704 low-order bits (as in an alignment operation) and FOO is already
7705 aligned to that boundary, mask C1 to that boundary as well.
7706 This may eliminate that PLUS and, later, the AND. */
7708 {
7712 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7713 number, sign extend it. */
7726 }
7728 /* ... fall through ... */
7731 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7732 most significant bit in MASK since carries from those bits will
7733 affect the bits we are interested in. */
7738 /* If X is (minus C Y) where C's least set bit is larger than any bit
7739 in the mask, then we may replace with (neg Y). */
7744 {
7748 }
7750 /* Similarly, if C contains every bit in the fuller_mask, then we may
7751 replace with (not Y). */
7755 {
7759 }
7766 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7767 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7768 operation which may be a bitfield extraction. Ensure that the
7769 constant we form is not wider than the mode of X. */
7781 {
7789 }
7791 binop:
7792 /* For most binary operations, just propagate into the operation and
7793 change the mode if we have an operation of that mode. */
7798 /* If we ended up truncating both operands, truncate the result of the
7799 operation instead. */
7802 {
7805 }
7815 /* For left shifts, do the same, but just for the first operand.
7816 However, we cannot do anything with shifts where we cannot
7817 guarantee that the counts are smaller than the size of the mode
7818 because such a count will have a different meaning in a
7819 wider mode. */
7829 /* If the shift count is a constant and we can do arithmetic in
7830 the mode of the shift, refine which bits we need. Otherwise, use the
7831 conservative form of the mask. */
7837 else
7849 /* Here we can only do something if the shift count is a constant,
7850 this shift constant is valid for the host, and we can do arithmetic
7851 in OP_MODE. */
7856 {
7860 /* Select the mask of the bits we need for the shift operand. */
7863 /* We can only change the mode of the shift if we can do arithmetic
7864 in the mode of the shift and INNER_MASK is no wider than the
7865 width of X's mode. */
7873 }
7875 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7876 shift and AND produces only copies of the sign bit (C2 is one less
7877 than a power of two), we can do this with just a shift. */
7881 /* The shift puts one of the sign bit copies in the least significant
7882 bit. */
7887 /* Number of bits left after the shift must be more than the mask
7888 needs. */
7891 /* Must be more sign bit copies than the mask needs. */
7901 /* If we are just looking for the sign bit, we don't need this shift at
7902 all, even if it has a variable count. */
7908 /* If this is a shift by a constant, get a mask that contains those bits
7909 that are not copies of the sign bit. We then have two cases: If
7910 MASK only includes those bits, this can be a logical shift, which may
7911 allow simplifications. If MASK is a single-bit field not within
7912 those bits, we are requesting a copy of the sign bit and hence can
7913 shift the sign bit to the appropriate location. */
7917 {
7920 /* If the considered data is wider than HOST_WIDE_INT, we can't
7921 represent a mask for all its bits in a single scalar.
7922 But we only care about the lower bits, so calculate these. */
7925 {
7928 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7929 is the number of bits a full-width mask would have set.
7930 We need only shift if these are fewer than nonzero can
7931 hold. If not, we must keep all bits set in nonzero. */
7936 + HOST_BITS_PER_WIDE_INT
7938 }
7939 else
7940 {
7943 }
7946 {
7951 }
7954 {
7955 x = simplify_shift_const
7961 }
7962 }
7964 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7965 even if the shift count isn't a constant. */
7970 shiftrt:
7972 /* If this is a zero- or sign-extension operation that just affects bits
7973 we don't care about, remove it. Be sure the call above returned
7974 something that is still a shift. */
7984 next_select);
7990 /* If the shift count is constant and we can do computations
7991 in the mode of X, compute where the bits we care about are.
7992 Otherwise, we can't do anything. Don't change the mode of
7993 the shift or propagate MODE into the shift, though. */
7996 {
8004 }
8008 /* If we just want the low-order bit, the NEG isn't needed since it
8009 won't change the low-order bit. */
8013 /* We need any bits less significant than the most significant bit in
8014 MASK since carries from those bits will affect the bits we are
8015 interested in. */
8020 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8021 same as the XOR case above. Ensure that the constant we form is not
8022 wider than the mode of X. */
8030 {
8039 }
8041 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8042 use the full mask inside the NOT. */
8045 unop:
8048 next_select));
8054 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8055 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8056 which is equal to STORE_FLAG_VALUE. */
8067 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8068 written in a narrower mode. We play it safe and do not do so. */
8082 }
8084 /* Ensure we return a value of the proper mode. */
8086 }
8087 \f
8088 /* Return nonzero if X is an expression that has one of two values depending on
8089 whether some other value is zero or nonzero. In that case, we return the
8090 value that is being tested, *PTRUE is set to the value if the rtx being
8091 returned has a nonzero value, and *PFALSE is set to the other alternative.
8093 If we return zero, we set *PTRUE and *PFALSE to X. */
8095 static rtx
8097 {
8103 /* If we are comparing a value against zero, we are done. */
8106 {
8110 }
8112 /* If this is a unary operation whose operand has one of two values, apply
8113 our opcode to compute those values. */
8116 {
8121 }
8123 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8124 make can't possibly match and would suppress other optimizations. */
8126 ;
8128 /* If this is a binary operation, see if either side has only one of two
8129 values. If either one does or if both do and they are conditional on
8130 the same value, compute the new true and false values. */
8132 {
8138 {
8139 /* If if_then_else_cond returned zero, then true/false are the
8140 same rtl. We must copy one of them to prevent invalid rtl
8141 sharing. */
8148 {
8153 }
8154 else
8155 {
8158 }
8161 }
8163 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8164 operands is zero when the other is nonzero, and vice-versa,
8165 and STORE_FLAG_VALUE is 1 or -1. */
8171 {
8188 {
8195 const_true_rtx);
8197 }
8198 }
8200 /* Similarly for MULT, AND and UMIN, except that for these the result
8201 is always zero. */
8205 {
8219 {
8222 }
8223 }
8224 }
8227 {
8228 /* If we have IF_THEN_ELSE already, extract the condition and
8229 canonicalize it if it is NE or EQ. */
8235 {
8238 }
8239 else
8241 }
8243 /* If X is a SUBREG, we can narrow both the true and false values
8244 if the inner expression, if there is a condition. */
8248 {
8254 {
8258 }
8259 }
8261 /* If X is a constant, this isn't special and will cause confusions
8262 if we treat it as such. Likewise if it is equivalent to a constant. */
8265 ;
8267 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8268 will be least confusing to the rest of the compiler. */
8270 {
8273 }
8275 /* If X is known to be either 0 or -1, those are the true and
8276 false values when testing X. */
8280 {
8283 }
8285 /* Likewise for 0 or a single bit. */
8289 {
8292 }
8294 /* Otherwise fail; show no condition with true and false values the same. */
8297 }
8298 \f
8299 /* Return the value of expression X given the fact that condition COND
8300 is known to be true when applied to REG as its first operand and VAL
8301 as its second. X is known to not be shared and so can be modified in
8302 place.
8304 We only handle the simplest cases, and specifically those cases that
8305 arise with IF_THEN_ELSE expressions. */
8307 static rtx
8309 {
8311 rtx temp;
8318 /* If either operand of the condition is a floating point value,
8319 then we have to avoid collapsing an EQ comparison. */
8329 /* If X is (abs REG) and we know something about REG's relationship
8330 with zero, we may be able to simplify this. */
8334 {
8343 }
8345 /* The only other cases we handle are MIN, MAX, and comparisons if the
8346 operands are the same as REG and VAL. */
8349 {
8354 {
8356 {
8364 else
8366 }
8369 {
8372 /* Do not reverse the condition when it is NE or EQ.
8373 This is because we cannot conclude anything about
8374 the value of 'SMAX (x, y)' when x is not equal to y,
8375 but we can when x equals y. */
8381 {
8392 }
8393 }
8394 }
8395 }
8397 {
8402 {
8403 /* We must simplify subreg here, before we lose track of the
8404 original inner_mode. */
8409 else
8411 }
8414 }
8415 /* We don't have to handle SIGN_EXTEND here, because even in the
8416 case of replacing something with a modeless CONST_INT, a
8417 CONST_INT is already (supposed to be) a valid sign extension for
8418 its narrower mode, which implies it's already properly
8419 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8420 story is different. */
8422 {
8427 {
8428 /* We must simplify the zero_extend here, before we lose
8429 track of the original inner_mode. */
8434 else
8436 }
8439 }
8443 {
8450 }
8453 }
8454 \f
8455 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8456 assignment as a field assignment. */
8458 static int
8460 {
8467 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8468 Note that all SUBREGs of MEM are paradoxical; otherwise they
8469 would have been rewritten. */
8482 /* We used to see if get_last_value of X and Y were the same but that's
8483 not correct. In one direction, we'll cause the assignment to have
8484 the wrong destination and in the case, we'll import a register into this
8485 insn that might have already have been dead. So fail if none of the
8486 above cases are true. */
8488 }
8489 \f
8490 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8491 Return that assignment if so.
8493 We only handle the most common cases. */
8495 static rtx
8497 {
8500 rtx assign;
8502 HOST_WIDE_INT c1;
8503 HOST_WIDE_INT pos;
8505 rtx other;
8508 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8509 a clear of a one-bit field. We will have changed it to
8510 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8511 for a SUBREG. */
8517 {
8523 }
8533 {
8540 }
8542 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8543 one-bit field. */
8547 {
8553 }
8555 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8556 SRC is an AND with all bits of that field set, then we can discard
8557 the AND. */
8562 {
8569 else
8572 /* Complete overlap. We can remove the source AND. */
8576 /* Partial overlap. We can reduce the source AND. */
8578 {
8583 }
8584 }
8586 /* The other case we handle is assignments into a constant-position
8587 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8588 a mask that has all one bits except for a group of zero bits and
8589 OTHER is known to have zeros where C1 has ones, this is such an
8590 assignment. Compute the position and length from C1. Shift OTHER
8591 to the appropriate position, force it to the required mode, and
8592 make the extraction. Check for the AND in both operands. */
8608 else
8621 /* The mode to use for the source is the mode of the assignment, or of
8622 what is inside a possible STRICT_LOW_PART. */
8626 /* Shift OTHER right POS places and make it the source, restricting it
8627 to the proper length and mode. */
8632 dest);
8639 /* If SRC is masked by an AND that does not make a difference in
8640 the value being stored, strip it. */
8651 }
8652 \f
8653 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8654 if so. */
8656 static rtx
8658 {
8662 rtx tem;
8664 /* Distributivity is not true for floating point as it can change the
8665 value. So we don't do it unless -funsafe-math-optimizations. */
8670 /* The outer operation can only be one of the following: */
8678 /* If either operand is a primitive we can't do anything, so get out
8679 fast. */
8689 /* See if the inner and outer operations distribute. */
8691 {
8696 /* These all distribute except over PLUS. */
8707 /* This is also a multiply, so it distributes over everything. */
8711 /* Non-paradoxical SUBREGs distributes over all operations,
8712 provided the inner modes and byte offsets are the same, this
8713 is an extraction of a low-order part, we don't convert an fp
8714 operation to int or vice versa, this is not a vector mode,
8715 and we would not be converting a single-word operation into a
8716 multi-word operation. The latter test is not required, but
8717 it prevents generating unneeded multi-word operations. Some
8718 of the previous tests are redundant given the latter test,
8719 but are retained because they are required for correctness.
8721 We produce the result slightly differently in this case. */
8732 /* Result might need to be truncated. Don't change mode if
8733 explicit truncation is needed. */
8734 || !TRULY_NOOP_TRUNCATION
8745 }
8747 /* Set LHS and RHS to the inner operands (A and B in the example
8748 above) and set OTHER to the common operand (C in the example).
8749 There is only one way to do this unless the inner operation is
8750 commutative. */
8762 else
8765 /* Form the new inner operation, seeing if it simplifies first. */
8768 /* There is one exception to the general way of distributing:
8769 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8771 {
8774 }
8776 /* We may be able to continuing distributing the result, so call
8777 ourselves recursively on the inner operation before forming the
8778 outer operation, which we return. */
8781 }
8783 /* See if X is of the form (* (+ A B) C), and if so convert to
8784 (+ (* A C) (* B C)) and try to simplify.
8786 Most of the time, this results in no change. However, if some of
8787 the operands are the same or inverses of each other, simplifications
8788 will result.
8790 For example, (and (ior A B) (not B)) can occur as the result of
8791 expanding a bit field assignment. When we apply the distributive
8792 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8793 which then simplifies to (and (A (not B))).
8795 Note that no checks happen on the validity of applying the inverse
8796 distributive law. This is pointless since we can do it in the
8797 few places where this routine is called.
8799 N is the index of the term that is decomposed (the arithmetic operation,
8800 i.e. (+ A B) in the first example above). !N is the index of the term that
8801 is distributed, i.e. of C in the first example above. */
8802 static rtx
8804 {
8809 /* Distributivity is not true for floating point as it can change the
8810 value. So we don't do it unless -funsafe-math-optimizations. */
8827 /* Special case (and (xor B C) (not A)), which is equivalent to
8828 (xor (ior A B) (ior A C)) */
8830 {
8833 }
8836 {
8837 /* Distribute the second term. */
8840 }
8841 else
8842 {
8843 /* Distribute the first term. */
8846 }
8856 }
8857 \f
8858 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8859 in MODE. Return an equivalent form, if different from (and VAROP
8860 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8862 static rtx
8865 {
8868 rtx orig_varop;
8876 /* Simplify VAROP knowing that we will be only looking at some of the
8877 bits in it.
8879 Note by passing in CONSTOP, we guarantee that the bits not set in
8880 CONSTOP are not significant and will never be examined. We must
8881 ensure that is the case by explicitly masking out those bits
8882 before returning. */
8885 /* If VAROP is a CLOBBER, we will fail so return it. */
8889 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8890 to VAROP and return the new constant. */
8894 /* See what bits may be nonzero in VAROP. Unlike the general case of
8895 a call to nonzero_bits, here we don't care about bits outside
8896 MODE. */
8900 /* Turn off all bits in the constant that are known to already be zero.
8901 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8902 which is tested below. */
8906 /* If we don't have any bits left, return zero. */
8910 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8911 a power of two, we can replace this with an ASHIFT. */
8916 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8917 or XOR, then try to apply the distributive law. This may eliminate
8918 operations if either branch can be simplified because of the AND.
8919 It may also make some cases more complex, but those cases probably
8920 won't match a pattern either with or without this. */
8923 return
8924 gen_lowpart
8926 apply_distributive_law
8931 constop),
8935 constop))));
8937 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8938 the AND and see if one of the operands simplifies to zero. If so, we
8939 may eliminate it. */
8943 {
8952 }
8954 /* Make a SUBREG if necessary. If we can't make it, fail. */
8959 /* If we are only masking insignificant bits, return VAROP. */
8966 /* Otherwise, return an AND. */
8968 }
8971 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8972 in MODE.
8974 Return an equivalent form, if different from X. Otherwise, return X. If
8975 X is zero, we are to always construct the equivalent form. */
8977 static rtx
8980 {
8991 }
8992 \f
8993 /* Given a REG, X, compute which bits in X can be nonzero.
8994 We don't care about bits outside of those defined in MODE.
8996 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8997 a shift, AND, or zero_extract, we can do better. */
8999 static rtx
9001 const_rtx known_x ATTRIBUTE_UNUSED,
9005 {
9006 rtx tem;
9009 /* If X is a register whose nonzero bits value is current, use it.
9010 Otherwise, if X is a register whose value we can find, use that
9011 value. Otherwise, use the previously-computed global nonzero bits
9012 for this register. */
9025 && !REGNO_REG_SET_P
9027 {
9030 }
9035 {
9036 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9037 /* If X is narrower than MODE and TEM is a non-negative
9038 constant that would appear negative in the mode of X,
9039 sign-extend it for use in reg_nonzero_bits because some
9040 machines (maybe most) will actually do the sign-extension
9041 and this is the conservative approach.
9043 ??? For 2.5, try to tighten up the MD files in this regard
9044 instead of this kludge. */
9055 #endif
9057 }
9059 {
9063 /* We don't know anything about the upper bits. */
9066 }
9069 }
9071 /* Return the number of bits at the high-order end of X that are known to
9072 be equal to the sign bit. X will be used in mode MODE; if MODE is
9073 VOIDmode, X will be used in its own mode. The returned value will always
9074 be between 1 and the number of bits in MODE. */
9076 static rtx
9078 const_rtx known_x ATTRIBUTE_UNUSED,
9079 enum machine_mode known_mode
9080 ATTRIBUTE_UNUSED,
9083 {
9084 rtx tem;
9096 && !REGNO_REG_SET_P
9098 {
9101 }
9112 }
9113 \f
9114 /* Return the number of "extended" bits there are in X, when interpreted
9115 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9116 unsigned quantities, this is the number of high-order zero bits.
9117 For signed quantities, this is the number of copies of the sign bit
9118 minus 1. In both case, this function returns the number of "spare"
9119 bits. For example, if two quantities for which this function returns
9120 at least 1 are added, the addition is known not to overflow.
9122 This function will always return 0 unless called during combine, which
9123 implies that it must be called from a define_split. */
9125 unsigned int
9127 {
9137 }
9138 \f
9139 /* This function is called from `simplify_shift_const' to merge two
9140 outer operations. Specifically, we have already found that we need
9141 to perform operation *POP0 with constant *PCONST0 at the outermost
9142 position. We would now like to also perform OP1 with constant CONST1
9143 (with *POP0 being done last).
9145 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9146 the resulting operation. *PCOMP_P is set to 1 if we would need to
9147 complement the innermost operand, otherwise it is unchanged.
9149 MODE is the mode in which the operation will be done. No bits outside
9150 the width of this mode matter. It is assumed that the width of this mode
9151 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9153 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9154 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9155 result is simply *PCONST0.
9157 If the resulting operation cannot be expressed as one operation, we
9158 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9160 static int
9161 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9162 {
9169 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9173 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9174 if OP0 is SET. */
9183 {
9185 {
9203 }
9204 }
9206 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9210 /* If the two constants aren't the same, we can't do anything. The
9211 remaining six cases can all be done. */
9215 else
9217 {
9220 /* (a & b) | b == b */
9223 /* (a ^ b) | b == a | b */
9224 {;}
9229 /* (a & b) ^ b == (~a) & b */
9232 /* (a | b) ^ b == a & ~b */
9238 /* (a | b) & b == b */
9241 /* (a ^ b) & b) == (~a) & b */
9246 }
9248 /* Check for NO-OP cases. */
9261 /* ??? Slightly redundant with the above mask, but not entirely.
9262 Moving this above means we'd have to sign-extend the mode mask
9263 for the final test. */
9268 }
9269 \f
9270 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9271 the shift in. The original shift operation CODE is performed on OP in
9272 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9273 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9274 result of the shift is subject to operation OUTER_CODE with operand
9275 OUTER_CONST. */
9277 static enum machine_mode
9281 {
9286 /* In general we can't perform in wider mode for right shift and rotate. */
9288 {
9290 /* We can still widen if the bits brought in from the left are identical
9291 to the sign bit of ORIG_MODE. */
9299 /* Similarly here but with zero bits. */
9304 /* We can also widen if the bits brought in will be masked off. This
9305 operation is performed in ORIG_MODE. */
9307 {
9313 }
9314 /* fall through */
9324 }
9325 }
9327 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9328 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9329 simplify it. Otherwise, return a simplified value.
9331 The shift is normally computed in the widest mode we find in VAROP, as
9332 long as it isn't a different number of words than RESULT_MODE. Exceptions
9333 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9335 static rtx
9338 {
9344 unsigned int mode_words
9346 /* We form (outer_op (code varop count) (outer_const)). */
9352 /* Make sure and truncate the "natural" shift on the way in. We don't
9353 want to do this inside the loop as it makes it more difficult to
9354 combine shifts. */
9358 /* If we were given an invalid count, don't do anything except exactly
9359 what was requested. */
9366 /* Unless one of the branches of the `if' in this loop does a `continue',
9367 we will `break' the loop after the `if'. */
9370 {
9371 /* If we have an operand of (clobber (const_int 0)), fail. */
9375 /* Convert ROTATERT to ROTATE. */
9377 {
9382 else
9384 }
9389 /* Handle cases where the count is greater than the size of the mode
9390 minus 1. For ASHIFT, use the size minus one as the count (this can
9391 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9392 take the count modulo the size. For other shifts, the result is
9393 zero.
9395 Since these shifts are being produced by the compiler by combining
9396 multiple operations, each of which are defined, we know what the
9397 result is supposed to be. */
9400 {
9405 else
9406 {
9407 /* We can't simply return zero because there may be an
9408 outer op. */
9412 }
9413 }
9415 /* If we discovered we had to complement VAROP, leave. Making a NOT
9416 here would cause an infinite loop. */
9420 /* An arithmetic right shift of a quantity known to be -1 or 0
9421 is a no-op. */
9425 {
9428 }
9430 /* If we are doing an arithmetic right shift and discarding all but
9431 the sign bit copies, this is equivalent to doing a shift by the
9432 bitsize minus one. Convert it into that shift because it will often
9433 allow other simplifications. */
9440 /* We simplify the tests below and elsewhere by converting
9441 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9442 `make_compound_operation' will convert it to an ASHIFTRT for
9443 those machines (such as VAX) that don't have an LSHIFTRT. */
9462 {
9469 {
9472 }
9476 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9477 minus the width of a smaller mode, we can do this with a
9478 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9484 {
9493 }
9497 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9498 the same number of words as what we've seen so far. Then store
9499 the widest mode in MODE. */
9506 {
9511 }
9515 /* Some machines use MULT instead of ASHIFT because MULT
9516 is cheaper. But it is still better on those machines to
9517 merge two shifts into one. */
9520 {
9521 varop
9527 }
9531 /* Similar, for when divides are cheaper. */
9534 {
9535 varop
9541 }
9545 /* If we are extracting just the sign bit of an arithmetic
9546 right shift, that shift is not needed. However, the sign
9547 bit of a wider mode may be different from what would be
9548 interpreted as the sign bit in a narrower mode, so, if
9549 the result is narrower, don't discard the shift. */
9554 {
9557 }
9559 /* ... fall through ... */
9564 /* Here we have two nested shifts. The result is usually the
9565 AND of a new shift with a mask. We compute the result below. */
9572 {
9576 rtx mask_rtx;
9578 /* We have one common special case. We can't do any merging if
9579 the inner code is an ASHIFTRT of a smaller mode. However, if
9580 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9581 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9582 we can convert it to
9583 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9584 This simplifies certain SIGN_EXTEND operations. */
9588 {
9589 /* C3 has the low-order C1 bits zero. */
9601 }
9603 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9604 than C1 high-order bits equal to the sign bit, we can convert
9605 this to either an ASHIFT or an ASHIFTRT depending on the
9606 two counts.
9608 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9614 {
9618 {
9621 }
9624 }
9626 /* There are some cases we can't do. If CODE is ASHIFTRT,
9627 we can only do this if FIRST_CODE is also ASHIFTRT.
9629 We can't do the case when CODE is ROTATE and FIRST_CODE is
9630 ASHIFTRT.
9632 If the mode of this shift is not the mode of the outer shift,
9633 we can't do this if either shift is a right shift or ROTATE.
9635 Finally, we can't do any of these if the mode is too wide
9636 unless the codes are the same.
9638 Handle the case where the shift codes are the same
9639 first. */
9642 {
9651 }
9662 /* To compute the mask to apply after the shift, shift the
9663 nonzero bits of the inner shift the same way the
9664 outer shift will. */
9668 mask_rtx
9672 /* Give up if we can't compute an outer operation to use. */
9680 /* If the shifts are in the same direction, we add the
9681 counts. Otherwise, we subtract them. */
9685 else
9688 /* If COUNT is positive, the new shift is usually CODE,
9689 except for the two exceptions below, in which case it is
9690 FIRST_CODE. If the count is negative, FIRST_CODE should
9691 always be used */
9701 }
9703 /* If we have (A << B << C) for any shift, we can convert this to
9704 (A << C << B). This wins if A is a constant. Only try this if
9705 B is not a constant. */
9710 {
9717 }
9724 /* Make this fit the case below. */
9732 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9733 with C the size of VAROP - 1 and the shift is logical if
9734 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9735 we have an (le X 0) operation. If we have an arithmetic shift
9736 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9737 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9745 {
9748 const0_rtx);
9754 }
9756 /* If we have (shift (logical)), move the logical to the outside
9757 to allow it to possibly combine with another logical and the
9758 shift to combine with another shift. This also canonicalizes to
9759 what a ZERO_EXTRACT looks like. Also, some machines have
9760 (and (shift)) insns. */
9763 /* We can't do this if we have (ashiftrt (xor)) and the
9764 constant has its sign bit set in shift_mode. */
9767 shift_mode))
9774 {
9777 }
9779 /* If we can't do that, try to simplify the shift in each arm of the
9780 logical expression, make a new logical expression, and apply
9781 the inverse distributive law. This also can't be done
9782 for some (ashiftrt (xor)). */
9786 shift_mode)))
9787 {
9799 }
9803 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9804 says that the sign bit can be tested, FOO has mode MODE, C is
9805 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9806 that may be nonzero. */
9817 {
9821 }
9825 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9826 than the number of bits in the mode is equivalent to A. */
9830 {
9834 }
9836 /* NEG commutes with ASHIFT since it is multiplication. Move the
9837 NEG outside to allow shifts to combine. */
9842 {
9845 }
9849 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9850 is one less than the number of bits in the mode is
9851 equivalent to (xor A 1). */
9859 {
9863 }
9865 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9866 that might be nonzero in BAR are those being shifted out and those
9867 bits are known zero in FOO, we can replace the PLUS with FOO.
9868 Similarly in the other operand order. This code occurs when
9869 we are computing the size of a variable-size array. */
9876 {
9879 }
9887 result_mode)))
9888 {
9891 }
9893 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9902 {
9905 }
9907 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9908 signbit', and attempt to change the PLUS to an XOR and move it to
9909 the outer operation as is done above in the AND/IOR/XOR case
9910 leg for shift(logical). See details in logical handling above
9911 for reasoning in doing so. */
9921 {
9924 }
9929 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9930 with C the size of VAROP - 1 and the shift is logical if
9931 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9932 we have a (gt X 0) operation. If the shift is arithmetic with
9933 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9934 we have a (neg (gt X 0)) operation. */
9943 {
9946 const0_rtx);
9952 }
9956 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9957 if the truncate does not affect the value. */
9964 {
9967 varop_inner
9970 GEN_INT
9975 }
9980 }
9983 }
9988 /* We have now finished analyzing the shift. The result should be
9989 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9990 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9991 to the result of the shift. OUTER_CONST is the relevant constant,
9992 but we must turn off all bits turned off in the shift. */
10000 /* Make a SUBREG if necessary. If we can't make it, fail. */
10005 /* If we have an outer operation and we just made a shift, it is
10006 possible that we could have simplified the shift were it not
10007 for the outer operation. So try to do the simplification
10008 recursively. */
10012 else
10018 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10019 turn off all the bits that the shift would have turned off. */
10024 /* Do the remainder of the processing in RESULT_MODE. */
10027 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10028 operation. */
10033 {
10041 {
10042 /* This means that we have determined that the result is
10043 equivalent to a constant. This should be rare. */
10046 }
10049 else
10052 }
10055 }
10057 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10058 The result of the shift is RESULT_MODE. If we cannot simplify it,
10059 return X or, if it is NULL, synthesize the expression with
10060 simplify_gen_binary. Otherwise, return a simplified value.
10062 The shift is normally computed in the widest mode we find in VAROP, as
10063 long as it isn't a different number of words than RESULT_MODE. Exceptions
10064 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10066 static rtx
10069 {
10079 }
10081 \f
10082 /* Like recog, but we receive the address of a pointer to a new pattern.
10083 We try to match the rtx that the pointer points to.
10084 If that fails, we may try to modify or replace the pattern,
10085 storing the replacement into the same pointer object.
10087 Modifications include deletion or addition of CLOBBERs.
10089 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10090 the CLOBBERs are placed.
10092 The value is the final insn code from the pattern ultimately matched,
10093 or -1. */
10095 static int
10097 {
10105 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10106 we use to indicate that something didn't match. If we find such a
10107 thing, force rejection. */
10121 {
10124 else
10127 }
10129 /* If it isn't, there is the possibility that we previously had an insn
10130 that clobbered some register as a side effect, but the combined
10131 insn doesn't need to do that. So try once more without the clobbers
10132 unless this represents an ASM insn. */
10136 {
10141 {
10144 pos++;
10145 }
10155 {
10158 else
10161 }
10162 }
10166 /* Recognize all noop sets, these will be killed by followup pass. */
10170 /* If we had any clobbers to add, make a new pattern than contains
10171 them. Then check to make sure that all of them are dead. */
10173 {
10183 else
10190 {
10195 {
10199 }
10200 }
10202 }
10208 }
10209 \f
10210 /* Like gen_lowpart_general but for use by combine. In combine it
10211 is not possible to create any new pseudoregs. However, it is
10212 safe to create invalid memory addresses, because combine will
10213 try to recognize them and all they will do is make the combine
10214 attempt fail.
10216 If for some reason this cannot do its job, an rtx
10217 (clobber (const_int 0)) is returned.
10218 An insn containing that will not be recognized. */
10220 static rtx
10222 {
10226 rtx result;
10231 /* Return identity if this is a CONST or symbolic reference. */
10238 /* We can only support MODE being wider than a word if X is a
10239 constant integer or has a mode the same size. */
10247 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10248 won't know what to do. So we will strip off the SUBREG here and
10249 process normally. */
10251 {
10254 /* For use in case we fall down into the address adjustments
10255 further below, we need to adjust the known mode and size of
10256 x; imode and isize, since we just adjusted x. */
10263 }
10271 {
10274 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10275 address. */
10279 /* If we want to refer to something bigger than the original memref,
10280 generate a paradoxical subreg instead. That will force a reload
10281 of the original memref X. */
10288 /* Adjust the address so that the address-after-the-data is
10289 unchanged. */
10294 }
10296 /* If X is a comparison operator, rewrite it in a new mode. This
10297 probably won't match, but may allow further simplifications. */
10301 /* If we couldn't simplify X any other way, just enclose it in a
10302 SUBREG. Normally, this SUBREG won't match, but some patterns may
10303 include an explicit SUBREG or we may simplify it further in combine. */
10304 else
10305 {
10307 rtx res;
10311 {
10316 }
10320 }
10322 fail:
10324 }
10325 \f
10326 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10327 comparison code that will be tested.
10329 The result is a possibly different comparison code to use. *POP0 and
10330 *POP1 may be updated.
10332 It is possible that we might detect that a comparison is either always
10333 true or always false. However, we do not perform general constant
10334 folding in combine, so this knowledge isn't useful. Such tautologies
10335 should have been detected earlier. Hence we ignore all such cases. */
10337 static enum rtx_code
10339 {
10346 /* Try a few ways of applying the same transformation to both operands. */
10348 {
10349 #ifndef WORD_REGISTER_OPERATIONS
10350 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10351 so check specially. */
10366 - (GET_MODE_BITSIZE
10368 {
10371 }
10372 #endif
10374 /* If both operands are the same constant shift, see if we can ignore the
10375 shift. We can if the shift is a rotate or if the bits shifted out of
10376 this shift are known to be zero for both inputs and if the type of
10377 comparison is compatible with the shift. */
10390 {
10403 else
10405 }
10407 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10408 SUBREGs are of the same mode, and, in both cases, the AND would
10409 be redundant if the comparison was done in the narrower mode,
10410 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10411 and the operand's possibly nonzero bits are 0xffffff01; in that case
10412 if we only care about QImode, we don't need the AND). This case
10413 occurs if the output mode of an scc insn is not SImode and
10414 STORE_FLAG_VALUE == 1 (e.g., the 386).
10416 Similarly, check for a case where the AND's are ZERO_EXTEND
10417 operations from some narrower mode even though a SUBREG is not
10418 present. */
10423 {
10441 {
10445 /* The resulting comparison is always unsigned since we masked
10446 off the original sign bit. */
10450 }
10457 {
10463 }
10467 }
10469 /* If both operands are NOT, we can strip off the outer operation
10470 and adjust the comparison code for swapped operands; similarly for
10471 NEG, except that this must be an equality comparison. */
10477 else
10479 }
10481 /* If the first operand is a constant, swap the operands and adjust the
10482 comparison code appropriately, but don't do this if the second operand
10483 is already a constant integer. */
10485 {
10488 }
10490 /* We now enter a loop during which we will try to simplify the comparison.
10491 For the most part, we only are concerned with comparisons with zero,
10492 but some things may really be comparisons with zero but not start
10493 out looking that way. */
10496 {
10503 HOST_WIDE_INT const_op;
10505 /* We only want to handle integral modes. This catches VOIDmode,
10506 CCmode, and the floating-point modes. An exception is that we
10507 can handle VOIDmode if OP0 is a COMPARE or a comparison
10508 operation. */
10515 /* Get the constant we are comparing against and turn off all bits
10516 not on in our mode. */
10522 /* If we are comparing against a constant power of two and the value
10523 being compared can only have that single bit nonzero (e.g., it was
10524 `and'ed with that bit), we can replace this with a comparison
10525 with zero. */
10532 {
10535 }
10537 /* Similarly, if we are comparing a value known to be either -1 or
10538 0 with -1, change it to the opposite comparison against zero. */
10544 {
10547 }
10549 /* Do some canonicalizations based on the comparison code. We prefer
10550 comparisons against zero and then prefer equality comparisons.
10551 If we can reduce the size of a constant, we will do that too. */
10554 {
10556 /* < C is equivalent to <= (C - 1) */
10558 {
10562 /* ... fall through to LE case below. */
10563 }
10564 else
10568 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10570 {
10574 }
10576 /* If we are doing a <= 0 comparison on a value known to have
10577 a zero sign bit, we can replace this with == 0. */
10586 /* >= C is equivalent to > (C - 1). */
10588 {
10592 /* ... fall through to GT below. */
10593 }
10594 else
10598 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10600 {
10604 }
10606 /* If we are doing a > 0 comparison on a value known to have
10607 a zero sign bit, we can replace this with != 0. */
10616 /* < C is equivalent to <= (C - 1). */
10618 {
10622 /* ... fall through ... */
10623 }
10625 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10628 {
10632 }
10633 else
10637 /* unsigned <= 0 is equivalent to == 0 */
10641 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10644 {
10647 }
10651 /* >= C is equivalent to > (C - 1). */
10653 {
10657 /* ... fall through ... */
10658 }
10660 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10663 {
10667 }
10668 else
10672 /* unsigned > 0 is equivalent to != 0 */
10676 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10679 {
10682 }
10687 }
10689 /* Compute some predicates to simplify code below. */
10696 /* If this is a sign bit comparison and we can do arithmetic in
10697 MODE, say that we will only be needing the sign bit of OP0. */
10705 /* Now try cases based on the opcode of OP0. If none of the cases
10706 does a "continue", we exit this loop immediately after the
10707 switch. */
10710 {
10712 /* If we are extracting a single bit from a variable position in
10713 a constant that has only a single bit set and are comparing it
10714 with zero, we can convert this into an equality comparison
10715 between the position and the location of the single bit. */
10716 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10717 have already reduced the shift count modulo the word size. */
10723 {
10725 {
10726 enum machine_mode new_mode
10730 else
10731 {
10734 }
10735 }
10741 /* Result is nonzero iff shift count is equal to I. */
10744 }
10746 /* ... fall through ... */
10751 {
10754 }
10758 /* If testing for equality, we can take the NOT of the constant. */
10761 {
10765 }
10767 /* If just looking at the sign bit, reverse the sense of the
10768 comparison. */
10770 {
10774 }
10778 /* If testing for equality, we can take the NEG of the constant. */
10781 {
10785 }
10787 /* The remaining cases only apply to comparisons with zero. */
10791 /* When X is ABS or is known positive,
10792 (neg X) is < 0 if and only if X != 0. */
10799 {
10803 }
10805 /* If we have NEG of something whose two high-order bits are the
10806 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10808 {
10812 }
10816 /* If we are testing equality and our count is a constant, we
10817 can perform the inverse operation on our RHS. */
10821 {
10825 }
10827 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10828 a particular bit. Convert it to an AND of a constant of that
10829 bit. This will be converted into a ZERO_EXTRACT. */
10833 {
10840 }
10842 /* Fall through. */
10845 /* ABS is ignorable inside an equality comparison with zero. */
10847 {
10850 }
10854 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10855 (compare FOO CONST) if CONST fits in FOO's mode and we
10856 are either testing inequality or have an unsigned
10857 comparison with ZERO_EXTEND or a signed comparison with
10858 SIGN_EXTEND. But don't do it if we don't have a compare
10859 insn of the given mode, since we'd have to revert it
10860 later on, and then we wouldn't know whether to sign- or
10861 zero-extend. */
10864 && ! unsigned_comparison_p
10870 {
10873 }
10877 /* Check for the case where we are comparing A - C1 with C2, that is
10879 (subreg:MODE (plus (A) (-C1))) op (C2)
10881 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10882 comparison in the wider mode. One of the following two conditions
10883 must be true in order for this to be valid:
10885 1. The mode extension results in the same bit pattern being added
10886 on both sides and the comparison is equality or unsigned. As
10887 C2 has been truncated to fit in MODE, the pattern can only be
10888 all 0s or all 1s.
10890 2. The mode extension results in the sign bit being copied on
10891 each side.
10893 The difficulty here is that we have predicates for A but not for
10894 (A - C1) so we need to check that C1 is within proper bounds so
10895 as to perturbate A as little as possible. */
10902 {
10911 /* (A - C1) zero-extends if it is positive and sign-extends
10912 if it is negative, C2 both zero- and sign-extends. */
10916 /* (A - C1) sign-extends if it is positive and 1-extends
10917 if it is negative, C2 both sign- and 1-extends. */
10924 /* (A - C1) always sign-extends, like C2. */
10928 {
10931 }
10932 }
10934 /* If the inner mode is narrower and we are extracting the low part,
10935 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10939 else
10942 /* ... fall through ... */
10951 {
10954 }
10958 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10959 this for equality comparisons due to pathological cases involving
10960 overflows. */
10964 {
10968 }
10970 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10973 {
10977 }
10981 /* We used to optimize signed comparisons against zero, but that
10982 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10983 arrive here as equality comparisons, or (GEU, LTU) are
10984 optimized away. No need to special-case them. */
10986 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10987 (eq B (minus A C)), whichever simplifies. We can only do
10988 this for equality comparisons due to pathological cases involving
10989 overflows. */
10993 {
10997 }
11002 {
11006 }
11008 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11009 of bits in X minus 1, is one iff X > 0. */
11015 {
11019 }
11023 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11024 if C is zero or B is a constant. */
11028 {
11032 }
11040 /* We can't do anything if OP0 is a condition code value, rather
11041 than an actual data value. */
11047 /* Get the two operands being compared. */
11050 else
11053 /* Check for the cases where we simply want the result of the
11054 earlier test or the opposite of that result. */
11058 && (STORE_FLAG_VALUE
11062 {
11066 else
11070 {
11075 }
11076 }
11080 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11081 iff X <= 0. */
11085 {
11089 }
11093 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11094 will be converted to a ZERO_EXTRACT later. */
11098 {
11099 op0 = simplify_and_const_int
11105 }
11107 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11108 zero and X is a comparison and C1 and C2 describe only bits set
11109 in STORE_FLAG_VALUE, we can compare with X. */
11117 {
11124 {
11127 }
11128 }
11130 /* If we are doing an equality comparison of an AND of a bit equal
11131 to the sign bit, replace this with a LT or GE comparison of
11132 the underlying value. */
11139 {
11143 }
11145 /* If this AND operation is really a ZERO_EXTEND from a narrower
11146 mode, the constant fits within that mode, and this is either an
11147 equality or unsigned comparison, try to do this comparison in
11148 the narrower mode.
11150 Note that in:
11152 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11153 -> (ne:DI (reg:SI 4) (const_int 0))
11155 unless TRULY_NOOP_TRUNCATION allows it or the register is
11156 known to hold a value of the required mode the
11157 transformation is invalid. */
11169 {
11172 }
11174 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11175 fits in both M1 and M2 and the SUBREG is either paradoxical
11176 or represents the low part, permute the SUBREG and the AND
11177 and try again. */
11179 {
11182 /* Require an integral mode, to avoid creating something like
11183 (AND:SF ...). */
11185 /* It is unsafe to commute the AND into the SUBREG if the
11186 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11187 not defined. As originally written the upper bits
11188 have a defined value due to the AND operation.
11189 However, if we commute the AND inside the SUBREG then
11190 they no longer have defined values and the meaning of
11191 the code has been changed. */
11193 #ifdef WORD_REGISTER_OPERATIONS
11196 #endif
11206 {
11212 }
11213 }
11215 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11219 {
11220 op0 = simplify_and_const_int
11224 }
11226 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11227 (eq (and (lshiftrt X) 1) 0).
11228 Also handle the case where (not X) is expressed using xor. */
11232 {
11243 {
11244 op0 = simplify_and_const_int
11250 }
11251 }
11255 /* If we have (compare (ashift FOO N) (const_int C)) and
11256 the high order N bits of FOO (N+1 if an inequality comparison)
11257 are known to be zero, we can do this by comparing FOO with C
11258 shifted right N bits so long as the low-order N bits of C are
11259 zero. */
11264 && ((const_op
11270 {
11271 /* We must perform a logical shift, not an arithmetic one,
11272 as we want the top N bits of C to be zero. */
11279 }
11281 /* If we are doing a sign bit comparison, it means we are testing
11282 a particular bit. Convert it to the appropriate AND. */
11285 {
11292 }
11294 /* If this an equality comparison with zero and we are shifting
11295 the low bit to the sign bit, we can convert this to an AND of the
11296 low-order bit. */
11301 {
11305 }
11309 /* If this is an equality comparison with zero, we can do this
11310 as a logical shift, which might be much simpler. */
11313 {
11318 }
11320 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11321 do the comparison in a narrower mode. */
11331 {
11334 }
11336 /* Likewise if OP0 is a PLUS of a sign extension with a
11337 constant, which is usually represented with the PLUS
11338 between the shifts. */
11350 {
11358 new_const);
11360 }
11362 /* ... fall through ... */
11364 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11365 the low order N bits of FOO are known to be zero, we can do this
11366 by comparing FOO with C shifted left N bits so long as no
11367 overflow occurs. */
11380 {
11381 /* If the shift was logical, then we must make the condition
11382 unsigned. */
11390 }
11392 /* If we are using this shift to extract just the sign bit, we
11393 can replace this with an LT or GE comparison. */
11399 {
11403 }
11408 }
11411 }
11413 /* Now make any compound operations involved in this comparison. Then,
11414 check for an outmost SUBREG on OP0 that is not doing anything or is
11415 paradoxical. The latter transformation must only be performed when
11416 it is known that the "extra" bits will be the same in op0 and op1 or
11417 that they don't matter. There are three cases to consider:
11419 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11420 care bits and we can assume they have any convenient value. So
11421 making the transformation is safe.
11423 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11424 In this case the upper bits of op0 are undefined. We should not make
11425 the simplification in that case as we do not know the contents of
11426 those bits.
11428 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11429 UNKNOWN. In that case we know those bits are zeros or ones. We must
11430 also be sure that they are the same as the upper bits of op1.
11432 We can never remove a SUBREG for a non-equality comparison because
11433 the sign bit is in a different place in the underlying object. */
11442 {
11445 {
11446 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11447 implemented. */
11449 {
11452 }
11453 }
11459 {
11465 }
11466 }
11468 /* We now do the opposite procedure: Some machines don't have compare
11469 insns in all modes. If OP0's mode is an integer mode smaller than a
11470 word and we can't do a compare in that mode, see if there is a larger
11471 mode for which we can do the compare. There are a number of cases in
11472 which we can use the wider mode. */
11483 {
11486 /* If this is a test for negative, we can make an explicit
11487 test of the sign bit. Test this first so we can use
11488 a paradoxical subreg to extend OP0. */
11492 {
11500 }
11502 /* If the only nonzero bits in OP0 and OP1 are those in the
11503 narrower mode and this is an equality or unsigned comparison,
11504 we can use the wider mode. Similarly for sign-extended
11505 values, in which case it is true for all comparisons. */
11522 {
11523 /* If OP0 is an AND and we don't have an AND in MODE either,
11524 make a new AND in the proper mode. */
11532 else
11533 {
11535 {
11538 }
11539 else
11540 {
11543 }
11545 }
11546 }
11547 }
11549 #ifdef CANONICALIZE_COMPARISON
11550 /* If this machine only supports a subset of valid comparisons, see if we
11551 can convert an unsupported one into a supported one. */
11553 #endif
11559 }
11560 \f
11561 /* Utility function for record_value_for_reg. Count number of
11562 rtxs in X. */
11563 static int
11565 {
11572 {
11592 }
11603 }
11604 \f
11605 /* Utility function for following routine. Called when X is part of a value
11606 being stored into last_set_value. Sets last_set_table_tick
11607 for each register mentioned. Similar to mention_regs in cse.c */
11609 static void
11611 {
11617 {
11623 {
11626 }
11629 }
11633 {
11634 /* Check for identical subexpressions. If x contains
11635 identical subexpression we only have to traverse one of
11636 them. */
11638 {
11639 /* Note that at this point x1 has already been
11640 processed. */
11644 /* If x0 and x1 are identical then there is no need to
11645 process x0. */
11649 /* If x0 is identical to a subexpression of x1 then while
11650 processing x1, x0 has already been processed. Thus we
11651 are done with x. */
11656 /* If x1 is identical to a subexpression of x0 then we
11657 still have to process the rest of x0. */
11660 {
11663 }
11664 }
11667 }
11671 }
11673 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11674 are saying that the register is clobbered and we no longer know its
11675 value. If INSN is zero, don't update reg_stat[].last_set; this is
11676 only permitted with VALUE also zero and is used to invalidate the
11677 register. */
11679 static void
11681 {
11687 /* If VALUE contains REG and we have a previous value for REG, substitute
11688 the previous value. */
11690 {
11691 rtx tem;
11693 /* Set things up so get_last_value is allowed to see anything set up to
11694 our insn. */
11698 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11699 it isn't going to be useful and will take a lot of time to process,
11700 so just use the CLOBBER. */
11703 {
11709 {
11710 /* If there are two or more occurrences of REG in VALUE,
11711 prevent the value from growing too much. */
11714 }
11717 }
11718 }
11720 /* For each register modified, show we don't know its value, that
11721 we don't know about its bitwise content, that its value has been
11722 updated, and that we don't know the location of the death of the
11723 register. */
11725 {
11737 }
11739 /* Mark registers that are being referenced in this value. */
11743 /* Now update the status of each register being set.
11744 If someone is using this register in this block, set this register
11745 to invalid since we will get confused between the two lives in this
11746 basic block. This makes using this register always invalid. In cse, we
11747 scan the table to invalidate all entries using this register, but this
11748 is too much work for us. */
11751 {
11757 else
11759 }
11761 /* The value being assigned might refer to X (like in "x++;"). In that
11762 case, we must replace it with (clobber (const_int 0)) to prevent
11763 infinite loops. */
11766 {
11770 }
11772 /* For the main register being modified, update the value, the mode, the
11773 nonzero bits, and the number of sign bit copies. */
11778 {
11786 rsp->last_set_sign_bit_copies
11788 }
11789 }
11791 /* Called via note_stores from record_dead_and_set_regs to handle one
11792 SET or CLOBBER in an insn. DATA is the instruction in which the
11793 set is occurring. */
11795 static void
11797 {
11804 {
11808 }
11811 {
11812 /* If we are setting the whole register, we know its value. Otherwise
11813 show that we don't know the value. We can handle SUBREG in
11814 some cases. */
11825 else
11827 }
11829 /* Ignore pushes, they clobber nothing. */
11832 }
11834 /* Update the records of when each REG was most recently set or killed
11835 for the things done by INSN. This is the last thing done in processing
11836 INSN in the combiner loop.
11838 We update reg_stat[], in particular fields last_set, last_set_value,
11839 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11840 last_death, and also the similar information mem_last_set (which insn
11841 most recently modified memory) and last_call_luid (which insn was the
11842 most recent subroutine call). */
11844 static void
11846 {
11847 rtx link;
11851 {
11854 {
11859 {
11864 }
11865 }
11868 }
11871 {
11874 {
11886 }
11890 /* We can't combine into a call pattern. Remember, though, that
11891 the return value register is set at this LUID. We could
11892 still replace a register with the return value from the
11893 wrong subroutine call! */
11895 }
11896 else
11898 }
11900 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11901 register present in the SUBREG, so for each such SUBREG go back and
11902 adjust nonzero and sign bit information of the registers that are
11903 known to have some zero/sign bits set.
11905 This is needed because when combine blows the SUBREGs away, the
11906 information on zero/sign bits is lost and further combines can be
11907 missed because of that. */
11909 static void
11911 {
11920 {
11929 {
11932 }
11936 {
11939 }
11942 {
11945 }
11946 else
11948 }
11949 }
11951 /* Check if X, a register, is known to contain a value already
11952 truncated to MODE. In this case we can use a subreg to refer to
11953 the truncated value even though in the generic case we would need
11954 an explicit truncation. */
11956 static bool
11958 {
11971 }
11973 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11974 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11975 might be able to turn a truncate into a subreg using this information.
11976 Return -1 if traversing *P is complete or 0 otherwise. */
11978 static int
11980 {
11986 {
11998 }
11999 /* ??? For hard-regs we now record everything. We might be able to
12000 optimize this using last_set_mode. */
12003 else
12011 {
12014 }
12017 }
12019 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12020 the modes they are used in. This can help truning TRUNCATEs into
12021 SUBREGs. */
12023 static void
12025 {
12027 }
12029 /* Scan X for promoted SUBREGs. For each one found,
12030 note what it implies to the registers used in it. */
12032 static void
12034 {
12039 else
12040 {
12046 {
12056 }
12057 }
12058 }
12059 \f
12060 /* Verify that all the registers and memory references mentioned in *LOC are
12061 still valid. *LOC was part of a value set in INSN when label_tick was
12062 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12063 the invalid references with (clobber (const_int 0)) and return 1. This
12064 replacement is useful because we often can get useful information about
12065 the form of a value (e.g., if it was produced by a shift that always
12066 produces -1 or 0) even though we don't know exactly what registers it
12067 was produced from. */
12069 static int
12071 {
12078 {
12084 {
12087 /* If this is a pseudo-register that was only set once and not
12088 live at the beginning of the function, it is always valid. */
12091 && (!REGNO_REG_SET_P
12094 {
12098 }
12099 }
12102 }
12103 /* If this is a memory reference, make sure that there were no stores after
12104 it that might have clobbered the value. We don't have alias info, so we
12105 assume any store invalidates it. Moreover, we only have local UIDs, so
12106 we also assume that there were stores in the intervening basic blocks. */
12109 {
12113 }
12116 {
12118 {
12119 /* Check for identical subexpressions. If x contains
12120 identical subexpression we only have to traverse one of
12121 them. */
12123 {
12124 /* Note that at this point x0 has already been checked
12125 and found valid. */
12129 /* If x0 and x1 are identical then x is also valid. */
12133 /* If x1 is identical to a subexpression of x0 then
12134 while checking x0, x1 has already been checked. Thus
12135 it is valid and so as x. */
12140 /* If x0 is identical to a subexpression of x1 then x is
12141 valid iff the rest of x1 is valid. */
12144 return
12148 }
12153 }
12159 }
12161 /* If we haven't found a reason for it to be invalid, it is valid. */
12163 }
12165 /* Get the last value assigned to X, if known. Some registers
12166 in the value may be replaced with (clobber (const_int 0)) if their value
12167 is known longer known reliably. */
12169 static rtx
12171 {
12173 rtx value;
12176 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12177 then convert it to the desired mode. If this is a paradoxical SUBREG,
12178 we cannot predict what values the "extra" bits might have. */
12193 /* If we don't have a value, or if it isn't for this basic block and
12194 it's either a hard register, set more than once, or it's a live
12195 at the beginning of the function, return 0.
12197 Because if it's not live at the beginning of the function then the reg
12198 is always set before being used (is never used without being set).
12199 And, if it's set only once, and it's always set before use, then all
12200 uses must have the same last value, even if it's not from this basic
12201 block. */
12207 || REGNO_REG_SET_P
12211 /* If the value was set in a later insn than the ones we are processing,
12212 we can't use it even if the register was only set once. */
12217 /* If the value has all its registers valid, return it. */
12221 /* Otherwise, make a copy and replace any invalid register with
12222 (clobber (const_int 0)). If that fails for some reason, return 0. */
12229 }
12230 \f
12231 /* Return nonzero if expression X refers to a REG or to memory
12232 that is set in an instruction more recent than FROM_LUID. */
12234 static int
12236 {
12242 {
12246 #ifdef PUSH_ROUNDING
12247 /* Don't allow uses of the stack pointer to be moved,
12248 because we don't know whether the move crosses a push insn. */
12251 #endif
12253 {
12259 }
12261 }
12269 {
12271 {
12276 }
12280 }
12282 }
12283 \f
12284 /* Define three variables used for communication between the following
12285 routines. */
12290 /* Function called via note_stores from reg_dead_at_p.
12292 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12293 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12295 static void
12297 {
12307 }
12309 /* Return nonzero if REG is known to be dead at INSN.
12311 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12312 referencing REG, it is dead. If we hit a SET referencing REG, it is
12313 live. Otherwise, see if it is live or dead at the start of the basic
12314 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12315 must be assumed to be always live. */
12317 static int
12319 {
12320 basic_block block;
12323 /* Set variables for reg_dead_at_p_1. */
12329 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12330 we allow the machine description to decide whether use-and-clobber
12331 patterns are OK. */
12333 {
12337 }
12339 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12340 beginning of basic block. */
12343 {
12345 {
12352 }
12358 }
12360 /* Look at live-in sets for the basic block that we were in. */
12366 }
12367 \f
12368 /* Note hard registers in X that are used. */
12370 static void
12372 {
12378 {
12389 #ifdef HAVE_cc0
12390 /* CC0 must die in the insn after it is set, so we don't need to take
12391 special note of it here. */
12393 #endif
12397 /* If we are clobbering a MEM, mark any hard registers inside the
12398 address as used. */
12405 /* A hard reg in a wide mode may really be multiple registers.
12406 If so, mark all of them just like the first. */
12408 {
12409 /* None of this applies to the stack, frame or arg pointers. */
12411 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12413 #endif
12414 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12416 #endif
12421 }
12425 {
12426 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12427 the address. */
12439 }
12444 }
12446 /* Recursively scan the operands of this expression. */
12448 {
12452 {
12456 {
12461 }
12462 }
12463 }
12464 }
12465 \f
12466 /* Remove register number REGNO from the dead registers list of INSN.
12468 Return the note used to record the death, if there was one. */
12470 rtx
12472 {
12479 }
12481 /* For each register (hardware or pseudo) used within expression X, if its
12482 death is in an instruction with luid between FROM_LUID (inclusive) and
12483 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12484 list headed by PNOTES.
12486 That said, don't move registers killed by maybe_kill_insn.
12488 This is done when X is being merged by combination into TO_INSN. These
12489 notes will then be distributed as needed. */
12491 static void
12494 {
12500 {
12504 /* Don't move the register if it gets killed in between from and to. */
12513 {
12516 /* It is possible for the call above to return 0. This can occur
12517 when last_death points to I2 or I1 that we combined with.
12518 In that case make a new note.
12520 We must also check for the case where X is a hard register
12521 and NOTE is a death note for a range of hard registers
12522 including X. In that case, we must put REG_DEAD notes for
12523 the remaining registers in place of NOTE. */
12528 {
12537 }
12539 /* If we didn't find any note, or if we found a REG_DEAD note that
12540 covers only part of the given reg, and we have a multi-reg hard
12541 register, then to be safe we must check for REG_DEAD notes
12542 for each register other than the first. They could have
12543 their own REG_DEAD notes lying around. */
12550 {
12557 else
12563 }
12566 {
12569 }
12570 else
12572 }
12575 }
12578 {
12583 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12584 that accesses one word of a multi-word item, some
12585 piece of everything register in the expression is used by
12586 this insn, so remove any old death. */
12587 /* ??? So why do we test for equality of the sizes? */
12596 {
12599 }
12601 /* If this is some other SUBREG, we know it replaces the entire
12602 value, so use that as the destination. */
12606 /* If this is a MEM, adjust deaths of anything used in the address.
12607 For a REG (the only other possibility), the entire value is
12608 being replaced so the old value is not used in this insn. */
12614 }
12623 {
12625 {
12630 }
12633 }
12634 }
12635 \f
12636 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12637 pattern of an insn. X must be a REG. */
12639 static int
12641 {
12645 {
12647 rtx target;
12654 else
12671 }
12679 }
12681 /* Return the next insn after INSN that is neither a NOTE nor a
12682 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12684 static rtx
12686 {
12688 {
12697 }
12700 }
12703 \f
12704 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12705 as appropriate. I3 and I2 are the insns resulting from the combination
12706 insns including FROM (I2 may be zero).
12708 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12709 not need REG_DEAD notes because they are being substituted for. This
12710 saves searching in the most common cases.
12712 Each note in the list is either ignored or placed on some insns, depending
12713 on the type of note. */
12715 static void
12717 rtx elim_i1)
12718 {
12720 rtx tem;
12723 {
12728 {
12731 /* Doesn't matter much where we put this, as long as it's somewhere.
12732 It is preferable to keep these notes on branches, which is most
12733 likely to be i3. */
12738 /* Just get rid of this note, as it is unused later anyway. */
12744 else
12745 {
12748 }
12752 /* These notes must remain with the call or trapping instruction. */
12757 else
12758 {
12764 /* ??? Otherwise assume we've combined things such that we
12765 can now prove that the instructions can't trap. Drop the
12766 note in this case. */
12767 }
12772 /* These notes must remain with the call. It should not be
12773 possible for both I2 and I3 to be a call. */
12776 else
12777 {
12780 }
12784 /* Any clobbers for i3 may still exist, and so we must process
12785 REG_UNUSED notes from that insn.
12787 Any clobbers from i2 or i1 can only exist if they were added by
12788 recog_for_combine. In that case, recog_for_combine created the
12789 necessary REG_UNUSED notes. Trying to keep any original
12790 REG_UNUSED notes from these insns can cause incorrect output
12791 if it is for the same register as the original i3 dest.
12792 In that case, we will notice that the register is set in i3,
12793 and then add a REG_UNUSED note for the destination of i3, which
12794 is wrong. However, it is possible to have REG_UNUSED notes from
12795 i2 or i1 for register which were both used and clobbered, so
12796 we keep notes from i2 or i1 if they will turn into REG_DEAD
12797 notes. */
12799 /* If this register is set or clobbered in I3, put the note there
12800 unless there is one already. */
12802 {
12810 }
12811 /* Otherwise, if this register is used by I3, then this register
12812 now dies here, so we must put a REG_DEAD note here unless there
12813 is one already. */
12819 {
12822 }
12828 /* These notes say something about results of an insn. We can
12829 only support them if they used to be on I3 in which case they
12830 remain on I3. Otherwise they are ignored.
12832 If the note refers to an expression that is not a constant, we
12833 must also ignore the note since we cannot tell whether the
12834 equivalence is still true. It might be possible to do
12835 slightly better than this (we only have a problem if I2DEST
12836 or I1DEST is present in the expression), but it doesn't
12837 seem worth the trouble. */
12845 /* These notes say something about how a register is used. They must
12846 be present on any use of the register in I2 or I3. */
12851 {
12854 else
12856 }
12861 /* This can show up in several ways -- either directly in the
12862 pattern, or hidden off in the constant pool with (or without?)
12863 a REG_EQUAL note. */
12864 /* ??? Ignore the without-reg_equal-note problem for now. */
12876 {
12879 else
12881 }
12883 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12884 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12885 there. */
12890 {
12897 }
12903 {
12911 }
12915 /* This note says something about the value of a register prior
12916 to the execution of an insn. It is too much trouble to see
12917 if the note is still correct in all situations. It is better
12918 to simply delete it. */
12922 /* If we replaced the right hand side of FROM_INSN with a
12923 REG_EQUAL note, the original use of the dying register
12924 will not have been combined into I3 and I2. In such cases,
12925 FROM_INSN is guaranteed to be the first of the combined
12926 instructions, so we simply need to search back before
12927 FROM_INSN for the previous use or set of this register,
12928 then alter the notes there appropriately.
12930 If the register is used as an input in I3, it dies there.
12931 Similarly for I2, if it is nonzero and adjacent to I3.
12933 If the register is not used as an input in either I3 or I2
12934 and it is not one of the registers we were supposed to eliminate,
12935 there are two possibilities. We might have a non-adjacent I2
12936 or we might have somehow eliminated an additional register
12937 from a computation. For example, we might have had A & B where
12938 we discover that B will always be zero. In this case we will
12939 eliminate the reference to A.
12941 In both cases, we must search to see if we can find a previous
12942 use of A and put the death note there. */
12948 else
12949 {
12960 && !(i2mod
12962 i2mod_old_rhs)))
12966 }
12969 {
12973 {
12975 {
12979 }
12981 /* If the register is being set at TEM, see if that is all
12982 TEM is doing. If so, delete TEM. Otherwise, make this
12983 into a REG_UNUSED note instead. Don't delete sets to
12984 global register vars. */
12988 {
12991 #ifdef HAVE_cc0
12993 #endif
13001 ;
13003 /* Verify that it was the set, and not a clobber that
13004 modified the register.
13006 CC0 targets must be careful to maintain setter/user
13007 pairs. If we cannot delete the setter due to side
13008 effects, mark the user with an UNUSED note instead
13009 of deleting it. */
13013 #ifdef HAVE_cc0
13017 #endif
13018 )
13019 {
13020 /* Move the notes and links of TEM elsewhere.
13021 This might delete other dead insns recursively.
13022 First set the pattern to something that won't use
13023 any register. */
13037 #ifdef HAVE_cc0
13038 /* Delete the setter too. */
13040 {
13053 }
13054 #endif
13055 }
13056 else
13057 {
13060 /* If there isn't already a REG_UNUSED note, put one
13061 here. Do not place a REG_DEAD note, even if
13062 the register is also used here; that would not
13063 match the algorithm used in lifetime analysis
13064 and can cause the consistency check in the
13065 scheduler to fail. */
13070 }
13071 }
13075 {
13078 /* If we are doing a 3->2 combination, and we have a
13079 register which formerly died in i3 and was not used
13080 by i2, which now no longer dies in i3 and is used in
13081 i2 but does not die in i2, and place is between i2
13082 and i3, then we may need to move a link from place to
13083 i2. */
13085 && from_insn
13088 {
13092 }
13094 }
13098 }
13100 }
13102 /* If the register is set or already dead at PLACE, we needn't do
13103 anything with this note if it is still a REG_DEAD note.
13104 We check here if it is set at all, not if is it totally replaced,
13105 which is what `dead_or_set_p' checks, so also check for it being
13106 set partially. */
13109 {
13115 {
13116 /* Unless the register previously died in PLACE, clear
13117 last_death. [I no longer understand why this is
13118 being done.] */
13122 }
13123 else
13126 /* If this is a death note for a hard reg that is occupying
13127 multiple registers, ensure that we are still using all
13128 parts of the object. If we find a piece of the object
13129 that is unused, we must arrange for an appropriate REG_DEAD
13130 note to be added for it. However, we can't just emit a USE
13131 and tag the note to it, since the register might actually
13132 be dead; so we recourse, and the recursive call then finds
13133 the previous insn that used this register. */
13137 {
13149 {
13150 /* Put only REG_DEAD notes for pieces that are
13151 not already dead or set. */
13155 {
13162 {
13164 NULL_RTX);
13168 }
13174 {
13176 {
13180 }
13184 {
13187 }
13188 }
13190 }
13193 }
13194 }
13195 }
13199 /* Any other notes should not be present at this point in the
13200 compilation. */
13202 }
13205 {
13208 }
13212 }
13213 }
13214 \f
13215 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13216 I3, I2, and I1 to new locations. This is also called to add a link
13217 pointing at I3 when I3's destination is changed. */
13219 static void
13221 {
13225 {
13227 rtx insn;
13232 /* If the insn that this link points to is a NOTE or isn't a single
13233 set, ignore it. In the latter case, it isn't clear what we
13234 can do other than ignore the link, since we can't tell which
13235 register it was for. Such links wouldn't be used by combine
13236 anyway.
13238 It is not possible for the destination of the target of the link to
13239 have been changed by combine. The only potential of this is if we
13240 replace I3, I2, and I1 by I3 and I2. But in that case the
13241 destination of I2 also remains unchanged. */
13252 /* A LOG_LINK is defined as being placed on the first insn that uses
13253 a register and points to the insn that sets the register. Start
13254 searching at the next insn after the target of the link and stop
13255 when we reach a set of the register or the end of the basic block.
13257 Note that this correctly handles the link that used to point from
13258 I3 to I2. Also note that not much searching is typically done here
13259 since most links don't point very far away. */
13268 {
13272 }
13275 {
13278 }
13282 /* If we found a place to put the link, place it there unless there
13283 is already a link to the same insn as LINK at that point. */
13286 {
13287 rtx link2;
13294 {
13298 /* Set added_links_insn to the earliest insn we added a
13299 link to. */
13303 }
13304 }
13305 }
13306 }
13307 \f
13308 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13309 Check whether the expression pointer to by LOC is a register or
13310 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13311 Otherwise return zero. */
13313 static int
13315 {
13323 }
13325 /* Check for any register or memory mentioned in EQUIV that is not
13326 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13327 of EXPR where some registers may have been replaced by constants. */
13329 static bool
13331 {
13333 }
13334 \f
13335 void
13337 {
13338 fprintf
13340 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13342 }
13344 void
13346 {
13347 fprintf
13349 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13351 }
13352 \f
13353 static bool
13355 {
13357 }
13359 /* Try combining insns through substitution. */
13360 static unsigned int
13362 {
13371 rebuild_jump_labels_after_combine
13374 /* Combining insns may have turned an indirect jump into a
13375 direct jump. Rebuild the JUMP_LABEL fields of jumping
13376 instructions. */
13378 {
13383 }
13387 }
13390 {
13391 {
13392 RTL_PASS,
13404 TODO_dump_func |
13407 }
13408 };