1 ;; Predicate definitions for NEC V850.
2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a register or 0.
22 (define_predicate "reg_or_0_operand"
23 (match_code "reg,subreg,const_int,const_double")
25 if (GET_CODE (op) == CONST_INT)
26 return INTVAL (op) == 0;
28 else if (GET_CODE (op) == CONST_DOUBLE)
29 return CONST_DOUBLE_OK_FOR_G (op);
32 return register_operand (op, mode);
35 ;; Return true if OP is either a register or a signed five bit
38 (define_predicate "reg_or_int5_operand"
39 (match_code "reg,subreg,const_int")
41 if (GET_CODE (op) == CONST_INT)
42 return CONST_OK_FOR_J (INTVAL (op));
45 return register_operand (op, mode);
48 ;; Return true if OP is either a register or a signed nine bit
51 (define_predicate "reg_or_int9_operand"
52 (match_code "reg,subreg,const_int")
54 if (GET_CODE (op) == CONST_INT)
55 return CONST_OK_FOR_O (INTVAL (op));
57 return register_operand (op, mode);
60 ;; Return true if OP is either a register or a const integer.
62 (define_predicate "reg_or_const_operand"
63 (match_code "reg,const_int")
65 if (GET_CODE (op) == CONST_INT)
68 return register_operand (op, mode);
71 ;; Return true if OP is a even number register.
73 (define_predicate "even_reg_operand"
76 return (GET_CODE (op) == REG
77 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
78 || ((REGNO (op) > 0) && (REGNO (op) < 32)
79 && ((REGNO (op) & 1)==0))));
82 ;; Return true if OP is a valid call operand.
84 (define_predicate "call_address_operand"
85 (match_code "reg,symbol_ref")
87 /* Only registers are valid call operands if TARGET_LONG_CALLS. */
88 if (TARGET_LONG_CALLS)
89 return GET_CODE (op) == REG;
90 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
93 ;; Return true if OP is a valid source operand for SImode move.
95 (define_predicate "movsi_source_operand"
96 (match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
98 /* Some constants, as well as symbolic operands
99 must be done with HIGH & LO_SUM patterns. */
101 && GET_CODE (op) != HIGH
102 && !(GET_CODE (op) == CONST_INT
103 && (CONST_OK_FOR_J (INTVAL (op))
104 || CONST_OK_FOR_K (INTVAL (op))
105 || CONST_OK_FOR_L (INTVAL (op)))))
106 return special_symbolref_operand (op, mode);
108 return general_operand (op, mode);
111 ;; Return true if OP is a valid operand for 23 bit displacement
114 (define_predicate "disp23_operand"
115 (match_code "const_int")
117 if (GET_CODE (op) == CONST_INT
118 && ((unsigned)(INTVAL (op)) >= 0x8000)
119 && ((unsigned)(INTVAL (op)) < 0x400000))
125 ;; Return true if OP is a symbol ref with 16-bit signed value.
127 (define_predicate "special_symbolref_operand"
128 (match_code "symbol_ref")
130 if (GET_CODE (op) == CONST
131 && GET_CODE (XEXP (op, 0)) == PLUS
132 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
133 && CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))))
134 op = XEXP (XEXP (op, 0), 0);
136 if (GET_CODE (op) == SYMBOL_REF)
137 return (SYMBOL_REF_FLAGS (op)
138 & (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
143 ;; Return true if OP is a valid operand for bit related operations
144 ;; containing only single 1 in its binary representation.
146 (define_predicate "power_of_two_operand"
147 (match_code "const_int")
149 if (GET_CODE (op) != CONST_INT)
152 if (exact_log2 (INTVAL (op)) == -1)
157 ;; Return nonzero if the given RTX is suitable for collapsing into a
158 ;; jump to a function prologue.
160 (define_predicate "pattern_is_ok_for_prologue"
161 (match_code "parallel")
163 int count = XVECLEN (op, 0);
167 /* If there are no registers to save then the function prologue
169 if (count <= (TARGET_LONG_CALLS ? 3 : 2))
172 /* The pattern matching has already established that we are adjusting the
173 stack and pushing at least one register. We must now check that the
174 remaining entries in the vector to make sure that they are also register
175 pushes, except for the last entry which should be a CLOBBER of r10.
177 The test below performs the C equivalent of this machine description
180 (set (mem:SI (plus:SI (reg:SI 3)
181 (match_operand:SI 2 "immediate_operand" "i")))
182 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
186 for (i = 2; i < count - (TARGET_LONG_CALLS ? 2: 1); i++)
192 vector_element = XVECEXP (op, 0, i);
194 if (GET_CODE (vector_element) != SET)
197 dest = SET_DEST (vector_element);
198 src = SET_SRC (vector_element);
200 if (GET_CODE (dest) != MEM
201 || GET_MODE (dest) != SImode
202 || GET_CODE (src) != REG
203 || GET_MODE (src) != SImode
204 || ! register_is_ok_for_epilogue (src, SImode))
207 plus = XEXP (dest, 0);
209 if ( GET_CODE (plus) != PLUS
210 || GET_CODE (XEXP (plus, 0)) != REG
211 || GET_MODE (XEXP (plus, 0)) != SImode
212 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
213 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
216 /* If the register is being pushed somewhere other than the stack
217 space just acquired by the first operand then abandon this quest.
218 Note: the test is <= because both values are negative. */
219 if (INTVAL (XEXP (plus, 1))
220 <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
226 /* Make sure that the last entries in the vector are clobbers. */
227 vector_element = XVECEXP (op, 0, i++);
229 if (GET_CODE (vector_element) != CLOBBER
230 || GET_CODE (XEXP (vector_element, 0)) != REG
231 || REGNO (XEXP (vector_element, 0)) != 10)
234 if (TARGET_LONG_CALLS)
236 vector_element = XVECEXP (op, 0, i++);
238 if (GET_CODE (vector_element) != CLOBBER
239 || GET_CODE (XEXP (vector_element, 0)) != REG
240 || REGNO (XEXP (vector_element, 0)) != 11)
247 ;; Return nonzero if the given RTX is suitable for collapsing into
248 ;; jump to a function epilogue.
250 (define_predicate "pattern_is_ok_for_epilogue"
251 (match_code "parallel")
253 int count = XVECLEN (op, 0);
256 /* If there are no registers to restore then the function epilogue
261 /* The pattern matching has already established that we are performing a
262 function epilogue and that we are popping at least one register. We must
263 now check the remaining entries in the vector to make sure that they are
264 also register pops. There is no good reason why there should ever be
265 anything else in this vector, but being paranoid always helps...
267 The test below performs the C equivalent of this machine description
270 (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
271 (mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
274 for (i = 2; i < count; i++)
276 rtx vector_element = XVECEXP (op, 0, i);
281 if (GET_CODE (vector_element) != SET)
284 dest = SET_DEST (vector_element);
285 src = SET_SRC (vector_element);
287 if (GET_CODE (dest) != REG
288 || GET_MODE (dest) != SImode
289 || ! register_is_ok_for_epilogue (dest, SImode)
290 || GET_CODE (src) != MEM
291 || GET_MODE (src) != SImode)
294 plus = XEXP (src, 0);
296 if (GET_CODE (plus) != PLUS
297 || GET_CODE (XEXP (plus, 0)) != REG
298 || GET_MODE (XEXP (plus, 0)) != SImode
299 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
300 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
307 ;; Return true if the given RTX is a register which can be restored by
308 ;; a function epilogue.
310 (define_predicate "register_is_ok_for_epilogue"
313 /* The save/restore routines can only cope with registers 20 - 31. */
314 return ((GET_CODE (op) == REG)
315 && (((REGNO (op) >= 20) && REGNO (op) <= 31)));
318 ;; Return nonzero if the given RTX is suitable for collapsing into a
319 ;; DISPOSE instruction.
321 (define_predicate "pattern_is_ok_for_dispose"
322 (match_code "parallel")
324 int count = XVECLEN (op, 0);
327 /* If there are no registers to restore then
328 the dispose instruction is not suitable. */
332 /* The pattern matching has already established that we are performing a
333 function epilogue and that we are popping at least one register. We must
334 now check the remaining entries in the vector to make sure that they are
335 also register pops. There is no good reason why there should ever be
336 anything else in this vector, but being paranoid always helps...
338 The test below performs the C equivalent of this machine description
341 (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
342 (mem:SI (plus:SI (reg:SI 3)
343 (match_operand:SI n "immediate_operand" "i"))))
346 for (i = 3; i < count; i++)
348 rtx vector_element = XVECEXP (op, 0, i);
353 if (GET_CODE (vector_element) != SET)
356 dest = SET_DEST (vector_element);
357 src = SET_SRC (vector_element);
359 if ( GET_CODE (dest) != REG
360 || GET_MODE (dest) != SImode
361 || ! register_is_ok_for_epilogue (dest, SImode)
362 || GET_CODE (src) != MEM
363 || GET_MODE (src) != SImode)
366 plus = XEXP (src, 0);
368 if ( GET_CODE (plus) != PLUS
369 || GET_CODE (XEXP (plus, 0)) != REG
370 || GET_MODE (XEXP (plus, 0)) != SImode
371 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
372 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
379 ;; Return nonzero if the given RTX is suitable for collapsing into a
380 ;; PREPARE instruction.
382 (define_predicate "pattern_is_ok_for_prepare"
383 (match_code "parallel")
385 int count = XVECLEN (op, 0);
388 /* If there are no registers to restore then the prepare instruction
393 /* The pattern matching has already established that we are adjusting the
394 stack and pushing at least one register. We must now check that the
395 remaining entries in the vector to make sure that they are also register
398 The test below performs the C equivalent of this machine description
401 (set (mem:SI (plus:SI (reg:SI 3)
402 (match_operand:SI 2 "immediate_operand" "i")))
403 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
407 for (i = 1; i < count; i++)
409 rtx vector_element = XVECEXP (op, 0, i);
414 if (GET_CODE (vector_element) == CLOBBER)
417 if (GET_CODE (vector_element) != SET)
420 dest = SET_DEST (vector_element);
421 src = SET_SRC (vector_element);
423 if ( GET_CODE (dest) != MEM
424 || GET_MODE (dest) != SImode
425 || GET_CODE (src) != REG
426 || GET_MODE (src) != SImode
427 || ! register_is_ok_for_epilogue (src, SImode)
431 plus = XEXP (dest, 0);
433 if ( GET_CODE (plus) != PLUS
434 || GET_CODE (XEXP (plus, 0)) != REG
435 || GET_MODE (XEXP (plus, 0)) != SImode
436 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
437 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
440 /* If the register is being pushed somewhere other than the stack
441 space just acquired by the first operand then abandon this quest.
442 Note: the test is <= because both values are negative. */
443 if (INTVAL (XEXP (plus, 1))
444 < INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
451 ;; Return true if OP is a valid operand for bit related operations
452 ;; containing only single 0 in its binary representation.
454 (define_predicate "not_power_of_two_operand"
455 (match_code "const_int")
461 else if (mode == HImode)
463 else if (mode == SImode)
468 if (GET_CODE (op) != CONST_INT)
471 if (exact_log2 (~INTVAL (op) & mask) == -1)
476 ;; Return true if OP is a float value operand with value as 1.
478 (define_predicate "const_float_1_operand"
479 (match_code "const_int")
481 if (GET_CODE (op) != CONST_DOUBLE
482 || mode != GET_MODE (op)
483 || (mode != DFmode && mode != SFmode))
486 return op == CONST1_RTX(mode);
489 ;; Return true if OP is a float value operand with value as 0.
491 (define_predicate "const_float_0_operand"
492 (match_code "const_int")
494 if (GET_CODE (op) != CONST_DOUBLE
495 || mode != GET_MODE (op)
496 || (mode != DFmode && mode != SFmode))
499 return op == CONST0_RTX(mode);