gcc/config/picochip/picochip.h

   1 /* Definitions of target machine for GNU compiler for picoChip
   2    Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
   3
   4    Contributed by Picochip Ltd. (http://www.picochip.com)
   5    Maintained by Daniel Towner (daniel.towner@picochip.com) and
   6    Hariharan Sandanagobalane (hariharan@picochip.com).
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 3, or (at your option)
  13 any later version.
  14
  15 GCC is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not, see
  22 <http://www.gnu.org/licenses/>. */
  23
  24 /* Which type of DFA scheduling to use - schedule for speed (VLIW), or
  25    schedule for space.  When scheduling for space, attempt to schedule
  26    into stall cycles, but don't pack instructions. */
  27
  28 enum picochip_dfa_type
  29 {
  30   DFA_TYPE_NONE,
  31   DFA_TYPE_SPACE,
  32   DFA_TYPE_SPEED
  33 };
  34
  35 extern enum picochip_dfa_type picochip_schedule_type;
  36
  37 /* Controlling the Compilation Driver */
  38
  39 /* Pass through the save-temps command option. */
  40 #define LINK_SPEC " %{save-temps:--save-temps}"
  41
  42 /* This is an embedded processor, and only supports a cut-down version of
  43  * the standard C library. */
  44 #define LIB_SPEC "-lpicoC"
  45
  46 /* The start file is automatically provided by the linker. */
  47 #define STARTFILE_SPEC ""
  48 \f
  49 /* Run-time Target Specification  */
  50
  51 /* Define some additional pre-processor macros. */
  52 #define TARGET_CPU_CPP_BUILTINS()                       \
  53   do                                                    \
  54     {                                                   \
  55       builtin_define ("NO_TRAMPOLINES");                \
  56       builtin_define ("PICOCHIP");                      \
  57       builtin_define ("__PICOCHIP__");                      \
  58     }                                                   \
  59   while (0)
  60
  61 /* Translate requests for particular AEs into their respective ISA
  62    options. Note that byte access is enabled by default. */
  63 #define DRIVER_SELF_SPECS                                       \
  64   "%{mae=ANY:-mmul-type=none -mno-byte-access} %<mae=ANY",      \
  65   "%{mae=ANY2:-mmul-type=none -mno-byte-access} %<mae=ANY2",    \
  66   "%{mae=ANY3:-mmul-type=none} %<mae=ANY3",                     \
  67   "%{mae=STAN:-mmul-type=none -mno-byte-access} %<mae=STAN",    \
  68   "%{mae=STAN2:-mmul-type=mac -mno-byte-access} %<mae=STAN2",   \
  69   "%{mae=STAN3:-mmul-type=mac} %<mae=STAN3",                    \
  70   "%{mae=MAC:-mmul-type=mac -mno-byte-access} %<mae=MAC",       \
  71   "%{mae=MUL:-mmul-type=mul} %<mae=MUL",                        \
  72   "%{mae=MEM:-mmul-type=mul} %<mae=MEM",                        \
  73   "%{mae=MEM2:-mmul-type=mul} %<mae=MEM2",                      \
  74   "%{mae=CTRL:-mmul-type=mul} %<mae=CTRL",                      \
  75   "%{mae=CTRL2:-mmul-type=mul} %<mae=CTRL2"
  76
  77 /* Specify the default options, so that the multilib build doesn't
  78    need to provide special cases for the defaults. */
  79 #define MULTILIB_DEFAULTS \
  80   { "mmul-type=mul", "mbyte-access"}
  81
  82 #define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
  83 #define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
  84 #define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
  85 #define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
  86
  87 #define TARGET_VERSION fprintf(stderr, "(picoChip)");
  88 \f
  89 /* Storage Layout */
  90
  91 /* picoChip processors are 16-bit machines, little endian. */
  92
  93 #define BITS_BIG_ENDIAN 0
  94 #define BYTES_BIG_ENDIAN 0
  95 #define WORDS_BIG_ENDIAN 0
  96
  97 #define BITS_PER_UNIT 8
  98
  99 #define BITS_PER_WORD 16
 100 #define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
 101
 102 #define POINTER_SIZE BITS_PER_WORD
 103
 104 /* Promote those modes that are smaller than an int, to int mode.  */
 105 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
 106   ((GET_MODE_CLASS (MODE) == MODE_INT                   \
 107       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)         \
 108       ? (MODE) = HImode : 0)
 109
 110 /* All parameters are at least this aligned.  Parameters are passed
 111    one-per-register. */
 112 #define PARM_BOUNDARY BITS_PER_WORD
 113
 114 /* The main stack pointer is guaranteed to be aligned to the most
 115    strict data alignment. */
 116 #define STACK_BOUNDARY 32
 117
 118 /* Function entry point is byte aligned. */
 119 #define FUNCTION_BOUNDARY 8
 120
 121 /* This is the biggest alignment that can be allowed on this machine.
 122    Since the STANs have only 256 byte memory, it doesnt make sense
 123    to have alignments greater than 32 bytes. Hence the value */
 124 #define MAX_OFILE_ALIGNMENT 32*8
 125
 126 /* The strictest data object alignment, which repesents a register pair. */
 127 #define BIGGEST_ALIGNMENT 32
 128
 129 /* The hardware doesn't allow unaligned memory access.  */
 130 #define STRICT_ALIGNMENT 1
 131
 132 /* We want the 'unix' style bitfield packing algorithm.  */
 133 #define PCC_BITFIELD_TYPE_MATTERS 1
 134
 135 /* Support up to 64-bit integers. */
 136 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
 137
 138 /* We don't support floating point, but give it a sensible definition. */
 139 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 140 \f
 141 /* Layout of Source Language Data Types.  */
 142
 143 #define INT_TYPE_SIZE BITS_PER_WORD
 144
 145 /* The normal sizes for C scalar data. */
 146 #define CHAR_TYPE_SIZE 8
 147 #define SHORT_TYPE_SIZE 16
 148 #define LONG_TYPE_SIZE 32
 149 #define LONG_LONG_TYPE_SIZE 64
 150
 151 /* We don't support the following data types, but still give them
 152    sensible values.  */
 153 #define FLOAT_TYPE_SIZE 32
 154 #define DOUBLE_TYPE_SIZE 32
 155 #define LONG_DOUBLE_TYPE_SIZE 32
 156
 157 /* Plain `char' is a signed type, since the hardware sign-extends
 158    bytes when loading them from memory into a register. */
 159 #define DEFAULT_SIGNED_CHAR 1
 160
 161 /* Note that the names of the types used in the following macros must
 162    be precisely the same as those defined internally in gcc.  For
 163    example, `unsigned short' wouldn't work as a type string, since gcc
 164    doesn't define any type with this exact string.  The correct string
 165    to use is `short unsigned int'. */
 166
 167 #define SIZE_TYPE "unsigned int"
 168
 169 #define PTRDIFF_TYPE "int"
 170
 171 #define WCHAR_TYPE "short unsigned int"
 172 #define WCHAR_TYPE_SIZE 16
 173
 174 #define WINT_TYPE "unsigned int"
 175 \f
 176 /* Register Usage  */
 177
 178 /* Picochip has 16 16-bit registers, a condition code register and an
 179    (inaccessible) instruction pointer.  One of these registers (r15) is
 180    special, and is either used to load a constant anywhere a register
 181    can normally be used, or is used to specify a dummy destination
 182    (e.g., when setting condition flags).  We also define some pseudo
 183    registers to represent condition codes, the frame pointer and the
 184    argument pointer.  The latter two are eliminated wherever possible.
 185
 186    Pairs of general registers may be combined to form 32-bit registers.
 187
 188    The picoChip registers are as follows:
 189
 190    0..1 - function return value
 191    0..5 - first 6 function parameters
 192    6..11 - General purpose
 193    12 - link register
 194    13 - stack pointer
 195    14 - specialized pointer
 196    15 - long constant or /dev/null
 197    (16) acc0
 198    (17) pseudo condition code
 199    (18) pseudo frame pointer
 200    (19) pseudo arg pointer
 201
 202    Registers 0..6, 12, 13, 14, 15 are caller save
 203    Registers 0..12, 14 are available to the register allocator.
 204
 205    In addition, the DSP variant of the ISA allows extra accumulator
 206    registers to be accessed.  These are special purpose registers,
 207    which are not currently used by the compiler.
 208
 209   */
 210
 211 /* Basic Characteristics of Registers  */
 212
 213 /* We have 16 hard registers plus 3 pseudo hard registers and an accumulator.  */
 214 #define FIRST_PSEUDO_REGISTER 20
 215
 216 /* The first non-hard register.  Only used internally by the picoChip port. */
 217 #define FIRST_NONHARD_REGISTER 18
 218
 219 /* Cannot use SP, CST, CC, FP, AP */
 220 #define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
 221
 222 /* Those that are clobbered by a function call (includes pseudo-regs) */
 223 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
 224 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
 225
 226 /* Define the number of the picoChip link and condition psuedo registers. */
 227 #define LINK_REGNUM 12
 228 #define CC_REGNUM 17
 229 #define ACC_REGNUM 16
 230
 231 /* Order of Allocation of Registers  */
 232
 233 /* The registers are allocated starting with the caller-clobbered
 234    registers, in reverse order.  The registers are then listed in an
 235    order which means that they are efficiently saved in pairs (i.e.,
 236    one 32-bit store can be used instead of two 16-bit stores to save
 237    the registers into the stack). The exception to this is the use of
 238    r14 (AP) register, which also appears early on.  This is because the
 239    AP register can be used to encode memory operations more
 240    efficiently than other registers.  Some code can be made more
 241    compact as a result. */
 242    /* My current feeling is that r14 should go to the end and maybe even r12.
 243    It seems like the overhead of store/load that will occur since we cant
 244    pair anything up with r14 will be higher than the advantage of smaller
 245    encoding.
 246    Also r12 is put towards the end for leaf functions. Since leaf functions
 247    do not have any calls, the prologue/epilogue for them wouldnt save up/
 248    restore its value. So, it doesnt make sense for us to use it in the middle,
 249    if we can avoid it. */
 250 #define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
 251 #define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
 252
 253 /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
 254    It would be desirable to change it for leaf functions so we can put
 255    r12 at the end of this list.*/
 256 #define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc ()
 257
 258 /* How Values Fit in Registers  */
 259
 260 /* Number of consecutive hard regs needed starting at reg REGNO
 261    to hold something of mode MODE.  */
 262 #define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
 263
 264 /* Is it ok to place MODE in REGNO?  Require that the register number
 265    be aligned. */
 266 #define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
 267
 268 #define MODES_TIEABLE_P(MODE1,MODE2) 1
 269
 270 /* Don't copy the cc register ('cos you can't put it back).  */
 271 #define AVOID_CCMODE_COPIES 1
 272 \f
 273 /* Register Classes */
 274
 275 enum reg_class
 276 {
 277   NO_REGS,                      /* no registers in set */
 278   FRAME_REGS,                   /* registers with a long offset  */
 279   PTR_REGS,                     /* registers without an offset  */
 280   CONST_REGS,                   /* registers for long constants  */
 281   NULL_REGS,                    /* registers which ignore writes  */
 282   CC_REGS,                      /* condition code registers  */
 283   ACC_REGS,                     /* Accumulator registers  */
 284   TWIN_REGS,                    /* registers which can be paired */
 285   GR_REGS,                      /* general purpose registers */
 286   ALL_REGS,                     /* all registers */
 287   LIM_REG_CLASSES,              /* max value + 1 */
 288
 289   /* Some aliases  */
 290   GENERAL_REGS = GR_REGS
 291 };
 292
 293 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 294
 295 /* The following macro defines cover classes for Integrated Register
 296    Allocator.  Cover classes is a set of non-intersected register
 297    classes covering all hard registers used for register allocation
 298    purpose.  Any move between two registers of a cover class should be
 299    cheaper than load or store of the registers.  The macro value is
 300    array of register classes with LIM_REG_CLASSES used as the end
 301    marker.  */
 302
 303 #define IRA_COVER_CLASSES                                               \
 304 {                                                                       \
 305   GR_REGS, LIM_REG_CLASSES                                              \
 306 }
 307
 308
 309 /* The names of the register classes  */
 310 #define REG_CLASS_NAMES                                                 \
 311 {                                                                       \
 312   "NO_REGS",                                                            \
 313   "FRAME_REGS",                                                         \
 314   "PTR_REGS",                                                           \
 315   "CONST_REGS",                                                         \
 316   "NULL_REGS",                                                          \
 317   "CC_REGS",                                                            \
 318   "ACC_REGS",                                                           \
 319   "TWIN_REGS",                                                          \
 320   "GR_REGS",                                                            \
 321   "ALL_REGS"                                                            \
 322 }
 323
 324 /* Each reg class is an array of 32-bit integers.  Each array must be
 325    long enough to store one bit for every pseudo register. Thus in the
 326    following code, each array only stores one 32-bit value. */
 327 #define REG_CLASS_CONTENTS                                              \
 328 {                                                                       \
 329   {0x00000000}, /* no registers */                                      \
 330   {0x00002000}, /* frame */                                             \
 331   {0x00004000}, /* pointer  */                                          \
 332   {0x00008000}, /* const */                                             \
 333   {0x00008000}, /* null  */                                             \
 334   {0x00020000}, /* cc */                                                \
 335   {0x00010000}, /* acc0 */                                              \
 336   {0x00000FFF}, /* twin */                                              \
 337   {0x000CFFFF}, /* general registers - includes pseudo-arg */           \
 338   {0x000FFFFF}  /* all registers - includes pseudo-arg */               \
 339 }
 340
 341 /* The earliest register class containing the given register.  */
 342 extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
 343 #define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
 344
 345 /* Any register can be a base pointer.  */
 346 #define BASE_REG_CLASS GR_REGS
 347
 348 /* Any register can be an index.  */
 349 #define INDEX_REG_CLASS GR_REGS
 350
 351 #define REGNO_OK_FOR_BASE_P(REGNO)                                      \
 352   (REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
 353
 354 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 355
 356 #define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
 357
 358 \f
 359 /* Stack Layout and Calling Conventions  */
 360
 361 #define STACK_GROWS_DOWNWARD 1
 362
 363 /* The frame pointer points to the outgoing argument area, so the
 364    locals are above that.  */
 365 #define STARTING_FRAME_OFFSET 0
 366
 367 #define FIRST_PARM_OFFSET(FNDECL) 0
 368
 369 /* Specify where the return address lives before entry to the
 370    prologue.  This is required to enable DWARF debug information to be
 371    generated. */
 372 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, LINK_REGNUM)
 373
 374 #define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
 375
 376 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
 377
 378 /* Registers that Address the Stack Frame  */
 379
 380 #define STACK_POINTER_REGNUM 13
 381 #define FRAME_POINTER_REGNUM 18
 382 #define ARG_POINTER_REGNUM   19
 383
 384 /* Eliminating Frame Pointer and Arg Pointer.  The frame and argument
 385    pointers are eliminated wherever possible, by replacing them with
 386    offsets from the stack pointer. */
 387
 388 #define ELIMINABLE_REGS                                                 \
 389   {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},                          \
 390    {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
 391
 392 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
 393   OFFSET = initial_elimination_offset(FROM, TO);
 394
 395 #define ACCUMULATE_OUTGOING_ARGS 1
 396
 397 #define PUSH_ARGS 0
 398
 399 /* Passing Arguments in Registers  */
 400
 401 /* Store the offset of the next argument. */
 402 #define CUMULATIVE_ARGS unsigned
 403
 404 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
 405   ((CUM) = 0)
 406
 407 /* The first 6 registers can hold parameters.  */
 408 #define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
 409
 410 /* How Scalar Function Values are Returned
 411    Do we need this?? */
 412 #define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
 413
 414 #define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
 415
 416 /* Results are in register zero.  If an SImode register is returned,
 417    reg0 will suffice to mean R[0:1]. */
 418 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
 419
 420 /* Don't automatically pass struct's in memory - use the
 421  * RETURN_IN_MEMORY macro to determine when structs are returned in
 422  * memory, and when in registers. */
 423 #define DEFAULT_PCC_STRUCT_RETURN 0
 424
 425 /* Function Entry and Exit  */
 426
 427 /* The epilogue doesn't clobber anything.  */
 428 #define EPILOGUE_USES(REGNO) 0
 429
 430 /* Generating Code for Profiling.  No profiling implemented  */
 431
 432 #define FUNCTION_PROFILER(FILE,LABELNO)
 433 \f
 434 /* Trampolines for Nested Functions  */
 435
 436 /* No trampolines.  */
 437 #define TRAMPOLINE_SIZE 0
 438 \f
 439 /* Addressing Modes  */
 440
 441 #define MAX_REGS_PER_ADDRESS 1
 442
 443 /* Legitimize reload address tries machine dependent means of
 444    reloading addresses.  There seems to be a strange error in gcc,
 445    which necessitates this macro.  Consider:
 446
 447      set (reg A) (symbol_ref)
 448      set (reg B) (plus (reg A) (const_int))
 449
 450    A symbol_ref is a valid constant, so the symbol_ref is propagated
 451    into the second instruction to generate the instruction:
 452
 453      set (reg B) (plus (symbol_ref) (const_int))
 454
 455    This is an invalid address, and find_reloads_address correctly
 456    determines this.  However, that function doesn't generate a valid
 457    replacement for the now invalid address, and the invalid address is
 458    output into the assembly language.  To fix the problem without
 459    changing gcc itself, the following macro tests when such an invalid
 460    address has been computed, and wraps it up inside a constant rtx.  A
 461    constant rtx can be correctly reloaded by the function, and hence
 462    correct code is generated. */
 463
 464 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)          \
 465 do {                                                                         \
 466   if (picochip_legitimize_reload_address(&X,MODE,OPNUM,TYPE,IND_LEVELS))     \
 467     goto WIN;                                                                \
 468   } while(0);                                                                \
 469
 470 /* Nonzero if the constant rtx X is a legitimate general operand.  X
 471    satisfies CONSTANT_P.  */
 472
 473 #define LEGITIMATE_CONSTANT_P(X) 1
 474
 475 \f
 476 /* Condition Code Status  */
 477
 478 #define CC_STATUS_MDEP unsigned
 479 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
 480 \f
 481 /* Describing Relative Costs of Operations  */
 482
 483 /* Bytes are no faster than words.  */
 484 #define SLOW_BYTE_ACCESS 1
 485
 486 /* The assembler is often able to optimise function call branches, so
 487    don't try to CSE them in the compiler. This was the thinking before.
 488    But now, we realise that the benefits from CSE would mostly outweigh
 489    the disadvantages. */
 490 #define NO_FUNCTION_CSE
 491
 492 \f
 493 /* Dividing the Output into Sections  */
 494
 495 #define TEXT_SECTION_ASM_OP ".section .text\n"
 496 #define DATA_SECTION_ASM_OP ".section .data\n"
 497 #define BSS_SECTION_ASM_OP ".section .bss\n"
 498 /* picoChip is Harvard (separate data/instruction memories), so
 499    read-only data must go into the data section. */
 500 #define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
 501 \f
 502 /* Defining the Output Assembler Language  */
 503
 504 /* The Overall Framework of an Assembler File  */
 505
 506 #define ASM_FILE_COMMENT "// "
 507
 508 #define ASM_APP_ON "// High-level ASM start\n"
 509 #define ASM_APP_OFF "// High-level ASM end\n"
 510
 511 #define ASM_OUTPUT_IDENT(STREAM,STRING) fprintf(STREAM, ".ident %s\n", STRING)
 512
 513 /* Output of Data  */
 514
 515 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
 516
 517 /* Output of Uninitialized Variables  */
 518 #define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
 519   picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
 520
 521 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
 522   picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
 523
 524 /* Output and Generation of Labels  */
 525
 526 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
 527   do { picochip_output_label(STREAM, NAME); } while (0);
 528
 529 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 530   { picochip_output_labelref(STREAM, NAME); }
 531
 532 /* Format must match that of picochip_output_label. */
 533 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
 534  picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
 535
 536 #define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
 537
 538 /* Store in OUTPUT a string (made with alloca) containing an
 539    assembler-name for a local static variable named NAME.  LABELNO is
 540    an integer which is different for each call.  The assembler can't
 541    use periods to generate the name, so we use a ___ separator
 542    instead. */
 543
 544 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  \
 545 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15),    \
 546   sprintf ((OUTPUT), "%s___%lu", (NAME), (unsigned long)(LABELNO)))
 547
 548 /* Macros Controlling Initialization Routines  */
 549
 550 /* By defining this, the main function won't try to call `__main'. */
 551 #define HAS_INIT_SECTION
 552
 553 /* Output of Assembler Instructions  */
 554
 555 #define REGISTER_NAMES                                                  \
 556 {"R0",  "R1",  "R2",  "R3",                                             \
 557  "R4",  "R5",  "R6",  "R7",                                             \
 558  "R8",  "R9",  "R10", "R11",                                            \
 559  "R12", "FP", "R14", "R15",                                             \
 560  "acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
 561
 562 #define ADDITIONAL_REGISTER_NAMES                                       \
 563 {                                                                       \
 564   { "R0",        0},                                                    \
 565   { "R1",        1},                                                    \
 566   { "R2",        2},                                                    \
 567   { "R3",        3},                                                    \
 568   { "R4",        4},                                                    \
 569   { "R5",        5},                                                    \
 570   { "R6",        6},                                                    \
 571   { "R7",        7},                                                    \
 572   { "R8",        8},                                                    \
 573   { "R9",        9},                                                    \
 574   { "R10",      10},                                                    \
 575   { "R11",      11},                                                    \
 576   { "R12",      12},                                                    \
 577   { "FP",       13},                                                    \
 578   { "R14",      14},                                                    \
 579   { "R15",      15},                                                    \
 580   { "acc0",     16},                                                    \
 581   { "sp",       12}, /* ABI stack pointer */                            \
 582   { "ln",       13}, /* arch link register */                           \
 583   { "ptr",      14}, /* arch constant pointer */                        \
 584   { "rc",       15}, /* arch constant register */                       \
 585   { "rz",       15}, /* arch zero */                                    \
 586 }
 587
 588 /* Final prescan insn is called just before an instruction is
 589    output.  In our case, we use this to detect the VLIW slot to which
 590    the instruction has been assigned, preparatory to generating the
 591    VLIW output in ASM_OUTPUT_OPCODE. */
 592 #define FINAL_PRESCAN_INSN(insn, operand, nop) \
 593   picochip_final_prescan_insn (insn, operand,nop)
 594
 595 #define ASM_OUTPUT_OPCODE(FILE,PTR) \
 596   { PTR = picochip_asm_output_opcode(FILE, PTR); }
 597
 598 #define PRINT_OPERAND(STREAM,X,CODE) \
 599   picochip_print_operand(STREAM, X, CODE)
 600
 601 #define PRINT_OPERAND_PUNCT_VALID_P(code) \
 602   (((code) == '|') || ((code) == '#') || ((code) == '>'))
 603
 604 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
 605   picochip_print_operand_address(STREAM,X)
 606
 607 /* Output of Dispatch Tables  */
 608
 609 /* Initialise a data memory location to an absolute code label.  Used
 610    for building switch statement jump tables.  Note - the format of the
 611    label must match that of the function picochip_output_label. */
 612 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 613   fprintf (stream, ".initWord _L%d\n", value);
 614
 615 /* Assembler Commands for Alignment  */
 616
 617 #define ASM_OUTPUT_SKIP(STREAM,BYTES) \
 618   fprintf(STREAM, ".skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", BYTES);
 619 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 620   fprintf(STREAM, ".align %u\n", 1 << POWER);
 621
 622 /* The elaborator doesn't output zero bytes in the text section. */
 623 #define ASM_NO_SKIP_IN_TEXT 1
 624 \f
 625 /* Controlling Debugging Information Format  */
 626
 627 /* Macros Affecting All Debugging Formats  */
 628
 629 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
 630
 631 #define DWARF2_DEBUGGING_INFO
 632 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 633 #define DWARF2_FRAME_INFO 1
 634
 635 /* Generate .file/.loc directives, so that the assembler generates the
 636    line table. */
 637 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 638 \f
 639 /* Miscellaneous Parameters  */
 640
 641 #define CASE_VECTOR_MODE HImode
 642 #define WORD_REGISTER_OPERATIONS
 643 #define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
 644 #define MOVE_MAX 4
 645 #define SHIFT_COUNT_TRUNCATED 1
 646 #define Pmode HImode
 647 #define FUNCTION_MODE QImode
 648 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
 649
 650 #define ASM_LONG ":TODO:.word\t"
 651
 652 /* Define builtins for selected special-purpose instructions. */
 653 enum picochip_builtins
 654 {
 655   PICOCHIP_BUILTIN_SBC,
 656   PICOCHIP_BUILTIN_PUT,
 657   PICOCHIP_BUILTIN_GET,
 658   PICOCHIP_BUILTIN_TESTPORT,
 659   PICOCHIP_BUILTIN_COPYSW,
 660   PICOCHIP_BUILTIN_ADDS,
 661   PICOCHIP_BUILTIN_SUBS,
 662   PICOCHIP_BUILTIN_BREV,
 663   PICOCHIP_BUILTIN_BYTESWAP,
 664   PICOCHIP_BUILTIN_GET_ARRAY,
 665   PICOCHIP_BUILTIN_PUT_ARRAY,
 666   PICOCHIP_BUILTIN_TESTPORT_ARRAY,
 667   PICOCHIP_BUILTIN_ASRI,
 668   PICOCHIP_BUILTIN_HALT
 669 };
 670
 671 #define NO_DOLLAR_IN_LABEL 1
 672 #define NO_DOT_IN_LABEL 1
 673
 674 /* The assembler does support LEB128, despite the auto-configure test
 675    not detecting this. */
 676 #define HAVE_AS_LEB128 1
 677
 678 /* The End */