| blob | 3fac01ca564669fd77ac7f7856ee54e6aac8459b |
1 ;;- Machine description for Blackfin for GNU compiler
2 ;; Copyright 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ; operand punctuation marks:
22 ;
23 ; X -- integer value printed as log2
24 ; Y -- integer value printed as log2(~value) - for bitclear
25 ; h -- print half word register, low part
26 ; d -- print half word register, high part
27 ; D -- print operand as dregs pairs
28 ; w -- print operand as accumulator register word (a0w, a1w)
29 ; H -- high part of double mode operand
30 ; T -- byte register representation Oct. 02 2001
32 ; constant operand classes
33 ;
34 ; J 2**N 5bit imm scaled
35 ; Ks7 -64 .. 63 signed 7bit imm
36 ; Ku5 0..31 unsigned 5bit imm
37 ; Ks4 -8 .. 7 signed 4bit imm
38 ; Ks3 -4 .. 3 signed 3bit imm
39 ; Ku3 0 .. 7 unsigned 3bit imm
40 ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
41 ;
42 ; register operands
43 ; d (r0..r7)
44 ; a (p0..p5,fp,sp)
45 ; e (a0, a1)
46 ; b (i0..i3)
47 ; f (m0..m3)
48 ; v (b0..b3)
49 ; c (i0..i3,m0..m3) CIRCREGS
50 ; C (CC) CCREGS
51 ; t (lt0,lt1)
52 ; k (lc0,lc1)
53 ; u (lb0,lb1)
54 ;
56 ;; Define constants for hard registers.
58 (define_constants
59 [(REG_R0 0)
60 (REG_R1 1)
61 (REG_R2 2)
62 (REG_R3 3)
63 (REG_R4 4)
64 (REG_R5 5)
65 (REG_R6 6)
66 (REG_R7 7)
68 (REG_P0 8)
69 (REG_P1 9)
70 (REG_P2 10)
71 (REG_P3 11)
72 (REG_P4 12)
73 (REG_P5 13)
74 (REG_P6 14)
75 (REG_P7 15)
77 (REG_SP 14)
78 (REG_FP 15)
80 (REG_I0 16)
81 (REG_I1 17)
82 (REG_I2 18)
83 (REG_I3 19)
85 (REG_B0 20)
86 (REG_B1 21)
87 (REG_B2 22)
88 (REG_B3 23)
90 (REG_L0 24)
91 (REG_L1 25)
92 (REG_L2 26)
93 (REG_L3 27)
95 (REG_M0 28)
96 (REG_M1 29)
97 (REG_M2 30)
98 (REG_M3 31)
100 (REG_A0 32)
101 (REG_A1 33)
103 (REG_CC 34)
104 (REG_RETS 35)
105 (REG_RETI 36)
106 (REG_RETX 37)
107 (REG_RETN 38)
108 (REG_RETE 39)
110 (REG_ASTAT 40)
111 (REG_SEQSTAT 41)
112 (REG_USP 42)
114 (REG_ARGP 43)
116 (REG_LT0 44)
117 (REG_LT1 45)
118 (REG_LC0 46)
119 (REG_LC1 47)
120 (REG_LB0 48)
121 (REG_LB1 49)])
123 ;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
125 (define_constants
126 [(UNSPEC_CBRANCH_TAKEN 0)
127 (UNSPEC_CBRANCH_NOPS 1)
128 (UNSPEC_RETURN 2)
129 (UNSPEC_MOVE_PIC 3)
130 (UNSPEC_LIBRARY_OFFSET 4)
131 (UNSPEC_PUSH_MULTIPLE 5)
132 ;; Multiply or MAC with extra CONST_INT operand specifying the macflag
133 (UNSPEC_MUL_WITH_FLAG 6)
134 (UNSPEC_MAC_WITH_FLAG 7)
135 (UNSPEC_MOVE_FDPIC 8)
136 (UNSPEC_FUNCDESC_GOT17M4 9)
137 (UNSPEC_LSETUP_END 10)
138 ;; Distinguish a 32-bit version of an insn from a 16-bit version.
139 (UNSPEC_32BIT 11)
140 (UNSPEC_NOP 12)
141 (UNSPEC_ONES 13)
142 (UNSPEC_ATOMIC 14)])
144 (define_constants
145 [(UNSPEC_VOLATILE_CSYNC 1)
146 (UNSPEC_VOLATILE_SSYNC 2)
147 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)
148 (UNSPEC_VOLATILE_STORE_EH_HANDLER 4)
149 (UNSPEC_VOLATILE_DUMMY 5)
150 (UNSPEC_VOLATILE_STALL 6)])
152 (define_constants
153 [(MACFLAG_NONE 0)
154 (MACFLAG_T 1)
155 (MACFLAG_FU 2)
156 (MACFLAG_TFU 3)
157 (MACFLAG_IS 4)
158 (MACFLAG_IU 5)
159 (MACFLAG_W32 6)
160 (MACFLAG_M 7)
161 (MACFLAG_IS_M 8)
162 (MACFLAG_S2RND 9)
163 (MACFLAG_ISS2 10)
164 (MACFLAG_IH 11)])
166 (define_attr "type"
167 "move,movcc,mvi,mcld,mcst,dsp32,dsp32shiftimm,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall"
168 (const_string "misc"))
170 (define_attr "addrtype" "32bit,preg,spreg,ireg"
171 (cond [(and (eq_attr "type" "mcld")
172 (and (match_operand 0 "dp_register_operand" "")
173 (match_operand 1 "mem_p_address_operand" "")))
174 (const_string "preg")
175 (and (eq_attr "type" "mcld")
176 (and (match_operand 0 "dp_register_operand" "")
177 (match_operand 1 "mem_spfp_address_operand" "")))
178 (const_string "spreg")
179 (and (eq_attr "type" "mcld")
180 (and (match_operand 0 "dp_register_operand" "")
181 (match_operand 1 "mem_i_address_operand" "")))
182 (const_string "ireg")
183 (and (eq_attr "type" "mcst")
184 (and (match_operand 1 "dp_register_operand" "")
185 (match_operand 0 "mem_p_address_operand" "")))
186 (const_string "preg")
187 (and (eq_attr "type" "mcst")
188 (and (match_operand 1 "dp_register_operand" "")
189 (match_operand 0 "mem_spfp_address_operand" "")))
190 (const_string "spreg")
191 (and (eq_attr "type" "mcst")
192 (and (match_operand 1 "dp_register_operand" "")
193 (match_operand 0 "mem_i_address_operand" "")))
194 (const_string "ireg")]
195 (const_string "32bit")))
197 (define_attr "storereg" "preg,other"
198 (cond [(and (eq_attr "type" "mcst")
199 (match_operand 1 "p_register_operand" ""))
200 (const_string "preg")]
201 (const_string "other")))
203 ;; Scheduling definitions
205 (define_automaton "bfin")
207 (define_cpu_unit "slot0" "bfin")
208 (define_cpu_unit "slot1" "bfin")
209 (define_cpu_unit "slot2" "bfin")
211 ;; Three units used to enforce parallel issue restrictions:
212 ;; only one of the 16-bit slots can use a P register in an address,
213 ;; and only one them can be a store.
214 (define_cpu_unit "store" "bfin")
215 (define_cpu_unit "pregs" "bfin")
217 ;; A dummy unit used to delay scheduling of loads after a conditional
218 ;; branch.
219 (define_cpu_unit "load" "bfin")
221 ;; A logical unit used to work around anomaly 05000074.
222 (define_cpu_unit "anomaly_05000074" "bfin")
224 (define_reservation "core" "slot0+slot1+slot2")
226 (define_insn_reservation "alu" 1
227 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
228 "core")
230 (define_insn_reservation "imul" 3
231 (eq_attr "type" "mult")
232 "core*3")
234 (define_insn_reservation "dsp32" 1
235 (eq_attr "type" "dsp32")
236 "slot0")
238 (define_insn_reservation "dsp32shiftimm" 1
239 (and (eq_attr "type" "dsp32shiftimm")
240 (eq (symbol_ref "ENABLE_WA_05000074")
241 (const_int 0)))
242 "slot0")
244 (define_insn_reservation "dsp32shiftimm_anomaly_05000074" 1
245 (and (eq_attr "type" "dsp32shiftimm")
246 (ne (symbol_ref "ENABLE_WA_05000074")
247 (const_int 0)))
248 "slot0+anomaly_05000074")
250 (define_insn_reservation "load32" 1
251 (and (not (eq_attr "seq_insns" "multi"))
252 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
253 "core+load")
255 (define_insn_reservation "loadp" 1
256 (and (not (eq_attr "seq_insns" "multi"))
257 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
258 "slot1+pregs+load")
260 (define_insn_reservation "loadsp" 1
261 (and (not (eq_attr "seq_insns" "multi"))
262 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "spreg")))
263 "slot1+pregs")
265 (define_insn_reservation "loadi" 1
266 (and (not (eq_attr "seq_insns" "multi"))
267 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
268 "(slot1|slot2)+load")
270 (define_insn_reservation "store32" 1
271 (and (not (eq_attr "seq_insns" "multi"))
272 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
273 "core")
275 (define_insn_reservation "storep" 1
276 (and (and (not (eq_attr "seq_insns" "multi"))
277 (and (eq_attr "type" "mcst")
278 (ior (eq_attr "addrtype" "preg")
279 (eq_attr "addrtype" "spreg"))))
280 (ior (eq (symbol_ref "ENABLE_WA_05000074")
281 (const_int 0))
282 (eq_attr "storereg" "other")))
283 "slot1+pregs+store")
285 (define_insn_reservation "storep_anomaly_05000074" 1
286 (and (and (not (eq_attr "seq_insns" "multi"))
287 (and (eq_attr "type" "mcst")
288 (ior (eq_attr "addrtype" "preg")
289 (eq_attr "addrtype" "spreg"))))
290 (and (ne (symbol_ref "ENABLE_WA_05000074")
291 (const_int 0))
292 (eq_attr "storereg" "preg")))
293 "slot1+anomaly_05000074+pregs+store")
295 (define_insn_reservation "storei" 1
296 (and (and (not (eq_attr "seq_insns" "multi"))
297 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
298 (ior (eq (symbol_ref "ENABLE_WA_05000074")
299 (const_int 0))
300 (eq_attr "storereg" "other")))
301 "(slot1|slot2)+store")
303 (define_insn_reservation "storei_anomaly_05000074" 1
304 (and (and (not (eq_attr "seq_insns" "multi"))
305 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
306 (and (ne (symbol_ref "ENABLE_WA_05000074")
307 (const_int 0))
308 (eq_attr "storereg" "preg")))
309 "((slot1+anomaly_05000074)|slot2)+store")
311 (define_insn_reservation "multi" 2
312 (eq_attr "seq_insns" "multi")
313 "core")
315 (define_insn_reservation "load_stall1" 1
316 (and (eq_attr "type" "stall")
317 (match_operand 0 "const1_operand" ""))
318 "core+load*2")
320 (define_insn_reservation "load_stall3" 1
321 (and (eq_attr "type" "stall")
322 (match_operand 0 "const3_operand" ""))
323 "core+load*4")
325 (absence_set "slot0" "slot1,slot2")
326 (absence_set "slot1" "slot2")
328 ;; Make sure genautomata knows about the maximum latency that can be produced
329 ;; by the adjust_cost function.
330 (define_insn_reservation "dummy" 5
331 (eq_attr "type" "dummy")
332 "core")
333 \f
334 ;; Operand and operator predicates
336 (include "predicates.md")
337 (include "constraints.md")
338 \f
339 ;;; FRIO branches have been optimized for code density
340 ;;; this comes at a slight cost of complexity when
341 ;;; a compiler needs to generate branches in the general
342 ;;; case. In order to generate the correct branching
343 ;;; mechanisms the compiler needs keep track of instruction
344 ;;; lengths. The follow table describes how to count instructions
345 ;;; for the FRIO architecture.
346 ;;;
347 ;;; unconditional br are 12-bit imm pcrelative branches *2
348 ;;; conditional br are 10-bit imm pcrelative branches *2
349 ;;; brcc 10-bit:
350 ;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
351 ;;; br 12-bit :
352 ;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
353 ;;; NOTE : For brcc we generate instructions such as
354 ;;; if cc jmp; jump.[sl] offset
355 ;;; offset of jump.[sl] is from the jump instruction but
356 ;;; gcc calculates length from the if cc jmp instruction
357 ;;; furthermore gcc takes the end address of the branch instruction
358 ;;; as (pc) for a forward branch
359 ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
360 ;;;
361 ;;; The way the (pc) rtx works in these calculations is somewhat odd;
362 ;;; for backward branches it's the address of the current instruction,
363 ;;; for forward branches it's the previously known address of the following
364 ;;; instruction - we have to take this into account by reducing the range
365 ;;; for a forward branch.
367 ;; Lengths for type "mvi" insns are always defined by the instructions
368 ;; themselves.
369 (define_attr "length" ""
370 (cond [(eq_attr "type" "mcld")
371 (if_then_else (match_operand 1 "effective_address_32bit_p" "")
372 (const_int 4) (const_int 2))
374 (eq_attr "type" "mcst")
375 (if_then_else (match_operand 0 "effective_address_32bit_p" "")
376 (const_int 4) (const_int 2))
378 (eq_attr "type" "move") (const_int 2)
380 (eq_attr "type" "dsp32") (const_int 4)
381 (eq_attr "type" "dsp32shiftimm") (const_int 4)
382 (eq_attr "type" "call") (const_int 4)
384 (eq_attr "type" "br")
385 (if_then_else (and
386 (le (minus (match_dup 0) (pc)) (const_int 4092))
387 (ge (minus (match_dup 0) (pc)) (const_int -4096)))
388 (const_int 2)
389 (const_int 4))
391 (eq_attr "type" "brcc")
392 (cond [(and
393 (le (minus (match_dup 3) (pc)) (const_int 1020))
394 (ge (minus (match_dup 3) (pc)) (const_int -1024)))
395 (const_int 2)
396 (and
397 (le (minus (match_dup 3) (pc)) (const_int 4092))
398 (ge (minus (match_dup 3) (pc)) (const_int -4094)))
399 (const_int 4)]
400 (const_int 6))
401 ]
403 (const_int 2)))
405 ;; Classify the insns into those that are one instruction and those that
406 ;; are more than one in sequence.
407 (define_attr "seq_insns" "single,multi"
408 (const_string "single"))
410 ;; Describe a user's asm statement.
411 (define_asm_attributes
412 [(set_attr "type" "misc")
413 (set_attr "seq_insns" "multi")
414 (set_attr "length" "4")])
416 ;; Conditional moves
418 (define_expand "movsicc"
419 [(set (match_operand:SI 0 "register_operand" "")
420 (if_then_else:SI (match_operand 1 "comparison_operator" "")
421 (match_operand:SI 2 "register_operand" "")
422 (match_operand:SI 3 "register_operand" "")))]
423 ""
424 {
425 operands[1] = bfin_gen_compare (operands[1], SImode);
426 })
428 (define_insn "*movsicc_insn1"
429 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
430 (if_then_else:SI
431 (eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
432 (const_int 0))
433 (match_operand:SI 1 "register_operand" "da,0,da")
434 (match_operand:SI 2 "register_operand" "0,da,da")))]
435 ""
436 "@
437 if !cc %0 =%1; /* movsicc-1a */
438 if cc %0 =%2; /* movsicc-1b */
439 if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */"
440 [(set_attr "length" "2,2,4")
441 (set_attr "type" "movcc")
442 (set_attr "seq_insns" "*,*,multi")])
444 (define_insn "*movsicc_insn2"
445 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
446 (if_then_else:SI
447 (ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
448 (const_int 0))
449 (match_operand:SI 1 "register_operand" "0,da,da")
450 (match_operand:SI 2 "register_operand" "da,0,da")))]
451 ""
452 "@
453 if !cc %0 =%2; /* movsicc-2b */
454 if cc %0 =%1; /* movsicc-2a */
455 if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */"
456 [(set_attr "length" "2,2,4")
457 (set_attr "type" "movcc")
458 (set_attr "seq_insns" "*,*,multi")])
460 ;; Insns to load HIGH and LO_SUM
462 (define_insn "movsi_high"
463 [(set (match_operand:SI 0 "register_operand" "=x")
464 (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
465 "reload_completed"
466 "%d0 = %d1;"
467 [(set_attr "type" "mvi")
468 (set_attr "length" "4")])
470 (define_insn "movstricthi_high"
471 [(set (match_operand:SI 0 "register_operand" "+x")
472 (ior:SI (and:SI (match_dup 0) (const_int 65535))
473 (match_operand:SI 1 "immediate_operand" "i")))]
474 "reload_completed"
475 "%d0 = %d1;"
476 [(set_attr "type" "mvi")
477 (set_attr "length" "4")])
479 (define_insn "movsi_low"
480 [(set (match_operand:SI 0 "register_operand" "=x")
481 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
482 (match_operand:SI 2 "immediate_operand" "i")))]
483 "reload_completed"
484 "%h0 = %h2;"
485 [(set_attr "type" "mvi")
486 (set_attr "length" "4")])
488 (define_insn "movsi_high_pic"
489 [(set (match_operand:SI 0 "register_operand" "=x")
490 (high:SI (unspec:SI [(match_operand:SI 1 "" "")]
491 UNSPEC_MOVE_PIC)))]
492 ""
493 "%d0 = %1@GOT_LOW;"
494 [(set_attr "type" "mvi")
495 (set_attr "length" "4")])
497 (define_insn "movsi_low_pic"
498 [(set (match_operand:SI 0 "register_operand" "=x")
499 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
500 (unspec:SI [(match_operand:SI 2 "" "")]
501 UNSPEC_MOVE_PIC)))]
502 ""
503 "%h0 = %h2@GOT_HIGH;"
504 [(set_attr "type" "mvi")
505 (set_attr "length" "4")])
507 ;;; Move instructions
509 (define_insn_and_split "movdi_insn"
510 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
511 (match_operand:DI 1 "general_operand" "iFx,r,mx"))]
512 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
513 "#"
514 "reload_completed"
515 [(set (match_dup 2) (match_dup 3))
516 (set (match_dup 4) (match_dup 5))]
517 {
518 rtx lo_half[2], hi_half[2];
519 split_di (operands, 2, lo_half, hi_half);
521 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
522 {
523 operands[2] = hi_half[0];
524 operands[3] = hi_half[1];
525 operands[4] = lo_half[0];
526 operands[5] = lo_half[1];
527 }
528 else
529 {
530 operands[2] = lo_half[0];
531 operands[3] = lo_half[1];
532 operands[4] = hi_half[0];
533 operands[5] = hi_half[1];
534 }
535 })
537 (define_insn "movbi"
538 [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C,P1")
539 (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0,P1"))]
541 ""
542 "@
543 %0 = %1;
544 %0 = %1 (X);
545 %0 = B %1 (Z)%!
546 B %0 = %1;
547 CC = %1;
548 %0 = CC;
549 CC = R0 < R0;
550 CC = R0 == R0;"
551 [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,compare,compare")
552 (set_attr "length" "2,2,*,*,2,2,2,2")
553 (set_attr "seq_insns" "*,*,*,*,*,*,*,*")])
555 (define_insn "movpdi"
556 [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
557 (match_operand:PDI 1 "general_operand" " e,e,>"))]
558 ""
559 "@
560 %0 = %1;
561 %0 = %x1; %0 = %w1;
562 %w0 = %1; %x0 = %1;"
563 [(set_attr "type" "move,mcst,mcld")
564 (set_attr "seq_insns" "*,multi,multi")])
566 (define_insn "load_accumulator"
567 [(set (match_operand:PDI 0 "register_operand" "=e")
568 (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
569 ""
570 "%0 = %1;"
571 [(set_attr "type" "move")])
573 (define_insn_and_split "load_accumulator_pair"
574 [(set (match_operand:V2PDI 0 "register_operand" "=e")
575 (sign_extend:V2PDI (vec_concat:V2SI
576 (match_operand:SI 1 "register_operand" "d")
577 (match_operand:SI 2 "register_operand" "d"))))]
578 ""
579 "#"
580 "reload_completed"
581 [(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
582 (set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
583 {
584 operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
585 operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
586 })
588 (define_insn "*pushsi_insn"
589 [(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
590 (match_operand:SI 0 "register_operand" "xy"))]
591 ""
592 "[--SP] = %0;"
593 [(set_attr "type" "mcst")
594 (set_attr "addrtype" "32bit")
595 (set_attr "length" "2")])
597 (define_insn "*popsi_insn"
598 [(set (match_operand:SI 0 "register_operand" "=d,xy")
599 (mem:SI (post_inc:SI (reg:SI REG_SP))))]
600 ""
601 "%0 = [SP++]%!"
602 [(set_attr "type" "mcld")
603 (set_attr "addrtype" "preg,32bit")
604 (set_attr "length" "2")])
606 ;; The first alternative is used to make reload choose a limited register
607 ;; class when faced with a movsi_insn that had its input operand replaced
608 ;; with a PLUS. We generally require fewer secondary reloads this way.
610 (define_insn "*movsi_insn"
611 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
612 (match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
613 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
614 "@
615 %0 = %1;
616 %0 = %1;
617 %0 = %1;
618 %0 = %1;
619 %0 = %1 (X);
620 %0 = %1 (X);
621 %0 = %1 (Z);
622 #
623 %0 = %1%!
624 %0 = %1%!"
625 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
626 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
628 (define_insn "*movsi_insn32"
629 [(set (match_operand:SI 0 "register_operand" "=d,d")
630 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
631 ""
632 "@
633 %0 = ROT %1 BY 0%!
634 %0 = %0 -|- %0%!"
635 [(set_attr "type" "dsp32shiftimm,dsp32")])
637 (define_split
638 [(set (match_operand:SI 0 "d_register_operand" "")
639 (const_int 0))]
640 "splitting_for_sched && !optimize_size"
641 [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))])
643 (define_split
644 [(set (match_operand:SI 0 "d_register_operand" "")
645 (match_operand:SI 1 "d_register_operand" ""))]
646 "splitting_for_sched && !optimize_size"
647 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))])
649 (define_insn_and_split "*movv2hi_insn"
650 [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
651 (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
653 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
654 "@
655 #
656 %0 = %1;
657 %0 = %1%!
658 %0 = %1%!"
659 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
660 [(set (match_dup 0) (high:SI (match_dup 2)))
661 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
662 {
663 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
664 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
666 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
667 operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
668 }
669 [(set_attr "type" "move,move,mcld,mcst")
670 (set_attr "length" "2,2,*,*")])
672 (define_insn "*movhi_insn"
673 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
674 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
675 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
676 {
677 static const char *templates[] = {
678 "%0 = %1;",
679 "%0 = %1 (X);",
680 "%0 = %1 (X);",
681 "%0 = W %1 (X)%!",
682 "W %0 = %1%!",
683 "%h0 = W %1%!",
684 "W %0 = %h1%!"
685 };
686 int alt = which_alternative;
687 rtx mem = (MEM_P (operands[0]) ? operands[0]
688 : MEM_P (operands[1]) ? operands[1] : NULL_RTX);
689 if (mem && bfin_dsp_memref_p (mem))
690 alt += 2;
691 return templates[alt];
692 }
693 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
694 (set_attr "length" "2,2,4,*,*")])
696 (define_insn "*movqi_insn"
697 [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
698 (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
699 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
700 "@
701 %0 = %1;
702 %0 = %1 (X);
703 %0 = %1 (X);
704 %0 = B %1 (X)%!
705 B %0 = %1%!"
706 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
707 (set_attr "length" "2,2,4,*,*")])
709 (define_insn "*movsf_insn"
710 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
711 (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
712 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
713 "@
714 %0 = %1;
715 #
716 %0 = %1%!
717 %0 = %1%!"
718 [(set_attr "type" "move,*,mcld,mcst")])
720 (define_insn_and_split "movdf_insn"
721 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
722 (match_operand:DF 1 "general_operand" "iFx,r,mx"))]
723 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
724 "#"
725 "reload_completed"
726 [(set (match_dup 2) (match_dup 3))
727 (set (match_dup 4) (match_dup 5))]
728 {
729 rtx lo_half[2], hi_half[2];
730 split_di (operands, 2, lo_half, hi_half);
732 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
733 {
734 operands[2] = hi_half[0];
735 operands[3] = hi_half[1];
736 operands[4] = lo_half[0];
737 operands[5] = lo_half[1];
738 }
739 else
740 {
741 operands[2] = lo_half[0];
742 operands[3] = lo_half[1];
743 operands[4] = hi_half[0];
744 operands[5] = hi_half[1];
745 }
746 })
748 ;; Storing halfwords.
749 (define_insn "*movsi_insv"
750 [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
751 (const_int 16)
752 (const_int 16))
753 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
754 ""
755 "@
756 %d0 = %h1 << 0%!
757 %d0 = %1;"
758 [(set_attr "type" "dsp32shiftimm,mvi")])
760 (define_expand "insv"
761 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
762 (match_operand:SI 1 "immediate_operand" "")
763 (match_operand:SI 2 "immediate_operand" ""))
764 (match_operand:SI 3 "nonmemory_operand" ""))]
765 ""
766 {
767 if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
768 FAIL;
770 /* From mips.md: insert_bit_field doesn't verify that our source
771 matches the predicate, so check it again here. */
772 if (! register_operand (operands[0], VOIDmode))
773 FAIL;
774 })
776 ;; This is the main "hook" for PIC code. When generating
777 ;; PIC, movsi is responsible for determining when the source address
778 ;; needs PIC relocation and appropriately calling legitimize_pic_address
779 ;; to perform the actual relocation.
781 (define_expand "movsi"
782 [(set (match_operand:SI 0 "nonimmediate_operand" "")
783 (match_operand:SI 1 "general_operand" ""))]
784 ""
785 {
786 if (expand_move (operands, SImode))
787 DONE;
788 })
790 (define_expand "movv2hi"
791 [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
792 (match_operand:V2HI 1 "general_operand" ""))]
793 ""
794 "expand_move (operands, V2HImode);")
796 (define_expand "movdi"
797 [(set (match_operand:DI 0 "nonimmediate_operand" "")
798 (match_operand:DI 1 "general_operand" ""))]
799 ""
800 "expand_move (operands, DImode);")
802 (define_expand "movsf"
803 [(set (match_operand:SF 0 "nonimmediate_operand" "")
804 (match_operand:SF 1 "general_operand" ""))]
805 ""
806 "expand_move (operands, SFmode);")
808 (define_expand "movdf"
809 [(set (match_operand:DF 0 "nonimmediate_operand" "")
810 (match_operand:DF 1 "general_operand" ""))]
811 ""
812 "expand_move (operands, DFmode);")
814 (define_expand "movhi"
815 [(set (match_operand:HI 0 "nonimmediate_operand" "")
816 (match_operand:HI 1 "general_operand" ""))]
817 ""
818 "expand_move (operands, HImode);")
820 (define_expand "movqi"
821 [(set (match_operand:QI 0 "nonimmediate_operand" "")
822 (match_operand:QI 1 "general_operand" ""))]
823 ""
824 " expand_move (operands, QImode); ")
826 ;; Some define_splits to break up SI/SFmode loads of immediate constants.
828 (define_split
829 [(set (match_operand:SI 0 "register_operand" "")
830 (match_operand:SI 1 "symbolic_or_const_operand" ""))]
831 "reload_completed
832 /* Always split symbolic operands; split integer constants that are
833 too large for a single instruction. */
834 && (GET_CODE (operands[1]) != CONST_INT
835 || (INTVAL (operands[1]) < -32768
836 || INTVAL (operands[1]) >= 65536
837 || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
838 [(set (match_dup 0) (high:SI (match_dup 1)))
839 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
840 {
841 if (GET_CODE (operands[1]) == CONST_INT
842 && split_load_immediate (operands))
843 DONE;
844 /* ??? Do something about TARGET_LOW_64K. */
845 })
847 (define_split
848 [(set (match_operand:SF 0 "register_operand" "")
849 (match_operand:SF 1 "immediate_operand" ""))]
850 "reload_completed"
851 [(set (match_dup 2) (high:SI (match_dup 3)))
852 (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
853 {
854 long values;
855 REAL_VALUE_TYPE value;
857 gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
859 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
860 REAL_VALUE_TO_TARGET_SINGLE (value, values);
862 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
863 operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
864 if (values >= -32768 && values < 65536)
865 {
866 emit_move_insn (operands[2], operands[3]);
867 DONE;
868 }
869 if (split_load_immediate (operands + 2))
870 DONE;
871 })
873 ;; Sadly, this can't be a proper named movstrict pattern, since the compiler
874 ;; expects to be able to use registers for operand 1.
875 ;; Note that the asm instruction is defined by the manual to take an unsigned
876 ;; constant, but it doesn't matter to the assembler, and the compiler only
877 ;; deals with sign-extended constants. Hence "Ksh".
878 (define_insn "movstricthi_1"
879 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
880 (match_operand:HI 1 "immediate_operand" "Ksh"))]
881 ""
882 "%h0 = %1;"
883 [(set_attr "type" "mvi")
884 (set_attr "length" "4")])
886 ;; Sign and zero extensions
888 (define_insn_and_split "extendhisi2"
889 [(set (match_operand:SI 0 "register_operand" "=d, d")
890 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
891 ""
892 "@
893 %0 = %h1 (X);
894 %0 = W %h1 (X)%!"
895 "reload_completed && bfin_dsp_memref_p (operands[1])"
896 [(set (match_dup 2) (match_dup 1))
897 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
898 {
899 operands[2] = gen_lowpart (HImode, operands[0]);
900 }
901 [(set_attr "type" "alu0,mcld")])
903 (define_insn_and_split "zero_extendhisi2"
904 [(set (match_operand:SI 0 "register_operand" "=d, d")
905 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
906 ""
907 "@
908 %0 = %h1 (Z);
909 %0 = W %h1 (Z)%!"
910 "reload_completed && bfin_dsp_memref_p (operands[1])"
911 [(set (match_dup 2) (match_dup 1))
912 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
913 {
914 operands[2] = gen_lowpart (HImode, operands[0]);
915 }
916 [(set_attr "type" "alu0,mcld")])
918 (define_insn "zero_extendbisi2"
919 [(set (match_operand:SI 0 "register_operand" "=d")
920 (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
921 ""
922 "%0 = %1;"
923 [(set_attr "type" "compare")])
925 (define_insn "extendqihi2"
926 [(set (match_operand:HI 0 "register_operand" "=d, d")
927 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
928 ""
929 "@
930 %0 = B %1 (X)%!
931 %0 = %T1 (X);"
932 [(set_attr "type" "mcld,alu0")])
934 (define_insn "extendqisi2"
935 [(set (match_operand:SI 0 "register_operand" "=d, d")
936 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
937 ""
938 "@
939 %0 = B %1 (X)%!
940 %0 = %T1 (X);"
941 [(set_attr "type" "mcld,alu0")])
944 (define_insn "zero_extendqihi2"
945 [(set (match_operand:HI 0 "register_operand" "=d, d")
946 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
947 ""
948 "@
949 %0 = B %1 (Z)%!
950 %0 = %T1 (Z);"
951 [(set_attr "type" "mcld,alu0")])
954 (define_insn "zero_extendqisi2"
955 [(set (match_operand:SI 0 "register_operand" "=d, d")
956 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
957 ""
958 "@
959 %0 = B %1 (Z)%!
960 %0 = %T1 (Z);"
961 [(set_attr "type" "mcld,alu0")])
963 ;; DImode logical operations
965 (define_code_iterator any_logical [and ior xor])
966 (define_code_attr optab [(and "and")
967 (ior "ior")
968 (xor "xor")])
969 (define_code_attr op [(and "&")
970 (ior "|")
971 (xor "^")])
972 (define_code_attr high_result [(and "0")
973 (ior "%H1")
974 (xor "%H1")])
976 ;; Keep this pattern around to avoid generating NO_CONFLICT blocks.
977 (define_expand "<optab>di3"
978 [(set (match_operand:DI 0 "register_operand" "=d")
979 (any_logical:DI (match_operand:DI 1 "register_operand" "0")
980 (match_operand:DI 2 "general_operand" "d")))]
981 ""
982 {
983 rtx hi_half[3], lo_half[3];
984 enum insn_code icode = CODE_FOR_<optab>si3;
985 if (!reg_overlap_mentioned_p (operands[0], operands[1])
986 && !reg_overlap_mentioned_p (operands[0], operands[2]))
987 emit_clobber (operands[0]);
988 split_di (operands, 3, lo_half, hi_half);
989 if (!(*insn_data[icode].operand[2].predicate) (lo_half[2], SImode))
990 lo_half[2] = force_reg (SImode, lo_half[2]);
991 emit_insn (GEN_FCN (icode) (lo_half[0], lo_half[1], lo_half[2]));
992 if (!(*insn_data[icode].operand[2].predicate) (hi_half[2], SImode))
993 hi_half[2] = force_reg (SImode, hi_half[2]);
994 emit_insn (GEN_FCN (icode) (hi_half[0], hi_half[1], hi_half[2]));
995 DONE;
996 })
998 (define_insn "zero_extendqidi2"
999 [(set (match_operand:DI 0 "register_operand" "=d")
1000 (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
1001 ""
1002 "%0 = %T1 (Z);\\n\\t%H0 = 0;"
1003 [(set_attr "length" "4")
1004 (set_attr "seq_insns" "multi")])
1006 (define_insn "zero_extendhidi2"
1007 [(set (match_operand:DI 0 "register_operand" "=d")
1008 (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
1009 ""
1010 "%0 = %h1 (Z);\\n\\t%H0 = 0;"
1011 [(set_attr "length" "4")
1012 (set_attr "seq_insns" "multi")])
1014 (define_insn_and_split "extendsidi2"
1015 [(set (match_operand:DI 0 "register_operand" "=d")
1016 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
1017 ""
1018 "#"
1019 "reload_completed"
1020 [(set (match_dup 3) (match_dup 1))
1021 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1022 {
1023 split_di (operands, 1, operands + 2, operands + 3);
1024 if (REGNO (operands[0]) != REGNO (operands[1]))
1025 emit_move_insn (operands[2], operands[1]);
1026 })
1028 (define_insn_and_split "extendqidi2"
1029 [(set (match_operand:DI 0 "register_operand" "=d")
1030 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
1031 ""
1032 "#"
1033 "reload_completed"
1034 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
1035 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
1036 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1037 {
1038 split_di (operands, 1, operands + 2, operands + 3);
1039 })
1041 (define_insn_and_split "extendhidi2"
1042 [(set (match_operand:DI 0 "register_operand" "=d")
1043 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
1044 ""
1045 "#"
1046 "reload_completed"
1047 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
1048 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
1049 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1050 {
1051 split_di (operands, 1, operands + 2, operands + 3);
1052 })
1054 ;; DImode arithmetic operations
1056 (define_insn "add_with_carry"
1057 [(set (match_operand:SI 0 "register_operand" "=d,d")
1058 (plus:SI (match_operand:SI 1 "register_operand" "%0,d")
1059 (match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
1060 (set (match_operand:BI 3 "register_operand" "=C,C")
1061 (ltu:BI (not:SI (match_dup 1)) (match_dup 2)))]
1062 ""
1063 "@
1064 %0 += %2; cc = ac0;
1065 %0 = %1 + %2; cc = ac0;"
1066 [(set_attr "type" "alu0")
1067 (set_attr "length" "4")
1068 (set_attr "seq_insns" "multi")])
1070 (define_insn "sub_with_carry"
1071 [(set (match_operand:SI 0 "register_operand" "=d")
1072 (minus:SI (match_operand:SI 1 "register_operand" "%d")
1073 (match_operand:SI 2 "nonmemory_operand" "d")))
1074 (set (match_operand:BI 3 "register_operand" "=C")
1075 (leu:BI (match_dup 2) (match_dup 1)))]
1076 ""
1077 "%0 = %1 - %2; cc = ac0;"
1078 [(set_attr "type" "alu0")
1079 (set_attr "length" "4")
1080 (set_attr "seq_insns" "multi")])
1082 (define_expand "adddi3"
1083 [(set (match_operand:DI 0 "register_operand" "")
1084 (plus:DI (match_operand:DI 1 "register_operand" "")
1085 (match_operand:DI 2 "nonmemory_operand" "")))
1086 (clobber (match_scratch:SI 3 ""))
1087 (clobber (reg:CC 34))]
1088 ""
1089 {
1090 rtx xops[8];
1091 xops[0] = gen_lowpart (SImode, operands[0]);
1092 xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4);
1093 xops[2] = gen_lowpart (SImode, operands[1]);
1094 xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4);
1095 xops[4] = gen_lowpart (SImode, operands[2]);
1096 xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4);
1097 xops[6] = gen_reg_rtx (SImode);
1098 xops[7] = gen_rtx_REG (BImode, REG_CC);
1099 if (!register_operand (xops[4], SImode)
1100 && (GET_CODE (xops[4]) != CONST_INT
1101 || !satisfies_constraint_Ks7 (xops[4])))
1102 xops[4] = force_reg (SImode, xops[4]);
1103 if (!reg_overlap_mentioned_p (operands[0], operands[1])
1104 && !reg_overlap_mentioned_p (operands[0], operands[2]))
1105 emit_clobber (operands[0]);
1106 emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7]));
1107 emit_insn (gen_movbisi (xops[6], xops[7]));
1108 if (!register_operand (xops[5], SImode)
1109 && (GET_CODE (xops[5]) != CONST_INT
1110 || !satisfies_constraint_Ks7 (xops[5])))
1111 xops[5] = force_reg (SImode, xops[5]);
1112 if (xops[5] != const0_rtx)
1113 emit_insn (gen_addsi3 (xops[1], xops[3], xops[5]));
1114 else
1115 emit_move_insn (xops[1], xops[3]);
1116 emit_insn (gen_addsi3 (xops[1], xops[1], xops[6]));
1117 DONE;
1118 })
1120 (define_expand "subdi3"
1121 [(set (match_operand:DI 0 "register_operand" "")
1122 (minus:DI (match_operand:DI 1 "register_operand" "")
1123 (match_operand:DI 2 "register_operand" "")))
1124 (clobber (reg:CC 34))]
1125 ""
1126 {
1127 rtx xops[8];
1128 xops[0] = gen_lowpart (SImode, operands[0]);
1129 xops[1] = simplify_gen_subreg (SImode, operands[0], DImode, 4);
1130 xops[2] = gen_lowpart (SImode, operands[1]);
1131 xops[3] = simplify_gen_subreg (SImode, operands[1], DImode, 4);
1132 xops[4] = gen_lowpart (SImode, operands[2]);
1133 xops[5] = simplify_gen_subreg (SImode, operands[2], DImode, 4);
1134 xops[6] = gen_reg_rtx (SImode);
1135 xops[7] = gen_rtx_REG (BImode, REG_CC);
1136 if (!reg_overlap_mentioned_p (operands[0], operands[1])
1137 && !reg_overlap_mentioned_p (operands[0], operands[2]))
1138 emit_clobber (operands[0]);
1139 emit_insn (gen_sub_with_carry (xops[0], xops[2], xops[4], xops[7]));
1140 emit_insn (gen_notbi (xops[7], xops[7]));
1141 emit_insn (gen_movbisi (xops[6], xops[7]));
1142 emit_insn (gen_subsi3 (xops[1], xops[3], xops[5]));
1143 emit_insn (gen_subsi3 (xops[1], xops[1], xops[6]));
1144 DONE;
1145 })
1147 ;; Combined shift/add instructions
1149 (define_insn ""
1150 [(set (match_operand:SI 0 "register_operand" "=a,d")
1151 (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1152 (match_operand:SI 2 "register_operand" "a,d"))
1153 (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
1154 ""
1155 "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
1156 [(set_attr "type" "alu0")])
1158 (define_insn ""
1159 [(set (match_operand:SI 0 "register_operand" "=a")
1160 (plus:SI (match_operand:SI 1 "register_operand" "a")
1161 (mult:SI (match_operand:SI 2 "register_operand" "a")
1162 (match_operand:SI 3 "scale_by_operand" "i"))))]
1163 ""
1164 "%0 = %1 + (%2 << %X3);"
1165 [(set_attr "type" "alu0")])
1167 (define_insn ""
1168 [(set (match_operand:SI 0 "register_operand" "=a")
1169 (plus:SI (match_operand:SI 1 "register_operand" "a")
1170 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1171 (match_operand:SI 3 "pos_scale_operand" "i"))))]
1172 ""
1173 "%0 = %1 + (%2 << %3);"
1174 [(set_attr "type" "alu0")])
1176 (define_insn ""
1177 [(set (match_operand:SI 0 "register_operand" "=a")
1178 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
1179 (match_operand:SI 2 "scale_by_operand" "i"))
1180 (match_operand:SI 3 "register_operand" "a")))]
1181 ""
1182 "%0 = %3 + (%1 << %X2);"
1183 [(set_attr "type" "alu0")])
1185 (define_insn ""
1186 [(set (match_operand:SI 0 "register_operand" "=a")
1187 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
1188 (match_operand:SI 2 "pos_scale_operand" "i"))
1189 (match_operand:SI 3 "register_operand" "a")))]
1190 ""
1191 "%0 = %3 + (%1 << %2);"
1192 [(set_attr "type" "alu0")])
1194 (define_insn "mulhisi3"
1195 [(set (match_operand:SI 0 "register_operand" "=d")
1196 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1197 (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1198 ""
1199 "%0 = %h1 * %h2 (IS)%!"
1200 [(set_attr "type" "dsp32")])
1202 (define_insn "umulhisi3"
1203 [(set (match_operand:SI 0 "register_operand" "=d")
1204 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1205 (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1206 ""
1207 "%0 = %h1 * %h2 (FU)%!"
1208 [(set_attr "type" "dsp32")])
1210 (define_insn "usmulhisi3"
1211 [(set (match_operand:SI 0 "register_operand" "=W")
1212 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
1213 (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
1214 ""
1215 "%0 = %h2 * %h1 (IS,M)%!"
1216 [(set_attr "type" "dsp32")])
1218 ;; The processor also supports ireg += mreg or ireg -= mreg, but these
1219 ;; are unusable if we don't ensure that the corresponding lreg is zero.
1220 ;; The same applies to the add/subtract constant versions involving
1221 ;; iregs
1223 (define_insn "addsi3"
1224 [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
1225 (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
1226 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
1227 ""
1228 "@
1229 %0 += %2;
1230 %0 = %1 + %2;
1231 %0 = %1 + %2;"
1232 [(set_attr "type" "alu0")
1233 (set_attr "length" "2,2,2")])
1235 (define_insn "ssaddsi3"
1236 [(set (match_operand:SI 0 "register_operand" "=d")
1237 (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1238 (match_operand:SI 2 "register_operand" "d")))]
1239 ""
1240 "%0 = %1 + %2 (S)%!"
1241 [(set_attr "type" "dsp32")])
1243 (define_insn "subsi3"
1244 [(set (match_operand:SI 0 "register_operand" "=da,d,a")
1245 (minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
1246 (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))]
1247 ""
1248 {
1249 static const char *const strings_subsi3[] = {
1250 "%0 += -%2;",
1251 "%0 = %1 - %2;",
1252 "%0 -= %2;",
1253 };
1255 if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
1256 rtx tmp_op = operands[2];
1257 operands[2] = GEN_INT (-INTVAL (operands[2]));
1258 output_asm_insn ("%0 += %2;", operands);
1259 operands[2] = tmp_op;
1260 return "";
1261 }
1263 return strings_subsi3[which_alternative];
1264 }
1265 [(set_attr "type" "alu0")])
1267 (define_insn "sssubsi3"
1268 [(set (match_operand:SI 0 "register_operand" "=d")
1269 (ss_minus:SI (match_operand:SI 1 "register_operand" "d")
1270 (match_operand:SI 2 "register_operand" "d")))]
1271 ""
1272 "%0 = %1 - %2 (S)%!"
1273 [(set_attr "type" "dsp32")])
1275 ;; Accumulator addition
1277 (define_insn "addpdi3"
1278 [(set (match_operand:PDI 0 "register_operand" "=A")
1279 (ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0")
1280 (match_operand:PDI 2 "nonmemory_operand" "B")))]
1281 ""
1282 "A0 += A1%!"
1283 [(set_attr "type" "dsp32")])
1285 (define_insn "sum_of_accumulators"
1286 [(set (match_operand:SI 0 "register_operand" "=d")
1287 (ss_truncate:SI
1288 (ss_plus:PDI (match_operand:PDI 2 "register_operand" "1")
1289 (match_operand:PDI 3 "register_operand" "B"))))
1290 (set (match_operand:PDI 1 "register_operand" "=A")
1291 (ss_plus:PDI (match_dup 2) (match_dup 3)))]
1292 ""
1293 "%0 = (A0 += A1)%!"
1294 [(set_attr "type" "dsp32")])
1296 (define_insn "us_truncpdisi2"
1297 [(set (match_operand:SI 0 "register_operand" "=D,W")
1298 (us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))]
1299 ""
1300 "%0 = %1 (FU)%!"
1301 [(set_attr "type" "dsp32")])
1303 ;; Bit test instructions
1305 (define_insn "*not_bittst"
1306 [(set (match_operand:BI 0 "register_operand" "=C")
1307 (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1308 (const_int 1)
1309 (match_operand:SI 2 "immediate_operand" "Ku5"))
1310 (const_int 0)))]
1311 ""
1312 "cc = !BITTST (%1,%2);"
1313 [(set_attr "type" "alu0")])
1315 (define_insn "*bittst"
1316 [(set (match_operand:BI 0 "register_operand" "=C")
1317 (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1318 (const_int 1)
1319 (match_operand:SI 2 "immediate_operand" "Ku5"))
1320 (const_int 0)))]
1321 ""
1322 "cc = BITTST (%1,%2);"
1323 [(set_attr "type" "alu0")])
1325 (define_insn_and_split "*bit_extract"
1326 [(set (match_operand:SI 0 "register_operand" "=d")
1327 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1328 (const_int 1)
1329 (match_operand:SI 2 "immediate_operand" "Ku5")))
1330 (clobber (reg:BI REG_CC))]
1331 ""
1332 "#"
1333 ""
1334 [(set (reg:BI REG_CC)
1335 (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1336 (const_int 0)))
1337 (set (match_dup 0)
1338 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1340 (define_insn_and_split "*not_bit_extract"
1341 [(set (match_operand:SI 0 "register_operand" "=d")
1342 (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1343 (const_int 1)
1344 (match_operand:SI 2 "immediate_operand" "Ku5")))
1345 (clobber (reg:BI REG_CC))]
1346 ""
1347 "#"
1348 ""
1349 [(set (reg:BI REG_CC)
1350 (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1351 (const_int 0)))
1352 (set (match_dup 0)
1353 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1355 (define_insn "*andsi_insn"
1356 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1357 (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
1358 (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
1359 ""
1360 "@
1361 BITCLR (%0,%Y2);
1362 %0 = %T1 (Z);
1363 %0 = %h1 (Z);
1364 %0 = %1 & %2;"
1365 [(set_attr "type" "alu0")])
1367 (define_expand "andsi3"
1368 [(set (match_operand:SI 0 "register_operand" "")
1369 (and:SI (match_operand:SI 1 "register_operand" "")
1370 (match_operand:SI 2 "general_operand" "")))]
1371 ""
1372 {
1373 if (highbits_operand (operands[2], SImode))
1374 {
1375 operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
1376 emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
1377 emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
1378 DONE;
1379 }
1380 if (! rhs_andsi3_operand (operands[2], SImode))
1381 operands[2] = force_reg (SImode, operands[2]);
1382 })
1384 (define_insn "iorsi3"
1385 [(set (match_operand:SI 0 "register_operand" "=d,d")
1386 (ior:SI (match_operand:SI 1 "register_operand" "%0,d")
1387 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1388 ""
1389 "@
1390 BITSET (%0, %X2);
1391 %0 = %1 | %2;"
1392 [(set_attr "type" "alu0")])
1394 (define_insn "xorsi3"
1395 [(set (match_operand:SI 0 "register_operand" "=d,d")
1396 (xor:SI (match_operand:SI 1 "register_operand" "%0,d")
1397 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1398 ""
1399 "@
1400 BITTGL (%0, %X2);
1401 %0 = %1 ^ %2;"
1402 [(set_attr "type" "alu0")])
1404 (define_insn "ones"
1405 [(set (match_operand:HI 0 "register_operand" "=d")
1406 (unspec:HI [(match_operand:SI 1 "register_operand" "d")]
1407 UNSPEC_ONES))]
1408 ""
1409 "%h0 = ONES %1;"
1410 [(set_attr "type" "alu0")])
1412 (define_insn "smaxsi3"
1413 [(set (match_operand:SI 0 "register_operand" "=d")
1414 (smax:SI (match_operand:SI 1 "register_operand" "d")
1415 (match_operand:SI 2 "register_operand" "d")))]
1416 ""
1417 "%0 = max(%1,%2)%!"
1418 [(set_attr "type" "dsp32")])
1420 (define_insn "sminsi3"
1421 [(set (match_operand:SI 0 "register_operand" "=d")
1422 (smin:SI (match_operand:SI 1 "register_operand" "d")
1423 (match_operand:SI 2 "register_operand" "d")))]
1424 ""
1425 "%0 = min(%1,%2)%!"
1426 [(set_attr "type" "dsp32")])
1428 (define_insn "abssi2"
1429 [(set (match_operand:SI 0 "register_operand" "=d")
1430 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1431 ""
1432 "%0 = abs %1%!"
1433 [(set_attr "type" "dsp32")])
1435 (define_insn "ssabssi2"
1436 [(set (match_operand:SI 0 "register_operand" "=d")
1437 (ss_abs:SI (match_operand:SI 1 "register_operand" "d")))]
1438 ""
1439 "%0 = abs %1%!"
1440 [(set_attr "type" "dsp32")])
1442 (define_insn "negsi2"
1443 [(set (match_operand:SI 0 "register_operand" "=d")
1444 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1445 ""
1446 "%0 = -%1;"
1447 [(set_attr "type" "alu0")])
1449 (define_insn "ssnegsi2"
1450 [(set (match_operand:SI 0 "register_operand" "=d")
1451 (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
1452 ""
1453 "%0 = -%1 (S)%!"
1454 [(set_attr "type" "dsp32")])
1456 (define_insn "one_cmplsi2"
1457 [(set (match_operand:SI 0 "register_operand" "=d")
1458 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1459 ""
1460 "%0 = ~%1;"
1461 [(set_attr "type" "alu0")])
1463 (define_insn "signbitssi2"
1464 [(set (match_operand:HI 0 "register_operand" "=d")
1465 (if_then_else:HI
1466 (lt (match_operand:SI 1 "register_operand" "d") (const_int 0))
1467 (clz:HI (not:SI (match_dup 1)))
1468 (clz:HI (match_dup 1))))]
1469 ""
1470 "%h0 = signbits %1%!"
1471 [(set_attr "type" "dsp32")])
1473 (define_insn "ssroundsi2"
1474 [(set (match_operand:HI 0 "register_operand" "=d")
1475 (truncate:HI
1476 (lshiftrt:SI (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1477 (const_int 32768))
1478 (const_int 16))))]
1479 ""
1480 "%h0 = %1 (RND)%!"
1481 [(set_attr "type" "dsp32")])
1483 (define_insn "smaxhi3"
1484 [(set (match_operand:HI 0 "register_operand" "=d")
1485 (smax:HI (match_operand:HI 1 "register_operand" "d")
1486 (match_operand:HI 2 "register_operand" "d")))]
1487 ""
1488 "%0 = max(%1,%2) (V)%!"
1489 [(set_attr "type" "dsp32")])
1491 (define_insn "sminhi3"
1492 [(set (match_operand:HI 0 "register_operand" "=d")
1493 (smin:HI (match_operand:HI 1 "register_operand" "d")
1494 (match_operand:HI 2 "register_operand" "d")))]
1495 ""
1496 "%0 = min(%1,%2) (V)%!"
1497 [(set_attr "type" "dsp32")])
1499 (define_insn "abshi2"
1500 [(set (match_operand:HI 0 "register_operand" "=d")
1501 (abs:HI (match_operand:HI 1 "register_operand" "d")))]
1502 ""
1503 "%0 = abs %1 (V)%!"
1504 [(set_attr "type" "dsp32")])
1506 (define_insn "neghi2"
1507 [(set (match_operand:HI 0 "register_operand" "=d")
1508 (neg:HI (match_operand:HI 1 "register_operand" "d")))]
1509 ""
1510 "%0 = -%1;"
1511 [(set_attr "type" "alu0")])
1513 (define_insn "ssneghi2"
1514 [(set (match_operand:HI 0 "register_operand" "=d")
1515 (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
1516 ""
1517 "%0 = -%1 (V)%!"
1518 [(set_attr "type" "dsp32")])
1520 (define_insn "signbitshi2"
1521 [(set (match_operand:HI 0 "register_operand" "=d")
1522 (if_then_else:HI
1523 (lt (match_operand:HI 1 "register_operand" "d") (const_int 0))
1524 (clz:HI (not:HI (match_dup 1)))
1525 (clz:HI (match_dup 1))))]
1526 ""
1527 "%h0 = signbits %h1%!"
1528 [(set_attr "type" "dsp32")])
1530 (define_insn "mulsi3"
1531 [(set (match_operand:SI 0 "register_operand" "=d")
1532 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1533 (match_operand:SI 2 "register_operand" "d")))]
1534 ""
1535 "%0 *= %2;"
1536 [(set_attr "type" "mult")])
1538 (define_expand "umulsi3_highpart"
1539 [(parallel
1540 [(set (match_operand:SI 0 "register_operand" "")
1541 (truncate:SI
1542 (lshiftrt:DI
1543 (mult:DI (zero_extend:DI
1544 (match_operand:SI 1 "nonimmediate_operand" ""))
1545 (zero_extend:DI
1546 (match_operand:SI 2 "register_operand" "")))
1547 (const_int 32))))
1548 (clobber (reg:PDI REG_A0))
1549 (clobber (reg:PDI REG_A1))])]
1550 ""
1551 {
1552 if (!optimize_size)
1553 {
1554 rtx a1reg = gen_rtx_REG (PDImode, REG_A1);
1555 rtx a0reg = gen_rtx_REG (PDImode, REG_A0);
1556 emit_insn (gen_flag_macinit1hi (a1reg,
1557 gen_lowpart (HImode, operands[1]),
1558 gen_lowpart (HImode, operands[2]),
1559 GEN_INT (MACFLAG_FU)));
1560 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
1561 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg,
1562 gen_lowpart (V2HImode, operands[1]),
1563 gen_lowpart (V2HImode, operands[2]),
1564 const1_rtx, const1_rtx,
1565 const1_rtx, const0_rtx, a1reg,
1566 const0_rtx, GEN_INT (MACFLAG_FU),
1567 GEN_INT (MACFLAG_FU)));
1568 emit_insn (gen_flag_machi_parts_acconly (a1reg,
1569 gen_lowpart (V2HImode, operands[2]),
1570 gen_lowpart (V2HImode, operands[1]),
1571 const1_rtx, const0_rtx,
1572 a1reg, const0_rtx, GEN_INT (MACFLAG_FU)));
1573 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
1574 emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg));
1575 emit_insn (gen_us_truncpdisi2 (operands[0], a0reg));
1576 }
1577 else
1578 {
1579 rtx umulsi3_highpart_libfunc
1580 = init_one_libfunc ("__umulsi3_highpart");
1582 emit_library_call_value (umulsi3_highpart_libfunc,
1583 operands[0], LCT_NORMAL, SImode,
1584 2, operands[1], SImode, operands[2], SImode);
1585 }
1586 DONE;
1587 })
1589 (define_expand "smulsi3_highpart"
1590 [(parallel
1591 [(set (match_operand:SI 0 "register_operand" "")
1592 (truncate:SI
1593 (lshiftrt:DI
1594 (mult:DI (sign_extend:DI
1595 (match_operand:SI 1 "nonimmediate_operand" ""))
1596 (sign_extend:DI
1597 (match_operand:SI 2 "register_operand" "")))
1598 (const_int 32))))
1599 (clobber (reg:PDI REG_A0))
1600 (clobber (reg:PDI REG_A1))])]
1601 ""
1602 {
1603 if (!optimize_size)
1604 {
1605 rtx a1reg = gen_rtx_REG (PDImode, REG_A1);
1606 rtx a0reg = gen_rtx_REG (PDImode, REG_A0);
1607 emit_insn (gen_flag_macinit1hi (a1reg,
1608 gen_lowpart (HImode, operands[1]),
1609 gen_lowpart (HImode, operands[2]),
1610 GEN_INT (MACFLAG_FU)));
1611 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
1612 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg,
1613 gen_lowpart (V2HImode, operands[1]),
1614 gen_lowpart (V2HImode, operands[2]),
1615 const1_rtx, const1_rtx,
1616 const1_rtx, const0_rtx, a1reg,
1617 const0_rtx, GEN_INT (MACFLAG_IS),
1618 GEN_INT (MACFLAG_IS_M)));
1619 emit_insn (gen_flag_machi_parts_acconly (a1reg,
1620 gen_lowpart (V2HImode, operands[2]),
1621 gen_lowpart (V2HImode, operands[1]),
1622 const1_rtx, const0_rtx,
1623 a1reg, const0_rtx, GEN_INT (MACFLAG_IS_M)));
1624 emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (16)));
1625 emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg));
1626 }
1627 else
1628 {
1629 rtx smulsi3_highpart_libfunc
1630 = init_one_libfunc ("__smulsi3_highpart");
1632 emit_library_call_value (smulsi3_highpart_libfunc,
1633 operands[0], LCT_NORMAL, SImode,
1634 2, operands[1], SImode, operands[2], SImode);
1635 }
1636 DONE;
1637 })
1639 (define_expand "ashlsi3"
1640 [(set (match_operand:SI 0 "register_operand" "")
1641 (ashift:SI (match_operand:SI 1 "register_operand" "")
1642 (match_operand:SI 2 "nonmemory_operand" "")))]
1643 ""
1644 {
1645 if (GET_CODE (operands[2]) == CONST_INT
1646 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
1647 {
1648 emit_insn (gen_movsi (operands[0], const0_rtx));
1649 DONE;
1650 }
1651 })
1653 (define_insn_and_split "*ashlsi3_insn"
1654 [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a")
1655 (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a")
1656 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))]
1657 ""
1658 "@
1659 %0 <<= %2;
1660 %0 = %1 << %2%!
1661 %0 = %1 + %1;
1662 %0 = %1 << %2;
1663 #"
1664 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1665 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1666 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1667 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1668 [(set_attr "type" "shft,dsp32shiftimm,shft,shft,*")])
1670 (define_insn "ashrsi3"
1671 [(set (match_operand:SI 0 "register_operand" "=d,d")
1672 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1673 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
1674 ""
1675 "@
1676 %0 >>>= %2;
1677 %0 = %1 >>> %2%!"
1678 [(set_attr "type" "shft,dsp32shiftimm")])
1680 (define_insn "rotl16"
1681 [(set (match_operand:SI 0 "register_operand" "=d")
1682 (rotate:SI (match_operand:SI 1 "register_operand" "d")
1683 (const_int 16)))]
1684 ""
1685 "%0 = PACK (%h1, %d1)%!"
1686 [(set_attr "type" "dsp32")])
1688 (define_expand "rotlsi3"
1689 [(set (match_operand:SI 0 "register_operand" "")
1690 (rotate:SI (match_operand:SI 1 "register_operand" "")
1691 (match_operand:SI 2 "immediate_operand" "")))]
1692 ""
1693 {
1694 if (INTVAL (operands[2]) != 16)
1695 FAIL;
1696 })
1698 (define_expand "rotrsi3"
1699 [(set (match_operand:SI 0 "register_operand" "")
1700 (rotatert:SI (match_operand:SI 1 "register_operand" "")
1701 (match_operand:SI 2 "immediate_operand" "")))]
1702 ""
1703 {
1704 if (INTVAL (operands[2]) != 16)
1705 FAIL;
1706 emit_insn (gen_rotl16 (operands[0], operands[1]));
1707 DONE;
1708 })
1711 (define_insn "ror_one"
1712 [(set (match_operand:SI 0 "register_operand" "=d")
1713 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1714 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1715 (set (reg:BI REG_CC)
1716 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1717 ""
1718 "%0 = ROT %1 BY -1%!"
1719 [(set_attr "type" "dsp32shiftimm")])
1721 (define_insn "rol_one"
1722 [(set (match_operand:SI 0 "register_operand" "+d")
1723 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1724 (zero_extend:SI (reg:BI REG_CC))))
1725 (set (reg:BI REG_CC)
1726 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1727 ""
1728 "%0 = ROT %1 BY 1%!"
1729 [(set_attr "type" "dsp32shiftimm")])
1731 (define_expand "lshrdi3"
1732 [(set (match_operand:DI 0 "register_operand" "")
1733 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1734 (match_operand:DI 2 "general_operand" "")))]
1735 ""
1736 {
1737 rtx lo_half[2], hi_half[2];
1739 if (operands[2] != const1_rtx)
1740 FAIL;
1741 if (! rtx_equal_p (operands[0], operands[1]))
1742 emit_move_insn (operands[0], operands[1]);
1744 split_di (operands, 2, lo_half, hi_half);
1746 emit_move_insn (bfin_cc_rtx, const0_rtx);
1747 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1748 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1749 DONE;
1750 })
1752 (define_expand "ashrdi3"
1753 [(set (match_operand:DI 0 "register_operand" "")
1754 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
1755 (match_operand:DI 2 "general_operand" "")))]
1756 ""
1757 {
1758 rtx lo_half[2], hi_half[2];
1760 if (operands[2] != const1_rtx)
1761 FAIL;
1762 if (! rtx_equal_p (operands[0], operands[1]))
1763 emit_move_insn (operands[0], operands[1]);
1765 split_di (operands, 2, lo_half, hi_half);
1767 emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
1768 hi_half[1], const0_rtx));
1769 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1770 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1771 DONE;
1772 })
1774 (define_expand "ashldi3"
1775 [(set (match_operand:DI 0 "register_operand" "")
1776 (ashift:DI (match_operand:DI 1 "register_operand" "")
1777 (match_operand:DI 2 "general_operand" "")))]
1778 ""
1779 {
1780 rtx lo_half[2], hi_half[2];
1782 if (operands[2] != const1_rtx)
1783 FAIL;
1784 if (! rtx_equal_p (operands[0], operands[1]))
1785 emit_move_insn (operands[0], operands[1]);
1787 split_di (operands, 2, lo_half, hi_half);
1789 emit_move_insn (bfin_cc_rtx, const0_rtx);
1790 emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
1791 emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
1792 DONE;
1793 })
1795 (define_insn "lshrsi3"
1796 [(set (match_operand:SI 0 "register_operand" "=d,d,a")
1797 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a")
1798 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))]
1799 ""
1800 "@
1801 %0 >>= %2;
1802 %0 = %1 >> %2%!
1803 %0 = %1 >> %2;"
1804 [(set_attr "type" "shft,dsp32shiftimm,shft")])
1806 (define_insn "lshrpdi3"
1807 [(set (match_operand:PDI 0 "register_operand" "=e")
1808 (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1809 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1810 ""
1811 "%0 = %1 >> %2%!"
1812 [(set_attr "type" "dsp32shiftimm")])
1814 (define_insn "ashrpdi3"
1815 [(set (match_operand:PDI 0 "register_operand" "=e")
1816 (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1817 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1818 ""
1819 "%0 = %1 >>> %2%!"
1820 [(set_attr "type" "dsp32shiftimm")])
1822 ;; A pattern to reload the equivalent of
1823 ;; (set (Dreg) (plus (FP) (large_constant)))
1824 ;; or
1825 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1826 ;; using a scratch register
1827 (define_expand "reload_insi"
1828 [(parallel [(set (match_operand:SI 0 "register_operand" "=w")
1829 (match_operand:SI 1 "fp_plus_const_operand" ""))
1830 (clobber (match_operand:SI 2 "register_operand" "=&a"))])]
1831 ""
1832 {
1833 rtx fp_op = XEXP (operands[1], 0);
1834 rtx const_op = XEXP (operands[1], 1);
1835 rtx primary = operands[0];
1836 rtx scratch = operands[2];
1838 emit_move_insn (scratch, const_op);
1839 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1840 emit_move_insn (primary, scratch);
1841 DONE;
1842 })
1844 (define_mode_iterator AREG [PDI V2PDI])
1846 (define_insn "reload_in<mode>"
1847 [(set (match_operand:AREG 0 "register_operand" "=e")
1848 (match_operand:AREG 1 "memory_operand" "m"))
1849 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1850 ""
1851 {
1852 rtx xops[4];
1853 xops[0] = operands[0];
1854 xops[1] = operands[2];
1855 split_di (operands + 1, 1, xops + 2, xops + 3);
1856 output_asm_insn ("%1 = %2;", xops);
1857 output_asm_insn ("%w0 = %1;", xops);
1858 output_asm_insn ("%1 = %3;", xops);
1859 output_asm_insn ("%x0 = %1;", xops);
1860 return "";
1861 }
1862 [(set_attr "seq_insns" "multi")
1863 (set_attr "type" "mcld")
1864 (set_attr "length" "12")])
1866 (define_insn "reload_out<mode>"
1867 [(set (match_operand:AREG 0 "memory_operand" "=m")
1868 (match_operand:AREG 1 "register_operand" "e"))
1869 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1870 ""
1871 {
1872 rtx xops[4];
1873 xops[0] = operands[1];
1874 xops[1] = operands[2];
1875 split_di (operands, 1, xops + 2, xops + 3);
1876 output_asm_insn ("%1 = %w0;", xops);
1877 output_asm_insn ("%2 = %1;", xops);
1878 output_asm_insn ("%1 = %x0;", xops);
1879 output_asm_insn ("%3 = %1;", xops);
1880 return "";
1881 }
1882 [(set_attr "seq_insns" "multi")
1883 (set_attr "type" "mcld")
1884 (set_attr "length" "12")])
1886 ;; Jump instructions
1888 (define_insn "jump"
1889 [(set (pc)
1890 (label_ref (match_operand 0 "" "")))]
1891 ""
1892 {
1893 if (get_attr_length (insn) == 2)
1894 return "jump.s %0;";
1895 else
1896 return "jump.l %0;";
1897 }
1898 [(set_attr "type" "br")])
1900 (define_insn "indirect_jump"
1901 [(set (pc)
1902 (match_operand:SI 0 "register_operand" "a"))]
1903 ""
1904 "jump (%0);"
1905 [(set_attr "type" "misc")])
1907 (define_expand "tablejump"
1908 [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1909 (use (label_ref (match_operand 1 "" "")))])]
1910 ""
1911 {
1912 /* In PIC mode, the table entries are stored PC relative.
1913 Convert the relative address to an absolute address. */
1914 if (flag_pic)
1915 {
1916 rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
1918 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
1919 op1, NULL_RTX, 0, OPTAB_DIRECT);
1920 }
1921 })
1923 (define_insn "*tablejump_internal"
1924 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1925 (use (label_ref (match_operand 1 "" "")))]
1926 ""
1927 "jump (%0);"
1928 [(set_attr "type" "misc")])
1930 ;; Hardware loop
1932 ; operand 0 is the loop count pseudo register
1933 ; operand 1 is the number of loop iterations or 0 if it is unknown
1934 ; operand 2 is the maximum number of loop iterations
1935 ; operand 3 is the number of levels of enclosed loops
1936 ; operand 4 is the label to jump to at the top of the loop
1937 (define_expand "doloop_end"
1938 [(parallel [(set (pc) (if_then_else
1939 (ne (match_operand:SI 0 "" "")
1940 (const_int 1))
1941 (label_ref (match_operand 4 "" ""))
1942 (pc)))
1943 (set (match_dup 0)
1944 (plus:SI (match_dup 0)
1945 (const_int -1)))
1946 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1947 (clobber (match_scratch:SI 5 ""))])]
1948 ""
1949 {
1950 /* The loop optimizer doesn't check the predicates... */
1951 if (GET_MODE (operands[0]) != SImode)
1952 FAIL;
1953 /* Due to limitations in the hardware (an initial loop count of 0
1954 does not loop 2^32 times) we must avoid to generate a hardware
1955 loops when we cannot rule out this case. */
1956 if (!flag_unsafe_loop_optimizations
1957 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF)
1958 FAIL;
1959 bfin_hardware_loop ();
1960 })
1962 (define_insn "loop_end"
1963 [(set (pc)
1964 (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m")
1965 (const_int 1))
1966 (label_ref (match_operand 1 "" ""))
1967 (pc)))
1968 (set (match_dup 0)
1969 (plus (match_dup 0)
1970 (const_int -1)))
1971 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1972 (clobber (match_scratch:SI 2 "=X,&r,&r"))]
1973 ""
1974 "@
1975 /* loop end %0 %l1 */
1976 #
1977 #"
1978 [(set_attr "length" "6,10,14")])
1980 (define_split
1981 [(set (pc)
1982 (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "")
1983 (const_int 1))
1984 (label_ref (match_operand 1 "" ""))
1985 (pc)))
1986 (set (match_dup 0)
1987 (plus (match_dup 0)
1988 (const_int -1)))
1989 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1990 (clobber (match_scratch:SI 2 "=&r"))]
1991 "splitting_loops"
1992 [(set (match_dup 2) (match_dup 0))
1993 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1994 (set (match_dup 0) (match_dup 2))
1995 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1996 (set (pc)
1997 (if_then_else (eq (reg:BI REG_CC)
1998 (const_int 0))
1999 (label_ref (match_dup 1))
2000 (pc)))]
2001 "")
2003 (define_insn "lsetup_with_autoinit"
2004 [(set (match_operand:SI 0 "lt_register_operand" "=t")
2005 (label_ref (match_operand 1 "" "")))
2006 (set (match_operand:SI 2 "lb_register_operand" "=u")
2007 (label_ref (match_operand 3 "" "")))
2008 (set (match_operand:SI 4 "lc_register_operand" "=k")
2009 (match_operand:SI 5 "register_operand" "a"))]
2010 ""
2011 "LSETUP (%1, %3) %4 = %5;"
2012 [(set_attr "length" "4")])
2014 (define_insn "lsetup_without_autoinit"
2015 [(set (match_operand:SI 0 "lt_register_operand" "=t")
2016 (label_ref (match_operand 1 "" "")))
2017 (set (match_operand:SI 2 "lb_register_operand" "=u")
2018 (label_ref (match_operand 3 "" "")))
2019 (use (match_operand:SI 4 "lc_register_operand" "k"))]
2020 ""
2021 "LSETUP (%1, %3) %4;"
2022 [(set_attr "length" "4")])
2024 ;; Call instructions..
2026 ;; The explicit MEM inside the UNSPEC prevents the compiler from moving
2027 ;; the load before a branch after a NULL test, or before a store that
2028 ;; initializes a function descriptor.
2030 (define_insn_and_split "load_funcdescsi"
2031 [(set (match_operand:SI 0 "register_operand" "=a")
2032 (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
2033 UNSPEC_VOLATILE_LOAD_FUNCDESC))]
2034 ""
2035 "#"
2036 "reload_completed"
2037 [(set (match_dup 0) (mem:SI (match_dup 1)))])
2039 (define_expand "call"
2040 [(parallel [(call (match_operand:SI 0 "" "")
2041 (match_operand 1 "" ""))
2042 (use (match_operand 2 "" ""))])]
2043 ""
2044 {
2045 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
2046 DONE;
2047 })
2049 (define_expand "sibcall"
2050 [(parallel [(call (match_operand:SI 0 "" "")
2051 (match_operand 1 "" ""))
2052 (use (match_operand 2 "" ""))
2053 (return)])]
2054 ""
2055 {
2056 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
2057 DONE;
2058 })
2060 (define_expand "call_value"
2061 [(parallel [(set (match_operand 0 "register_operand" "")
2062 (call (match_operand:SI 1 "" "")
2063 (match_operand 2 "" "")))
2064 (use (match_operand 3 "" ""))])]
2065 ""
2066 {
2067 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
2068 DONE;
2069 })
2071 (define_expand "sibcall_value"
2072 [(parallel [(set (match_operand 0 "register_operand" "")
2073 (call (match_operand:SI 1 "" "")
2074 (match_operand 2 "" "")))
2075 (use (match_operand 3 "" ""))
2076 (return)])]
2077 ""
2078 {
2079 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
2080 DONE;
2081 })
2083 (define_insn "*call_symbol_fdpic"
2084 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2085 (match_operand 1 "general_operand" "g"))
2086 (use (match_operand:SI 2 "register_operand" "Z"))
2087 (use (match_operand 3 "" ""))
2088 (clobber (reg:SI REG_RETS))]
2089 "! SIBLING_CALL_P (insn)
2090 && GET_CODE (operands[0]) == SYMBOL_REF
2091 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
2092 "call %0;"
2093 [(set_attr "type" "call")
2094 (set_attr "length" "4")])
2096 (define_insn "*sibcall_symbol_fdpic"
2097 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2098 (match_operand 1 "general_operand" "g"))
2099 (use (match_operand:SI 2 "register_operand" "Z"))
2100 (use (match_operand 3 "" ""))
2101 (return)]
2102 "SIBLING_CALL_P (insn)
2103 && GET_CODE (operands[0]) == SYMBOL_REF
2104 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
2105 "jump.l %0;"
2106 [(set_attr "type" "br")
2107 (set_attr "length" "4")])
2109 (define_insn "*call_value_symbol_fdpic"
2110 [(set (match_operand 0 "register_operand" "=d")
2111 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2112 (match_operand 2 "general_operand" "g")))
2113 (use (match_operand:SI 3 "register_operand" "Z"))
2114 (use (match_operand 4 "" ""))
2115 (clobber (reg:SI REG_RETS))]
2116 "! SIBLING_CALL_P (insn)
2117 && GET_CODE (operands[1]) == SYMBOL_REF
2118 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
2119 "call %1;"
2120 [(set_attr "type" "call")
2121 (set_attr "length" "4")])
2123 (define_insn "*sibcall_value_symbol_fdpic"
2124 [(set (match_operand 0 "register_operand" "=d")
2125 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2126 (match_operand 2 "general_operand" "g")))
2127 (use (match_operand:SI 3 "register_operand" "Z"))
2128 (use (match_operand 4 "" ""))
2129 (return)]
2130 "SIBLING_CALL_P (insn)
2131 && GET_CODE (operands[1]) == SYMBOL_REF
2132 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
2133 "jump.l %1;"
2134 [(set_attr "type" "br")
2135 (set_attr "length" "4")])
2137 (define_insn "*call_insn_fdpic"
2138 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
2139 (match_operand 1 "general_operand" "g"))
2140 (use (match_operand:SI 2 "register_operand" "Z"))
2141 (use (match_operand 3 "" ""))
2142 (clobber (reg:SI REG_RETS))]
2143 "! SIBLING_CALL_P (insn)"
2144 "call (%0);"
2145 [(set_attr "type" "call")
2146 (set_attr "length" "2")])
2148 (define_insn "*sibcall_insn_fdpic"
2149 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
2150 (match_operand 1 "general_operand" "g"))
2151 (use (match_operand:SI 2 "register_operand" "Z"))
2152 (use (match_operand 3 "" ""))
2153 (return)]
2154 "SIBLING_CALL_P (insn)"
2155 "jump (%0);"
2156 [(set_attr "type" "br")
2157 (set_attr "length" "2")])
2159 (define_insn "*call_value_insn_fdpic"
2160 [(set (match_operand 0 "register_operand" "=d")
2161 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
2162 (match_operand 2 "general_operand" "g")))
2163 (use (match_operand:SI 3 "register_operand" "Z"))
2164 (use (match_operand 4 "" ""))
2165 (clobber (reg:SI REG_RETS))]
2166 "! SIBLING_CALL_P (insn)"
2167 "call (%1);"
2168 [(set_attr "type" "call")
2169 (set_attr "length" "2")])
2171 (define_insn "*sibcall_value_insn_fdpic"
2172 [(set (match_operand 0 "register_operand" "=d")
2173 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
2174 (match_operand 2 "general_operand" "g")))
2175 (use (match_operand:SI 3 "register_operand" "Z"))
2176 (use (match_operand 4 "" ""))
2177 (return)]
2178 "SIBLING_CALL_P (insn)"
2179 "jump (%1);"
2180 [(set_attr "type" "br")
2181 (set_attr "length" "2")])
2183 (define_insn "*call_symbol"
2184 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2185 (match_operand 1 "general_operand" "g"))
2186 (use (match_operand 2 "" ""))
2187 (clobber (reg:SI REG_RETS))]
2188 "! SIBLING_CALL_P (insn)
2189 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2190 && GET_CODE (operands[0]) == SYMBOL_REF
2191 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
2192 "call %0;"
2193 [(set_attr "type" "call")
2194 (set_attr "length" "4")])
2196 (define_insn "*sibcall_symbol"
2197 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2198 (match_operand 1 "general_operand" "g"))
2199 (use (match_operand 2 "" ""))
2200 (return)]
2201 "SIBLING_CALL_P (insn)
2202 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2203 && GET_CODE (operands[0]) == SYMBOL_REF
2204 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
2205 "jump.l %0;"
2206 [(set_attr "type" "br")
2207 (set_attr "length" "4")])
2209 (define_insn "*call_value_symbol"
2210 [(set (match_operand 0 "register_operand" "=d")
2211 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2212 (match_operand 2 "general_operand" "g")))
2213 (use (match_operand 3 "" ""))
2214 (clobber (reg:SI REG_RETS))]
2215 "! SIBLING_CALL_P (insn)
2216 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2217 && GET_CODE (operands[1]) == SYMBOL_REF
2218 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2219 "call %1;"
2220 [(set_attr "type" "call")
2221 (set_attr "length" "4")])
2223 (define_insn "*sibcall_value_symbol"
2224 [(set (match_operand 0 "register_operand" "=d")
2225 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2226 (match_operand 2 "general_operand" "g")))
2227 (use (match_operand 3 "" ""))
2228 (return)]
2229 "SIBLING_CALL_P (insn)
2230 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2231 && GET_CODE (operands[1]) == SYMBOL_REF
2232 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2233 "jump.l %1;"
2234 [(set_attr "type" "br")
2235 (set_attr "length" "4")])
2237 (define_insn "*call_insn"
2238 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
2239 (match_operand 1 "general_operand" "g"))
2240 (use (match_operand 2 "" ""))
2241 (clobber (reg:SI REG_RETS))]
2242 "! SIBLING_CALL_P (insn)"
2243 "call (%0);"
2244 [(set_attr "type" "call")
2245 (set_attr "length" "2")])
2247 (define_insn "*sibcall_insn"
2248 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
2249 (match_operand 1 "general_operand" "g"))
2250 (use (match_operand 2 "" ""))
2251 (return)]
2252 "SIBLING_CALL_P (insn)"
2253 "jump (%0);"
2254 [(set_attr "type" "br")
2255 (set_attr "length" "2")])
2257 (define_insn "*call_value_insn"
2258 [(set (match_operand 0 "register_operand" "=d")
2259 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
2260 (match_operand 2 "general_operand" "g")))
2261 (use (match_operand 3 "" ""))
2262 (clobber (reg:SI REG_RETS))]
2263 "! SIBLING_CALL_P (insn)"
2264 "call (%1);"
2265 [(set_attr "type" "call")
2266 (set_attr "length" "2")])
2268 (define_insn "*sibcall_value_insn"
2269 [(set (match_operand 0 "register_operand" "=d")
2270 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
2271 (match_operand 2 "general_operand" "g")))
2272 (use (match_operand 3 "" ""))
2273 (return)]
2274 "SIBLING_CALL_P (insn)"
2275 "jump (%1);"
2276 [(set_attr "type" "br")
2277 (set_attr "length" "2")])
2279 ;; Block move patterns
2281 ;; We cheat. This copies one more word than operand 2 indicates.
2283 (define_insn "rep_movsi"
2284 [(set (match_operand:SI 0 "register_operand" "=&a")
2285 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2286 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2287 (const_int 2)))
2288 (const_int 4)))
2289 (set (match_operand:SI 1 "register_operand" "=&b")
2290 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2291 (ashift:SI (match_dup 2) (const_int 2)))
2292 (const_int 4)))
2293 (set (mem:BLK (match_dup 3))
2294 (mem:BLK (match_dup 4)))
2295 (use (match_dup 2))
2296 (clobber (match_scratch:HI 5 "=&d"))
2297 (clobber (reg:SI REG_LT1))
2298 (clobber (reg:SI REG_LC1))
2299 (clobber (reg:SI REG_LB1))]
2300 ""
2301 "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
2302 [(set_attr "type" "misc")
2303 (set_attr "length" "16")
2304 (set_attr "seq_insns" "multi")])
2306 (define_insn "rep_movhi"
2307 [(set (match_operand:SI 0 "register_operand" "=&a")
2308 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2309 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2310 (const_int 1)))
2311 (const_int 2)))
2312 (set (match_operand:SI 1 "register_operand" "=&b")
2313 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2314 (ashift:SI (match_dup 2) (const_int 1)))
2315 (const_int 2)))
2316 (set (mem:BLK (match_dup 3))
2317 (mem:BLK (match_dup 4)))
2318 (use (match_dup 2))
2319 (clobber (match_scratch:HI 5 "=&d"))
2320 (clobber (reg:SI REG_LT1))
2321 (clobber (reg:SI REG_LC1))
2322 (clobber (reg:SI REG_LB1))]
2323 ""
2324 "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
2325 [(set_attr "type" "misc")
2326 (set_attr "length" "16")
2327 (set_attr "seq_insns" "multi")])
2329 (define_expand "movmemsi"
2330 [(match_operand:BLK 0 "general_operand" "")
2331 (match_operand:BLK 1 "general_operand" "")
2332 (match_operand:SI 2 "const_int_operand" "")
2333 (match_operand:SI 3 "const_int_operand" "")]
2334 ""
2335 {
2336 if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
2337 DONE;
2338 FAIL;
2339 })
2341 ;; Conditional branch patterns
2342 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
2344 (define_insn "compare_eq"
2345 [(set (match_operand:BI 0 "register_operand" "=C,C")
2346 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
2347 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2348 ""
2349 "cc =%1==%2;"
2350 [(set_attr "type" "compare")])
2352 (define_insn "compare_ne"
2353 [(set (match_operand:BI 0 "register_operand" "=C,C")
2354 (ne:BI (match_operand:SI 1 "register_operand" "d,a")
2355 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2356 "0"
2357 "cc =%1!=%2;"
2358 [(set_attr "type" "compare")])
2360 (define_insn "compare_lt"
2361 [(set (match_operand:BI 0 "register_operand" "=C,C")
2362 (lt:BI (match_operand:SI 1 "register_operand" "d,a")
2363 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2364 ""
2365 "cc =%1<%2;"
2366 [(set_attr "type" "compare")])
2368 (define_insn "compare_le"
2369 [(set (match_operand:BI 0 "register_operand" "=C,C")
2370 (le:BI (match_operand:SI 1 "register_operand" "d,a")
2371 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2372 ""
2373 "cc =%1<=%2;"
2374 [(set_attr "type" "compare")])
2376 (define_insn "compare_leu"
2377 [(set (match_operand:BI 0 "register_operand" "=C,C")
2378 (leu:BI (match_operand:SI 1 "register_operand" "d,a")
2379 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2380 ""
2381 "cc =%1<=%2 (iu);"
2382 [(set_attr "type" "compare")])
2384 (define_insn "compare_ltu"
2385 [(set (match_operand:BI 0 "register_operand" "=C,C")
2386 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
2387 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2388 ""
2389 "cc =%1<%2 (iu);"
2390 [(set_attr "type" "compare")])
2392 ;; Same as above, but and CC with the overflow bit generated by the first
2393 ;; multiplication.
2394 (define_insn "flag_mul_macv2hi_parts_acconly_andcc0"
2395 [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
2396 (unspec:PDI [(vec_select:HI
2397 (match_operand:V2HI 2 "register_operand" "d,d,d")
2398 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
2399 (vec_select:HI
2400 (match_operand:V2HI 3 "register_operand" "d,d,d")
2401 (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
2402 (match_operand 10 "const_int_operand" "PB,PA,PA")]
2403 UNSPEC_MUL_WITH_FLAG))
2404 (set (match_operand:PDI 1 "register_operand" "=B,e,e")
2405 (unspec:PDI [(vec_select:HI
2406 (match_dup 2)
2407 (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
2408 (vec_select:HI
2409 (match_dup 3)
2410 (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
2411 (match_operand:PDI 8 "register_operand" "1,1,1")
2412 (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
2413 (match_operand 11 "const_int_operand" "PA,PB,PA")]
2414 UNSPEC_MAC_WITH_FLAG))
2415 (set (reg:BI REG_CC)
2416 (and:BI (reg:BI REG_CC)
2417 (unspec:BI [(vec_select:HI (match_dup 2) (parallel [(match_dup 4)]))
2418 (vec_select:HI (match_dup 3) (parallel [(match_dup 6)]))
2419 (match_dup 10)]
2420 UNSPEC_MUL_WITH_FLAG)))]
2421 "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
2422 {
2423 rtx xops[6];
2424 const char *templates[] = {
2425 "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
2426 "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
2427 "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
2428 "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
2429 "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
2430 "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5;\n\tCC &= %v0;",
2431 "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
2432 "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5;\n\tCC &= %v0;",
2433 "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
2434 "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
2435 "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
2436 "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
2437 "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
2438 "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5;\n\tCC &= %v0;",
2439 "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;",
2440 "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5;\n\tCC &= %v0;" };
2441 int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
2442 + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
2443 xops[0] = operands[0];
2444 xops[1] = operands[1];
2445 xops[2] = operands[2];
2446 xops[3] = operands[3];
2447 xops[4] = operands[9];
2448 xops[5] = which_alternative == 0 ? operands[10] : operands[11];
2449 output_asm_insn (templates[alt], xops);
2450 return "";
2451 }
2452 [(set_attr "type" "misc")
2453 (set_attr "length" "6")
2454 (set_attr "seq_insns" "multi")])
2456 (define_expand "cbranchsi4"
2457 [(set (pc)
2458 (if_then_else (match_operator 0 "ordered_comparison_operator"
2459 [(match_operand:SI 1 "register_operand" "")
2460 (match_operand:SI 2 "reg_or_const_int_operand" "")])
2461 (label_ref (match_operand 3 "" ""))
2462 (pc)))]
2463 ""
2464 {
2465 rtx bi_compare = bfin_gen_compare (operands[0], SImode);
2466 emit_jump_insn (gen_cbranchbi4 (bi_compare, bfin_cc_rtx, CONST0_RTX (BImode),
2467 operands[3]));
2468 DONE;
2469 })
2471 (define_insn "cbranchbi4"
2472 [(set (pc)
2473 (if_then_else
2474 (match_operator 0 "bfin_bimode_comparison_operator"
2475 [(match_operand:BI 1 "register_operand" "C")
2476 (match_operand:BI 2 "immediate_operand" "P0")])
2477 (label_ref (match_operand 3 "" ""))
2478 (pc)))]
2479 ""
2480 {
2481 asm_conditional_branch (insn, operands, 0, 0);
2482 return "";
2483 }
2484 [(set_attr "type" "brcc")])
2486 ;; Special cbranch patterns to deal with the speculative load problem - see
2487 ;; bfin_reorg for details.
2489 (define_insn "cbranch_predicted_taken"
2490 [(set (pc)
2491 (if_then_else
2492 (match_operator 0 "bfin_bimode_comparison_operator"
2493 [(match_operand:BI 1 "register_operand" "C")
2494 (match_operand:BI 2 "immediate_operand" "P0")])
2495 (label_ref (match_operand 3 "" ""))
2496 (pc)))
2497 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2498 ""
2499 {
2500 asm_conditional_branch (insn, operands, 0, 1);
2501 return "";
2502 }
2503 [(set_attr "type" "brcc")])
2505 (define_insn "cbranch_with_nops"
2506 [(set (pc)
2507 (if_then_else
2508 (match_operator 0 "bfin_bimode_comparison_operator"
2509 [(match_operand:BI 1 "register_operand" "C")
2510 (match_operand:BI 2 "immediate_operand" "P0")])
2511 (label_ref (match_operand 3 "" ""))
2512 (pc)))
2513 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2514 "reload_completed"
2515 {
2516 asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
2517 return "";
2518 }
2519 [(set_attr "type" "brcc")
2520 (set_attr "length" "8")])
2522 ;; setcc insns.
2524 (define_expand "cstorebi4"
2525 [(set (match_dup 4)
2526 (match_operator:BI 1 "bfin_bimode_comparison_operator"
2527 [(match_operand:BI 2 "register_operand" "")
2528 (match_operand:BI 3 "reg_or_const_int_operand" "")]))
2529 (set (match_operand:SI 0 "register_operand" "")
2530 (ne:SI (match_dup 4) (const_int 0)))]
2531 ""
2532 {
2533 /* It could be expanded as a movbisi instruction, but the portable
2534 alternative produces better code. */
2535 if (GET_CODE (operands[1]) == NE)
2536 FAIL;
2538 operands[4] = bfin_cc_rtx;
2539 })
2541 (define_expand "cstoresi4"
2542 [(set (match_operand:SI 0 "register_operand")
2543 (match_operator:SI 1 "ordered_comparison_operator"
2544 [(match_operand:SI 2 "register_operand" "")
2545 (match_operand:SI 3 "reg_or_const_int_operand" "")]))]
2546 ""
2547 {
2548 rtx bi_compare, test;
2550 if (!bfin_direct_comparison_operator (operands[1], SImode))
2551 {
2552 if (!register_operand (operands[3], SImode)
2553 || GET_CODE (operands[1]) == NE)
2554 FAIL;
2555 test = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
2556 SImode, operands[3], operands[2]);
2557 }
2558 else
2559 test = operands[1];
2561 bi_compare = bfin_gen_compare (test, SImode);
2562 gcc_assert (GET_CODE (bi_compare) == NE);
2563 emit_insn (gen_movbisi (operands[0], bfin_cc_rtx));
2564 DONE;
2565 })
2567 (define_insn "nop"
2568 [(const_int 0)]
2569 ""
2570 "nop;")
2572 ;; A nop which stays there when emitted.
2573 (define_insn "forced_nop"
2574 [(unspec [(const_int 0)] UNSPEC_NOP)]
2575 ""
2576 "nop;")
2578 (define_insn "mnop"
2579 [(unspec [(const_int 0)] UNSPEC_32BIT)]
2580 ""
2581 "mnop%!"
2582 [(set_attr "type" "dsp32")])
2584 ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
2585 (define_insn "movsibi"
2586 [(set (match_operand:BI 0 "register_operand" "=C")
2587 (ne:BI (match_operand:SI 1 "register_operand" "d")
2588 (const_int 0)))]
2589 ""
2590 "CC = %1;"
2591 [(set_attr "length" "2")])
2593 (define_insn_and_split "movbisi"
2594 [(set (match_operand:SI 0 "register_operand" "=d")
2595 (ne:SI (match_operand:BI 1 "register_operand" "C")
2596 (const_int 0)))]
2597 ""
2598 "#"
2599 ""
2600 [(set (match_operand:SI 0 "register_operand" "")
2601 (zero_extend:SI (match_operand:BI 1 "register_operand" "")))]
2602 "")
2604 (define_insn "notbi"
2605 [(set (match_operand:BI 0 "register_operand" "=C")
2606 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2607 (const_int 0)))]
2608 ""
2609 "%0 = ! %0;" /* NOT CC;" */
2610 [(set_attr "type" "compare")])
2612 ;; Vector and DSP insns
2614 (define_insn ""
2615 [(set (match_operand:SI 0 "register_operand" "=d")
2616 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2617 (const_int 24))
2618 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2619 (const_int 8))))]
2620 ""
2621 "%0 = ALIGN8(%1, %2)%!"
2622 [(set_attr "type" "dsp32")])
2624 (define_insn ""
2625 [(set (match_operand:SI 0 "register_operand" "=d")
2626 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2627 (const_int 16))
2628 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2629 (const_int 16))))]
2630 ""
2631 "%0 = ALIGN16(%1, %2)%!"
2632 [(set_attr "type" "dsp32")])
2634 (define_insn ""
2635 [(set (match_operand:SI 0 "register_operand" "=d")
2636 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2637 (const_int 8))
2638 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2639 (const_int 24))))]
2640 ""
2641 "%0 = ALIGN24(%1, %2)%!"
2642 [(set_attr "type" "dsp32")])
2644 ;; Prologue and epilogue.
2646 (define_expand "prologue"
2647 [(const_int 1)]
2648 ""
2649 "bfin_expand_prologue (); DONE;")
2651 (define_expand "epilogue"
2652 [(const_int 1)]
2653 ""
2654 "bfin_expand_epilogue (1, 0, 0); DONE;")
2656 (define_expand "sibcall_epilogue"
2657 [(const_int 1)]
2658 ""
2659 "bfin_expand_epilogue (0, 0, 1); DONE;")
2661 (define_expand "eh_return"
2662 [(use (match_operand:SI 0 "register_operand" ""))]
2663 ""
2664 {
2665 emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0]));
2666 emit_jump_insn (gen_eh_return_internal ());
2667 emit_barrier ();
2668 DONE;
2669 })
2671 (define_insn "eh_store_handler"
2672 [(unspec_volatile [(match_operand:SI 1 "register_operand" "da")]
2673 UNSPEC_VOLATILE_STORE_EH_HANDLER)
2674 (clobber (match_operand:SI 0 "memory_operand" "=m"))]
2675 ""
2676 "%0 = %1%!"
2677 [(set_attr "type" "mcst")])
2679 (define_insn_and_split "eh_return_internal"
2680 [(eh_return)]
2681 ""
2682 "#"
2683 "epilogue_completed"
2684 [(const_int 1)]
2685 "bfin_expand_epilogue (1, 1, 0); DONE;")
2687 (define_insn "link"
2688 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2689 (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
2690 (set (reg:SI REG_FP)
2691 (plus:SI (reg:SI REG_SP) (const_int -8)))
2692 (set (reg:SI REG_SP)
2693 (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
2694 ""
2695 "LINK %Z0;"
2696 [(set_attr "length" "4")])
2698 (define_insn "unlink"
2699 [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
2700 (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
2701 (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
2702 ""
2703 "UNLINK;"
2704 [(set_attr "length" "4")])
2706 ;; This pattern is slightly clumsy. The stack adjust must be the final SET in
2707 ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
2708 ;; where on the stack, since it goes through all elements of the parallel in
2709 ;; sequence.
2710 (define_insn "push_multiple"
2711 [(match_parallel 0 "push_multiple_operation"
2712 [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
2713 ""
2714 {
2715 output_push_multiple (insn, operands);
2716 return "";
2717 })
2719 (define_insn "pop_multiple"
2720 [(match_parallel 0 "pop_multiple_operation"
2721 [(set (reg:SI REG_SP)
2722 (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
2723 ""
2724 {
2725 output_pop_multiple (insn, operands);
2726 return "";
2727 })
2729 (define_insn "return_internal"
2730 [(return)
2731 (use (match_operand 0 "register_operand" ""))]
2732 "reload_completed"
2733 {
2734 switch (REGNO (operands[0]))
2735 {
2736 case REG_RETX:
2737 return "rtx;";
2738 case REG_RETN:
2739 return "rtn;";
2740 case REG_RETI:
2741 return "rti;";
2742 case REG_RETS:
2743 return "rts;";
2744 }
2745 gcc_unreachable ();
2746 })
2748 ;; When used at a location where CC contains 1, causes a speculative load
2749 ;; that is later cancelled. This is used for certain workarounds in
2750 ;; interrupt handler prologues.
2751 (define_insn "dummy_load"
2752 [(unspec_volatile [(match_operand 0 "register_operand" "a")
2753 (match_operand 1 "register_operand" "C")]
2754 UNSPEC_VOLATILE_DUMMY)]
2755 ""
2756 "if cc jump 4;\n\tr7 = [%0];"
2757 [(set_attr "type" "misc")
2758 (set_attr "length" "4")
2759 (set_attr "seq_insns" "multi")])
2761 ;; A placeholder insn inserted before the final scheduling pass. It is used
2762 ;; to improve scheduling of loads when workarounds for speculative loads are
2763 ;; needed, by not placing them in the first few cycles after a conditional
2764 ;; branch.
2765 (define_insn "stall"
2766 [(unspec_volatile [(match_operand 0 "const_int_operand" "P1P3")]
2767 UNSPEC_VOLATILE_STALL)]
2768 ""
2769 ""
2770 [(set_attr "type" "stall")])
2772 (define_insn "csync"
2773 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2774 ""
2775 "csync;"
2776 [(set_attr "type" "sync")])
2778 (define_insn "ssync"
2779 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
2780 ""
2781 "ssync;"
2782 [(set_attr "type" "sync")])
2784 (define_insn "trap"
2785 [(trap_if (const_int 1) (const_int 3))]
2786 ""
2787 "excpt 3;"
2788 [(set_attr "type" "misc")
2789 (set_attr "length" "2")])
2791 (define_insn "trapifcc"
2792 [(trap_if (reg:BI REG_CC) (const_int 3))]
2793 ""
2794 "if !cc jump 4 (bp); excpt 3;"
2795 [(set_attr "type" "misc")
2796 (set_attr "length" "4")
2797 (set_attr "seq_insns" "multi")])
2799 ;;; Vector instructions
2801 ;; First, all sorts of move variants
2803 (define_insn "movhiv2hi_low"
2804 [(set (match_operand:V2HI 0 "register_operand" "=d")
2805 (vec_concat:V2HI
2806 (match_operand:HI 2 "register_operand" "d")
2807 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2808 (parallel [(const_int 1)]))))]
2809 ""
2810 "%h0 = %h2 << 0%!"
2811 [(set_attr "type" "dsp32shiftimm")])
2813 (define_insn "movhiv2hi_high"
2814 [(set (match_operand:V2HI 0 "register_operand" "=d")
2815 (vec_concat:V2HI
2816 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2817 (parallel [(const_int 0)]))
2818 (match_operand:HI 2 "register_operand" "d")))]
2819 ""
2820 "%d0 = %h2 << 0%!"
2821 [(set_attr "type" "dsp32shiftimm")])
2823 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2824 ;; The order of operands is intentional to match the VDSP builtin (high word
2825 ;; is passed first).
2826 (define_insn_and_split "composev2hi"
2827 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
2828 (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
2829 (match_operand:HI 1 "register_operand" "d,d")))]
2830 ""
2831 "@
2832 %d0 = %h1 << 0%!
2833 #"
2834 "reload_completed"
2835 [(set (match_dup 0)
2836 (vec_concat:V2HI
2837 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
2838 (match_dup 1)))
2839 (set (match_dup 0)
2840 (vec_concat:V2HI
2841 (match_dup 2)
2842 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2843 ""
2844 [(set_attr "type" "dsp32shiftimm")])
2846 ; Like composev2hi, but operating on elements of V2HI vectors.
2847 ; Useful on its own, and as a combiner bridge for the multiply and
2848 ; mac patterns.
2849 (define_insn "packv2hi"
2850 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d,d,d,d,d")
2851 (vec_concat:V2HI (vec_select:HI
2852 (match_operand:V2HI 1 "register_operand" "0,0,d,d,d,d,d,d")
2853 (parallel [(match_operand 3 "const01_operand" "P0,P0,P0,P1,P0,P1,P0,P1")]))
2854 (vec_select:HI
2855 (match_operand:V2HI 2 "register_operand" "d,d,0,0,d,d,d,d")
2856 (parallel [(match_operand 4 "const01_operand" "P0,P1,P1,P1,P0,P0,P1,P1")]))))]
2857 ""
2858 "@
2859 %d0 = %h2 << 0%!
2860 %d0 = %d2 << 0%!
2861 %h0 = %h1 << 0%!
2862 %h0 = %d1 << 0%!
2863 %0 = PACK (%h2,%h1)%!
2864 %0 = PACK (%h2,%d1)%!
2865 %0 = PACK (%d2,%h1)%!
2866 %0 = PACK (%d2,%d1)%!"
2867 [(set_attr "type" "dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32,dsp32,dsp32,dsp32")])
2869 (define_insn "movv2hi_hi"
2870 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2871 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2872 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2873 ""
2874 "@
2875 /* optimized out */
2876 %h0 = %h1 << 0%!
2877 %h0 = %d1 << 0%!"
2878 [(set_attr "type" "dsp32shiftimm")])
2880 (define_expand "movv2hi_hi_low"
2881 [(set (match_operand:HI 0 "register_operand" "")
2882 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2883 (parallel [(const_int 0)])))]
2884 ""
2885 "")
2887 (define_expand "movv2hi_hi_high"
2888 [(set (match_operand:HI 0 "register_operand" "")
2889 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2890 (parallel [(const_int 1)])))]
2891 ""
2892 "")
2894 ;; Unusual arithmetic operations on 16-bit registers.
2896 (define_code_iterator sp_or_sm [ss_plus ss_minus])
2897 (define_code_attr spm_string [(ss_plus "+") (ss_minus "-")])
2898 (define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")])
2900 (define_insn "ss<spm_name>hi3"
2901 [(set (match_operand:HI 0 "register_operand" "=d")
2902 (sp_or_sm:HI (match_operand:HI 1 "register_operand" "d")
2903 (match_operand:HI 2 "register_operand" "d")))]
2904 ""
2905 "%h0 = %h1 <spm_string> %h2 (S)%!"
2906 [(set_attr "type" "dsp32")])
2908 (define_insn "ss<spm_name>hi3_parts"
2909 [(set (match_operand:HI 0 "register_operand" "=d")
2910 (sp_or_sm:HI (vec_select:HI
2911 (match_operand:V2HI 1 "register_operand" "d")
2912 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2913 (vec_select:HI
2914 (match_operand:V2HI 2 "register_operand" "d")
2915 (parallel [(match_operand 4 "const01_operand" "P0P1")]))))]
2916 ""
2917 {
2918 const char *templates[] = {
2919 "%h0 = %h1 <spm_string> %h2 (S)%!",
2920 "%h0 = %d1 <spm_string> %h2 (S)%!",
2921 "%h0 = %h1 <spm_string> %d2 (S)%!",
2922 "%h0 = %d1 <spm_string> %d2 (S)%!" };
2923 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
2924 return templates[alt];
2925 }
2926 [(set_attr "type" "dsp32")])
2928 (define_insn "ss<spm_name>hi3_low_parts"
2929 [(set (match_operand:V2HI 0 "register_operand" "=d")
2930 (vec_concat:V2HI
2931 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2932 (parallel [(const_int 0)]))
2933 (sp_or_sm:HI (vec_select:HI
2934 (match_operand:V2HI 2 "register_operand" "d")
2935 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
2936 (vec_select:HI
2937 (match_operand:V2HI 3 "register_operand" "d")
2938 (parallel [(match_operand 5 "const01_operand" "P0P1")])))))]
2939 ""
2940 {
2941 const char *templates[] = {
2942 "%h0 = %h2 <spm_string> %h3 (S)%!",
2943 "%h0 = %d2 <spm_string> %h3 (S)%!",
2944 "%h0 = %h2 <spm_string> %d3 (S)%!",
2945 "%h0 = %d2 <spm_string> %d3 (S)%!" };
2946 int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
2947 return templates[alt];
2948 }
2949 [(set_attr "type" "dsp32")])
2951 (define_insn "ss<spm_name>hi3_high_parts"
2952 [(set (match_operand:V2HI 0 "register_operand" "=d")
2953 (vec_concat:V2HI
2954 (sp_or_sm:HI (vec_select:HI
2955 (match_operand:V2HI 2 "register_operand" "d")
2956 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
2957 (vec_select:HI
2958 (match_operand:V2HI 3 "register_operand" "d")
2959 (parallel [(match_operand 5 "const01_operand" "P0P1")])))
2960 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2961 (parallel [(const_int 1)]))))]
2962 ""
2963 {
2964 const char *templates[] = {
2965 "%d0 = %h2 <spm_string> %h3 (S)%!",
2966 "%d0 = %d2 <spm_string> %h3 (S)%!",
2967 "%d0 = %h2 <spm_string> %d3 (S)%!",
2968 "%d0 = %d2 <spm_string> %d3 (S)%!" };
2969 int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
2970 return templates[alt];
2971 }
2972 [(set_attr "type" "dsp32")])
2974 ;; V2HI vector insns
2976 (define_insn "addv2hi3"
2977 [(set (match_operand:V2HI 0 "register_operand" "=d")
2978 (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2979 (match_operand:V2HI 2 "register_operand" "d")))]
2980 ""
2981 "%0 = %1 +|+ %2%!"
2982 [(set_attr "type" "dsp32")])
2984 (define_insn "ssaddv2hi3"
2985 [(set (match_operand:V2HI 0 "register_operand" "=d")
2986 (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2987 (match_operand:V2HI 2 "register_operand" "d")))]
2988 ""
2989 "%0 = %1 +|+ %2 (S)%!"
2990 [(set_attr "type" "dsp32")])
2992 (define_insn "subv2hi3"
2993 [(set (match_operand:V2HI 0 "register_operand" "=d")
2994 (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2995 (match_operand:V2HI 2 "register_operand" "d")))]
2996 ""
2997 "%0 = %1 -|- %2%!"
2998 [(set_attr "type" "dsp32")])
3000 (define_insn "sssubv2hi3"
3001 [(set (match_operand:V2HI 0 "register_operand" "=d")
3002 (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
3003 (match_operand:V2HI 2 "register_operand" "d")))]
3004 ""
3005 "%0 = %1 -|- %2 (S)%!"
3006 [(set_attr "type" "dsp32")])
3008 (define_insn "addsubv2hi3"
3009 [(set (match_operand:V2HI 0 "register_operand" "=d")
3010 (vec_concat:V2HI
3011 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3012 (parallel [(const_int 0)]))
3013 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3014 (parallel [(const_int 0)])))
3015 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
3016 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3017 ""
3018 "%0 = %1 +|- %2%!"
3019 [(set_attr "type" "dsp32")])
3021 (define_insn "subaddv2hi3"
3022 [(set (match_operand:V2HI 0 "register_operand" "=d")
3023 (vec_concat:V2HI
3024 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3025 (parallel [(const_int 0)]))
3026 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3027 (parallel [(const_int 0)])))
3028 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
3029 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3030 ""
3031 "%0 = %1 -|+ %2%!"
3032 [(set_attr "type" "dsp32")])
3034 (define_insn "ssaddsubv2hi3"
3035 [(set (match_operand:V2HI 0 "register_operand" "=d")
3036 (vec_concat:V2HI
3037 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3038 (parallel [(const_int 0)]))
3039 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3040 (parallel [(const_int 0)])))
3041 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
3042 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3043 ""
3044 "%0 = %1 +|- %2 (S)%!"
3045 [(set_attr "type" "dsp32")])
3047 (define_insn "sssubaddv2hi3"
3048 [(set (match_operand:V2HI 0 "register_operand" "=d")
3049 (vec_concat:V2HI
3050 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3051 (parallel [(const_int 0)]))
3052 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3053 (parallel [(const_int 0)])))
3054 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
3055 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3056 ""
3057 "%0 = %1 -|+ %2 (S)%!"
3058 [(set_attr "type" "dsp32")])
3060 (define_insn "sublohiv2hi3"
3061 [(set (match_operand:HI 0 "register_operand" "=d")
3062 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3063 (parallel [(const_int 1)]))
3064 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3065 (parallel [(const_int 0)]))))]
3066 ""
3067 "%h0 = %d1 - %h2%!"
3068 [(set_attr "type" "dsp32")])
3070 (define_insn "subhilov2hi3"
3071 [(set (match_operand:HI 0 "register_operand" "=d")
3072 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3073 (parallel [(const_int 0)]))
3074 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3075 (parallel [(const_int 1)]))))]
3076 ""
3077 "%h0 = %h1 - %d2%!"
3078 [(set_attr "type" "dsp32")])
3080 (define_insn "sssublohiv2hi3"
3081 [(set (match_operand:HI 0 "register_operand" "=d")
3082 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3083 (parallel [(const_int 1)]))
3084 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3085 (parallel [(const_int 0)]))))]
3086 ""
3087 "%h0 = %d1 - %h2 (S)%!"
3088 [(set_attr "type" "dsp32")])
3090 (define_insn "sssubhilov2hi3"
3091 [(set (match_operand:HI 0 "register_operand" "=d")
3092 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3093 (parallel [(const_int 0)]))
3094 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3095 (parallel [(const_int 1)]))))]
3096 ""
3097 "%h0 = %h1 - %d2 (S)%!"
3098 [(set_attr "type" "dsp32")])
3100 (define_insn "addlohiv2hi3"
3101 [(set (match_operand:HI 0 "register_operand" "=d")
3102 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3103 (parallel [(const_int 1)]))
3104 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3105 (parallel [(const_int 0)]))))]
3106 ""
3107 "%h0 = %d1 + %h2%!"
3108 [(set_attr "type" "dsp32")])
3110 (define_insn "addhilov2hi3"
3111 [(set (match_operand:HI 0 "register_operand" "=d")
3112 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3113 (parallel [(const_int 0)]))
3114 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3115 (parallel [(const_int 1)]))))]
3116 ""
3117 "%h0 = %h1 + %d2%!"
3118 [(set_attr "type" "dsp32")])
3120 (define_insn "ssaddlohiv2hi3"
3121 [(set (match_operand:HI 0 "register_operand" "=d")
3122 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3123 (parallel [(const_int 1)]))
3124 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3125 (parallel [(const_int 0)]))))]
3126 ""
3127 "%h0 = %d1 + %h2 (S)%!"
3128 [(set_attr "type" "dsp32")])
3130 (define_insn "ssaddhilov2hi3"
3131 [(set (match_operand:HI 0 "register_operand" "=d")
3132 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3133 (parallel [(const_int 0)]))
3134 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3135 (parallel [(const_int 1)]))))]
3136 ""
3137 "%h0 = %h1 + %d2 (S)%!"
3138 [(set_attr "type" "dsp32")])
3140 (define_insn "sminv2hi3"
3141 [(set (match_operand:V2HI 0 "register_operand" "=d")
3142 (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
3143 (match_operand:V2HI 2 "register_operand" "d")))]
3144 ""
3145 "%0 = MIN (%1, %2) (V)%!"
3146 [(set_attr "type" "dsp32")])
3148 (define_insn "smaxv2hi3"
3149 [(set (match_operand:V2HI 0 "register_operand" "=d")
3150 (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
3151 (match_operand:V2HI 2 "register_operand" "d")))]
3152 ""
3153 "%0 = MAX (%1, %2) (V)%!"
3154 [(set_attr "type" "dsp32")])
3156 ;; Multiplications.
3158 ;; The Blackfin allows a lot of different options, and we need many patterns to
3159 ;; cover most of the hardware's abilities.
3160 ;; There are a few simple patterns using MULT rtx codes, but most of them use
3161 ;; an unspec with a const_int operand that determines which flag to use in the
3162 ;; instruction.
3163 ;; There are variants for single and parallel multiplications.
3164 ;; There are variants which just use 16-bit lowparts as inputs, and variants
3165 ;; which allow the user to choose just which halves to use as input values.
3166 ;; There are variants which set D registers, variants which set accumulators,
3167 ;; variants which set both, some of them optionally using the accumulators as
3168 ;; inputs for multiply-accumulate operations.
3170 (define_insn "flag_mulhi"
3171 [(set (match_operand:HI 0 "register_operand" "=d")
3172 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
3173 (match_operand:HI 2 "register_operand" "d")
3174 (match_operand 3 "const_int_operand" "n")]
3175 UNSPEC_MUL_WITH_FLAG))]
3176 ""
3177 "%h0 = %h1 * %h2 %M3%!"
3178 [(set_attr "type" "dsp32")])
3180 (define_insn "flag_mulhi_parts"
3181 [(set (match_operand:HI 0 "register_operand" "=d")
3182 (unspec:HI [(vec_select:HI
3183 (match_operand:V2HI 1 "register_operand" "d")
3184 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3185 (vec_select:HI
3186 (match_operand:V2HI 2 "register_operand" "d")
3187 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
3188 (match_operand 5 "const_int_operand" "n")]
3189 UNSPEC_MUL_WITH_FLAG))]
3190 ""
3191 {
3192 const char *templates[] = {
3193 "%h0 = %h1 * %h2 %M5%!",
3194 "%h0 = %d1 * %h2 %M5%!",
3195 "%h0 = %h1 * %d2 %M5%!",
3196 "%h0 = %d1 * %d2 %M5%!" };
3197 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3198 return templates[alt];
3199 }
3200 [(set_attr "type" "dsp32")])
3202 (define_insn "flag_mulhisi"
3203 [(set (match_operand:SI 0 "register_operand" "=d")
3204 (unspec:SI [(match_operand:HI 1 "register_operand" "d")
3205 (match_operand:HI 2 "register_operand" "d")
3206 (match_operand 3 "const_int_operand" "n")]
3207 UNSPEC_MUL_WITH_FLAG))]
3208 ""
3209 "%0 = %h1 * %h2 %M3%!"
3210 [(set_attr "type" "dsp32")])
3212 (define_insn "flag_mulhisi_parts"
3213 [(set (match_operand:SI 0 "register_operand" "=d")
3214 (unspec:SI [(vec_select:HI
3215 (match_operand:V2HI 1 "register_operand" "d")
3216 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3217 (vec_select:HI
3218 (match_operand:V2HI 2 "register_operand" "d")
3219 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
3220 (match_operand 5 "const_int_operand" "n")]
3221 UNSPEC_MUL_WITH_FLAG))]
3222 ""
3223 {
3224 const char *templates[] = {
3225 "%0 = %h1 * %h2 %M5%!",
3226 "%0 = %d1 * %h2 %M5%!",
3227 "%0 = %h1 * %d2 %M5%!",
3228 "%0 = %d1 * %d2 %M5%!" };
3229 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3230 return templates[alt];
3231 }
3232 [(set_attr "type" "dsp32")])
3234 ;; Three alternatives here to cover all possible allocations:
3235 ;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG
3236 ;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG
3237 ;; 2. mac flag is usable in any accumulator - use A1 and odd DREG
3238 ;; Other patterns which don't have a DREG destination can collapse cases
3239 ;; 1 and 2 into one.
3240 (define_insn "flag_machi"
3241 [(set (match_operand:HI 0 "register_operand" "=W,D,W")
3242 (unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d")
3243 (match_operand:HI 3 "register_operand" "d,d,d")
3244 (match_operand 4 "register_operand" "1,1,1")
3245 (match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")
3246 (match_operand 6 "const_int_operand" "PB,PA,PA")]
3247 UNSPEC_MAC_WITH_FLAG))
3248 (set (match_operand:PDI 1 "register_operand" "=B,A,B")
3249 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
3250 (match_dup 4) (match_dup 5)]
3251 UNSPEC_MAC_WITH_FLAG))]
3252 ""
3253 "%h0 = (%1 %b5 %h2 * %h3) %M6%!"
3254 [(set_attr "type" "dsp32")])
3256 (define_insn "flag_machi_acconly"
3257 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3258 (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
3259 (match_operand:HI 2 "register_operand" "d,d")
3260 (match_operand 3 "register_operand" "0,0")
3261 (match_operand 4 "const01_operand" "P0P1,P0P1")
3262 (match_operand 5 "const_int_operand" "PB,PA")]
3263 UNSPEC_MAC_WITH_FLAG))]
3264 ""
3265 "%0 %b4 %h1 * %h2 %M5%!"
3266 [(set_attr "type" "dsp32")])
3268 (define_insn "flag_machi_parts_acconly"
3269 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3270 (unspec:PDI [(vec_select:HI
3271 (match_operand:V2HI 1 "register_operand" "d,d")
3272 (parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")]))
3273 (vec_select:HI
3274 (match_operand:V2HI 2 "register_operand" "d,d")
3275 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")]))
3276 (match_operand:PDI 5 "register_operand" "0,0")
3277 (match_operand 6 "const01_operand" "P0P1,P0P1")
3278 (match_operand 7 "const_int_operand" "PB,PA")]
3279 UNSPEC_MAC_WITH_FLAG))]
3280 ""
3281 {
3282 const char *templates[] = {
3283 "%0 %b6 %h1 * %h2 %M7%!",
3284 "%0 %b6 %d1 * %h2 %M7%!",
3285 "%0 %b6 %h1 * %d2 %M7%!",
3286 "%0 %b6 %d1 * %d2 %M7%!"
3287 };
3288 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3289 return templates[alt];
3290 }
3291 [(set_attr "type" "dsp32")])
3293 (define_insn "flag_macinithi"
3294 [(set (match_operand:HI 0 "register_operand" "=W,D,W")
3295 (unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d")
3296 (match_operand:HI 2 "register_operand" "d,d,d")
3297 (match_operand 3 "const_int_operand" "PB,PA,PA")]
3298 UNSPEC_MAC_WITH_FLAG))
3299 (set (match_operand:PDI 4 "register_operand" "=B,A,B")
3300 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
3301 UNSPEC_MAC_WITH_FLAG))]
3302 ""
3303 "%h0 = (%4 = %h1 * %h2) %M3%!"
3304 [(set_attr "type" "dsp32")])
3306 (define_insn "flag_macinit1hi"
3307 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3308 (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
3309 (match_operand:HI 2 "register_operand" "d,d")
3310 (match_operand 3 "const_int_operand" "PB,PA")]
3311 UNSPEC_MAC_WITH_FLAG))]
3312 ""
3313 "%0 = %h1 * %h2 %M3%!"
3314 [(set_attr "type" "dsp32")])
3316 (define_insn "mulv2hi3"
3317 [(set (match_operand:V2HI 0 "register_operand" "=d")
3318 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
3319 (match_operand:V2HI 2 "register_operand" "d")))]
3320 ""
3321 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!"
3322 [(set_attr "type" "dsp32")])
3324 (define_insn "flag_mulv2hi"
3325 [(set (match_operand:V2HI 0 "register_operand" "=d")
3326 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
3327 (match_operand:V2HI 2 "register_operand" "d")
3328 (match_operand 3 "const_int_operand" "n")]
3329 UNSPEC_MUL_WITH_FLAG))]
3330 ""
3331 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!"
3332 [(set_attr "type" "dsp32")])
3334 (define_insn "flag_mulv2hi_parts"
3335 [(set (match_operand:V2HI 0 "register_operand" "=d")
3336 (unspec:V2HI [(vec_concat:V2HI
3337 (vec_select:HI
3338 (match_operand:V2HI 1 "register_operand" "d")
3339 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3340 (vec_select:HI
3341 (match_dup 1)
3342 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3343 (vec_concat:V2HI
3344 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3345 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3346 (vec_select:HI (match_dup 2)
3347 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3348 (match_operand 7 "const_int_operand" "n")]
3349 UNSPEC_MUL_WITH_FLAG))]
3350 ""
3351 {
3352 const char *templates[] = {
3353 "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!",
3354 "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!",
3355 "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!",
3356 "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!",
3357 "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!",
3358 "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!",
3359 "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!",
3360 "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!",
3361 "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!",
3362 "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!",
3363 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!",
3364 "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!",
3365 "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!",
3366 "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!",
3367 "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!",
3368 "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" };
3369 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3370 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3371 return templates[alt];
3372 }
3373 [(set_attr "type" "dsp32")])
3375 ;; A slightly complicated pattern.
3376 ;; Operand 0 is the halfword output; operand 11 is the accumulator output
3377 ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
3378 ;; parts of these 2x16 bit registers to use.
3379 ;; Operand 7 is the accumulator input.
3380 ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
3381 ;; Operand 10 is the macflag to be used.
3382 (define_insn "flag_macv2hi_parts"
3383 [(set (match_operand:V2HI 0 "register_operand" "=d")
3384 (unspec:V2HI [(vec_concat:V2HI
3385 (vec_select:HI
3386 (match_operand:V2HI 1 "register_operand" "d")
3387 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3388 (vec_select:HI
3389 (match_dup 1)
3390 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3391 (vec_concat:V2HI
3392 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3393 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3394 (vec_select:HI (match_dup 2)
3395 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3396 (match_operand:V2PDI 7 "register_operand" "e")
3397 (match_operand 8 "const01_operand" "P0P1")
3398 (match_operand 9 "const01_operand" "P0P1")
3399 (match_operand 10 "const_int_operand" "n")]
3400 UNSPEC_MAC_WITH_FLAG))
3401 (set (match_operand:V2PDI 11 "register_operand" "=e")
3402 (unspec:V2PDI [(vec_concat:V2HI
3403 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3404 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3405 (vec_concat:V2HI
3406 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3407 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3408 (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
3409 UNSPEC_MAC_WITH_FLAG))]
3410 ""
3411 {
3412 const char *templates[] = {
3413 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3414 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3415 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3416 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3417 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3418 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3419 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3420 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3421 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3422 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3423 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3424 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3425 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3426 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3427 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3428 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" };
3429 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3430 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3431 return templates[alt];
3432 }
3433 [(set_attr "type" "dsp32")])
3435 (define_insn "flag_macv2hi_parts_acconly"
3436 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3437 (unspec:V2PDI [(vec_concat:V2HI
3438 (vec_select:HI
3439 (match_operand:V2HI 1 "register_operand" "d")
3440 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3441 (vec_select:HI
3442 (match_dup 1)
3443 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3444 (vec_concat:V2HI
3445 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3446 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3447 (vec_select:HI (match_dup 2)
3448 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3449 (match_operand:V2PDI 7 "register_operand" "e")
3450 (match_operand 8 "const01_operand" "P0P1")
3451 (match_operand 9 "const01_operand" "P0P1")
3452 (match_operand 10 "const_int_operand" "n")]
3453 UNSPEC_MAC_WITH_FLAG))]
3454 ""
3455 {
3456 const char *templates[] = {
3457 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3458 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3459 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3460 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3461 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3462 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3463 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3464 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3465 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3466 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3467 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3468 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3469 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3470 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3471 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!",
3472 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" };
3473 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3474 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3475 return templates[alt];
3476 }
3477 [(set_attr "type" "dsp32")])
3479 ;; Same as above, but initializing the accumulators and therefore a couple fewer
3480 ;; necessary operands.
3481 (define_insn "flag_macinitv2hi_parts"
3482 [(set (match_operand:V2HI 0 "register_operand" "=d")
3483 (unspec:V2HI [(vec_concat:V2HI
3484 (vec_select:HI
3485 (match_operand:V2HI 1 "register_operand" "d")
3486 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3487 (vec_select:HI
3488 (match_dup 1)
3489 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3490 (vec_concat:V2HI
3491 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3492 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3493 (vec_select:HI (match_dup 2)
3494 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3495 (match_operand 7 "const_int_operand" "n")]
3496 UNSPEC_MAC_WITH_FLAG))
3497 (set (match_operand:V2PDI 8 "register_operand" "=e")
3498 (unspec:V2PDI [(vec_concat:V2HI
3499 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3500 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3501 (vec_concat:V2HI
3502 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3503 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3504 (match_dup 7)]
3505 UNSPEC_MAC_WITH_FLAG))]
3506 ""
3507 {
3508 const char *templates[] = {
3509 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3510 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3511 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3512 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3513 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3514 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3515 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3516 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3517 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3518 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3519 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3520 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3521 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3522 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3523 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!",
3524 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" };
3525 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3526 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3527 return templates[alt];
3528 }
3529 [(set_attr "type" "dsp32")])
3531 (define_insn "flag_macinit1v2hi_parts"
3532 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3533 (unspec:V2PDI [(vec_concat:V2HI
3534 (vec_select:HI
3535 (match_operand:V2HI 1 "register_operand" "d")
3536 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3537 (vec_select:HI
3538 (match_dup 1)
3539 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3540 (vec_concat:V2HI
3541 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3542 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3543 (vec_select:HI (match_dup 2)
3544 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3545 (match_operand 7 "const_int_operand" "n")]
3546 UNSPEC_MAC_WITH_FLAG))]
3547 ""
3548 {
3549 const char *templates[] = {
3550 "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!",
3551 "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!",
3552 "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!",
3553 "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!",
3554 "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!",
3555 "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!",
3556 "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!",
3557 "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!",
3558 "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!",
3559 "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!",
3560 "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!",
3561 "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!",
3562 "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!",
3563 "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!",
3564 "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!",
3565 "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" };
3566 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3567 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3568 return templates[alt];
3569 }
3570 [(set_attr "type" "dsp32")])
3572 ;; A mixture of multiply and multiply-accumulate for when we only want to
3573 ;; initialize one part.
3574 (define_insn "flag_mul_macv2hi_parts_acconly"
3575 [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
3576 (unspec:PDI [(vec_select:HI
3577 (match_operand:V2HI 2 "register_operand" "d,d,d")
3578 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
3579 (vec_select:HI
3580 (match_operand:V2HI 3 "register_operand" "d,d,d")
3581 (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
3582 (match_operand 10 "const_int_operand" "PB,PA,PA")]
3583 UNSPEC_MUL_WITH_FLAG))
3584 (set (match_operand:PDI 1 "register_operand" "=B,e,e")
3585 (unspec:PDI [(vec_select:HI
3586 (match_dup 2)
3587 (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
3588 (vec_select:HI
3589 (match_dup 3)
3590 (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
3591 (match_operand:PDI 8 "register_operand" "1,1,1")
3592 (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
3593 (match_operand 11 "const_int_operand" "PA,PB,PA")]
3594 UNSPEC_MAC_WITH_FLAG))]
3595 "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
3596 {
3597 rtx xops[6];
3598 const char *templates[] = {
3599 "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
3600 "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
3601 "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
3602 "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
3603 "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
3604 "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
3605 "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
3606 "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
3607 "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
3608 "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
3609 "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
3610 "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
3611 "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
3612 "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
3613 "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!",
3614 "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" };
3615 int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
3616 + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
3617 xops[0] = operands[0];
3618 xops[1] = operands[1];
3619 xops[2] = operands[2];
3620 xops[3] = operands[3];
3621 xops[4] = operands[9];
3622 xops[5] = which_alternative == 0 ? operands[10] : operands[11];
3623 output_asm_insn (templates[alt], xops);
3624 return "";
3625 }
3626 [(set_attr "type" "dsp32")])
3629 (define_code_iterator s_or_u [sign_extend zero_extend])
3630 (define_code_attr su_optab [(sign_extend "mul")
3631 (zero_extend "umul")])
3632 (define_code_attr su_modifier [(sign_extend "IS")
3633 (zero_extend "FU")])
3635 (define_insn "<su_optab>hisi_ll"
3636 [(set (match_operand:SI 0 "register_operand" "=d")
3637 (mult:SI (s_or_u:SI
3638 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3639 (parallel [(const_int 0)])))
3640 (s_or_u:SI
3641 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3642 (parallel [(const_int 0)])))))]
3643 ""
3644 "%0 = %h1 * %h2 (<su_modifier>)%!"
3645 [(set_attr "type" "dsp32")])
3647 (define_insn "<su_optab>hisi_lh"
3648 [(set (match_operand:SI 0 "register_operand" "=d")
3649 (mult:SI (s_or_u:SI
3650 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3651 (parallel [(const_int 0)])))
3652 (s_or_u:SI
3653 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3654 (parallel [(const_int 1)])))))]
3655 ""
3656 "%0 = %h1 * %d2 (<su_modifier>)%!"
3657 [(set_attr "type" "dsp32")])
3659 (define_insn "<su_optab>hisi_hl"
3660 [(set (match_operand:SI 0 "register_operand" "=d")
3661 (mult:SI (s_or_u:SI
3662 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3663 (parallel [(const_int 1)])))
3664 (s_or_u:SI
3665 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3666 (parallel [(const_int 0)])))))]
3667 ""
3668 "%0 = %d1 * %h2 (<su_modifier>)%!"
3669 [(set_attr "type" "dsp32")])
3671 (define_insn "<su_optab>hisi_hh"
3672 [(set (match_operand:SI 0 "register_operand" "=d")
3673 (mult:SI (s_or_u:SI
3674 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3675 (parallel [(const_int 1)])))
3676 (s_or_u:SI
3677 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3678 (parallel [(const_int 1)])))))]
3679 ""
3680 "%0 = %d1 * %d2 (<su_modifier>)%!"
3681 [(set_attr "type" "dsp32")])
3683 ;; Additional variants for signed * unsigned multiply.
3685 (define_insn "usmulhisi_ull"
3686 [(set (match_operand:SI 0 "register_operand" "=W")
3687 (mult:SI (zero_extend:SI
3688 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3689 (parallel [(const_int 0)])))
3690 (sign_extend:SI
3691 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3692 (parallel [(const_int 0)])))))]
3693 ""
3694 "%0 = %h2 * %h1 (IS,M)%!"
3695 [(set_attr "type" "dsp32")])
3697 (define_insn "usmulhisi_ulh"
3698 [(set (match_operand:SI 0 "register_operand" "=W")
3699 (mult:SI (zero_extend:SI
3700 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3701 (parallel [(const_int 0)])))
3702 (sign_extend:SI
3703 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3704 (parallel [(const_int 1)])))))]
3705 ""
3706 "%0 = %d2 * %h1 (IS,M)%!"
3707 [(set_attr "type" "dsp32")])
3709 (define_insn "usmulhisi_uhl"
3710 [(set (match_operand:SI 0 "register_operand" "=W")
3711 (mult:SI (zero_extend:SI
3712 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3713 (parallel [(const_int 1)])))
3714 (sign_extend:SI
3715 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3716 (parallel [(const_int 0)])))))]
3717 ""
3718 "%0 = %h2 * %d1 (IS,M)%!"
3719 [(set_attr "type" "dsp32")])
3721 (define_insn "usmulhisi_uhh"
3722 [(set (match_operand:SI 0 "register_operand" "=W")
3723 (mult:SI (zero_extend:SI
3724 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3725 (parallel [(const_int 1)])))
3726 (sign_extend:SI
3727 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3728 (parallel [(const_int 1)])))))]
3729 ""
3730 "%0 = %d2 * %d1 (IS,M)%!"
3731 [(set_attr "type" "dsp32")])
3733 ;; Parallel versions of these operations. First, normal signed or unsigned
3734 ;; multiplies.
3736 (define_insn "<su_optab>hisi_ll_lh"
3737 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3738 (mult:SI (s_or_u:SI
3739 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3740 (parallel [(const_int 0)])))
3741 (s_or_u:SI
3742 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3743 (parallel [(const_int 0)])))))
3744 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3745 (mult:SI (s_or_u:SI
3746 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3747 (s_or_u:SI
3748 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3749 ""
3750 "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
3751 [(set_attr "type" "dsp32")])
3753 (define_insn "<su_optab>hisi_ll_hl"
3754 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3755 (mult:SI (s_or_u:SI
3756 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3757 (parallel [(const_int 0)])))
3758 (s_or_u:SI
3759 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3760 (parallel [(const_int 0)])))))
3761 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3762 (mult:SI (s_or_u:SI
3763 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3764 (s_or_u:SI
3765 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3766 ""
3767 "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
3768 [(set_attr "type" "dsp32")])
3770 (define_insn "<su_optab>hisi_ll_hh"
3771 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3772 (mult:SI (s_or_u:SI
3773 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3774 (parallel [(const_int 0)])))
3775 (s_or_u:SI
3776 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3777 (parallel [(const_int 0)])))))
3778 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3779 (mult:SI (s_or_u:SI
3780 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3781 (s_or_u:SI
3782 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3783 ""
3784 "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3785 [(set_attr "type" "dsp32")])
3787 (define_insn "<su_optab>hisi_lh_hl"
3788 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3789 (mult:SI (s_or_u:SI
3790 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3791 (parallel [(const_int 0)])))
3792 (s_or_u:SI
3793 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3794 (parallel [(const_int 1)])))))
3795 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3796 (mult:SI (s_or_u:SI
3797 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3798 (s_or_u:SI
3799 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3800 ""
3801 "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
3802 [(set_attr "type" "dsp32")])
3804 (define_insn "<su_optab>hisi_lh_hh"
3805 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3806 (mult:SI (s_or_u:SI
3807 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3808 (parallel [(const_int 0)])))
3809 (s_or_u:SI
3810 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3811 (parallel [(const_int 1)])))))
3812 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3813 (mult:SI (s_or_u:SI
3814 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3815 (s_or_u:SI
3816 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3817 ""
3818 "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
3819 [(set_attr "type" "dsp32")])
3821 (define_insn "<su_optab>hisi_hl_hh"
3822 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3823 (mult:SI (s_or_u:SI
3824 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3825 (parallel [(const_int 1)])))
3826 (s_or_u:SI
3827 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3828 (parallel [(const_int 0)])))))
3829 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3830 (mult:SI (s_or_u:SI
3831 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3832 (s_or_u:SI
3833 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3834 ""
3835 "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3836 [(set_attr "type" "dsp32")])
3838 ;; Special signed * unsigned variants.
3840 (define_insn "usmulhisi_ll_lul"
3841 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3842 (mult:SI (sign_extend:SI
3843 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3844 (parallel [(const_int 0)])))
3845 (sign_extend:SI
3846 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3847 (parallel [(const_int 0)])))))
3848 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3849 (mult:SI (sign_extend:SI
3850 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3851 (zero_extend:SI
3852 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3853 ""
3854 "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3855 [(set_attr "type" "dsp32")])
3857 (define_insn "usmulhisi_ll_luh"
3858 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3859 (mult:SI (sign_extend:SI
3860 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3861 (parallel [(const_int 0)])))
3862 (sign_extend:SI
3863 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3864 (parallel [(const_int 0)])))))
3865 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3866 (mult:SI (sign_extend:SI
3867 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3868 (zero_extend:SI
3869 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3870 ""
3871 "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3872 [(set_attr "type" "dsp32")])
3874 (define_insn "usmulhisi_ll_hul"
3875 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3876 (mult:SI (sign_extend:SI
3877 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3878 (parallel [(const_int 0)])))
3879 (sign_extend:SI
3880 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3881 (parallel [(const_int 0)])))))
3882 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3883 (mult:SI (sign_extend:SI
3884 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3885 (zero_extend:SI
3886 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3887 ""
3888 "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3889 [(set_attr "type" "dsp32")])
3891 (define_insn "usmulhisi_ll_huh"
3892 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3893 (mult:SI (sign_extend:SI
3894 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3895 (parallel [(const_int 0)])))
3896 (sign_extend:SI
3897 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3898 (parallel [(const_int 0)])))))
3899 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3900 (mult:SI (sign_extend:SI
3901 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3902 (zero_extend:SI
3903 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3904 ""
3905 "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3906 [(set_attr "type" "dsp32")])
3908 (define_insn "usmulhisi_lh_lul"
3909 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3910 (mult:SI (sign_extend:SI
3911 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3912 (parallel [(const_int 0)])))
3913 (sign_extend:SI
3914 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3915 (parallel [(const_int 1)])))))
3916 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3917 (mult:SI (sign_extend:SI
3918 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3919 (zero_extend:SI
3920 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3921 ""
3922 "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3923 [(set_attr "type" "dsp32")])
3925 (define_insn "usmulhisi_lh_luh"
3926 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3927 (mult:SI (sign_extend:SI
3928 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3929 (parallel [(const_int 0)])))
3930 (sign_extend:SI
3931 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3932 (parallel [(const_int 1)])))))
3933 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3934 (mult:SI (sign_extend:SI
3935 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3936 (zero_extend:SI
3937 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3938 ""
3939 "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3940 [(set_attr "type" "dsp32")])
3942 (define_insn "usmulhisi_lh_hul"
3943 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3944 (mult:SI (sign_extend:SI
3945 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3946 (parallel [(const_int 0)])))
3947 (sign_extend:SI
3948 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3949 (parallel [(const_int 1)])))))
3950 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3951 (mult:SI (sign_extend:SI
3952 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3953 (zero_extend:SI
3954 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3955 ""
3956 "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3957 [(set_attr "type" "dsp32")])
3959 (define_insn "usmulhisi_lh_huh"
3960 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3961 (mult:SI (sign_extend:SI
3962 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3963 (parallel [(const_int 0)])))
3964 (sign_extend:SI
3965 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3966 (parallel [(const_int 1)])))))
3967 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3968 (mult:SI (sign_extend:SI
3969 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3970 (zero_extend:SI
3971 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3972 ""
3973 "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
3974 [(set_attr "type" "dsp32")])
3976 (define_insn "usmulhisi_hl_lul"
3977 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3978 (mult:SI (sign_extend:SI
3979 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3980 (parallel [(const_int 1)])))
3981 (sign_extend:SI
3982 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3983 (parallel [(const_int 0)])))))
3984 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3985 (mult:SI (sign_extend:SI
3986 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3987 (zero_extend:SI
3988 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3989 ""
3990 "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3991 [(set_attr "type" "dsp32")])
3993 (define_insn "usmulhisi_hl_luh"
3994 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3995 (mult:SI (sign_extend:SI
3996 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3997 (parallel [(const_int 1)])))
3998 (sign_extend:SI
3999 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4000 (parallel [(const_int 0)])))))
4001 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4002 (mult:SI (sign_extend:SI
4003 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
4004 (zero_extend:SI
4005 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
4006 ""
4007 "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
4008 [(set_attr "type" "dsp32")])
4010 (define_insn "usmulhisi_hl_hul"
4011 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
4012 (mult:SI (sign_extend:SI
4013 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
4014 (parallel [(const_int 1)])))
4015 (sign_extend:SI
4016 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4017 (parallel [(const_int 0)])))))
4018 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4019 (mult:SI (sign_extend:SI
4020 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4021 (zero_extend:SI
4022 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
4023 ""
4024 "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
4025 [(set_attr "type" "dsp32")])
4027 (define_insn "usmulhisi_hl_huh"
4028 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
4029 (mult:SI (sign_extend:SI
4030 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
4031 (parallel [(const_int 1)])))
4032 (sign_extend:SI
4033 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4034 (parallel [(const_int 0)])))))
4035 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4036 (mult:SI (sign_extend:SI
4037 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4038 (zero_extend:SI
4039 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
4040 ""
4041 "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
4042 [(set_attr "type" "dsp32")])
4044 (define_insn "usmulhisi_hh_lul"
4045 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
4046 (mult:SI (sign_extend:SI
4047 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
4048 (parallel [(const_int 1)])))
4049 (sign_extend:SI
4050 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4051 (parallel [(const_int 1)])))))
4052 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4053 (mult:SI (sign_extend:SI
4054 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
4055 (zero_extend:SI
4056 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
4057 ""
4058 "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
4059 [(set_attr "type" "dsp32")])
4061 (define_insn "usmulhisi_hh_luh"
4062 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
4063 (mult:SI (sign_extend:SI
4064 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
4065 (parallel [(const_int 1)])))
4066 (sign_extend:SI
4067 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4068 (parallel [(const_int 1)])))))
4069 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4070 (mult:SI (sign_extend:SI
4071 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
4072 (zero_extend:SI
4073 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
4074 ""
4075 "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
4076 [(set_attr "type" "dsp32")])
4078 (define_insn "usmulhisi_hh_hul"
4079 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
4080 (mult:SI (sign_extend:SI
4081 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
4082 (parallel [(const_int 1)])))
4083 (sign_extend:SI
4084 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4085 (parallel [(const_int 1)])))))
4086 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4087 (mult:SI (sign_extend:SI
4088 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4089 (zero_extend:SI
4090 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
4091 ""
4092 "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
4093 [(set_attr "type" "dsp32")])
4095 (define_insn "usmulhisi_hh_huh"
4096 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
4097 (mult:SI (sign_extend:SI
4098 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
4099 (parallel [(const_int 1)])))
4100 (sign_extend:SI
4101 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
4102 (parallel [(const_int 1)])))))
4103 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
4104 (mult:SI (sign_extend:SI
4105 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4106 (zero_extend:SI
4107 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
4108 ""
4109 "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
4110 [(set_attr "type" "dsp32")])
4112 ;; Vector neg/abs.
4114 (define_insn "ssnegv2hi2"
4115 [(set (match_operand:V2HI 0 "register_operand" "=d")
4116 (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
4117 ""
4118 "%0 = - %1 (V)%!"
4119 [(set_attr "type" "dsp32")])
4121 (define_insn "ssabsv2hi2"
4122 [(set (match_operand:V2HI 0 "register_operand" "=d")
4123 (ss_abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
4124 ""
4125 "%0 = ABS %1 (V)%!"
4126 [(set_attr "type" "dsp32")])
4128 ;; Shifts.
4130 (define_insn "ssashiftv2hi3"
4131 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
4132 (if_then_else:V2HI
4133 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4134 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
4135 (match_dup 2))
4136 (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
4137 ""
4138 "@
4139 %0 = ASHIFT %1 BY %h2 (V, S)%!
4140 %0 = %1 << %2 (V,S)%!
4141 %0 = %1 >>> %N2 (V,S)%!"
4142 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4144 (define_insn "ssashifthi3"
4145 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4146 (if_then_else:HI
4147 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4148 (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
4149 (match_dup 2))
4150 (ss_ashift:HI (match_dup 1) (match_dup 2))))]
4151 ""
4152 "@
4153 %0 = ASHIFT %1 BY %h2 (V, S)%!
4154 %0 = %1 << %2 (V,S)%!
4155 %0 = %1 >>> %N2 (V,S)%!"
4156 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4158 (define_insn "ssashiftsi3"
4159 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4160 (if_then_else:SI
4161 (lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0))
4162 (ashiftrt:SI (match_operand:HI 1 "register_operand" "d,d,d")
4163 (match_dup 2))
4164 (ss_ashift:SI (match_dup 1) (match_dup 2))))]
4165 ""
4166 "@
4167 %0 = ASHIFT %1 BY %h2 (S)%!
4168 %0 = %1 << %2 (S)%!
4169 %0 = %1 >>> %N2 (S)%!"
4170 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4172 (define_insn "lshiftv2hi3"
4173 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
4174 (if_then_else:V2HI
4175 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4176 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
4177 (match_dup 2))
4178 (ashift:V2HI (match_dup 1) (match_dup 2))))]
4179 ""
4180 "@
4181 %0 = LSHIFT %1 BY %h2 (V)%!
4182 %0 = %1 << %2 (V)%!
4183 %0 = %1 >> %N2 (V)%!"
4184 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4186 (define_insn "lshifthi3"
4187 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4188 (if_then_else:HI
4189 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4190 (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
4191 (match_dup 2))
4192 (ashift:HI (match_dup 1) (match_dup 2))))]
4193 ""
4194 "@
4195 %0 = LSHIFT %1 BY %h2 (V)%!
4196 %0 = %1 << %2 (V)%!
4197 %0 = %1 >> %N2 (V)%!"
4198 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4200 ;; Load without alignment exception (masking off low bits)
4202 (define_insn "loadbytes"
4203 [(set (match_operand:SI 0 "register_operand" "=d")
4204 (mem:SI (and:SI (match_operand:SI 1 "register_operand" "b")
4205 (const_int -4))))]
4206 ""
4207 "DISALGNEXCPT || %0 = [%1];"
4208 [(set_attr "type" "mcld")
4209 (set_attr "length" "8")])
4211 (include "sync.md")