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Merge from mainline (163495:164578).
[official-gcc/graphite-test-results.git] / gcc / config / sh / sh.h
blob2e9ee76d3ef6e5b03c3a76463de9c8beef903fb5
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #include "config/vxworks-dummy.h"
28
29 #define TARGET_VERSION \
30 fputs (" (Hitachi SH)", stderr);
31
32 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
33 include it here, because bconfig.h is also included by gencodes.c . */
34 /* ??? No longer true. */
35 extern int code_for_indirect_jump_scratch;
36
37 #define TARGET_CPU_CPP_BUILTINS() \
38 do { \
39 builtin_define ("__sh__"); \
40 builtin_assert ("cpu=sh"); \
41 builtin_assert ("machine=sh"); \
42 switch ((int) sh_cpu) \
43 { \
44 case PROCESSOR_SH1: \
45 builtin_define ("__sh1__"); \
46 break; \
47 case PROCESSOR_SH2: \
48 builtin_define ("__sh2__"); \
49 break; \
50 case PROCESSOR_SH2E: \
51 builtin_define ("__SH2E__"); \
52 break; \
53 case PROCESSOR_SH2A: \
54 builtin_define ("__SH2A__"); \
55 builtin_define (TARGET_SH2A_DOUBLE \
56 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
57 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
58 : "__SH2A_NOFPU__"); \
59 break; \
60 case PROCESSOR_SH3: \
61 builtin_define ("__sh3__"); \
62 builtin_define ("__SH3__"); \
63 if (TARGET_HARD_SH4) \
64 builtin_define ("__SH4_NOFPU__"); \
65 break; \
66 case PROCESSOR_SH3E: \
67 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
68 break; \
69 case PROCESSOR_SH4: \
70 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
71 break; \
72 case PROCESSOR_SH4A: \
73 builtin_define ("__SH4A__"); \
74 builtin_define (TARGET_SH4 \
75 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
76 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
77 : "__SH4_NOFPU__"); \
78 break; \
79 case PROCESSOR_SH5: \
80 { \
81 builtin_define_with_value ("__SH5__", \
82 TARGET_SHMEDIA64 ? "64" : "32", 0); \
83 builtin_define_with_value ("__SHMEDIA__", \
84 TARGET_SHMEDIA ? "1" : "0", 0); \
85 if (! TARGET_FPU_DOUBLE) \
86 builtin_define ("__SH4_NOFPU__"); \
87 } \
88 } \
89 if (TARGET_FPU_ANY) \
90 builtin_define ("__SH_FPU_ANY__"); \
91 if (TARGET_FPU_DOUBLE) \
92 builtin_define ("__SH_FPU_DOUBLE__"); \
93 if (TARGET_HITACHI) \
94 builtin_define ("__HITACHI__"); \
95 if (TARGET_FMOVD) \
96 builtin_define ("__FMOVD_ENABLED__"); \
97 builtin_define (TARGET_LITTLE_ENDIAN \
98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
99 } while (0)
100
101 #define CAN_DEBUG_WITHOUT_FP
102
103 /* Value should be nonzero if functions must have frame pointers.
104 Zero means the frame pointer need not be set up (and parms may be accessed
105 via the stack pointer) in functions that seem suitable. */
106
107 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
108 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
109 #endif
110
111 #define CONDITIONAL_REGISTER_USAGE do \
112 { \
113 int regno; \
114 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
115 if (! VALID_REGISTER_P (regno)) \
116 fixed_regs[regno] = call_used_regs[regno] = 1; \
117 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
118 if (TARGET_SH5) \
119 { \
120 call_used_regs[FIRST_GENERAL_REG + 8] \
121 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
122 call_really_used_regs[FIRST_GENERAL_REG + 8] \
123 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
124 } \
125 if (TARGET_SHMEDIA) \
126 { \
127 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
128 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
129 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
130 } \
131 if (flag_pic) \
132 { \
133 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
134 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
135 } \
136 /* Renesas saves and restores mac registers on call. */ \
137 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
138 { \
139 call_really_used_regs[MACH_REG] = 0; \
140 call_really_used_regs[MACL_REG] = 0; \
141 } \
142 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
143 regno <= LAST_FP_REG; regno += 2) \
144 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
145 if (TARGET_SHMEDIA) \
146 { \
147 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
148 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
149 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
150 } \
151 else \
152 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
153 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
154 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
155 } while (0)
156 \f
157 /* Nonzero if this is an ELF target - compile time only */
158 #define TARGET_ELF 0
159
160 /* Nonzero if we should generate code using type 2E insns. */
161 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
162
163 /* Nonzero if we should generate code using type 2A insns. */
164 #define TARGET_SH2A TARGET_HARD_SH2A
165 /* Nonzero if we should generate code using type 2A SF insns. */
166 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
167 /* Nonzero if we should generate code using type 2A DF insns. */
168 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
169
170 /* Nonzero if we should generate code using type 3E insns. */
171 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
172
173 /* Nonzero if the cache line size is 32. */
174 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
175
176 /* Nonzero if we schedule for a superscalar implementation. */
177 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
178
179 /* Nonzero if the target has separate instruction and data caches. */
180 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
181
182 /* Nonzero if a double-precision FPU is available. */
183 #define TARGET_FPU_DOUBLE \
184 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
185
186 /* Nonzero if an FPU is available. */
187 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
188
189 /* Nonzero if we should generate code using type 4 insns. */
190 #undef TARGET_SH4
191 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
192
193 /* Nonzero if we're generating code for the common subset of
194 instructions present on both SH4a and SH4al-dsp. */
195 #define TARGET_SH4A_ARCH TARGET_SH4A
196
197 /* Nonzero if we're generating code for SH4a, unless the use of the
198 FPU is disabled (which makes it compatible with SH4al-dsp). */
199 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
200
201 /* Nonzero if we should generate code using the SHcompact instruction
202 set and 32-bit ABI. */
203 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
204
205 /* Nonzero if we should generate code using the SHmedia instruction
206 set and ABI. */
207 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
208
209 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
210 ABI. */
211 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
212
213 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
214 ABI. */
215 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
216
217 /* Nonzero if we should generate code using SHmedia FPU instructions. */
218 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
219
220 /* This is not used by the SH2E calling convention */
221 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
222 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
223 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
224
225 #ifndef TARGET_CPU_DEFAULT
226 #define TARGET_CPU_DEFAULT SELECT_SH1
227 #define SUPPORT_SH1 1
228 #define SUPPORT_SH2E 1
229 #define SUPPORT_SH4 1
230 #define SUPPORT_SH4_SINGLE 1
231 #define SUPPORT_SH2A 1
232 #define SUPPORT_SH2A_SINGLE 1
233 #endif
234
235 #define TARGET_DIVIDE_INV \
236 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
237 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
238 || sh_div_strategy == SH_DIV_INV_CALL \
239 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
240 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
241 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
242 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
243 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
244 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
245 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
246 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
247 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
248 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
249 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
250 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
251
252 #define SELECT_SH1 (MASK_SH1)
253 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
254 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
255 | MASK_FPU_SINGLE)
256 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
257 | MASK_HARD_SH2A_DOUBLE \
258 | MASK_SH2 | MASK_SH1)
259 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
260 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
261 | MASK_SH1 | MASK_FPU_SINGLE)
262 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
263 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
264 | MASK_SH2 | MASK_SH1)
265 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
266 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
267 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
268 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
269 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
270 | SELECT_SH3)
271 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
272 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
273 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
274 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
275 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
276 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
277 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
278 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
279 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
280 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
281 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
282
283 #if SUPPORT_SH1
284 #define SUPPORT_SH2 1
285 #endif
286 #if SUPPORT_SH2
287 #define SUPPORT_SH3 1
288 #define SUPPORT_SH2A_NOFPU 1
289 #endif
290 #if SUPPORT_SH3
291 #define SUPPORT_SH4_NOFPU 1
292 #endif
293 #if SUPPORT_SH4_NOFPU
294 #define SUPPORT_SH4A_NOFPU 1
295 #define SUPPORT_SH4AL 1
296 #endif
297
298 #if SUPPORT_SH2E
299 #define SUPPORT_SH3E 1
300 #define SUPPORT_SH2A_SINGLE_ONLY 1
301 #endif
302 #if SUPPORT_SH3E
303 #define SUPPORT_SH4_SINGLE_ONLY 1
304 #endif
305 #if SUPPORT_SH4_SINGLE_ONLY
306 #define SUPPORT_SH4A_SINGLE_ONLY 1
307 #endif
308
309 #if SUPPORT_SH4
310 #define SUPPORT_SH4A 1
311 #endif
312
313 #if SUPPORT_SH4_SINGLE
314 #define SUPPORT_SH4A_SINGLE 1
315 #endif
316
317 #if SUPPORT_SH5_COMPAT
318 #define SUPPORT_SH5_32MEDIA 1
319 #endif
320
321 #if SUPPORT_SH5_COMPACT_NOFPU
322 #define SUPPORT_SH5_32MEDIA_NOFPU 1
323 #endif
324
325 #define SUPPORT_ANY_SH5_32MEDIA \
326 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
327 #define SUPPORT_ANY_SH5_64MEDIA \
328 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
329 #define SUPPORT_ANY_SH5 \
330 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
331
332 /* Reset all target-selection flags. */
333 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
334 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
335 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
336
337 /* This defaults us to big-endian. */
338 #ifndef TARGET_ENDIAN_DEFAULT
339 #define TARGET_ENDIAN_DEFAULT 0
340 #endif
341
342 #ifndef TARGET_OPT_DEFAULT
343 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
344 #endif
345
346 #define TARGET_DEFAULT \
347 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
348
349 #ifndef SH_MULTILIB_CPU_DEFAULT
350 #define SH_MULTILIB_CPU_DEFAULT "m1"
351 #endif
352
353 #if TARGET_ENDIAN_DEFAULT
354 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
355 #else
356 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
357 #endif
358
359 #define CPP_SPEC " %(subtarget_cpp_spec) "
360
361 #ifndef SUBTARGET_CPP_SPEC
362 #define SUBTARGET_CPP_SPEC ""
363 #endif
364
365 #ifndef SUBTARGET_EXTRA_SPECS
366 #define SUBTARGET_EXTRA_SPECS
367 #endif
368
369 #define EXTRA_SPECS \
370 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
371 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
372 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
373 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
374 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
375 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
376 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
377 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
378 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
379 SUBTARGET_EXTRA_SPECS
380
381 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
382 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
383 #else
384 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
385 #endif
386
387 #define SH_ASM_SPEC \
388 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
389 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
390 %{m2a:--isa=sh2a} \
391 %{m2a-single:--isa=sh2a} \
392 %{m2a-single-only:--isa=sh2a} \
393 %{m2a-nofpu:--isa=sh2a-nofpu} \
394 %{m5-compact*:--isa=SHcompact} \
395 %{m5-32media*:--isa=SHmedia --abi=32} \
396 %{m5-64media*:--isa=SHmedia --abi=64} \
397 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
398
399 #define ASM_SPEC SH_ASM_SPEC
400
401 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
402 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
403 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
404 #else
405 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
406 #endif
407 #endif
408
409 #if STRICT_NOFPU == 1
410 /* Strict nofpu means that the compiler should tell the assembler
411 to reject FPU instructions. E.g. from ASM inserts. */
412 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
413 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
414 #else
415 /* If there were an -isa option for sh5-nofpu then it would also go here. */
416 #define SUBTARGET_ASM_ISA_SPEC \
417 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
418 #endif
419 #else /* ! STRICT_NOFPU */
420 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
421 #endif
422
423 #ifndef SUBTARGET_ASM_SPEC
424 #define SUBTARGET_ASM_SPEC ""
425 #endif
426
427 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
428 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
429 #else
430 #define LINK_EMUL_PREFIX "sh%{ml:l}"
431 #endif
432
433 #if TARGET_CPU_DEFAULT & MASK_SH5
434 #if TARGET_CPU_DEFAULT & MASK_SH_E
435 #define LINK_DEFAULT_CPU_EMUL "32"
436 #if TARGET_CPU_DEFAULT & MASK_SH1
437 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
438 #else
439 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
440 #endif /* MASK_SH1 */
441 #else /* !MASK_SH_E */
442 #define LINK_DEFAULT_CPU_EMUL "64"
443 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
444 #endif /* MASK_SH_E */
445 #define ASM_ISA_DEFAULT_SPEC \
446 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
447 #else /* !MASK_SH5 */
448 #define LINK_DEFAULT_CPU_EMUL ""
449 #define ASM_ISA_DEFAULT_SPEC ""
450 #endif /* MASK_SH5 */
451
452 #define SUBTARGET_LINK_EMUL_SUFFIX ""
453 #define SUBTARGET_LINK_SPEC ""
454
455 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
456 so that we can undo the damage without code replication. */
457 #define LINK_SPEC SH_LINK_SPEC
458
459 #define SH_LINK_SPEC "\
460 -m %(link_emul_prefix)\
461 %{m5-compact*|m5-32media*:32}\
462 %{m5-64media*:64}\
463 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
464 %(subtarget_link_emul_suffix) \
465 %{mrelax:-relax} %(subtarget_link_spec)"
466
467 #ifndef SH_DIV_STR_FOR_SIZE
468 #define SH_DIV_STR_FOR_SIZE "call"
469 #endif
470
471 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
472
473 #define ASSEMBLER_DIALECT assembler_dialect
474
475 extern int assembler_dialect;
476
477 enum sh_divide_strategy_e {
478 /* SH5 strategies. */
479 SH_DIV_CALL,
480 SH_DIV_CALL2,
481 SH_DIV_FP, /* We could do this also for SH4. */
482 SH_DIV_INV,
483 SH_DIV_INV_MINLAT,
484 SH_DIV_INV20U,
485 SH_DIV_INV20L,
486 SH_DIV_INV_CALL,
487 SH_DIV_INV_CALL2,
488 SH_DIV_INV_FP,
489 /* SH1 .. SH4 strategies. Because of the small number of registers
490 available, the compiler uses knowledge of the actual set of registers
491 being clobbered by the different functions called. */
492 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
493 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
494 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
495 SH_DIV_INTRINSIC
496 };
497
498 extern enum sh_divide_strategy_e sh_div_strategy;
499
500 #ifndef SH_DIV_STRATEGY_DEFAULT
501 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
502 #endif
503
504 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
505
506 extern const char *sh_fixed_range_str;
507
508 \f
509 /* Target machine storage layout. */
510
511 /* Define this if most significant bit is lowest numbered
512 in instructions that operate on numbered bit-fields. */
513
514 #define BITS_BIG_ENDIAN 0
515
516 /* Define this if most significant byte of a word is the lowest numbered. */
517 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
518
519 /* Define this if most significant word of a multiword number is the lowest
520 numbered. */
521 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
522
523 /* Define this to set the endianness to use in libgcc2.c, which can
524 not depend on target_flags. */
525 #if defined(__LITTLE_ENDIAN__)
526 #define LIBGCC2_WORDS_BIG_ENDIAN 0
527 #else
528 #define LIBGCC2_WORDS_BIG_ENDIAN 1
529 #endif
530
531 #define MAX_BITS_PER_WORD 64
532
533 /* Width in bits of an `int'. We want just 32-bits, even if words are
534 longer. */
535 #define INT_TYPE_SIZE 32
536
537 /* Width in bits of a `long'. */
538 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
539
540 /* Width in bits of a `long long'. */
541 #define LONG_LONG_TYPE_SIZE 64
542
543 /* Width in bits of a `long double'. */
544 #define LONG_DOUBLE_TYPE_SIZE 64
545
546 /* Width of a word, in units (bytes). */
547 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
548 #define MIN_UNITS_PER_WORD 4
549
550 /* Scaling factor for Dwarf data offsets for CFI information.
551 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
552 SHmedia; however, since we do partial register saves for the registers
553 visible to SHcompact, and for target registers for SHMEDIA32, we have
554 to allow saves that are only 4-byte aligned. */
555 #define DWARF_CIE_DATA_ALIGNMENT -4
556
557 /* Width in bits of a pointer.
558 See also the macro `Pmode' defined below. */
559 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
560
561 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
562 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
563
564 /* Boundary (in *bits*) on which stack pointer should be aligned. */
565 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
566
567 /* The log (base 2) of the cache line size, in bytes. Processors prior to
568 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
569 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
570 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
571
572 /* ABI given & required minimum allocation boundary (in *bits*) for the
573 code of a function. */
574 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
575
576 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
577 the vbit must go into the delta field of
578 pointers-to-member-functions. */
579 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
580 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
581
582 /* Alignment of field after `int : 0' in a structure. */
583 #define EMPTY_FIELD_BOUNDARY 32
584
585 /* No data type wants to be aligned rounder than this. */
586 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
587
588 /* The best alignment to use in cases where we have a choice. */
589 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
590
591 /* Make strings word-aligned so strcpy from constants will be faster. */
592 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
593 ((TREE_CODE (EXP) == STRING_CST \
594 && (ALIGN) < FASTEST_ALIGNMENT) \
595 ? FASTEST_ALIGNMENT : (ALIGN))
596
597 /* get_mode_alignment assumes complex values are always held in multiple
598 registers, but that is not the case on the SH; CQImode and CHImode are
599 held in a single integer register. SH5 also holds CSImode and SCmode
600 values in integer registers. This is relevant for argument passing on
601 SHcompact as we use a stack temp in order to pass CSImode by reference. */
602 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
603 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
604 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
605 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
606 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
607
608 /* Make arrays of chars word-aligned for the same reasons. */
609 #define DATA_ALIGNMENT(TYPE, ALIGN) \
610 (TREE_CODE (TYPE) == ARRAY_TYPE \
611 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
612 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
613
614 /* Number of bits which any structure or union's size must be a
615 multiple of. Each structure or union's size is rounded up to a
616 multiple of this. */
617 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
618
619 /* Set this nonzero if move instructions will actually fail to work
620 when given unaligned data. */
621 #define STRICT_ALIGNMENT 1
622
623 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
624 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
625 barrier_align (LABEL_AFTER_BARRIER)
626
627 #define LOOP_ALIGN(A_LABEL) \
628 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
629 ? 0 : sh_loop_align (A_LABEL))
630
631 #define LABEL_ALIGN(A_LABEL) \
632 ( \
633 (PREV_INSN (A_LABEL) \
634 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
635 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
636 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
637 /* explicit alignment insn in constant tables. */ \
638 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
639 : 0)
640
641 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
642 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
643
644 /* The base two logarithm of the known minimum alignment of an insn length. */
645 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
646 (NONJUMP_INSN_P (A_INSN) \
647 ? 1 << TARGET_SHMEDIA \
648 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
649 ? 1 << TARGET_SHMEDIA \
650 : CACHE_LOG)
651 \f
652 /* Standard register usage. */
653
654 /* Register allocation for the Renesas calling convention:
655
656 r0 arg return
657 r1..r3 scratch
658 r4..r7 args in
659 r8..r13 call saved
660 r14 frame pointer/call saved
661 r15 stack pointer
662 ap arg pointer (doesn't really exist, always eliminated)
663 pr subroutine return address
664 t t bit
665 mach multiply/accumulate result, high part
666 macl multiply/accumulate result, low part.
667 fpul fp/int communication register
668 rap return address pointer register
669 fr0 fp arg return
670 fr1..fr3 scratch floating point registers
671 fr4..fr11 fp args in
672 fr12..fr15 call saved floating point registers */
673
674 #define MAX_REGISTER_NAME_LENGTH 5
675 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
676
677 #define SH_REGISTER_NAMES_INITIALIZER \
678 { \
679 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
680 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
681 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
682 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
683 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
684 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
685 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
686 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
687 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
688 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
689 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
690 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
691 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
692 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
693 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
694 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
695 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
696 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
697 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
698 "rap", "sfp" \
699 }
700
701 #define REGNAMES_ARR_INDEX_1(index) \
702 (sh_register_names[index])
703 #define REGNAMES_ARR_INDEX_2(index) \
704 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
705 #define REGNAMES_ARR_INDEX_4(index) \
706 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
707 #define REGNAMES_ARR_INDEX_8(index) \
708 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
709 #define REGNAMES_ARR_INDEX_16(index) \
710 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
711 #define REGNAMES_ARR_INDEX_32(index) \
712 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
713 #define REGNAMES_ARR_INDEX_64(index) \
714 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
715
716 #define REGISTER_NAMES \
717 { \
718 REGNAMES_ARR_INDEX_64 (0), \
719 REGNAMES_ARR_INDEX_64 (64), \
720 REGNAMES_ARR_INDEX_8 (128), \
721 REGNAMES_ARR_INDEX_8 (136), \
722 REGNAMES_ARR_INDEX_8 (144), \
723 REGNAMES_ARR_INDEX_2 (152) \
724 }
725
726 #define ADDREGNAMES_SIZE 32
727 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
728 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
729 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
730
731 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
732 { \
733 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
734 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
735 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
736 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
737 }
738
739 #define ADDREGNAMES_REGNO(index) \
740 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
741 : (-1))
742
743 #define ADDREGNAMES_ARR_INDEX_1(index) \
744 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
745 #define ADDREGNAMES_ARR_INDEX_2(index) \
746 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
747 #define ADDREGNAMES_ARR_INDEX_4(index) \
748 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
749 #define ADDREGNAMES_ARR_INDEX_8(index) \
750 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
751 #define ADDREGNAMES_ARR_INDEX_16(index) \
752 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
753 #define ADDREGNAMES_ARR_INDEX_32(index) \
754 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
755
756 #define ADDITIONAL_REGISTER_NAMES \
757 { \
758 ADDREGNAMES_ARR_INDEX_32 (0) \
759 }
760
761 /* Number of actual hardware registers.
762 The hardware registers are assigned numbers for the compiler
763 from 0 to just below FIRST_PSEUDO_REGISTER.
764 All registers that the compiler knows about must be given numbers,
765 even those that are not normally considered general registers. */
766
767 /* There are many other relevant definitions in sh.md's md_constants. */
768
769 #define FIRST_GENERAL_REG R0_REG
770 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
771 #define FIRST_FP_REG DR0_REG
772 #define LAST_FP_REG (FIRST_FP_REG + \
773 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
774 #define FIRST_XD_REG XD0_REG
775 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
776 #define FIRST_TARGET_REG TR0_REG
777 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
778
779 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
780
781 #define FIRST_BANKED_REG R0_REG
782 #define LAST_BANKED_REG R7_REG
783
784 #define BANKED_REGISTER_P(REGNO) \
785 IN_RANGE ((REGNO), \
786 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
787 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
788
789 #define GENERAL_REGISTER_P(REGNO) \
790 IN_RANGE ((REGNO), \
791 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
792 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
793
794 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
795 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
796 || ((REGNO) == FRAME_POINTER_REGNUM))
797
798 #define FP_REGISTER_P(REGNO) \
799 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
800
801 #define XD_REGISTER_P(REGNO) \
802 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
803
804 #define FP_OR_XD_REGISTER_P(REGNO) \
805 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
806
807 #define FP_ANY_REGISTER_P(REGNO) \
808 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
809
810 #define SPECIAL_REGISTER_P(REGNO) \
811 ((REGNO) == GBR_REG || (REGNO) == T_REG \
812 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
813
814 #define TARGET_REGISTER_P(REGNO) \
815 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
816
817 #define SHMEDIA_REGISTER_P(REGNO) \
818 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
819 || TARGET_REGISTER_P (REGNO))
820
821 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
822 that should be fixed. */
823 #define VALID_REGISTER_P(REGNO) \
824 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
825 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
826 || (REGNO) == FRAME_POINTER_REGNUM \
827 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
828 || (TARGET_SH2E && (REGNO) == FPUL_REG))
829
830 /* The mode that should be generally used to store a register by
831 itself in the stack, or to load it back. */
832 #define REGISTER_NATURAL_MODE(REGNO) \
833 (FP_REGISTER_P (REGNO) ? SFmode \
834 : XD_REGISTER_P (REGNO) ? DFmode \
835 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
836 ? DImode \
837 : SImode)
838
839 #define FIRST_PSEUDO_REGISTER 154
840
841 /* Don't count soft frame pointer. */
842 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
843
844 /* 1 for registers that have pervasive standard uses
845 and are not available for the register allocator.
846
847 Mach register is fixed 'cause it's only 10 bits wide for SH1.
848 It is 32 bits wide for SH2. */
849
850 #define FIXED_REGISTERS \
851 { \
852 /* Regular registers. */ \
853 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 1, \
855 /* r16 is reserved, r18 is the former pr. */ \
856 1, 0, 0, 0, 0, 0, 0, 0, \
857 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
858 /* r26 is a global variable data pointer; r27 is for constants. */ \
859 1, 1, 1, 1, 0, 0, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, \
861 0, 0, 0, 0, 0, 0, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 1, \
864 /* FP registers. */ \
865 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, \
868 0, 0, 0, 0, 0, 0, 0, 0, \
869 0, 0, 0, 0, 0, 0, 0, 0, \
870 0, 0, 0, 0, 0, 0, 0, 0, \
871 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, \
873 /* Branch target registers. */ \
874 0, 0, 0, 0, 0, 0, 0, 0, \
875 /* XD registers. */ \
876 0, 0, 0, 0, 0, 0, 0, 0, \
877 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
878 1, 1, 1, 1, 1, 1, 0, 1, \
879 /*"rap", "sfp" */ \
880 1, 1, \
881 }
882
883 /* 1 for registers not available across function calls.
884 These must include the FIXED_REGISTERS and also any
885 registers that can be used without being saved.
886 The latter must include the registers where values are returned
887 and the register where structure-value addresses are passed.
888 Aside from that, you can include as many other registers as you like. */
889
890 #define CALL_USED_REGISTERS \
891 { \
892 /* Regular registers. */ \
893 1, 1, 1, 1, 1, 1, 1, 1, \
894 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
895 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
896 across SH5 function calls. */ \
897 0, 0, 0, 0, 0, 0, 0, 1, \
898 1, 1, 1, 1, 1, 1, 1, 1, \
899 1, 1, 1, 1, 0, 0, 0, 0, \
900 0, 0, 0, 0, 1, 1, 1, 1, \
901 1, 1, 1, 1, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, \
903 0, 0, 0, 0, 1, 1, 1, 1, \
904 /* FP registers. */ \
905 1, 1, 1, 1, 1, 1, 1, 1, \
906 1, 1, 1, 1, 0, 0, 0, 0, \
907 1, 1, 1, 1, 1, 1, 1, 1, \
908 1, 1, 1, 1, 1, 1, 1, 1, \
909 1, 1, 1, 1, 0, 0, 0, 0, \
910 0, 0, 0, 0, 0, 0, 0, 0, \
911 0, 0, 0, 0, 0, 0, 0, 0, \
912 0, 0, 0, 0, 0, 0, 0, 0, \
913 /* Branch target registers. */ \
914 1, 1, 1, 1, 1, 0, 0, 0, \
915 /* XD registers. */ \
916 1, 1, 1, 1, 1, 1, 0, 0, \
917 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
918 1, 1, 1, 1, 1, 1, 1, 1, \
919 /*"rap", "sfp" */ \
920 1, 1, \
921 }
922
923 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
924 fixed, like PIC_OFFSET_TABLE_REGNUM. */
925 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
926
927 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
928 across SHcompact function calls. We can't tell whether a called
929 function is SHmedia or SHcompact, so we assume it may be when
930 compiling SHmedia code with the 32-bit ABI, since that's the only
931 ABI that can be linked with SHcompact code. */
932 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
933 (TARGET_SHMEDIA32 \
934 && GET_MODE_SIZE (MODE) > 4 \
935 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
936 && (REGNO) <= FIRST_GENERAL_REG + 15) \
937 || TARGET_REGISTER_P (REGNO) \
938 || (REGNO) == PR_MEDIA_REG))
939
940 /* Return number of consecutive hard regs needed starting at reg REGNO
941 to hold something of mode MODE.
942 This is ordinarily the length in words of a value of mode MODE
943 but can be less for certain modes in special long registers.
944
945 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
946
947 #define HARD_REGNO_NREGS(REGNO, MODE) \
948 (XD_REGISTER_P (REGNO) \
949 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
950 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
951 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
952 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
953
954 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
955
956 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
957 sh_hard_regno_mode_ok ((REGNO), (MODE))
958
959 /* Value is 1 if it is a good idea to tie two pseudo registers
960 when one has mode MODE1 and one has mode MODE2.
961 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
962 for any hard reg, then this must be 0 for correct output.
963 That's the case for xd registers: we don't hold SFmode values in
964 them, so we can't tie an SFmode pseudos with one in another
965 floating-point mode. */
966
967 #define MODES_TIEABLE_P(MODE1, MODE2) \
968 ((MODE1) == (MODE2) \
969 || (TARGET_SHMEDIA \
970 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
971 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
972 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
973 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
974 && (GET_MODE_SIZE (MODE2) <= 4)) \
975 : ((MODE1) != SFmode && (MODE2) != SFmode))))
976
977 /* A C expression that is nonzero if hard register NEW_REG can be
978 considered for use as a rename register for OLD_REG register */
979
980 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
981 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
982
983 /* Specify the registers used for certain standard purposes.
984 The values of these macros are register numbers. */
985
986 /* Define this if the program counter is overloaded on a register. */
987 /* #define PC_REGNUM 15*/
988
989 /* Register to use for pushing function arguments. */
990 #define STACK_POINTER_REGNUM SP_REG
991
992 /* Base register for access to local variables of the function. */
993 #define HARD_FRAME_POINTER_REGNUM FP_REG
994
995 /* Base register for access to local variables of the function. */
996 #define FRAME_POINTER_REGNUM 153
997
998 /* Fake register that holds the address on the stack of the
999 current function's return address. */
1000 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1001
1002 /* Register to hold the addressing base for position independent
1003 code access to data items. */
1004 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1005
1006 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1007
1008 /* Definitions for register eliminations.
1009
1010 We have three registers that can be eliminated on the SH. First, the
1011 frame pointer register can often be eliminated in favor of the stack
1012 pointer register. Secondly, the argument pointer register can always be
1013 eliminated; it is replaced with either the stack or frame pointer.
1014 Third, there is the return address pointer, which can also be replaced
1015 with either the stack or the frame pointer. */
1016
1017 /* This is an array of structures. Each structure initializes one pair
1018 of eliminable registers. The "from" register number is given first,
1019 followed by "to". Eliminations of the same "from" register are listed
1020 in order of preference. */
1021
1022 /* If you add any registers here that are not actually hard registers,
1023 and that have any alternative of elimination that doesn't always
1024 apply, you need to amend calc_live_regs to exclude it, because
1025 reload spills all eliminable registers where it sees an
1026 can_eliminate == 0 entry, thus making them 'live' .
1027 If you add any hard registers that can be eliminated in different
1028 ways, you have to patch reload to spill them only when all alternatives
1029 of elimination fail. */
1030
1031 #define ELIMINABLE_REGS \
1032 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1033 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1034 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1035 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1036 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1037 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1038 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1039
1040 /* Define the offset between two registers, one to be eliminated, and the other
1041 its replacement, at the start of a routine. */
1042
1043 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1044 OFFSET = initial_elimination_offset ((FROM), (TO))
1045
1046 /* Base register for access to arguments of the function. */
1047 #define ARG_POINTER_REGNUM AP_REG
1048
1049 /* Register in which the static-chain is passed to a function. */
1050 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1051
1052 /* Don't default to pcc-struct-return, because we have already specified
1053 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1054 target hook. */
1055
1056 #define DEFAULT_PCC_STRUCT_RETURN 0
1057
1058 #define SHMEDIA_REGS_STACK_ADJUST() \
1059 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1060 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1061 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1062 : 0)
1063
1064 \f
1065 /* Define the classes of registers for register constraints in the
1066 machine description. Also define ranges of constants.
1067
1068 One of the classes must always be named ALL_REGS and include all hard regs.
1069 If there is more than one class, another class must be named NO_REGS
1070 and contain no registers.
1071
1072 The name GENERAL_REGS must be the name of a class (or an alias for
1073 another name such as ALL_REGS). This is the class of registers
1074 that is allowed by "g" or "r" in a register constraint.
1075 Also, registers outside this class are allocated only when
1076 instructions express preferences for them.
1077
1078 The classes must be numbered in nondecreasing order; that is,
1079 a larger-numbered class must never be contained completely
1080 in a smaller-numbered class.
1081
1082 For any two classes, it is very desirable that there be another
1083 class that represents their union. */
1084
1085 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1086 be used as the destination of some of the arithmetic ops. There are
1087 also some special purpose registers; the T bit register, the
1088 Procedure Return Register and the Multiply Accumulate Registers. */
1089 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1090 reg_class_subunion. We don't want to have an actual union class
1091 of these, because it would only be used when both classes are calculated
1092 to give the same cost, but there is only one FPUL register.
1093 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1094 applying to the actual instruction alternative considered. E.g., the
1095 y/r alternative of movsi_ie is considered to have no more cost that
1096 the r/r alternative, which is patently untrue. */
1097
1098 enum reg_class
1099 {
1100 NO_REGS,
1101 R0_REGS,
1102 PR_REGS,
1103 T_REGS,
1104 MAC_REGS,
1105 FPUL_REGS,
1106 SIBCALL_REGS,
1107 GENERAL_REGS,
1108 FP0_REGS,
1109 FP_REGS,
1110 DF_HI_REGS,
1111 DF_REGS,
1112 FPSCR_REGS,
1113 GENERAL_FP_REGS,
1114 GENERAL_DF_REGS,
1115 TARGET_REGS,
1116 ALL_REGS,
1117 LIM_REG_CLASSES
1118 };
1119
1120 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1121
1122 /* Give names of register classes as strings for dump file. */
1123 #define REG_CLASS_NAMES \
1124 { \
1125 "NO_REGS", \
1126 "R0_REGS", \
1127 "PR_REGS", \
1128 "T_REGS", \
1129 "MAC_REGS", \
1130 "FPUL_REGS", \
1131 "SIBCALL_REGS", \
1132 "GENERAL_REGS", \
1133 "FP0_REGS", \
1134 "FP_REGS", \
1135 "DF_HI_REGS", \
1136 "DF_REGS", \
1137 "FPSCR_REGS", \
1138 "GENERAL_FP_REGS", \
1139 "GENERAL_DF_REGS", \
1140 "TARGET_REGS", \
1141 "ALL_REGS", \
1142 }
1143
1144 /* Define which registers fit in which classes.
1145 This is an initializer for a vector of HARD_REG_SET
1146 of length N_REG_CLASSES. */
1147
1148 #define REG_CLASS_CONTENTS \
1149 { \
1150 /* NO_REGS: */ \
1151 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1152 /* R0_REGS: */ \
1153 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1154 /* PR_REGS: */ \
1155 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1156 /* T_REGS: */ \
1157 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1158 /* MAC_REGS: */ \
1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1160 /* FPUL_REGS: */ \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1162 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1164 /* GENERAL_REGS: */ \
1165 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1166 /* FP0_REGS: */ \
1167 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1168 /* FP_REGS: */ \
1169 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1170 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1171 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1172 /* DF_REGS: */ \
1173 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1174 /* FPSCR_REGS: */ \
1175 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1176 /* GENERAL_FP_REGS: */ \
1177 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1178 /* GENERAL_DF_REGS: */ \
1179 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1180 /* TARGET_REGS: */ \
1181 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1182 /* ALL_REGS: */ \
1183 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1184 }
1185
1186 /* The same information, inverted:
1187 Return the class number of the smallest class containing
1188 reg number REGNO. This could be a conditional expression
1189 or could index an array. */
1190
1191 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1192 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1193
1194 /* The following macro defines cover classes for Integrated Register
1195 Allocator. Cover classes is a set of non-intersected register
1196 classes covering all hard registers used for register allocation
1197 purpose. Any move between two registers of a cover class should be
1198 cheaper than load or store of the registers. The macro value is
1199 array of register classes with LIM_REG_CLASSES used as the end
1200 marker. */
1201
1202 #define IRA_COVER_CLASSES \
1203 { \
1204 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1205 FPUL_REGS, LIM_REG_CLASSES \
1206 }
1207
1208 /* When this hook returns true for MODE, the compiler allows
1209 registers explicitly used in the rtl to be used as spill registers
1210 but prevents the compiler from extending the lifetime of these
1211 registers. */
1212 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1213 sh_small_register_classes_for_mode_p
1214
1215 /* The order in which register should be allocated. */
1216 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1217 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1218 spilled or used otherwise, we better have the FP_REGS allocated first. */
1219 #define REG_ALLOC_ORDER \
1220 {/* Caller-saved FPRs */ \
1221 65, 66, 67, 68, 69, 70, 71, 64, \
1222 72, 73, 74, 75, 80, 81, 82, 83, \
1223 84, 85, 86, 87, 88, 89, 90, 91, \
1224 92, 93, 94, 95, 96, 97, 98, 99, \
1225 /* Callee-saved FPRs */ \
1226 76, 77, 78, 79,100,101,102,103, \
1227 104,105,106,107,108,109,110,111, \
1228 112,113,114,115,116,117,118,119, \
1229 120,121,122,123,124,125,126,127, \
1230 136,137,138,139,140,141,142,143, \
1231 /* FPSCR */ 151, \
1232 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1233 1, 2, 3, 7, 6, 5, 4, 0, \
1234 8, 9, 17, 19, 20, 21, 22, 23, \
1235 36, 37, 38, 39, 40, 41, 42, 43, \
1236 60, 61, 62, \
1237 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1238 10, 11, 12, 13, 14, 18, \
1239 /* SH5 callee-saved GPRs */ \
1240 28, 29, 30, 31, 32, 33, 34, 35, \
1241 44, 45, 46, 47, 48, 49, 50, 51, \
1242 52, 53, 54, 55, 56, 57, 58, 59, \
1243 /* FPUL */ 150, \
1244 /* SH5 branch target registers */ \
1245 128,129,130,131,132,133,134,135, \
1246 /* Fixed registers */ \
1247 15, 16, 24, 25, 26, 27, 63,144, \
1248 145,146,147,148,149,152,153 }
1249
1250 /* The class value for index registers, and the one for base regs. */
1251 #define INDEX_REG_CLASS \
1252 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1253 #define BASE_REG_CLASS GENERAL_REGS
1254 \f
1255 /* Defines for sh.md and constraints.md. */
1256
1257 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1258 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1259 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1260 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1261 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1262 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1263 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1264 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1265
1266 #define CONST_OK_FOR_J16(VALUE) \
1267 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1268 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1269
1270 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1271 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1272
1273 /* Given an rtx X being reloaded into a reg required to be
1274 in class CLASS, return the class of reg to actually use.
1275 In general this is just CLASS; but on some machines
1276 in some cases it is preferable to use a more restrictive class. */
1277
1278 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1279 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1280 && (GET_CODE (X) == CONST_DOUBLE \
1281 || GET_CODE (X) == SYMBOL_REF \
1282 || PIC_ADDR_P (X)) \
1283 ? GENERAL_REGS \
1284 : (CLASS)) \
1285
1286 #if 0
1287 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1288 ((((REGCLASS_HAS_FP_REG (CLASS) \
1289 && (REG_P (X) \
1290 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1291 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1292 && TARGET_FMOVD)))) \
1293 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1294 && REG_P (X) \
1295 && FP_REGISTER_P (REGNO (X)))) \
1296 && ! TARGET_SHMEDIA \
1297 && ((MODE) == SFmode || (MODE) == SImode)) \
1298 ? FPUL_REGS \
1299 : (((CLASS) == FPUL_REGS \
1300 || (REGCLASS_HAS_FP_REG (CLASS) \
1301 && ! TARGET_SHMEDIA && MODE == SImode)) \
1302 && (MEM_P (X) \
1303 || (REG_P (X) \
1304 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1305 || REGNO (X) == T_REG \
1306 || system_reg_operand (X, VOIDmode))))) \
1307 ? GENERAL_REGS \
1308 : (((CLASS) == TARGET_REGS \
1309 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1310 && !satisfies_constraint_Csy (X) \
1311 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1312 ? GENERAL_REGS \
1313 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1314 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1315 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1316 ? GENERAL_REGS \
1317 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1318 && TARGET_REGISTER_P (REGNO (X))) \
1319 ? GENERAL_REGS : (ELSE))
1320
1321 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1322 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1323
1324 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1325 ((REGCLASS_HAS_FP_REG (CLASS) \
1326 && ! TARGET_SHMEDIA \
1327 && immediate_operand ((X), (MODE)) \
1328 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1329 && (MODE) == SFmode && fldi_ok ())) \
1330 ? R0_REGS \
1331 : ((CLASS) == FPUL_REGS \
1332 && ((REG_P (X) \
1333 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1334 || REGNO (X) == T_REG)) \
1335 || GET_CODE (X) == PLUS)) \
1336 ? GENERAL_REGS \
1337 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1338 ? (satisfies_constraint_I08 (X) \
1339 ? GENERAL_REGS \
1340 : R0_REGS) \
1341 : ((CLASS) == FPSCR_REGS \
1342 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1343 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1344 ? GENERAL_REGS \
1345 : (REGCLASS_HAS_FP_REG (CLASS) \
1346 && TARGET_SHMEDIA \
1347 && immediate_operand ((X), (MODE)) \
1348 && (X) != CONST0_RTX (GET_MODE (X)) \
1349 && GET_MODE (X) != V4SFmode) \
1350 ? GENERAL_REGS \
1351 : (((MODE) == QImode || (MODE) == HImode) \
1352 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1353 ? GENERAL_REGS \
1354 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1355 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1356 ? TARGET_REGS \
1357 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1358 #endif
1359
1360 /* Return the maximum number of consecutive registers
1361 needed to represent mode MODE in a register of class CLASS.
1362
1363 If TARGET_SHMEDIA, we need two FP registers per word.
1364 Otherwise we will need at most one register per word. */
1365 #define CLASS_MAX_NREGS(CLASS, MODE) \
1366 (TARGET_SHMEDIA \
1367 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1368 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1369 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1370
1371 /* If defined, gives a class of registers that cannot be used as the
1372 operand of a SUBREG that changes the mode of the object illegally. */
1373 /* ??? We need to renumber the internal numbers for the frnn registers
1374 when in little endian in order to allow mode size changes. */
1375
1376 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1377 sh_cannot_change_mode_class (FROM, TO, CLASS)
1378 \f
1379 /* Stack layout; function entry, exit and calling. */
1380
1381 /* Define the number of registers that can hold parameters.
1382 These macros are used only in other macro definitions below. */
1383
1384 #define NPARM_REGS(MODE) \
1385 (TARGET_FPU_ANY && (MODE) == SFmode \
1386 ? (TARGET_SH5 ? 12 : 8) \
1387 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1388 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1389 ? (TARGET_SH5 ? 12 : 8) \
1390 : (TARGET_SH5 ? 8 : 4))
1391
1392 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1393 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1394
1395 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1396 #define FIRST_FP_RET_REG FIRST_FP_REG
1397
1398 /* Define this if pushing a word on the stack
1399 makes the stack pointer a smaller address. */
1400 #define STACK_GROWS_DOWNWARD
1401
1402 /* Define this macro to nonzero if the addresses of local variable slots
1403 are at negative offsets from the frame pointer. */
1404 #define FRAME_GROWS_DOWNWARD 1
1405
1406 /* Offset from the frame pointer to the first local variable slot to
1407 be allocated. */
1408 #define STARTING_FRAME_OFFSET 0
1409
1410 /* If we generate an insn to push BYTES bytes,
1411 this says how many the stack pointer really advances by. */
1412 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1413 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1414 do correct alignment. */
1415 #if 0
1416 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1417 #endif
1418
1419 /* Offset of first parameter from the argument pointer register value. */
1420 #define FIRST_PARM_OFFSET(FNDECL) 0
1421
1422 /* Value is the number of bytes of arguments automatically popped when
1423 calling a subroutine.
1424 CUM is the accumulated argument list.
1425
1426 On SHcompact, the call trampoline pops arguments off the stack. */
1427 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1428
1429 /* Some subroutine macros specific to this machine. */
1430
1431 #define BASE_RETURN_VALUE_REG(MODE) \
1432 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1433 ? FIRST_FP_RET_REG \
1434 : TARGET_FPU_ANY && (MODE) == SCmode \
1435 ? FIRST_FP_RET_REG \
1436 : (TARGET_FPU_DOUBLE \
1437 && ((MODE) == DFmode || (MODE) == SFmode \
1438 || (MODE) == DCmode || (MODE) == SCmode )) \
1439 ? FIRST_FP_RET_REG \
1440 : FIRST_RET_REG)
1441
1442 #define BASE_ARG_REG(MODE) \
1443 ((TARGET_SH2E && ((MODE) == SFmode)) \
1444 ? FIRST_FP_PARM_REG \
1445 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1446 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1447 ? FIRST_FP_PARM_REG \
1448 : FIRST_PARM_REG)
1449
1450 /* 1 if N is a possible register number for function argument passing. */
1451 /* ??? There are some callers that pass REGNO as int, and others that pass
1452 it as unsigned. We get warnings unless we do casts everywhere. */
1453 #define FUNCTION_ARG_REGNO_P(REGNO) \
1454 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1455 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1456 || (TARGET_FPU_ANY \
1457 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1458 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1459 + NPARM_REGS (SFmode))))
1460 \f
1461 /* Define a data type for recording info about an argument list
1462 during the scan of that argument list. This data type should
1463 hold all necessary information about the function itself
1464 and about the args processed so far, enough to enable macros
1465 such as FUNCTION_ARG to determine where the next arg should go.
1466
1467 On SH, this is a single integer, which is a number of words
1468 of arguments scanned so far (including the invisible argument,
1469 if any, which holds the structure-value-address).
1470 Thus NARGREGS or more means all following args should go on the stack. */
1471
1472 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1473 struct sh_args {
1474 int arg_count[2];
1475 int force_mem;
1476 /* Nonzero if a prototype is available for the function. */
1477 int prototype_p;
1478 /* The number of an odd floating-point register, that should be used
1479 for the next argument of type float. */
1480 int free_single_fp_reg;
1481 /* Whether we're processing an outgoing function call. */
1482 int outgoing;
1483 /* The number of general-purpose registers that should have been
1484 used to pass partial arguments, that are passed totally on the
1485 stack. On SHcompact, a call trampoline will pop them off the
1486 stack before calling the actual function, and, if the called
1487 function is implemented in SHcompact mode, the incoming arguments
1488 decoder will push such arguments back onto the stack. For
1489 incoming arguments, STACK_REGS also takes into account other
1490 arguments passed by reference, that the decoder will also push
1491 onto the stack. */
1492 int stack_regs;
1493 /* The number of general-purpose registers that should have been
1494 used to pass arguments, if the arguments didn't have to be passed
1495 by reference. */
1496 int byref_regs;
1497 /* Set as by shcompact_byref if the current argument is to be passed
1498 by reference. */
1499 int byref;
1500
1501 /* call_cookie is a bitmask used by call expanders, as well as
1502 function prologue and epilogues, to allow SHcompact to comply
1503 with the SH5 32-bit ABI, that requires 64-bit registers to be
1504 used even though only the lower 32-bit half is visible in
1505 SHcompact mode. The strategy is to call SHmedia trampolines.
1506
1507 The alternatives for each of the argument-passing registers are
1508 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1509 contents from the address in it; (d) add 8 to it, storing the
1510 result in the next register, then (c); (e) copy it from some
1511 floating-point register,
1512
1513 Regarding copies from floating-point registers, r2 may only be
1514 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1515 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1516 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1517 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1518 dr10.
1519
1520 The bit mask is structured as follows:
1521
1522 - 1 bit to tell whether to set up a return trampoline.
1523
1524 - 3 bits to count the number consecutive registers to pop off the
1525 stack.
1526
1527 - 4 bits for each of r9, r8, r7 and r6.
1528
1529 - 3 bits for each of r5, r4, r3 and r2.
1530
1531 - 3 bits set to 0 (the most significant ones)
1532
1533 3 2 1 0
1534 1098 7654 3210 9876 5432 1098 7654 3210
1535 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1536 2223 3344 4555 6666 7777 8888 9999 SSS-
1537
1538 - If F is set, the register must be copied from an FP register,
1539 whose number is encoded in the remaining bits.
1540
1541 - Else, if L is set, the register must be loaded from the address
1542 contained in it. If the P bit is *not* set, the address of the
1543 following dword should be computed first, and stored in the
1544 following register.
1545
1546 - Else, if P is set, the register alone should be popped off the
1547 stack.
1548
1549 - After all this processing, the number of registers represented
1550 in SSS will be popped off the stack. This is an optimization
1551 for pushing/popping consecutive registers, typically used for
1552 varargs and large arguments partially passed in registers.
1553
1554 - If T is set, a return trampoline will be set up for 64-bit
1555 return values to be split into 2 32-bit registers. */
1556 long call_cookie;
1557
1558 /* This is set to nonzero when the call in question must use the Renesas ABI,
1559 even without the -mrenesas option. */
1560 int renesas_abi;
1561 };
1562
1563 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1564 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1565 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1566 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1567 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1568 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1569 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1570 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1571 #define CALL_COOKIE_INT_REG(REG, VAL) \
1572 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1573 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1574 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1575
1576 #define CUMULATIVE_ARGS struct sh_args
1577
1578 #define GET_SH_ARG_CLASS(MODE) \
1579 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1580 ? SH_ARG_FLOAT \
1581 /* There's no mention of complex float types in the SH5 ABI, so we
1582 should presumably handle them as aggregate types. */ \
1583 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1584 ? SH_ARG_INT \
1585 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1586 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1587 ? SH_ARG_FLOAT : SH_ARG_INT)
1588
1589 #define ROUND_ADVANCE(SIZE) \
1590 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1591
1592 /* Round a register number up to a proper boundary for an arg of mode
1593 MODE.
1594
1595 The SH doesn't care about double alignment, so we only
1596 round doubles to even regs when asked to explicitly. */
1597
1598 #define ROUND_REG(CUM, MODE) \
1599 (((TARGET_ALIGN_DOUBLE \
1600 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1601 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1602 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1603 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1604 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1605 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1606
1607 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1608 for a call to a function whose data type is FNTYPE.
1609 For a library call, FNTYPE is 0.
1610
1611 On SH, the offset always starts at 0: the first parm reg is always
1612 the same reg for a given argument class.
1613
1614 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1615
1616 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1617 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1618
1619 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1620 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1621
1622 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1623 This macro is only used in this file. */
1624
1625 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1626 (((TYPE) == 0 \
1627 || (! TREE_ADDRESSABLE ((TYPE)) \
1628 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1629 || ! (AGGREGATE_TYPE_P (TYPE) \
1630 || (!TARGET_FPU_ANY \
1631 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1632 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1633 && ! (CUM).force_mem \
1634 && (TARGET_SH2E \
1635 ? ((MODE) == BLKmode \
1636 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1637 + int_size_in_bytes (TYPE)) \
1638 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1639 : ((ROUND_REG((CUM), (MODE)) \
1640 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1641 <= NPARM_REGS (MODE))) \
1642 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1643
1644 /* By accident we got stuck with passing SCmode on SH4 little endian
1645 in two registers that are nominally successive - which is different from
1646 two single SFmode values, where we take endianness translation into
1647 account. That does not work at all if an odd number of registers is
1648 already in use, so that got fixed, but library functions are still more
1649 likely to use complex numbers without mixing them with SFmode arguments
1650 (which in C would have to be structures), so for the sake of ABI
1651 compatibility the way SCmode values are passed when an even number of
1652 FP registers is in use remains different from a pair of SFmode values for
1653 now.
1654 I.e.:
1655 foo (double); a: fr5,fr4
1656 foo (float a, float b); a: fr5 b: fr4
1657 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1658 this should be the other way round...
1659 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1660 #define FUNCTION_ARG_SCmode_WART 1
1661
1662 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1663 register in SHcompact mode, it must be padded in the most
1664 significant end. This means that passing it by reference wouldn't
1665 pad properly on a big-endian machine. In this particular case, we
1666 pass this argument on the stack, in a way that the call trampoline
1667 will load its value into the appropriate register. */
1668 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1669 ((MODE) == BLKmode \
1670 && TARGET_SHCOMPACT \
1671 && ! TARGET_LITTLE_ENDIAN \
1672 && int_size_in_bytes (TYPE) > 4 \
1673 && int_size_in_bytes (TYPE) < 8)
1674
1675 /* Minimum alignment for an argument to be passed by callee-copy
1676 reference. We need such arguments to be aligned to 8 byte
1677 boundaries, because they'll be loaded using quad loads. */
1678 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1679
1680 /* The SH5 ABI requires floating-point arguments to be passed to
1681 functions without a prototype in both an FP register and a regular
1682 register or the stack. When passing the argument in both FP and
1683 general-purpose registers, list the FP register first. */
1684 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1685 (gen_rtx_PARALLEL \
1686 ((MODE), \
1687 gen_rtvec (2, \
1688 gen_rtx_EXPR_LIST \
1689 (VOIDmode, \
1690 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1691 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1692 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1693 : NULL_RTX), \
1694 const0_rtx), \
1695 gen_rtx_EXPR_LIST \
1696 (VOIDmode, \
1697 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1698 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1699 + (CUM).arg_count[(int) SH_ARG_INT]) \
1700 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1701 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1702 const0_rtx))))
1703
1704 /* The SH5 ABI requires regular registers or stack slots to be
1705 reserved for floating-point arguments. Registers are taken care of
1706 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1707 Unfortunately, there's no way to just reserve a stack slot, so
1708 we'll end up needlessly storing a copy of the argument in the
1709 stack. For incoming arguments, however, the PARALLEL will be
1710 optimized to the register-only form, and the value in the stack
1711 slot won't be used at all. */
1712 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1713 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1714 ? gen_rtx_REG ((MODE), (REG)) \
1715 : gen_rtx_PARALLEL ((MODE), \
1716 gen_rtvec (2, \
1717 gen_rtx_EXPR_LIST \
1718 (VOIDmode, NULL_RTX, \
1719 const0_rtx), \
1720 gen_rtx_EXPR_LIST \
1721 (VOIDmode, gen_rtx_REG ((MODE), \
1722 (REG)), \
1723 const0_rtx))))
1724
1725 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1726 (TARGET_SH5 \
1727 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1728 || (MODE) == DCmode) \
1729 && ((CUM).arg_count[(int) SH_ARG_INT] \
1730 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1731 : GET_MODE_SIZE (MODE)) \
1732 + 7) / 8) > NPARM_REGS (SImode))
1733
1734 /* Perform any needed actions needed for a function that is receiving a
1735 variable number of arguments. */
1736
1737 /* Call the function profiler with a given profile label.
1738 We use two .aligns, so as to make sure that both the .long is aligned
1739 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1740 from the trapa instruction. */
1741
1742 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1743 { \
1744 if (TARGET_SHMEDIA) \
1745 { \
1746 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1747 fprintf((STREAM), "\ttrapa\tr0\n"); \
1748 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1749 } \
1750 else \
1751 { \
1752 fprintf((STREAM), "\t.align\t2\n"); \
1753 fprintf((STREAM), "\ttrapa\t#33\n"); \
1754 fprintf((STREAM), "\t.align\t2\n"); \
1755 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1756 } \
1757 }
1758
1759 /* Define this macro if the code for function profiling should come
1760 before the function prologue. Normally, the profiling code comes
1761 after. */
1762
1763 #define PROFILE_BEFORE_PROLOGUE
1764
1765 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1766 the stack pointer does not matter. The value is tested only in
1767 functions that have frame pointers.
1768 No definition is equivalent to always zero. */
1769
1770 #define EXIT_IGNORE_STACK 1
1771
1772 /*
1773 On the SH, the trampoline looks like
1774 2 0002 D202 mov.l l2,r2
1775 1 0000 D301 mov.l l1,r3
1776 3 0004 422B jmp @r2
1777 4 0006 0009 nop
1778 5 0008 00000000 l1: .long area
1779 6 000c 00000000 l2: .long function */
1780
1781 /* Length in units of the trampoline for entering a nested function. */
1782 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1783
1784 /* Alignment required for a trampoline in bits . */
1785 #define TRAMPOLINE_ALIGNMENT \
1786 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
1787 : TARGET_SHMEDIA ? 256 : 64)
1788
1789 /* A C expression whose value is RTL representing the value of the return
1790 address for the frame COUNT steps up from the current frame.
1791 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1792 can ignore COUNT. */
1793
1794 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1795 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1796
1797 /* A C expression whose value is RTL representing the location of the
1798 incoming return address at the beginning of any function, before the
1799 prologue. This RTL is either a REG, indicating that the return
1800 value is saved in REG, or a MEM representing a location in
1801 the stack. */
1802 #define INCOMING_RETURN_ADDR_RTX \
1803 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1804 \f
1805 /* Addressing modes, and classification of registers for them. */
1806 #define HAVE_POST_INCREMENT TARGET_SH1
1807 #define HAVE_PRE_DECREMENT TARGET_SH1
1808
1809 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1810 ? 0 : TARGET_SH1)
1811 #define USE_LOAD_PRE_DECREMENT(mode) 0
1812 #define USE_STORE_POST_INCREMENT(mode) 0
1813 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1814 ? 0 : TARGET_SH1)
1815
1816 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1817 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1818 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1819
1820 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1821 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1822 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1823
1824 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1825
1826 /* Macros to check register numbers against specific register classes. */
1827
1828 /* These assume that REGNO is a hard or pseudo reg number.
1829 They give nonzero only if REGNO is a hard reg of the suitable class
1830 or a pseudo reg currently allocated to a suitable hard reg.
1831 Since they use reg_renumber, they are safe only once reg_renumber
1832 has been allocated, which happens in local-alloc.c. */
1833
1834 #define REGNO_OK_FOR_BASE_P(REGNO) \
1835 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1836 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1837 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1838 (TARGET_SHMEDIA \
1839 ? (GENERAL_REGISTER_P (REGNO) \
1840 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1841 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1842
1843 /* Maximum number of registers that can appear in a valid memory
1844 address. */
1845
1846 #define MAX_REGS_PER_ADDRESS 2
1847
1848 /* Recognize any constant value that is a valid address. */
1849
1850 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1851
1852 /* Nonzero if the constant value X is a legitimate general operand. */
1853 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
1854
1855 #define LEGITIMATE_CONSTANT_P(X) \
1856 (TARGET_SHMEDIA \
1857 ? ((GET_MODE (X) != DFmode \
1858 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
1859 || (X) == CONST0_RTX (GET_MODE (X)) \
1860 || ! TARGET_SHMEDIA_FPU \
1861 || TARGET_SHMEDIA64) \
1862 : (GET_CODE (X) != CONST_DOUBLE \
1863 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1864 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
1865
1866 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1867 and check its validity for a certain class.
1868 The suitable hard regs are always accepted and all pseudo regs
1869 are also accepted if STRICT is not set. */
1870
1871 /* Nonzero if X is a reg that can be used as a base reg. */
1872 #define REG_OK_FOR_BASE_P(X, STRICT) \
1873 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1874 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1875
1876 /* Nonzero if X is a reg that can be used as an index. */
1877 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1878 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1879 : REGNO (X) == R0_REG) \
1880 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1881
1882 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1883 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1884 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1885 : REGNO (X) == R0_REG && OFFSET == 0) \
1886 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1887
1888 /* Macros for extra constraints. */
1889
1890 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1891 ((GET_CODE ((OP)) == LABEL_REF) \
1892 || (GET_CODE ((OP)) == CONST \
1893 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1894 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1895 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1896
1897 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1898 (CONSTANT_P (OP) \
1899 && !CONST_INT_P (OP) \
1900 && GET_CODE (OP) != CONST_DOUBLE \
1901 && (!flag_pic \
1902 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1903 && !PIC_ADDR_P (OP) \
1904 && GET_CODE (OP) != LABEL_REF)))
1905
1906 /* Check whether OP is a datalabel unspec. */
1907 #define DATALABEL_REF_NO_CONST_P(OP) \
1908 (GET_CODE (OP) == UNSPEC \
1909 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1910 && XVECLEN ((OP), 0) == 1 \
1911 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1912
1913 #define GOT_ENTRY_P(OP) \
1914 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1915 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1916
1917 #define GOTPLT_ENTRY_P(OP) \
1918 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1919 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1920
1921 #define UNSPEC_GOTOFF_P(OP) \
1922 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1923
1924 #define GOTOFF_P(OP) \
1925 (GET_CODE (OP) == CONST \
1926 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1927 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1928 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1929 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1930
1931 #define PIC_ADDR_P(OP) \
1932 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1933 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1934
1935 #define PCREL_SYMOFF_P(OP) \
1936 (GET_CODE (OP) == CONST \
1937 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1938 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1939
1940 #define NON_PIC_REFERENCE_P(OP) \
1941 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1942 || (GET_CODE (OP) == CONST \
1943 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1944 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1945 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1946 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1947 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1948 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1949 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1950 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1951
1952 #define PIC_REFERENCE_P(OP) \
1953 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1954 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1955
1956 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1957 (flag_pic \
1958 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1959 || PCREL_SYMOFF_P (OP)) \
1960 : NON_PIC_REFERENCE_P (OP))
1961 \f
1962 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1963 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1964 || (GET_CODE (X) == SUBREG \
1965 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1966 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1967 && REG_P (SUBREG_REG (X)) \
1968 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1969
1970 /* Since this must be r0, which is a single register class, we must check
1971 SUBREGs more carefully, to be sure that we don't accept one that extends
1972 outside the class. */
1973 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1974 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1975 || (GET_CODE (X) == SUBREG \
1976 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1977 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1978 && REG_P (SUBREG_REG (X)) \
1979 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1980
1981 #ifdef REG_OK_STRICT
1982 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1983 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1984 #else
1985 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1986 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1987 #endif
1988
1989 #define ALLOW_INDEXED_ADDRESS \
1990 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1991
1992 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
1993 do { \
1994 if (sh_legitimate_index_p ((MODE), (OP))) \
1995 goto WIN; \
1996 } while (0)
1997 \f
1998 /* A C compound statement that attempts to replace X, which is an address
1999 that needs reloading, with a valid memory address for an operand of
2000 mode MODE. WIN is a C statement label elsewhere in the code. */
2001
2002 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2003 do { \
2004 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
2005 goto WIN; \
2006 } while (0)
2007 \f
2008 /* Specify the machine mode that this machine uses
2009 for the index in the tablejump instruction. */
2010 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2011
2012 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2013 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2014 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2015 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2016 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2017 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2018 : SImode)
2019
2020 /* Define as C expression which evaluates to nonzero if the tablejump
2021 instruction expects the table to contain offsets from the address of the
2022 table.
2023 Do not define this if the table should contain absolute addresses. */
2024 #define CASE_VECTOR_PC_RELATIVE 1
2025
2026 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2027 #define FLOAT_TYPE_SIZE 32
2028
2029 /* Since the SH2e has only `float' support, it is desirable to make all
2030 floating point types equivalent to `float'. */
2031 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2032
2033 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2034 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2035 #else
2036 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2037 #endif
2038
2039 /* 'char' is signed by default. */
2040 #define DEFAULT_SIGNED_CHAR 1
2041
2042 /* The type of size_t unsigned int. */
2043 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2044
2045 #undef PTRDIFF_TYPE
2046 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2047
2048 #define WCHAR_TYPE "short unsigned int"
2049 #define WCHAR_TYPE_SIZE 16
2050
2051 #define SH_ELF_WCHAR_TYPE "long int"
2052
2053 /* Max number of bytes we can move from memory to memory
2054 in one reasonably fast instruction. */
2055 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2056
2057 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2058 MOVE_MAX is not a compile-time constant. */
2059 #define MAX_MOVE_MAX 8
2060
2061 /* Max number of bytes we want move_by_pieces to be able to copy
2062 efficiently. */
2063 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2064
2065 /* Define if operations between registers always perform the operation
2066 on the full register even if a narrower mode is specified. */
2067 #define WORD_REGISTER_OPERATIONS
2068
2069 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2070 will either zero-extend or sign-extend. The value of this macro should
2071 be the code that says which one of the two operations is implicitly
2072 done, UNKNOWN if none. */
2073 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2074 /* FP registers can load SImode values, but don't implicitly sign-extend
2075 them to DImode. */
2076 #define LOAD_EXTEND_OP(MODE) \
2077 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2078 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2079
2080 /* Define if loading short immediate values into registers sign extends. */
2081 #define SHORT_IMMEDIATES_SIGN_EXTEND
2082
2083 /* Nonzero if access to memory by bytes is no faster than for words. */
2084 #define SLOW_BYTE_ACCESS 1
2085
2086 /* Immediate shift counts are truncated by the output routines (or was it
2087 the assembler?). Shift counts in a register are truncated by SH. Note
2088 that the native compiler puts too large (> 32) immediate shift counts
2089 into a register and shifts by the register, letting the SH decide what
2090 to do instead of doing that itself. */
2091 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2092 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2093 expects - the sign bit is significant - so it appears that we need to
2094 leave this zero for correct SH3 code. */
2095 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2096
2097 /* All integers have the same format so truncation is easy. */
2098 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2099 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2100 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2101
2102 /* Define this if addresses of constant functions
2103 shouldn't be put through pseudo regs where they can be cse'd.
2104 Desirable on machines where ordinary constants are expensive
2105 but a CALL with constant address is cheap. */
2106 /*#define NO_FUNCTION_CSE 1*/
2107
2108 /* The machine modes of pointers and functions. */
2109 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2110 #define FUNCTION_MODE Pmode
2111
2112 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2113 are actually function calls with some special constraints on arguments
2114 and register usage.
2115
2116 These macros tell reorg that the references to arguments and
2117 register clobbers for insns of type sfunc do not appear to happen
2118 until after the millicode call. This allows reorg to put insns
2119 which set the argument registers into the delay slot of the millicode
2120 call -- thus they act more like traditional CALL_INSNs.
2121
2122 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2123 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2124 in particular. */
2125
2126 #define INSN_SETS_ARE_DELAYED(X) \
2127 ((NONJUMP_INSN_P (X) \
2128 && GET_CODE (PATTERN (X)) != SEQUENCE \
2129 && GET_CODE (PATTERN (X)) != USE \
2130 && GET_CODE (PATTERN (X)) != CLOBBER \
2131 && get_attr_is_sfunc (X)))
2132
2133 #define INSN_REFERENCES_ARE_DELAYED(X) \
2134 ((NONJUMP_INSN_P (X) \
2135 && GET_CODE (PATTERN (X)) != SEQUENCE \
2136 && GET_CODE (PATTERN (X)) != USE \
2137 && GET_CODE (PATTERN (X)) != CLOBBER \
2138 && get_attr_is_sfunc (X)))
2139
2140 \f
2141 /* Position Independent Code. */
2142
2143 /* We can't directly access anything that contains a symbol,
2144 nor can we indirect via the constant pool. */
2145 #define LEGITIMATE_PIC_OPERAND_P(X) \
2146 ((! nonpic_symbol_mentioned_p (X) \
2147 && (GET_CODE (X) != SYMBOL_REF \
2148 || ! CONSTANT_POOL_ADDRESS_P (X) \
2149 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2150 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2151
2152 #define SYMBOLIC_CONST_P(X) \
2153 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2154 && nonpic_symbol_mentioned_p (X))
2155 \f
2156 /* Compute extra cost of moving data between one register class
2157 and another. */
2158
2159 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2160 uses this information. Hence, the general register <-> floating point
2161 register information here is not used for SFmode. */
2162
2163 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2164 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2165 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2166
2167 #define REGCLASS_HAS_FP_REG(CLASS) \
2168 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2169 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2170
2171 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2172 would be so that people with slow memory systems could generate
2173 different code that does fewer memory accesses. */
2174
2175 /* A C expression for the cost of a branch instruction. A value of 1
2176 is the default; other values are interpreted relative to that.
2177 The SH1 does not have delay slots, hence we get a pipeline stall
2178 at every branch. The SH4 is superscalar, so the single delay slot
2179 is not sufficient to keep both pipelines filled. */
2180 #define BRANCH_COST(speed_p, predictable_p) \
2181 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2182 \f
2183 /* Assembler output control. */
2184
2185 /* A C string constant describing how to begin a comment in the target
2186 assembler language. The compiler assumes that the comment will end at
2187 the end of the line. */
2188 #define ASM_COMMENT_START "!"
2189
2190 #define ASM_APP_ON ""
2191 #define ASM_APP_OFF ""
2192 #define FILE_ASM_OP "\t.file\n"
2193 #define SET_ASM_OP "\t.set\t"
2194
2195 /* How to change between sections. */
2196
2197 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2198 #define DATA_SECTION_ASM_OP "\t.data"
2199
2200 #if defined CRT_BEGIN || defined CRT_END
2201 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2202 # undef TEXT_SECTION_ASM_OP
2203 # if __SHMEDIA__ == 1 && __SH5__ == 32
2204 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2205 # else
2206 # define TEXT_SECTION_ASM_OP "\t.text"
2207 # endif
2208 #endif
2209
2210
2211 /* If defined, a C expression whose value is a string containing the
2212 assembler operation to identify the following data as
2213 uninitialized global data. If not defined, and neither
2214 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2215 uninitialized global data will be output in the data section if
2216 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2217 used. */
2218 #ifndef BSS_SECTION_ASM_OP
2219 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2220 #endif
2221
2222 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2223 separate, explicit argument. If you define this macro, it is used
2224 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2225 handling the required alignment of the variable. The alignment is
2226 specified as the number of bits.
2227
2228 Try to use function `asm_output_aligned_bss' defined in file
2229 `varasm.c' when defining this macro. */
2230 #ifndef ASM_OUTPUT_ALIGNED_BSS
2231 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2232 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2233 #endif
2234
2235 /* Define this so that jump tables go in same section as the current function,
2236 which could be text or it could be a user defined section. */
2237 #define JUMP_TABLES_IN_TEXT_SECTION 1
2238
2239 #undef DO_GLOBAL_CTORS_BODY
2240 #define DO_GLOBAL_CTORS_BODY \
2241 { \
2242 typedef void (*pfunc) (void); \
2243 extern pfunc __ctors[]; \
2244 extern pfunc __ctors_end[]; \
2245 pfunc *p; \
2246 for (p = __ctors_end; p > __ctors; ) \
2247 { \
2248 (*--p)(); \
2249 } \
2250 }
2251
2252 #undef DO_GLOBAL_DTORS_BODY
2253 #define DO_GLOBAL_DTORS_BODY \
2254 { \
2255 typedef void (*pfunc) (void); \
2256 extern pfunc __dtors[]; \
2257 extern pfunc __dtors_end[]; \
2258 pfunc *p; \
2259 for (p = __dtors; p < __dtors_end; p++) \
2260 { \
2261 (*p)(); \
2262 } \
2263 }
2264
2265 #define ASM_OUTPUT_REG_PUSH(file, v) \
2266 { \
2267 if (TARGET_SHMEDIA) \
2268 { \
2269 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2270 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2271 } \
2272 else \
2273 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2274 }
2275
2276 #define ASM_OUTPUT_REG_POP(file, v) \
2277 { \
2278 if (TARGET_SHMEDIA) \
2279 { \
2280 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2281 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2282 } \
2283 else \
2284 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2285 }
2286
2287 /* DBX register number for a given compiler register number. */
2288 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2289 to match gdb. */
2290 /* svr4.h undefines this macro, yet we really want to use the same numbers
2291 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2292 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2293 register exists, so we should return -1 for invalid register numbers. */
2294 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2295
2296 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2297 used to use the encodings 245..260, but that doesn't make sense:
2298 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2299 the FP registers stay the same when switching between compact and media
2300 mode. Hence, we also need to use the same dwarf frame columns.
2301 Likewise, we need to support unwind information for SHmedia registers
2302 even in compact code. */
2303 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2304 (IN_RANGE ((REGNO), \
2305 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2306 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2307 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2308 : ((int) (REGNO) >= FIRST_FP_REG \
2309 && ((int) (REGNO) \
2310 <= (FIRST_FP_REG + \
2311 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2312 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2313 + (TARGET_SH5 ? 77 : 25)) \
2314 : XD_REGISTER_P (REGNO) \
2315 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2316 : TARGET_REGISTER_P (REGNO) \
2317 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2318 : (REGNO) == PR_REG \
2319 ? (TARGET_SH5 ? 18 : 17) \
2320 : (REGNO) == PR_MEDIA_REG \
2321 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2322 : (REGNO) == GBR_REG \
2323 ? (TARGET_SH5 ? 238 : 18) \
2324 : (REGNO) == MACH_REG \
2325 ? (TARGET_SH5 ? 239 : 20) \
2326 : (REGNO) == MACL_REG \
2327 ? (TARGET_SH5 ? 240 : 21) \
2328 : (REGNO) == T_REG \
2329 ? (TARGET_SH5 ? 242 : 22) \
2330 : (REGNO) == FPUL_REG \
2331 ? (TARGET_SH5 ? 244 : 23) \
2332 : (REGNO) == FPSCR_REG \
2333 ? (TARGET_SH5 ? 243 : 24) \
2334 : (unsigned) -1)
2335
2336 /* This is how to output a reference to a symbol_ref. On SH5,
2337 references to non-code symbols must be preceded by `datalabel'. */
2338 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2339 do \
2340 { \
2341 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2342 fputs ("datalabel ", (FILE)); \
2343 assemble_name ((FILE), XSTR ((SYM), 0)); \
2344 } \
2345 while (0)
2346
2347 /* This is how to output an assembler line
2348 that says to advance the location counter
2349 to a multiple of 2**LOG bytes. */
2350
2351 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2352 if ((LOG) != 0) \
2353 fprintf ((FILE), "\t.align %d\n", (LOG))
2354
2355 /* Globalizing directive for a label. */
2356 #define GLOBAL_ASM_OP "\t.global\t"
2357
2358 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2359
2360 /* Output a relative address table. */
2361
2362 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2363 switch (GET_MODE (BODY)) \
2364 { \
2365 case SImode: \
2366 if (TARGET_SH5) \
2367 { \
2368 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2369 (VALUE), (REL)); \
2370 break; \
2371 } \
2372 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2373 break; \
2374 case HImode: \
2375 if (TARGET_SH5) \
2376 { \
2377 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2378 (VALUE), (REL)); \
2379 break; \
2380 } \
2381 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2382 break; \
2383 case QImode: \
2384 if (TARGET_SH5) \
2385 { \
2386 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2387 (VALUE), (REL)); \
2388 break; \
2389 } \
2390 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2391 break; \
2392 default: \
2393 break; \
2394 }
2395
2396 /* Output an absolute table element. */
2397
2398 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2399 if (! optimize || TARGET_BIGTABLE) \
2400 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2401 else \
2402 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2403
2404 \f
2405 /* A C statement to be executed just prior to the output of
2406 assembler code for INSN, to modify the extracted operands so
2407 they will be output differently.
2408
2409 Here the argument OPVEC is the vector containing the operands
2410 extracted from INSN, and NOPERANDS is the number of elements of
2411 the vector which contain meaningful data for this insn.
2412 The contents of this vector are what will be used to convert the insn
2413 template into assembler code, so you can change the assembler output
2414 by changing the contents of the vector. */
2415
2416 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2417 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2418
2419 /* Recognize machine-specific patterns that may appear within
2420 constants. Used for PIC-specific UNSPECs. */
2421 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2422 do \
2423 if (GET_CODE (X) == UNSPEC) \
2424 { \
2425 switch (XINT ((X), 1)) \
2426 { \
2427 case UNSPEC_DATALABEL: \
2428 fputs ("datalabel ", (STREAM)); \
2429 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2430 break; \
2431 case UNSPEC_PIC: \
2432 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2433 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2434 break; \
2435 case UNSPEC_GOT: \
2436 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2437 fputs ("@GOT", (STREAM)); \
2438 break; \
2439 case UNSPEC_GOTOFF: \
2440 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2441 fputs ("@GOTOFF", (STREAM)); \
2442 break; \
2443 case UNSPEC_PLT: \
2444 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2445 fputs ("@PLT", (STREAM)); \
2446 break; \
2447 case UNSPEC_GOTPLT: \
2448 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2449 fputs ("@GOTPLT", (STREAM)); \
2450 break; \
2451 case UNSPEC_DTPOFF: \
2452 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2453 fputs ("@DTPOFF", (STREAM)); \
2454 break; \
2455 case UNSPEC_GOTTPOFF: \
2456 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2457 fputs ("@GOTTPOFF", (STREAM)); \
2458 break; \
2459 case UNSPEC_TPOFF: \
2460 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2461 fputs ("@TPOFF", (STREAM)); \
2462 break; \
2463 case UNSPEC_CALLER: \
2464 { \
2465 char name[32]; \
2466 /* LPCS stands for Label for PIC Call Site. */ \
2467 ASM_GENERATE_INTERNAL_LABEL \
2468 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2469 assemble_name ((STREAM), name); \
2470 } \
2471 break; \
2472 case UNSPEC_EXTRACT_S16: \
2473 case UNSPEC_EXTRACT_U16: \
2474 { \
2475 rtx val, shift; \
2476 \
2477 val = XVECEXP (X, 0, 0); \
2478 shift = XVECEXP (X, 0, 1); \
2479 fputc ('(', STREAM); \
2480 if (shift != const0_rtx) \
2481 fputc ('(', STREAM); \
2482 if (GET_CODE (val) == CONST \
2483 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
2484 { \
2485 fputc ('(', STREAM); \
2486 output_addr_const (STREAM, val); \
2487 fputc (')', STREAM); \
2488 } \
2489 else \
2490 output_addr_const (STREAM, val); \
2491 if (shift != const0_rtx) \
2492 { \
2493 fputs (" >> ", STREAM); \
2494 output_addr_const (STREAM, shift); \
2495 fputc (')', STREAM); \
2496 } \
2497 fputs (" & 65535)", STREAM); \
2498 } \
2499 break; \
2500 case UNSPEC_SYMOFF: \
2501 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2502 fputc ('-', STREAM); \
2503 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
2504 { \
2505 fputc ('(', STREAM); \
2506 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2507 fputc (')', STREAM); \
2508 } \
2509 else \
2510 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2511 break; \
2512 case UNSPEC_PCREL_SYMOFF: \
2513 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2514 fputs ("-(", STREAM); \
2515 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2516 fputs ("-.)", STREAM); \
2517 break; \
2518 default: \
2519 goto FAIL; \
2520 } \
2521 break; \
2522 } \
2523 else \
2524 goto FAIL; \
2525 while (0)
2526
2527 \f
2528 extern struct rtx_def *sh_compare_op0;
2529 extern struct rtx_def *sh_compare_op1;
2530
2531 /* Which processor to schedule for. The elements of the enumeration must
2532 match exactly the cpu attribute in the sh.md file. */
2533
2534 enum processor_type {
2535 PROCESSOR_SH1,
2536 PROCESSOR_SH2,
2537 PROCESSOR_SH2E,
2538 PROCESSOR_SH2A,
2539 PROCESSOR_SH3,
2540 PROCESSOR_SH3E,
2541 PROCESSOR_SH4,
2542 PROCESSOR_SH4A,
2543 PROCESSOR_SH5
2544 };
2545
2546 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2547 extern enum processor_type sh_cpu;
2548
2549 extern int optimize; /* needed for gen_casesi. */
2550
2551 enum mdep_reorg_phase_e
2552 {
2553 SH_BEFORE_MDEP_REORG,
2554 SH_INSERT_USES_LABELS,
2555 SH_SHORTEN_BRANCHES0,
2556 SH_FIXUP_PCLOAD,
2557 SH_SHORTEN_BRANCHES1,
2558 SH_AFTER_MDEP_REORG
2559 };
2560
2561 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2562
2563 /* Handle Renesas compiler's pragmas. */
2564 #define REGISTER_TARGET_PRAGMAS() do { \
2565 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2566 c_register_pragma (0, "trapa", sh_pr_trapa); \
2567 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2568 } while (0)
2569
2570 extern tree sh_deferred_function_attributes;
2571 extern tree *sh_deferred_function_attributes_tail;
2572
2573 /* Set when processing a function with interrupt attribute. */
2574
2575 extern int current_function_interrupt;
2576
2577 \f
2578 /* Instructions with unfilled delay slots take up an
2579 extra two bytes for the nop in the delay slot.
2580 sh-dsp parallel processing insns are four bytes long. */
2581
2582 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2583 (LENGTH) += sh_insn_length_adjustment (X);
2584 \f
2585 /* Define this macro if it is advisable to hold scalars in registers
2586 in a wider mode than that declared by the program. In such cases,
2587 the value is constrained to be within the bounds of the declared
2588 type, but kept valid in the wider mode. The signedness of the
2589 extension may differ from that of the type.
2590
2591 Leaving the unsignedp unchanged gives better code than always setting it
2592 to 0. This is despite the fact that we have only signed char and short
2593 load instructions. */
2594 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2595 if (GET_MODE_CLASS (MODE) == MODE_INT \
2596 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2597 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2598 (MODE) = (TARGET_SH1 ? SImode \
2599 : TARGET_SHMEDIA32 ? SImode : DImode);
2600
2601 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2602
2603 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2604
2605 /* Better to allocate once the maximum space for outgoing args in the
2606 prologue rather than duplicate around each call. */
2607 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2608
2609 #define SH_DYNAMIC_SHIFT_COST \
2610 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2611
2612
2613 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2614
2615 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2616
2617 #define ACTUAL_NORMAL_MODE(ENTITY) \
2618 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2619
2620 #define NORMAL_MODE(ENTITY) \
2621 (sh_cfun_interrupt_handler_p () \
2622 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2623 : ACTUAL_NORMAL_MODE (ENTITY))
2624
2625 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2626
2627 #define MODE_EXIT(ENTITY) \
2628 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2629
2630 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2631 && (REGNO) == FPSCR_REG)
2632
2633 #define MODE_NEEDED(ENTITY, INSN) \
2634 (recog_memoized (INSN) >= 0 \
2635 ? get_attr_fp_mode (INSN) \
2636 : FP_MODE_NONE)
2637
2638 #define MODE_AFTER(MODE, INSN) \
2639 (TARGET_HITACHI \
2640 && recog_memoized (INSN) >= 0 \
2641 && get_attr_fp_set (INSN) != FP_SET_NONE \
2642 ? (int) get_attr_fp_set (INSN) \
2643 : (MODE))
2644
2645 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2646 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2647
2648 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2649 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2650
2651 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2652 sh_can_redirect_branch ((INSN), (SEQ))
2653
2654 #define DWARF_FRAME_RETURN_COLUMN \
2655 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2656
2657 #define EH_RETURN_DATA_REGNO(N) \
2658 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2659
2660 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2661 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2662
2663 /* We have to distinguish between code and data, so that we apply
2664 datalabel where and only where appropriate. Use sdataN for data. */
2665 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2666 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2667 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2668 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2669
2670 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2671 indirect are handled automatically. */
2672 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2673 do { \
2674 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2675 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2676 { \
2677 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2678 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2679 if (0) goto DONE; \
2680 } \
2681 } while (0)
2682
2683 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2684 /* SH constant pool breaks the devices in crtstuff.c to control section
2685 in where code resides. We have to write it as asm code. */
2686 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2687 asm (SECTION_OP "\n\
2688 mov.l 1f,r1\n\
2689 mova 2f,r0\n\
2690 braf r1\n\
2691 lds r0,pr\n\
2692 0: .p2align 2\n\
2693 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2694 2:\n" TEXT_SECTION_ASM_OP);
2695 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2696
2697 /* FIXME: middle-end support for highpart optimizations is missing. */
2698 #define high_life_started reload_in_progress
2699
2700 #endif /* ! GCC_SH_H */
GCC graphite test results