gcc/config/s390/s390.h

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   5                   Ulrich Weigand (uweigand@de.ibm.com).
   6                   Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free
  12 Software Foundation; either version 3, or (at your option) any later
  13 version.
  14
  15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18 for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not see
  22 <http://www.gnu.org/licenses/>.  */
  23
  24 #ifndef _S390_H
  25 #define _S390_H
  26
  27 /* Which processor to generate code or schedule for. The cpu attribute
  28    defines a list that mirrors this list, so changes to s390.md must be
  29    made at the same time.  */
  30
  31 enum processor_type
  32 {
  33   PROCESSOR_9672_G5,
  34   PROCESSOR_9672_G6,
  35   PROCESSOR_2064_Z900,
  36   PROCESSOR_2084_Z990,
  37   PROCESSOR_2094_Z9_109,
  38   PROCESSOR_2097_Z10,
  39   PROCESSOR_max
  40 };
  41
  42 /* Optional architectural facilities supported by the processor.  */
  43
  44 enum processor_flags
  45 {
  46   PF_IEEE_FLOAT = 1,
  47   PF_ZARCH = 2,
  48   PF_LONG_DISPLACEMENT = 4,
  49   PF_EXTIMM = 8,
  50   PF_DFP = 16,
  51   PF_Z10 = 32
  52 };
  53
  54 extern enum processor_type s390_tune;
  55 extern int s390_tune_flags;
  56
  57 /* This is necessary to avoid a warning about comparing different enum
  58    types.  */
  59 #define s390_tune_attr ((enum attr_cpu)s390_tune)
  60
  61 extern enum processor_type s390_arch;
  62 extern int s390_arch_flags;
  63
  64 /* These flags indicate that the generated code should run on a cpu
  65    providing the respective hardware facility regardless of the
  66    current cpu mode (ESA or z/Architecture).  */
  67
  68 #define TARGET_CPU_IEEE_FLOAT \
  69         (s390_arch_flags & PF_IEEE_FLOAT)
  70 #define TARGET_CPU_ZARCH \
  71         (s390_arch_flags & PF_ZARCH)
  72 #define TARGET_CPU_LONG_DISPLACEMENT \
  73         (s390_arch_flags & PF_LONG_DISPLACEMENT)
  74 #define TARGET_CPU_EXTIMM \
  75         (s390_arch_flags & PF_EXTIMM)
  76 #define TARGET_CPU_DFP \
  77         (s390_arch_flags & PF_DFP)
  78 #define TARGET_CPU_Z10 \
  79         (s390_arch_flags & PF_Z10)
  80
  81 /* These flags indicate that the generated code should run on a cpu
  82    providing the respective hardware facility when run in
  83    z/Architecture mode.  */
  84
  85 #define TARGET_LONG_DISPLACEMENT \
  86        (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
  87 #define TARGET_EXTIMM \
  88        (TARGET_ZARCH && TARGET_CPU_EXTIMM)
  89 #define TARGET_DFP \
  90        (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
  91 #define TARGET_Z10 \
  92        (TARGET_ZARCH && TARGET_CPU_Z10)
  93
  94 /* Run-time target specification.  */
  95
  96 /* Defaults for option flags defined only on some subtargets.  */
  97 #ifndef TARGET_TPF_PROFILING
  98 #define TARGET_TPF_PROFILING 0
  99 #endif
 100
 101 /* This will be overridden by OS headers.  */
 102 #define TARGET_TPF 0
 103
 104 /* Target CPU builtins.  */
 105 #define TARGET_CPU_CPP_BUILTINS()                       \
 106   do                                                    \
 107     {                                                   \
 108       builtin_assert ("cpu=s390");                      \
 109       builtin_assert ("machine=s390");                  \
 110       builtin_define ("__s390__");                      \
 111       if (TARGET_ZARCH)                                 \
 112         builtin_define ("__zarch__");                   \
 113       if (TARGET_64BIT)                                 \
 114         builtin_define ("__s390x__");                   \
 115       if (TARGET_LONG_DOUBLE_128)                       \
 116         builtin_define ("__LONG_DOUBLE_128__");         \
 117     }                                                   \
 118   while (0)
 119
 120 #ifdef DEFAULT_TARGET_64BIT
 121 #define TARGET_DEFAULT             (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP)
 122 #else
 123 #define TARGET_DEFAULT             0
 124 #endif
 125
 126 /* Support for configure-time defaults.  */
 127 #define OPTION_DEFAULT_SPECS                                    \
 128   { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" },                 \
 129   { "arch", "%{!march=*:-march=%(VALUE)}" },                    \
 130   { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
 131
 132 /* Defaulting rules.  */
 133 #ifdef DEFAULT_TARGET_64BIT
 134 #define DRIVER_SELF_SPECS                                       \
 135   "%{!m31:%{!m64:-m64}}",                                       \
 136   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
 137   "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
 138 #else
 139 #define DRIVER_SELF_SPECS                                       \
 140   "%{!m31:%{!m64:-m31}}",                                       \
 141   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
 142   "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
 143 #endif
 144
 145 /* Target version string.  Overridden by the OS header.  */
 146 #ifdef DEFAULT_TARGET_64BIT
 147 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
 148 #else
 149 #define TARGET_VERSION fprintf (stderr, " (S/390)");
 150 #endif
 151
 152 /* Frame pointer is not used for debugging.  */
 153 #define CAN_DEBUG_WITHOUT_FP
 154
 155 /* Constants needed to control the TEST DATA CLASS (TDC) instruction.  */
 156 #define S390_TDC_POSITIVE_ZERO                     (1 << 11)
 157 #define S390_TDC_NEGATIVE_ZERO                     (1 << 10)
 158 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER    (1 << 9)
 159 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER    (1 << 8)
 160 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER  (1 << 7)
 161 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER  (1 << 6)
 162 #define S390_TDC_POSITIVE_INFINITY                 (1 << 5)
 163 #define S390_TDC_NEGATIVE_INFINITY                 (1 << 4)
 164 #define S390_TDC_POSITIVE_QUIET_NAN                (1 << 3)
 165 #define S390_TDC_NEGATIVE_QUIET_NAN                (1 << 2)
 166 #define S390_TDC_POSITIVE_SIGNALING_NAN            (1 << 1)
 167 #define S390_TDC_NEGATIVE_SIGNALING_NAN            (1 << 0)
 168
 169 /* The following values are different for DFP.  */
 170 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
 171 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
 172 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER   (1 << 7)
 173 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER   (1 << 6)
 174
 175 /* For signbit, the BFP-DFP-difference makes no difference. */
 176 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
 177                           | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
 178                           | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
 179                           | S390_TDC_NEGATIVE_INFINITY \
 180                           | S390_TDC_NEGATIVE_QUIET_NAN \
 181                           | S390_TDC_NEGATIVE_SIGNALING_NAN )
 182
 183 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
 184                           | S390_TDC_NEGATIVE_INFINITY )
 185
 186 /* Target machine storage layout.  */
 187
 188 /* Everything is big-endian.  */
 189 #define BITS_BIG_ENDIAN 1
 190 #define BYTES_BIG_ENDIAN 1
 191 #define WORDS_BIG_ENDIAN 1
 192
 193 #define STACK_SIZE_MODE (Pmode)
 194
 195 #ifndef IN_LIBGCC2
 196
 197 /* Width of a word, in units (bytes).  */
 198   #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
 199
 200 /* Width of a pointer.  To be used instead of UNITS_PER_WORD in
 201    ABI-relevant contexts.  This always matches
 202    GET_MODE_SIZE (Pmode).  */
 203   #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
 204   #define MIN_UNITS_PER_WORD 4
 205   #define MAX_BITS_PER_WORD 64
 206 #else
 207
 208   /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
 209      the library should export TImode functions or not.  Thus, we have
 210      to redefine UNITS_PER_WORD depending on __s390x__ for libgcc.  */
 211   #ifdef __s390x__
 212     #define UNITS_PER_WORD 8
 213   #else
 214     #define UNITS_PER_WORD 4
 215   #endif
 216 #endif
 217
 218 /* Width of a pointer, in bits.  */
 219 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
 220
 221 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 222 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
 223
 224 /* Boundary (in *bits*) on which stack pointer should be aligned.  */
 225 #define STACK_BOUNDARY 64
 226
 227 /* Allocation boundary (in *bits*) for the code of a function.  */
 228 #define FUNCTION_BOUNDARY 32
 229
 230 /* There is no point aligning anything to a rounder boundary than this.  */
 231 #define BIGGEST_ALIGNMENT 64
 232
 233 /* Alignment of field after `int : 0' in a structure.  */
 234 #define EMPTY_FIELD_BOUNDARY 32
 235
 236 /* Alignment on even addresses for LARL instruction.  */
 237 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
 238 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
 239
 240 /* Alignment is not required by the hardware.  */
 241 #define STRICT_ALIGNMENT 0
 242
 243 /* Mode of stack savearea.
 244    FUNCTION is VOIDmode because calling convention maintains SP.
 245    BLOCK needs Pmode for SP.
 246    NONLOCAL needs twice Pmode to maintain both backchain and SP.  */
 247 #define STACK_SAVEAREA_MODE(LEVEL)      \
 248   (LEVEL == SAVE_FUNCTION ? VOIDmode    \
 249   : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
 250
 251
 252 /* Type layout.  */
 253
 254 /* Sizes in bits of the source language data types.  */
 255 #define SHORT_TYPE_SIZE 16
 256 #define INT_TYPE_SIZE 32
 257 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
 258 #define LONG_LONG_TYPE_SIZE 64
 259 #define FLOAT_TYPE_SIZE 32
 260 #define DOUBLE_TYPE_SIZE 64
 261 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
 262
 263 /* Define this to set long double type size to use in libgcc2.c, which can
 264    not depend on target_flags.  */
 265 #ifdef __LONG_DOUBLE_128__
 266 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
 267 #else
 268 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
 269 #endif
 270
 271 /* Work around target_flags dependency in ada/targtyps.c.  */
 272 #define WIDEST_HARDWARE_FP_SIZE 64
 273
 274 /* We use "unsigned char" as default.  */
 275 #define DEFAULT_SIGNED_CHAR 0
 276
 277
 278 /* Register usage.  */
 279
 280 /* We have 16 general purpose registers (registers 0-15),
 281    and 16 floating point registers (registers 16-31).
 282    (On non-IEEE machines, we have only 4 fp registers.)
 283
 284    Amongst the general purpose registers, some are used
 285    for specific purposes:
 286    GPR 11: Hard frame pointer (if needed)
 287    GPR 12: Global offset table pointer (if needed)
 288    GPR 13: Literal pool base register
 289    GPR 14: Return address register
 290    GPR 15: Stack pointer
 291
 292    Registers 32-35 are 'fake' hard registers that do not
 293    correspond to actual hardware:
 294    Reg 32: Argument pointer
 295    Reg 33: Condition code
 296    Reg 34: Frame pointer
 297    Reg 35: Return address pointer
 298
 299    Registers 36 and 37 are mapped to access registers
 300    0 and 1, used to implement thread-local storage.  */
 301
 302 #define FIRST_PSEUDO_REGISTER 38
 303
 304 /* Standard register usage.  */
 305 #define GENERAL_REGNO_P(N)      ((int)(N) >= 0 && (N) < 16)
 306 #define ADDR_REGNO_P(N)         ((N) >= 1 && (N) < 16)
 307 #define FP_REGNO_P(N)           ((N) >= 16 && (N) < 32)
 308 #define CC_REGNO_P(N)           ((N) == 33)
 309 #define FRAME_REGNO_P(N)        ((N) == 32 || (N) == 34 || (N) == 35)
 310 #define ACCESS_REGNO_P(N)       ((N) == 36 || (N) == 37)
 311
 312 #define GENERAL_REG_P(X)        (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
 313 #define ADDR_REG_P(X)           (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
 314 #define FP_REG_P(X)             (REG_P (X) && FP_REGNO_P (REGNO (X)))
 315 #define CC_REG_P(X)             (REG_P (X) && CC_REGNO_P (REGNO (X)))
 316 #define FRAME_REG_P(X)          (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
 317 #define ACCESS_REG_P(X)         (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
 318
 319 /* Set up fixed registers and calling convention:
 320
 321    GPRs 0-5 are always call-clobbered,
 322    GPRs 6-15 are always call-saved.
 323    GPR 12 is fixed if used as GOT pointer.
 324    GPR 13 is always fixed (as literal pool pointer).
 325    GPR 14 is always fixed on S/390 machines (as return address).
 326    GPR 15 is always fixed (as stack pointer).
 327    The 'fake' hard registers are call-clobbered and fixed.
 328    The access registers are call-saved and fixed.
 329
 330    On 31-bit, FPRs 18-19 are call-clobbered;
 331    on 64-bit, FPRs 24-31 are call-clobbered.
 332    The remaining FPRs are call-saved.  */
 333
 334 #define FIXED_REGISTERS                         \
 335 { 0, 0, 0, 0,                                   \
 336   0, 0, 0, 0,                                   \
 337   0, 0, 0, 0,                                   \
 338   0, 1, 1, 1,                                   \
 339   0, 0, 0, 0,                                   \
 340   0, 0, 0, 0,                                   \
 341   0, 0, 0, 0,                                   \
 342   0, 0, 0, 0,                                   \
 343   1, 1, 1, 1,                                   \
 344   1, 1 }
 345
 346 #define CALL_USED_REGISTERS                     \
 347 { 1, 1, 1, 1,                                   \
 348   1, 1, 0, 0,                                   \
 349   0, 0, 0, 0,                                   \
 350   0, 1, 1, 1,                                   \
 351   1, 1, 1, 1,                                   \
 352   1, 1, 1, 1,                                   \
 353   1, 1, 1, 1,                                   \
 354   1, 1, 1, 1,                                   \
 355   1, 1, 1, 1,                                   \
 356   1, 1 }
 357
 358 #define CALL_REALLY_USED_REGISTERS              \
 359 { 1, 1, 1, 1,                                   \
 360   1, 1, 0, 0,                                   \
 361   0, 0, 0, 0,                                   \
 362   0, 0, 0, 0,                                   \
 363   1, 1, 1, 1,                                   \
 364   1, 1, 1, 1,                                   \
 365   1, 1, 1, 1,                                   \
 366   1, 1, 1, 1,                                   \
 367   1, 1, 1, 1,                                   \
 368   0, 0 }
 369
 370 #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage ()
 371
 372 /* Preferred register allocation order.  */
 373 #define REG_ALLOC_ORDER                                         \
 374 {  1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13,            \
 375    16, 17, 18, 19, 20, 21, 22, 23,                              \
 376    24, 25, 26, 27, 28, 29, 30, 31,                              \
 377    15, 32, 33, 34, 35, 36, 37 }
 378
 379
 380 /* Fitting values into registers.  */
 381
 382 /* Integer modes <= word size fit into any GPR.
 383    Integer modes > word size fit into successive GPRs, starting with
 384    an even-numbered register.
 385    SImode and DImode fit into FPRs as well.
 386
 387    Floating point modes <= word size fit into any FPR or GPR.
 388    Floating point modes > word size (i.e. DFmode on 32-bit) fit
 389    into any FPR, or an even-odd GPR pair.
 390    TFmode fits only into an even-odd FPR pair.
 391
 392    Complex floating point modes fit either into two FPRs, or into
 393    successive GPRs (again starting with an even number).
 394    TCmode fits only into two successive even-odd FPR pairs.
 395
 396    Condition code modes fit only into the CC register.  */
 397
 398 /* Because all registers in a class have the same size HARD_REGNO_NREGS
 399    is equivalent to CLASS_MAX_NREGS.  */
 400 #define HARD_REGNO_NREGS(REGNO, MODE)                           \
 401   s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
 402
 403 #define HARD_REGNO_MODE_OK(REGNO, MODE)         \
 404   s390_hard_regno_mode_ok ((REGNO), (MODE))
 405
 406 #define HARD_REGNO_RENAME_OK(FROM, TO)          \
 407   s390_hard_regno_rename_ok (FROM, TO)
 408
 409 #define MODES_TIEABLE_P(MODE1, MODE2)           \
 410    (((MODE1) == SFmode || (MODE1) == DFmode)    \
 411    == ((MODE2) == SFmode || (MODE2) == DFmode))
 412
 413 /* When generating code that runs in z/Architecture mode,
 414    but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
 415    the ABI guarantees only that the lower 4 bytes are
 416    saved across calls, however.  */
 417 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)             \
 418   (!TARGET_64BIT && TARGET_ZARCH                                \
 419    && GET_MODE_SIZE (MODE) > 4                                  \
 420    && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
 421
 422 /* Maximum number of registers to represent a value of mode MODE
 423    in a register of class CLASS.  */
 424 #define CLASS_MAX_NREGS(CLASS, MODE)                                    \
 425   s390_class_max_nregs ((CLASS), (MODE))
 426
 427 /* If a 4-byte value is loaded into a FPR, it is placed into the
 428    *upper* half of the register, not the lower.  Therefore, we
 429    cannot use SUBREGs to switch between modes in FP registers.
 430    Likewise for access registers, since they have only half the
 431    word size on 64-bit.  */
 432 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)                       \
 433   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)                           \
 434    ? ((reg_classes_intersect_p (FP_REGS, CLASS)                         \
 435        && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8))         \
 436       || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0)
 437
 438 /* Register classes.  */
 439
 440 /* We use the following register classes:
 441    GENERAL_REGS     All general purpose registers
 442    ADDR_REGS        All general purpose registers except %r0
 443                     (These registers can be used in address generation)
 444    FP_REGS          All floating point registers
 445    CC_REGS          The condition code register
 446    ACCESS_REGS      The access registers
 447
 448    GENERAL_FP_REGS  Union of GENERAL_REGS and FP_REGS
 449    ADDR_FP_REGS     Union of ADDR_REGS and FP_REGS
 450    GENERAL_CC_REGS  Union of GENERAL_REGS and CC_REGS
 451    ADDR_CC_REGS     Union of ADDR_REGS and CC_REGS
 452
 453    NO_REGS          No registers
 454    ALL_REGS         All registers
 455
 456    Note that the 'fake' frame pointer and argument pointer registers
 457    are included amongst the address registers here.  */
 458
 459 enum reg_class
 460 {
 461   NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
 462   ADDR_CC_REGS, GENERAL_CC_REGS,
 463   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
 464   ALL_REGS, LIM_REG_CLASSES
 465 };
 466 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 467
 468 #define REG_CLASS_NAMES                                                 \
 469 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS",     \
 470   "ADDR_CC_REGS", "GENERAL_CC_REGS",                                    \
 471   "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
 472
 473 /* Class -> register mapping.  */
 474 #define REG_CLASS_CONTENTS \
 475 {                                                       \
 476   { 0x00000000, 0x00000000 },   /* NO_REGS */           \
 477   { 0x00000000, 0x00000002 },   /* CC_REGS */           \
 478   { 0x0000fffe, 0x0000000d },   /* ADDR_REGS */         \
 479   { 0x0000ffff, 0x0000000d },   /* GENERAL_REGS */      \
 480   { 0x00000000, 0x00000030 },   /* ACCESS_REGS */       \
 481   { 0x0000fffe, 0x0000000f },   /* ADDR_CC_REGS */      \
 482   { 0x0000ffff, 0x0000000f },   /* GENERAL_CC_REGS */   \
 483   { 0xffff0000, 0x00000000 },   /* FP_REGS */           \
 484   { 0xfffffffe, 0x0000000d },   /* ADDR_FP_REGS */      \
 485   { 0xffffffff, 0x0000000d },   /* GENERAL_FP_REGS */   \
 486   { 0xffffffff, 0x0000003f },   /* ALL_REGS */          \
 487 }
 488
 489 /* The following macro defines cover classes for Integrated Register
 490    Allocator.  Cover classes is a set of non-intersected register
 491    classes covering all hard registers used for register allocation
 492    purpose.  Any move between two registers of a cover class should be
 493    cheaper than load or store of the registers.  The macro value is
 494    array of register classes with LIM_REG_CLASSES used as the end
 495    marker.  */
 496
 497 #define IRA_COVER_CLASSES                                                    \
 498 {                                                                            \
 499   GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES               \
 500 }
 501
 502 /* In some case register allocation order is not enough for IRA to
 503    generate a good code.  The following macro (if defined) increases
 504    cost of REGNO for a pseudo approximately by pseudo usage frequency
 505    multiplied by the macro value.
 506
 507    We avoid usage of BASE_REGNUM by nonzero macro value because the
 508    reload can decide not to use the hard register because some
 509    constant was forced to be in memory.  */
 510 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno)       \
 511   (regno == BASE_REGNUM ? 0.0 : 0.5)
 512
 513 /* Register -> class mapping.  */
 514 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 515 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
 516
 517 /* ADDR_REGS can be used as base or index register.  */
 518 #define INDEX_REG_CLASS ADDR_REGS
 519 #define BASE_REG_CLASS ADDR_REGS
 520
 521 /* Check whether REGNO is a hard register of the suitable class
 522    or a pseudo register currently allocated to one such.  */
 523 #define REGNO_OK_FOR_INDEX_P(REGNO)                                     \
 524     (((REGNO) < FIRST_PSEUDO_REGISTER                                   \
 525       && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS)                        \
 526      || ADDR_REGNO_P (reg_renumber[REGNO]))
 527 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
 528
 529
 530 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
 531    return the class of reg to actually use.  */
 532 #define PREFERRED_RELOAD_CLASS(X, CLASS)        \
 533   s390_preferred_reload_class ((X), (CLASS))
 534
 535 /* We need secondary memory to move data between GPRs and FPRs.  With
 536    DFP the ldgr lgdr instructions are available.  But these
 537    instructions do not handle GPR pairs so it is not possible for 31
 538    bit.  */
 539 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
 540  ((CLASS1) != (CLASS2)                                \
 541   && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)     \
 542   && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8))
 543
 544 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
 545    because the movsi and movsf patterns don't handle r/f moves.  */
 546 #define SECONDARY_MEMORY_NEEDED_MODE(MODE)              \
 547  (GET_MODE_BITSIZE (MODE) < 32                          \
 548   ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)        \
 549   : MODE)
 550
 551
 552 /* Stack layout and calling conventions.  */
 553
 554 /* Our stack grows from higher to lower addresses.  However, local variables
 555    are accessed by positive offsets, and function arguments are stored at
 556    increasing addresses.  */
 557 #define STACK_GROWS_DOWNWARD
 558 #define FRAME_GROWS_DOWNWARD 1
 559 /* #undef ARGS_GROW_DOWNWARD */
 560
 561 /* The basic stack layout looks like this: the stack pointer points
 562    to the register save area for called functions.  Above that area
 563    is the location to place outgoing arguments.  Above those follow
 564    dynamic allocations (alloca), and finally the local variables.  */
 565
 566 /* Offset from stack-pointer to first location of outgoing args.  */
 567 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
 568
 569 /* Offset within stack frame to start allocating local variables at.  */
 570 #define STARTING_FRAME_OFFSET 0
 571
 572 /* Offset from the stack pointer register to an item dynamically
 573    allocated on the stack, e.g., by `alloca'.  */
 574 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
 575   (STACK_POINTER_OFFSET + crtl->outgoing_args_size)
 576
 577 /* Offset of first parameter from the argument pointer register value.
 578    We have a fake argument pointer register that points directly to
 579    the argument area.  */
 580 #define FIRST_PARM_OFFSET(FNDECL) 0
 581
 582 /* Defining this macro makes __builtin_frame_address(0) and
 583    __builtin_return_address(0) work with -fomit-frame-pointer.  */
 584 #define INITIAL_FRAME_ADDRESS_RTX                                             \
 585   (plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
 586
 587 /* The return address of the current frame is retrieved
 588    from the initial value of register RETURN_REGNUM.
 589    For frames farther back, we use the stack slot where
 590    the corresponding RETURN_REGNUM register was saved.  */
 591 #define DYNAMIC_CHAIN_ADDRESS(FRAME)                                          \
 592   (TARGET_PACKED_STACK ?                                                      \
 593    plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
 594
 595 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
 596    builtin_frame_address.  Otherwise arg pointer -
 597    STACK_POINTER_OFFSET would be returned for
 598    __builtin_frame_address(0) what might result in an address pointing
 599    somewhere into the middle of the local variables since the packed
 600    stack layout generally does not need all the bytes in the register
 601    save area.  */
 602 #define FRAME_ADDR_RTX(FRAME)                   \
 603   DYNAMIC_CHAIN_ADDRESS ((FRAME))
 604
 605 #define RETURN_ADDR_RTX(COUNT, FRAME)                                         \
 606   s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
 607
 608 /* In 31-bit mode, we need to mask off the high bit of return addresses.  */
 609 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
 610
 611
 612 /* Exception handling.  */
 613
 614 /* Describe calling conventions for DWARF-2 exception handling.  */
 615 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, RETURN_REGNUM)
 616 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
 617 #define DWARF_FRAME_RETURN_COLUMN  14
 618
 619 /* Describe how we implement __builtin_eh_return.  */
 620 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
 621 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
 622
 623 /* Select a format to encode pointers in exception handling data.  */
 624 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)                          \
 625   (flag_pic                                                                 \
 626     ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
 627    : DW_EH_PE_absptr)
 628
 629 /* Register save slot alignment.  */
 630 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
 631
 632
 633 /* Frame registers.  */
 634
 635 #define STACK_POINTER_REGNUM 15
 636 #define FRAME_POINTER_REGNUM 34
 637 #define HARD_FRAME_POINTER_REGNUM 11
 638 #define ARG_POINTER_REGNUM 32
 639 #define RETURN_ADDRESS_POINTER_REGNUM 35
 640
 641 /* The static chain must be call-clobbered, but not used for
 642    function argument passing.  As register 1 is clobbered by
 643    the trampoline code, we only have one option.  */
 644 #define STATIC_CHAIN_REGNUM 0
 645
 646 /* Number of hardware registers that go into the DWARF-2 unwind info.
 647    To avoid ABI incompatibility, this number must not change even as
 648    'fake' hard registers are added or removed.  */
 649 #define DWARF_FRAME_REGISTERS 34
 650
 651
 652 /* Frame pointer and argument pointer elimination.  */
 653
 654 #define ELIMINABLE_REGS                                         \
 655 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },                \
 656  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },           \
 657  { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },                  \
 658  { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },             \
 659  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM },       \
 660  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },  \
 661  { BASE_REGNUM, BASE_REGNUM }}
 662
 663 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 664   (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
 665
 666
 667 /* Stack arguments.  */
 668
 669 /* We need current_function_outgoing_args to be valid.  */
 670 #define ACCUMULATE_OUTGOING_ARGS 1
 671
 672
 673 /* Register arguments.  */
 674
 675 typedef struct s390_arg_structure
 676 {
 677   int gprs;                     /* gpr so far */
 678   int fprs;                     /* fpr so far */
 679 }
 680 CUMULATIVE_ARGS;
 681
 682 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
 683   ((CUM).gprs=0, (CUM).fprs=0)
 684
 685 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
 686   s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
 687
 688 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)   \
 689   s390_function_arg (&CUM, MODE, TYPE, NAMED)
 690
 691 /* Arguments can be placed in general registers 2 to 6, or in floating
 692    point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64
 693    bit.  */
 694 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
 695   (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19)))
 696
 697
 698 /* Scalar return values.  */
 699
 700 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 701   s390_function_value ((VALTYPE), (FUNC), VOIDmode)
 702
 703 #define LIBCALL_VALUE(MODE) \
 704   s390_function_value (NULL, NULL, (MODE))
 705
 706 /* Only gpr 2 and fpr 0 are ever used as return registers.  */
 707 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
 708
 709
 710 /* Function entry and exit.  */
 711
 712 /* When returning from a function, the stack pointer does not matter.  */
 713 #define EXIT_IGNORE_STACK       1
 714
 715
 716 /* Profiling.  */
 717
 718 #define FUNCTION_PROFILER(FILE, LABELNO)                        \
 719   s390_function_profiler ((FILE), ((LABELNO)))
 720
 721 #define PROFILE_BEFORE_PROLOGUE 1
 722
 723
 724 /* Trampolines for nested functions.  */
 725
 726 #define TRAMPOLINE_SIZE         (TARGET_64BIT ? 32 : 16)
 727 #define TRAMPOLINE_ALIGNMENT    BITS_PER_WORD
 728
 729 /* Addressing modes, and classification of registers for them.  */
 730
 731 /* Recognize any constant value that is a valid address.  */
 732 #define CONSTANT_ADDRESS_P(X) 0
 733
 734 /* Maximum number of registers that can appear in a valid memory address.  */
 735 #define MAX_REGS_PER_ADDRESS 2
 736
 737 /* This definition replaces the formerly used 'm' constraint with a
 738    different constraint letter in order to avoid changing semantics of
 739    the 'm' constraint when accepting new address formats in
 740    TARGET_LEGITIMATE_ADDRESS_P.  The constraint letter defined here
 741    must not be used in insn definitions or inline assemblies.  */
 742 #define TARGET_MEM_CONSTRAINT 'e'
 743
 744 /* Try a machine-dependent way of reloading an illegitimate address
 745    operand.  If we find one, push the reload and jump to WIN.  This
 746    macro is used in only one place: `find_reloads_address' in reload.c.  */
 747 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN)      \
 748 do {                                                                    \
 749   rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE));       \
 750   if (new_rtx)                                                          \
 751     {                                                                   \
 752       (AD) = new_rtx;                                                   \
 753       goto WIN;                                                         \
 754     }                                                                   \
 755 } while (0)
 756
 757 /* Nonzero if the constant value X is a legitimate general operand.
 758    It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
 759 #define LEGITIMATE_CONSTANT_P(X) \
 760      legitimate_constant_p (X)
 761
 762 /* Helper macro for s390.c and s390.md to check for symbolic constants.  */
 763 #define SYMBOLIC_CONST(X)       \
 764 (GET_CODE (X) == SYMBOL_REF                                             \
 765  || GET_CODE (X) == LABEL_REF                                           \
 766  || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
 767
 768 #define TLS_SYMBOLIC_CONST(X)   \
 769 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X))       \
 770  || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
 771
 772
 773 /* Condition codes.  */
 774
 775 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
 776    return the mode to be used for the comparison.  */
 777 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
 778
 779 /* Canonicalize a comparison from one we don't have to one we do have.  */
 780 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
 781   s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
 782
 783 /* Relative costs of operations.  */
 784
 785 /* On s390, copy between fprs and gprs is expensive.  */
 786 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)                        \
 787   ((   (   reg_classes_intersect_p ((CLASS1), GENERAL_REGS)             \
 788         && reg_classes_intersect_p ((CLASS2), FP_REGS))                 \
 789     || (   reg_classes_intersect_p ((CLASS1), FP_REGS)                  \
 790         && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
 791
 792 /* A C expression for the cost of moving data of mode M between a
 793    register and memory.  A value of 2 is the default; this cost is
 794    relative to those in `REGISTER_MOVE_COST'.  */
 795 #define MEMORY_MOVE_COST(M, C, I) 1
 796
 797 /* A C expression for the cost of a branch instruction.  A value of 1
 798    is the default; other values are interpreted relative to that.  */
 799 #define BRANCH_COST(speed_p, predictable_p) 1
 800
 801 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 802 #define SLOW_BYTE_ACCESS 1
 803
 804 /* An integer expression for the size in bits of the largest integer machine
 805    mode that should actually be used.  We allow pairs of registers.  */
 806 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 807
 808 /* The maximum number of bytes that a single instruction can move quickly
 809    between memory and registers or between two memory locations.  */
 810 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
 811 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
 812 #define MAX_MOVE_MAX 16
 813
 814 /* Determine whether to use move_by_pieces or block move insn.  */
 815 #define MOVE_BY_PIECES_P(SIZE, ALIGN)           \
 816   ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
 817     || (TARGET_ZARCH && (SIZE) == 8) )
 818
 819 /* Determine whether to use clear_by_pieces or block clear insn.  */
 820 #define CLEAR_BY_PIECES_P(SIZE, ALIGN)          \
 821   ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
 822     || (TARGET_ZARCH && (SIZE) == 8) )
 823
 824 /* This macro is used to determine whether store_by_pieces should be
 825    called to "memcpy" storage when the source is a constant string.  */
 826 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
 827
 828 /* Likewise to decide whether to "memset" storage with byte values
 829    other than zero.  */
 830 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN)
 831
 832 /* Don't perform CSE on function addresses.  */
 833 #define NO_FUNCTION_CSE
 834
 835 /* This value is used in tree-sra to decide whether it might benefical
 836    to split a struct move into several word-size moves.  For S/390
 837    only small values make sense here since struct moves are relatively
 838    cheap thanks to mvc so the small default value choosen for archs
 839    with memmove patterns should be ok.  But this value is multiplied
 840    in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
 841    here to compensate for that factor since mvc costs exactly the same
 842    on 31 and 64 bit.  */
 843 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4)
 844
 845
 846 /* Sections.  */
 847
 848 /* Output before read-only data.  */
 849 #define TEXT_SECTION_ASM_OP ".text"
 850
 851 /* Output before writable (initialized) data.  */
 852 #define DATA_SECTION_ASM_OP ".data"
 853
 854 /* Output before writable (uninitialized) data.  */
 855 #define BSS_SECTION_ASM_OP ".bss"
 856
 857 /* S/390 constant pool breaks the devices in crtstuff.c to control section
 858    in where code resides.  We have to write it as asm code.  */
 859 #ifndef __s390x__
 860 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
 861     asm (SECTION_OP "\n\
 862         bras\t%r2,1f\n\
 863 0:      .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
 864 1:      l\t%r3,0(%r2)\n\
 865         bas\t%r14,0(%r3,%r2)\n\
 866         .previous");
 867 #endif
 868
 869
 870 /* Position independent code.  */
 871
 872 extern int flag_pic;
 873
 874 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
 875
 876 #define LEGITIMATE_PIC_OPERAND_P(X)  legitimate_pic_operand_p (X)
 877
 878
 879 /* Assembler file format.  */
 880
 881 /* Character to start a comment.  */
 882 #define ASM_COMMENT_START "#"
 883
 884 /* Declare an uninitialized external linkage data object.  */
 885 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
 886   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
 887
 888 /* Globalizing directive for a label.  */
 889 #define GLOBAL_ASM_OP ".globl "
 890
 891 /* Advance the location counter to a multiple of 2**LOG bytes.  */
 892 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
 893   if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
 894
 895 /* Advance the location counter by SIZE bytes.  */
 896 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
 897   fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
 898
 899 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h.  */
 900 #define LOCAL_LABEL_PREFIX "."
 901
 902 /* How to refer to registers in assembler output.  This sequence is
 903    indexed by compiler's hard-register-number (see above).  */
 904 #define REGISTER_NAMES                                                  \
 905 { "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",        \
 906   "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",       \
 907   "%f0",  "%f2",  "%f4",  "%f6",  "%f1",  "%f3",  "%f5",  "%f7",        \
 908   "%f8",  "%f10", "%f12", "%f14", "%f9",  "%f11", "%f13", "%f15",       \
 909   "%ap",  "%cc",  "%fp",  "%rp",  "%a0",  "%a1"                         \
 910 }
 911
 912 /* Print operand X (an rtx) in assembler syntax to file FILE.  */
 913 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
 914 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
 915
 916 /* Output machine-dependent UNSPECs in address constants.  */
 917 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL)          \
 918 do {                                                    \
 919   if (!s390_output_addr_const_extra (FILE, (X)))        \
 920     goto FAIL;                                          \
 921 } while (0);
 922
 923 /* Output an element of a case-vector that is absolute.  */
 924 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)                            \
 925 do {                                                                    \
 926   char buf[32];                                                         \
 927   fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
 928   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
 929   assemble_name ((FILE), buf);                                          \
 930   fputc ('\n', (FILE));                                                 \
 931 } while (0)
 932
 933 /* Output an element of a case-vector that is relative.  */
 934 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)                \
 935 do {                                                                    \
 936   char buf[32];                                                         \
 937   fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
 938   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
 939   assemble_name ((FILE), buf);                                          \
 940   fputc ('-', (FILE));                                                  \
 941   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL));                        \
 942   assemble_name ((FILE), buf);                                          \
 943   fputc ('\n', (FILE));                                                 \
 944 } while (0)
 945
 946
 947 /* Miscellaneous parameters.  */
 948
 949 /* Specify the machine mode that this machine uses for the index in the
 950    tablejump instruction.  */
 951 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
 952
 953 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
 954    is done just by pretending it is already truncated.  */
 955 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
 956
 957 /* Specify the machine mode that pointers have.
 958    After generation of rtl, the compiler makes no further distinction
 959    between pointers and any other objects of this machine mode.  */
 960 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
 961
 962 /* This is -1 for "pointer mode" extend.  See ptr_extend in s390.md.  */
 963 #define POINTERS_EXTEND_UNSIGNED -1
 964
 965 /* A function address in a call instruction is a byte address (for
 966    indexing purposes) so give the MEM rtx a byte's mode.  */
 967 #define FUNCTION_MODE QImode
 968
 969 /* Specify the value which is used when clz operand is zero.  */
 970 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
 971
 972 /* Machine-specific symbol_ref flags.  */
 973 #define SYMBOL_FLAG_ALIGN1                (SYMBOL_FLAG_MACH_DEP << 0)
 974 #define SYMBOL_REF_ALIGN1_P(X)          \
 975   ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1))
 976 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1)
 977 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \
 978   ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED))
 979
 980 /* Check whether integer displacement is in range.  */
 981 #define DISP_IN_RANGE(d) \
 982   (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
 983                            : ((d) >= 0 && (d) <= 4095))
 984
 985 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c.  */
 986 #define READ_CAN_USE_WRITE_PREFETCH 1
 987 #endif