1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 Free Software
5 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
7 ; This file is part of GCC.
9 ; GCC is free software; you can redistribute it and/or modify it under
10 ; the terms of the GNU General Public License as published by the Free
11 ; Software Foundation; either version 3, or (at your option) any later
14 ; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ; License for more details.
19 ; You should have received a copy of the GNU General Public License
20 ; along with GCC; see the file COPYING3. If not see
21 ; <http://www.gnu.org/licenses/>.
24 Target Report RejectNegative Mask(POWER)
25 Use POWER instruction set
28 Target Report RejectNegative
29 Do not use POWER instruction set
32 Target Report Mask(POWER2)
33 Use POWER2 instruction set
36 Target Report RejectNegative Mask(POWERPC)
37 Use PowerPC instruction set
40 Target Report RejectNegative
41 Do not use PowerPC instruction set
44 Target Report Mask(POWERPC64)
45 Use PowerPC-64 instruction set
48 Target Report Mask(PPC_GPOPT)
49 Use PowerPC General Purpose group optional instructions
52 Target Report Mask(PPC_GFXOPT)
53 Use PowerPC Graphics group optional instructions
56 Target Report Mask(MFCRF)
57 Use PowerPC V2.01 single field mfcr instruction
60 Target Report Mask(POPCNTB)
61 Use PowerPC V2.02 popcntb instruction
64 Target Report Mask(FPRND)
65 Use PowerPC V2.02 floating point rounding instructions
68 Target Report Mask(CMPB)
69 Use PowerPC V2.05 compare bytes instruction
72 Target Report Mask(MFPGPR)
73 Use extended PowerPC V2.05 move floating point to/from GPR instructions
76 Target Report Mask(ALTIVEC)
77 Use AltiVec instructions
80 Target Report Mask(DFP)
81 Use decimal floating point instructions
84 Target Report Mask(MULHW)
85 Use 4xx half-word multiply instructions
88 Target Report Mask(DLMZB)
89 Use 4xx string-search dlmzb instruction
92 Target Report Mask(MULTIPLE)
93 Generate load/store multiple instructions
96 Target Report Mask(STRING)
97 Generate string instructions for block moves
100 Target Report RejectNegative Mask(NEW_MNEMONICS)
101 Use new mnemonics for PowerPC architecture
104 Target Report RejectNegative InverseMask(NEW_MNEMONICS)
105 Use old mnemonics for PowerPC architecture
108 Target Report RejectNegative Mask(SOFT_FLOAT)
109 Do not use hardware floating point
112 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
113 Use hardware floating point
116 Target Report Mask(POPCNTD)
117 Use PowerPC V2.06 popcntd instruction
120 Target Report Var(TARGET_FRIZ) Init(-1)
121 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions
124 Target RejectNegative Joined Var(rs6000_veclibabi_name)
125 Vector library ABI to use
128 Target Report Mask(VSX)
129 Use vector/scalar (VSX) instructions
132 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
133 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
136 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
137 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
140 Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
141 ; If -mvsx, set alignment to 128 bits instead of 32/64
144 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
145 ; Allow/disallow the movmisalign in DF/DI vectors
148 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
149 ; Allow/disallow permutation of DF/DI vectors
152 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
153 ; Explicitly set/unset whether rs6000_sched_groups is set
156 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
157 ; Explicitly set/unset whether rs6000_always_hint is set
159 malign-branch-targets
160 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
161 ; Explicitly set/unset whether rs6000_align_branch_targets is set
164 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
165 ; Explicitly control whether we vectorize the builtins or not.
168 Target Report RejectNegative Mask(NO_UPDATE)
169 Do not generate load/store with update instructions
172 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
173 Generate load/store with update instructions
175 mavoid-indexed-addresses
176 Target Report Var(TARGET_AVOID_XFORM) Init(-1)
177 Avoid generation of indexed load/store instructions when possible
180 Target Report Var(TARGET_FUSED_MADD) Init(1)
181 Generate fused multiply/add instructions
184 Target Report Var(tls_markers) Init(1)
185 Mark __tls_get_addr calls with argument info
188 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1)
191 Target Report Var(TARGET_SCHED_PROLOG) VarExists
192 Schedule the start and end of the procedure
195 Target Report RejectNegative Var(aix_struct_return)
196 Return all structures in memory (AIX default)
199 Target Report RejectNegative Var(aix_struct_return,0) VarExists
200 Return small structures in registers (SVR4 default)
203 Target Report Var(TARGET_XL_COMPAT)
204 Conform more closely to IBM XLC semantics
208 Generate software reciprocal divide and square root for better throughput.
211 Target Report RejectNegative Joined
212 Generate software reciprocal divide and square root for better throughput.
215 Target Report Mask(RECIP_PRECISION)
216 Assume that the reciprocal estimate instructions provide more accuracy.
219 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC)
220 Do not place floating point constants in TOC
223 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0)
224 Place floating point constants in TOC
227 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC)
228 Do not place symbol+offset constants in TOC
231 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists
232 Place symbol+offset constants in TOC
234 ; Output only one TOC entry per module. Normally linking fails if
235 ; there are more than 16K unique variables/constants in an executable. With
236 ; this option, linking fails only if there are more than 16K modules, or
237 ; if there are more than 16K unique variables/constant in a single module.
239 ; This is at the cost of having 2 extra loads and one extra store per
240 ; function, and one less allocable register.
242 Target Report Mask(MINIMAL_TOC)
243 Use only one TOC entry per procedure
247 Put everything in the regular TOC
250 Target Report Var(TARGET_ALTIVEC_VRSAVE)
251 Generate VRSAVE instructions when generating AltiVec code
254 Target RejectNegative Joined
255 -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
257 mblock-move-inline-limit=
258 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger
259 Specify how many bytes should be moved inline before calling out to memcpy/memmove
262 Target Report Mask(ISEL)
263 Generate isel instructions
266 Target RejectNegative Joined
267 -misel=yes/no Deprecated option. Use -misel/-mno-isel instead
271 Generate SPE SIMD instructions on E500
274 Target Var(rs6000_paired_float)
275 Generate PPC750CL paired-single instructions
278 Target RejectNegative Joined
279 -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead
282 Target RejectNegative Joined
283 -mdebug= Enable debug output
286 Target RejectNegative Joined
287 -mabi= Specify ABI to use
290 Target RejectNegative Joined
291 -mcpu= Use features of and schedule code for given CPU
294 Target RejectNegative Joined
295 -mtune= Schedule code for given CPU
298 Target RejectNegative Joined
299 -mtraceback= Select full, part, or no traceback table
302 Target Report Var(rs6000_default_long_calls)
303 Avoid all range limits on call instructions
306 Target Report Var(rs6000_gen_cell_microcode) Init(-1)
307 Generate Cell microcode
310 Target Var(rs6000_warn_cell_microcode) Init(0) Warning
311 Warn when a Cell microcoded instruction is emitted
314 Target Var(rs6000_warn_altivec_long) Init(1)
315 Warn about deprecated 'vector long ...' AltiVec type usage
318 Target RejectNegative Joined
319 -mfloat-gprs= Select GPR floating point method
322 Target RejectNegative Joined UInteger
323 -mlong-double-<n> Specify size of long double (64 or 128 bits)
326 Target RejectNegative Joined
327 Determine which dependences between insns are considered costly
330 Target RejectNegative Joined
331 Specify which post scheduling nop insertion scheme to apply
334 Target RejectNegative Joined
335 Specify alignment of structure fields default/natural
337 mprioritize-restricted-insns=
338 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority)
339 Specify scheduling priority for dispatch slot restricted insns
342 Target RejectNegative Var(rs6000_single_float)
343 Single-precision floating point unit
346 Target RejectNegative Var(rs6000_double_float)
347 Double-precision floating point unit
350 Target RejectNegative Var(rs6000_simple_fpu)
351 Floating point unit does not support divide & sqrt
354 Target RejectNegative Joined
355 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
358 Target Var(rs6000_xilinx_fpu)