gcc/config/picochip/picochip.h

   1 /* Definitions of target machine for GNU compiler for picoChip
   2    Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
   3
   4    Contributed by picoChip Designs Ltd. (http://www.picochip.com)
   5    Maintained by Daniel Towner (daniel.towner@picochip.com) and
   6    Hariharan Sandanagobalane (hariharan@picochip.com).
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 3, or (at your option)
  13 any later version.
  14
  15 GCC is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not, see
  22 <http://www.gnu.org/licenses/>. */
  23
  24 /* Which type of DFA scheduling to use - schedule for speed (VLIW), or
  25    schedule for space.  When scheduling for space, attempt to schedule
  26    into stall cycles, but don't pack instructions. */
  27
  28 enum picochip_dfa_type
  29 {
  30   DFA_TYPE_NONE,
  31   DFA_TYPE_SPACE,
  32   DFA_TYPE_SPEED
  33 };
  34
  35 extern enum picochip_dfa_type picochip_schedule_type;
  36
  37 /* Controlling the Compilation Driver */
  38
  39 /* Pass through the save-temps command option. */
  40 #define LINK_SPEC " %{save-temps:--save-temps}"
  41
  42 /* This is an embedded processor, and only supports a cut-down version of
  43  * the standard C library. */
  44 #define LIB_SPEC "-lpicoC"
  45
  46 /* The start file is automatically provided by the linker. */
  47 #define STARTFILE_SPEC ""
  48 \f
  49 /* Run-time Target Specification  */
  50
  51 /* Define some additional pre-processor macros. */
  52 #define TARGET_CPU_CPP_BUILTINS()                       \
  53   do                                                    \
  54     {                                                   \
  55       builtin_define ("NO_TRAMPOLINES");                \
  56       builtin_define ("PICOCHIP");                      \
  57       builtin_define ("__PICOCHIP__");                      \
  58     }                                                   \
  59   while (0)
  60
  61 /* Translate requests for particular AEs into their respective ISA
  62    options. Note that byte access is enabled by default. */
  63 #define TARGET_OPTION_TRANSLATE_TABLE                         \
  64   { "-mae=ANY",   "-mmul-type=none -mno-byte-access" },       \
  65   { "-mae=ANY2",  "-mmul-type=none -mno-byte-access" },       \
  66   { "-mae=ANY3",  "-mmul-type=none" },                        \
  67   { "-mae=STAN",  "-mmul-type=none -mno-byte-access" },       \
  68   { "-mae=STAN2", "-mmul-type=mac -mno-byte-access" },        \
  69   { "-mae=STAN3", "-mmul-type=mac " },                        \
  70   { "-mae=MAC",   "-mmul-type=mac -mno-byte-access" },        \
  71   { "-mae=MUL",   "-mmul-type=mul" },                         \
  72   { "-mae=MEM",   "-mmul-type=mul" },                         \
  73   { "-mae=MEM2",  "-mmul-type=mul" },                         \
  74   { "-mae=CTRL",  "-mmul-type=mul" },                         \
  75   { "-mae=CTRL2", "-mmul-type=mul" }
  76
  77 /* Specify the default options, so that the multilib build doesn't
  78    need to provide special cases for the defaults. */
  79 #define MULTILIB_DEFAULTS \
  80   { "mmul-type=mul", "mbyte-access"}
  81
  82 #define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
  83 #define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
  84 #define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
  85 #define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
  86
  87 #define CAN_DEBUG_WITHOUT_FP 1
  88
  89 #define TARGET_VERSION fprintf(stderr, "(picoChip)");
  90 \f
  91 /* Storage Layout */
  92
  93 /* picoChip processors are 16-bit machines, little endian. */
  94
  95 #define BITS_BIG_ENDIAN 0
  96 #define BYTES_BIG_ENDIAN 0
  97 #define WORDS_BIG_ENDIAN 0
  98
  99 #define BITS_PER_UNIT 8
 100
 101 #define BITS_PER_WORD 16
 102 #define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
 103
 104 #define POINTER_SIZE BITS_PER_WORD
 105
 106 /* Promote those modes that are smaller than an int, to int mode.  */
 107 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
 108   ((GET_MODE_CLASS (MODE) == MODE_INT                   \
 109       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)         \
 110       ? (MODE) = HImode : 0)
 111
 112 /* All parameters are at least this aligned.  Parameters are passed
 113    one-per-register. */
 114 #define PARM_BOUNDARY BITS_PER_WORD
 115
 116 /* The main stack pointer is guaranteed to be aligned to the most
 117    strict data alignment. */
 118 #define STACK_BOUNDARY 32
 119
 120 /* Function entry point is byte aligned. */
 121 #define FUNCTION_BOUNDARY 8
 122
 123 /* This is the biggest alignment that can be allowed on this machine.
 124    Since the STANs have only 256 byte memory, it doesnt make sense
 125    to have alignments greater than 32 bytes. Hence the value */
 126 #define MAX_OFILE_ALIGNMENT 32*8
 127
 128 /* The strictest data object alignment, which repesents a register pair. */
 129 #define BIGGEST_ALIGNMENT 32
 130
 131 /* The hardware doesn't allow unaligned memory access.  */
 132 #define STRICT_ALIGNMENT 1
 133
 134 /* We want the 'unix' style bitfield packing algorithm.  */
 135 #define PCC_BITFIELD_TYPE_MATTERS 1
 136
 137 /* Support up to 64-bit integers. */
 138 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
 139
 140 /* We don't support floating point, but give it a sensible definition. */
 141 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 142 \f
 143 /* Layout of Source Language Data Types.  */
 144
 145 #define INT_TYPE_SIZE BITS_PER_WORD
 146
 147 /* The normal sizes for C scalar data. */
 148 #define CHAR_TYPE_SIZE 8
 149 #define SHORT_TYPE_SIZE 16
 150 #define LONG_TYPE_SIZE 32
 151 #define LONG_LONG_TYPE_SIZE 64
 152
 153 /* We don't support the following data types, but still give them
 154    sensible values.  */
 155 #define FLOAT_TYPE_SIZE 32
 156 #define DOUBLE_TYPE_SIZE 32
 157 #define LONG_DOUBLE_TYPE_SIZE 32
 158
 159 /* Plain `char' is a signed type, since the hardware sign-extends
 160    bytes when loading them from memory into a register. */
 161 #define DEFAULT_SIGNED_CHAR 1
 162
 163 /* Note that the names of the types used in the following macros must
 164    be precisely the same as those defined internally in gcc.  For
 165    example, `unsigned short' wouldn't work as a type string, since gcc
 166    doesn't define any type with this exact string.  The correct string
 167    to use is `short unsigned int'. */
 168
 169 #define SIZE_TYPE "unsigned int"
 170
 171 #define PTRDIFF_TYPE "int"
 172
 173 #define WCHAR_TYPE "short unsigned int"
 174 #define WCHAR_TYPE_SIZE 16
 175
 176 #define WINT_TYPE "unsigned int"
 177 \f
 178 /* Register Usage  */
 179
 180 /* Picochip has 16 16-bit registers, a condition code register and an
 181    (inaccessible) instruction pointer.  One of these registers (r15) is
 182    special, and is either used to load a constant anywhere a register
 183    can normally be used, or is used to specify a dummy destination
 184    (e.g., when setting condition flags).  We also define some pseudo
 185    registers to represent condition codes, the frame pointer and the
 186    argument pointer.  The latter two are eliminated wherever possible.
 187
 188    Pairs of general registers may be combined to form 32-bit registers.
 189
 190    The picoChip registers are as follows:
 191
 192    0..1 - function return value
 193    0..5 - first 6 function parameters
 194    6..11 - General purpose
 195    12 - link register
 196    13 - stack pointer
 197    14 - specialized pointer
 198    15 - long constant or /dev/null
 199    (16) acc0
 200    (17) pseudo condition code
 201    (18) pseudo frame pointer
 202    (19) pseudo arg pointer
 203
 204    Registers 0..6, 12, 13, 14, 15 are caller save
 205    Registers 0..12, 14 are available to the register allocator.
 206
 207    In addition, the DSP variant of the ISA allows extra accumulator
 208    registers to be accessed.  These are special purpose registers,
 209    which are not currently used by the compiler.
 210
 211   */
 212
 213 /* Basic Characteristics of Registers  */
 214
 215 /* We have 16 hard registers plus 3 pseudo hard registers and an accumulator.  */
 216 #define FIRST_PSEUDO_REGISTER 20
 217
 218 /* The first non-hard register.  Only used internally by the picoChip port. */
 219 #define FIRST_NONHARD_REGISTER 18
 220
 221 /* Cannot use SP, CST, CC, FP, AP */
 222 #define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
 223
 224 /* Those that are clobbered by a function call (includes pseudo-regs) */
 225 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
 226 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
 227
 228 /* Define the number of the picoChip link and condition psuedo registers. */
 229 #define LINK_REGNUM 12
 230 #define CC_REGNUM 17
 231 #define ACC_REGNUM 16
 232
 233 /* Order of Allocation of Registers  */
 234
 235 /* The registers are allocated starting with the caller-clobbered
 236    registers, in reverse order.  The registers are then listed in an
 237    order which means that they are efficiently saved in pairs (i.e.,
 238    one 32-bit store can be used instead of two 16-bit stores to save
 239    the registers into the stack). The exception to this is the use of
 240    r14 (AP) register, which also appears early on.  This is because the
 241    AP register can be used to encode memory operations more
 242    efficiently than other registers.  Some code can be made more
 243    compact as a result. */
 244    /* My current feeling is that r14 should go to the end and maybe even r12.
 245    It seems like the overhead of store/load that will occur since we cant
 246    pair anything up with r14 will be higher than the advantage of smaller
 247    encoding.
 248    Also r12 is put towards the end for leaf functions. Since leaf functions
 249    do not have any calls, the prologue/epilogue for them wouldnt save up/
 250    restore its value. So, it doesnt make sense for us to use it in the middle,
 251    if we can avoid it. */
 252 #define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
 253 #define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
 254
 255 /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
 256    It would be desirable to change it for leaf functions so we can put
 257    r12 at the end of this list.*/
 258 #define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc ()
 259
 260 /* How Values Fit in Registers  */
 261
 262 /* Number of consecutive hard regs needed starting at reg REGNO
 263    to hold something of mode MODE.  */
 264 #define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
 265
 266 /* Is it ok to place MODE in REGNO?  Require that the register number
 267    be aligned. */
 268 #define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
 269
 270 #define MODES_TIEABLE_P(MODE1,MODE2) 1
 271
 272 /* Don't copy the cc register ('cos you can't put it back).  */
 273 #define AVOID_CCMODE_COPIES 1
 274 \f
 275 /* Register Classes */
 276
 277 enum reg_class
 278 {
 279   NO_REGS,                      /* no registers in set */
 280   FRAME_REGS,                   /* registers with a long offset  */
 281   PTR_REGS,                     /* registers without an offset  */
 282   CONST_REGS,                   /* registers for long constants  */
 283   NULL_REGS,                    /* registers which ignore writes  */
 284   CC_REGS,                      /* condition code registers  */
 285   ACC_REGS,                     /* Accumulator registers  */
 286   TWIN_REGS,                    /* registers which can be paired */
 287   GR_REGS,                      /* general purpose registers */
 288   ALL_REGS,                     /* all registers */
 289   LIM_REG_CLASSES,              /* max value + 1 */
 290
 291   /* Some aliases  */
 292   GENERAL_REGS = GR_REGS
 293 };
 294
 295 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 296
 297 /* The following macro defines cover classes for Integrated Register
 298    Allocator.  Cover classes is a set of non-intersected register
 299    classes covering all hard registers used for register allocation
 300    purpose.  Any move between two registers of a cover class should be
 301    cheaper than load or store of the registers.  The macro value is
 302    array of register classes with LIM_REG_CLASSES used as the end
 303    marker.  */
 304
 305 #define IRA_COVER_CLASSES                                               \
 306 {                                                                       \
 307   GR_REGS, LIM_REG_CLASSES                                              \
 308 }
 309
 310
 311 /* The names of the register classes  */
 312 #define REG_CLASS_NAMES                                                 \
 313 {                                                                       \
 314   "NO_REGS",                                                            \
 315   "FRAME_REGS",                                                         \
 316   "PTR_REGS",                                                           \
 317   "CONST_REGS",                                                         \
 318   "NULL_REGS",                                                          \
 319   "CC_REGS",                                                            \
 320   "ACC_REGS",                                                           \
 321   "TWIN_REGS",                                                          \
 322   "GR_REGS",                                                            \
 323   "ALL_REGS"                                                            \
 324 }
 325
 326 /* Each reg class is an array of 32-bit integers.  Each array must be
 327    long enough to store one bit for every pseudo register. Thus in the
 328    following code, each array only stores one 32-bit value. */
 329 #define REG_CLASS_CONTENTS                                              \
 330 {                                                                       \
 331   {0x00000000}, /* no registers */                                      \
 332   {0x00002000}, /* frame */                                             \
 333   {0x00004000}, /* pointer  */                                          \
 334   {0x00008000}, /* const */                                             \
 335   {0x00008000}, /* null  */                                             \
 336   {0x00020000}, /* cc */                                                \
 337   {0x00010000}, /* acc0 */                                              \
 338   {0x00000FFF}, /* twin */                                              \
 339   {0x000CFFFF}, /* general registers - includes pseudo-arg */           \
 340   {0x000FFFFF}  /* all registers - includes pseudo-arg */               \
 341 }
 342
 343 /* The earliest register class containing the given register.  */
 344 extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
 345 #define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
 346
 347 /* Any register can be a base pointer.  */
 348 #define BASE_REG_CLASS GR_REGS
 349
 350 /* Any register can be an index.  */
 351 #define INDEX_REG_CLASS GR_REGS
 352
 353 #define REGNO_OK_FOR_BASE_P(REGNO)                                      \
 354   (REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
 355
 356 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 357
 358 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
 359
 360 #define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
 361
 362 \f
 363 /* Stack Layout and Calling Conventions  */
 364
 365 #define STACK_GROWS_DOWNWARD 1
 366
 367 /* The frame pointer points to the outgoing argument area, so the
 368    locals are above that.  */
 369 #define STARTING_FRAME_OFFSET 0
 370
 371 #define FIRST_PARM_OFFSET(FNDECL) 0
 372
 373 /* Specify where the return address lives before entry to the
 374    prologue.  This is required to enable DWARF debug information to be
 375    generated. */
 376 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, LINK_REGNUM)
 377
 378 #define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
 379
 380 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
 381
 382 /* Registers that Address the Stack Frame  */
 383
 384 #define STACK_POINTER_REGNUM 13
 385 #define FRAME_POINTER_REGNUM 18
 386 #define ARG_POINTER_REGNUM   19
 387
 388 /* Eliminating Frame Pointer and Arg Pointer.  The frame and argument
 389    pointers are eliminated wherever possible, by replacing them with
 390    offsets from the stack pointer. */
 391
 392 #define ELIMINABLE_REGS                                                 \
 393   {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},                          \
 394    {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
 395
 396 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
 397   OFFSET = initial_elimination_offset(FROM, TO);
 398
 399 #define ACCUMULATE_OUTGOING_ARGS 1
 400
 401 #define PUSH_ARGS 0
 402
 403 /* Passing Arguments in Registers  */
 404
 405 /* Store the offset of the next argument. */
 406 #define CUMULATIVE_ARGS unsigned
 407
 408 /* Decide how function arguments are handled. */
 409 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
 410   picochip_function_arg (CUM, MODE, TYPE, NAMED)
 411
 412 /* Incoming arguments are always the same as normal arguments, except
 413    for a function which uses variadic arguments, in which case all
 414    arguments are effectively passed on the stack. */
 415 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
 416   picochip_incoming_function_arg(CUM, MODE, TYPE, NAMED)
 417
 418 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
 419   ((CUM) = 0)
 420
 421 #define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \
 422   (CUM) = picochip_arg_advance (CUM, MODE, TYPE, NAMED)
 423
 424 /* Originally this used TYPE_ALIGN to determine the
 425    alignment.  Unfortunately, this fails in some cases, because the
 426    type is unknown (e.g., libcall's). Instead, use GET_MODE_ALIGNMENT
 427    since the mode is always present. */
 428 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
 429   picochip_get_function_arg_boundary(MODE)
 430
 431 /* The first 6 registers can hold parameters.  */
 432 #define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
 433
 434 /* How Scalar Function Values are Returned
 435    Do we need this?? */
 436 #define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
 437
 438 #define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
 439
 440 /* Results are in register zero.  If an SImode register is returned,
 441    reg0 will suffice to mean R[0:1]. */
 442 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
 443
 444 /* Don't automatically pass struct's in memory - use the
 445  * RETURN_IN_MEMORY macro to determine when structs are returned in
 446  * memory, and when in registers. */
 447 #define DEFAULT_PCC_STRUCT_RETURN 0
 448
 449 /* Function Entry and Exit  */
 450
 451 /* The epilogue doesn't clobber anything.  */
 452 #define EPILOGUE_USES(REGNO) 0
 453
 454 /* Generating Code for Profiling.  No profiling implemented  */
 455
 456 #define FUNCTION_PROFILER(FILE,LABELNO)
 457 \f
 458 /* Trampolines for Nested Functions  */
 459
 460 /* No trampolines.  */
 461 #define TRAMPOLINE_SIZE 0
 462 \f
 463 /* Addressing Modes  */
 464
 465 #define MAX_REGS_PER_ADDRESS 1
 466
 467 /* Legitimize reload address tries machine dependent means of
 468    reloading addresses.  There seems to be a strange error in gcc,
 469    which necessitates this macro.  Consider:
 470
 471      set (reg A) (symbol_ref)
 472      set (reg B) (plus (reg A) (const_int))
 473
 474    A symbol_ref is a valid constant, so the symbol_ref is propagated
 475    into the second instruction to generate the instruction:
 476
 477      set (reg B) (plus (symbol_ref) (const_int))
 478
 479    This is an invalid address, and find_reloads_address correctly
 480    determines this.  However, that function doesn't generate a valid
 481    replacement for the now invalid address, and the invalid address is
 482    output into the assembly language.  To fix the problem without
 483    changing gcc itself, the following macro tests when such an invalid
 484    address has been computed, and wraps it up inside a constant rtx.  A
 485    constant rtx can be correctly reloaded by the function, and hence
 486    correct code is generated. */
 487
 488 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)          \
 489 do {                                                                         \
 490   if (picochip_legitimize_reload_address(&X,MODE,OPNUM,TYPE,IND_LEVELS))     \
 491     goto WIN;                                                                \
 492   } while(0);                                                                \
 493
 494 /* Nonzero if the constant rtx X is a legitimate general operand.  X
 495    satisfies CONSTANT_P.  */
 496
 497 #define LEGITIMATE_CONSTANT_P(X) 1
 498
 499 \f
 500 /* Condition Code Status  */
 501
 502 #define CC_STATUS_MDEP unsigned
 503 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
 504 \f
 505 /* Describing Relative Costs of Operations  */
 506
 507 /* Bytes are no faster than words.  */
 508 #define SLOW_BYTE_ACCESS 1
 509
 510 /* The assembler is often able to optimise function call branches, so
 511    don't try to CSE them in the compiler. This was the thinking before.
 512    But now, we realise that the benefits from CSE would mostly outweigh
 513    the disadvantages. */
 514 #define NO_FUNCTION_CSE
 515
 516 \f
 517 /* Dividing the Output into Sections  */
 518
 519 #define TEXT_SECTION_ASM_OP ".section .text\n"
 520 #define DATA_SECTION_ASM_OP ".section .data\n"
 521 #define BSS_SECTION_ASM_OP ".section .bss\n"
 522 /* picoChip is Harvard (separate data/instruction memories), so
 523    read-only data must go into the data section. */
 524 #define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
 525 \f
 526 /* Defining the Output Assembler Language  */
 527
 528 /* The Overall Framework of an Assembler File  */
 529
 530 #define ASM_FILE_COMMENT "// "
 531
 532 #define ASM_APP_ON "// High-level ASM start\n"
 533 #define ASM_APP_OFF "// High-level ASM end\n"
 534
 535 #define ASM_OUTPUT_IDENT(STREAM,STRING) fprintf(STREAM, ".ident %s\n", STRING)
 536
 537 /* Output of Data  */
 538
 539 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
 540
 541 /* Output of Uninitialized Variables  */
 542 #define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
 543   picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
 544
 545 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
 546   picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
 547
 548 /* Output and Generation of Labels  */
 549
 550 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
 551   do { picochip_output_label(STREAM, NAME); } while (0);
 552
 553 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 554   { picochip_output_labelref(STREAM, NAME); }
 555
 556 /* Format must match that of picochip_output_label. */
 557 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
 558  picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
 559
 560 #define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
 561
 562 /* Store in OUTPUT a string (made with alloca) containing an
 563    assembler-name for a local static variable named NAME.  LABELNO is
 564    an integer which is different for each call.  The assembler can't
 565    use periods to generate the name, so we use a ___ separator
 566    instead. */
 567
 568 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  \
 569 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15),    \
 570   sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
 571
 572 /* Macros Controlling Initialization Routines  */
 573
 574 /* By defining this, the main function won't try to call `__main'. */
 575 #define HAS_INIT_SECTION
 576
 577 /* Output of Assembler Instructions  */
 578
 579 #define REGISTER_NAMES                                                  \
 580 {"R0",  "R1",  "R2",  "R3",                                             \
 581  "R4",  "R5",  "R6",  "R7",                                             \
 582  "R8",  "R9",  "R10", "R11",                                            \
 583  "R12", "FP", "R14", "R15",                                             \
 584  "acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
 585
 586 #define ADDITIONAL_REGISTER_NAMES                                       \
 587 {                                                                       \
 588   { "R0",        0},                                                    \
 589   { "R1",        1},                                                    \
 590   { "R2",        2},                                                    \
 591   { "R3",        3},                                                    \
 592   { "R4",        4},                                                    \
 593   { "R5",        5},                                                    \
 594   { "R6",        6},                                                    \
 595   { "R7",        7},                                                    \
 596   { "R8",        8},                                                    \
 597   { "R9",        9},                                                    \
 598   { "R10",      10},                                                    \
 599   { "R11",      11},                                                    \
 600   { "R12",      12},                                                    \
 601   { "FP",       13},                                                    \
 602   { "R14",      14},                                                    \
 603   { "R15",      15},                                                    \
 604   { "acc0",     16},                                                    \
 605   { "sp",       12}, /* ABI stack pointer */                            \
 606   { "ln",       13}, /* arch link register */                           \
 607   { "ptr",      14}, /* arch constant pointer */                        \
 608   { "rc",       15}, /* arch constant register */                       \
 609   { "rz",       15}, /* arch zero */                                    \
 610 }
 611
 612 /* Final prescan insn is called just before an instruction is
 613    output.  In our case, we use this to detect the VLIW slot to which
 614    the instruction has been assigned, preparatory to generating the
 615    VLIW output in ASM_OUTPUT_OPCODE. */
 616 #define FINAL_PRESCAN_INSN(insn, operand, nop) \
 617   picochip_final_prescan_insn (insn, operand,nop)
 618
 619 #define ASM_OUTPUT_OPCODE(FILE,PTR) \
 620   { PTR = picochip_asm_output_opcode(FILE, PTR); }
 621
 622 #define PRINT_OPERAND(STREAM,X,CODE) \
 623   picochip_print_operand(STREAM, X, CODE)
 624
 625 #define PRINT_OPERAND_PUNCT_VALID_P(code) \
 626   (((code) == '|') || ((code) == '#') || ((code) == '>'))
 627
 628 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
 629   picochip_print_operand_address(STREAM,X)
 630
 631 /* Output of Dispatch Tables  */
 632
 633 /* Initialise a data memory location to an absolute code label.  Used
 634    for building switch statement jump tables.  Note - the format of the
 635    label must match that of the function picochip_output_label. */
 636 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 637   fprintf (stream, ".initWord _L%d\n", value);
 638
 639 /* Assembler Commands for Alignment  */
 640
 641 #define ASM_OUTPUT_SKIP(STREAM,BYTES) \
 642   fprintf(STREAM, ".skip %u\n", BYTES);
 643 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 644   fprintf(STREAM, ".align %u\n", 1 << POWER);
 645
 646 /* The elaborator doesn't output zero bytes in the text section. */
 647 #define ASM_NO_SKIP_IN_TEXT 1
 648 \f
 649 /* Controlling Debugging Information Format  */
 650
 651 /* Macros Affecting All Debugging Formats  */
 652
 653 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
 654
 655 #define DWARF2_DEBUGGING_INFO
 656 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 657 #define DWARF2_FRAME_INFO 1
 658
 659 /* Generate .file/.loc directives, so that the assembler generates the
 660    line table. */
 661 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 662 \f
 663 /* Miscellaneous Parameters  */
 664
 665 #define CASE_VECTOR_MODE HImode
 666 #define WORD_REGISTER_OPERATIONS
 667 #define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
 668 #define MOVE_MAX 4
 669 #define SHIFT_COUNT_TRUNCATED 1
 670 #define Pmode HImode
 671 #define FUNCTION_MODE QImode
 672 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
 673
 674 #define ASM_LONG ":TODO:.word\t"
 675
 676 /* Define builtins for selected special-purpose instructions. */
 677 enum picochip_builtins
 678 {
 679   PICOCHIP_BUILTIN_SBC,
 680   PICOCHIP_BUILTIN_PUT,
 681   PICOCHIP_BUILTIN_GET,
 682   PICOCHIP_BUILTIN_TESTPORT,
 683   PICOCHIP_BUILTIN_COPYSW,
 684   PICOCHIP_BUILTIN_ADDS,
 685   PICOCHIP_BUILTIN_SUBS,
 686   PICOCHIP_BUILTIN_BREV,
 687   PICOCHIP_BUILTIN_BYTESWAP,
 688   PICOCHIP_BUILTIN_GET_ARRAY,
 689   PICOCHIP_BUILTIN_PUT_ARRAY,
 690   PICOCHIP_BUILTIN_TESTPORT_ARRAY,
 691   PICOCHIP_BUILTIN_ASRI,
 692   PICOCHIP_BUILTIN_HALT
 693 };
 694
 695 #define NO_DOLLAR_IN_LABEL 1
 696 #define NO_DOT_IN_LABEL 1
 697
 698 /* The assembler does support LEB128, despite the auto-configure test
 699    not detecting this. */
 700 #define HAVE_AS_LEB128 1
 701
 702 /* The End */