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Merge from mainline (163495:164578).
[official-gcc/graphite-test-results.git] / gcc / config / mn10300 / mn10300.c
blobfe03742e7e417fc0b79348ccd1fcf2f96944e3fe
1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "output.h"
33 #include "insn-attr.h"
34 #include "flags.h"
35 #include "recog.h"
36 #include "reload.h"
37 #include "expr.h"
38 #include "optabs.h"
39 #include "function.h"
40 #include "obstack.h"
41 #include "diagnostic-core.h"
42 #include "toplev.h"
43 #include "tm_p.h"
44 #include "target.h"
45 #include "target-def.h"
46
47 /* This is used by GOTaddr2picreg to uniquely identify
48 UNSPEC_INT_LABELs. */
49 int mn10300_unspec_int_label_counter;
50
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label;
56
57 /* The selected processor. */
58 enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
59
60 /* The size of the callee register save area. Right now we save everything
61 on entry since it costs us nothing in code size. It does cost us from a
62 speed standpoint, so we want to optimize this sooner or later. */
63 #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
64 + 4 * df_regs_ever_live_p (3) \
65 + 4 * df_regs_ever_live_p (6) \
66 + 4 * df_regs_ever_live_p (7) \
67 + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \
68 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)))
69
70
71 static bool mn10300_handle_option (size_t, const char *, int);
72 static void mn10300_option_override (void);
73 static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool);
74 static int mn10300_address_cost_1 (rtx, int *);
75 static int mn10300_address_cost (rtx, bool);
76 static bool mn10300_rtx_costs (rtx, int, int, int *, bool);
77 static void mn10300_file_start (void);
78 static bool mn10300_return_in_memory (const_tree, const_tree);
79 static rtx mn10300_builtin_saveregs (void);
80 static void mn10300_va_start (tree, rtx);
81 static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode);
82 static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
83 const_tree, bool);
84 static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
85 tree, bool);
86 static unsigned int mn10300_case_values_threshold (void);
87 static void mn10300_encode_section_info (tree, rtx, int);
88 static void mn10300_asm_trampoline_template (FILE *);
89 static void mn10300_trampoline_init (rtx, tree, rtx);
90 static rtx mn10300_function_value (const_tree, const_tree, bool);
91 static rtx mn10300_libcall_value (enum machine_mode, const_rtx);
92 static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
93 static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
94 \f
95 /* Initialize the GCC target structure. */
96 #undef TARGET_ASM_ALIGNED_HI_OP
97 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
98
99 #undef TARGET_LEGITIMIZE_ADDRESS
100 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
101
102 #undef TARGET_RTX_COSTS
103 #define TARGET_RTX_COSTS mn10300_rtx_costs
104 #undef TARGET_ADDRESS_COST
105 #define TARGET_ADDRESS_COST mn10300_address_cost
106
107 #undef TARGET_ASM_FILE_START
108 #define TARGET_ASM_FILE_START mn10300_file_start
109 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
110 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
111
112 #undef TARGET_DEFAULT_TARGET_FLAGS
113 #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
114 #undef TARGET_HANDLE_OPTION
115 #define TARGET_HANDLE_OPTION mn10300_handle_option
116 #undef TARGET_OPTION_OVERRIDE
117 #define TARGET_OPTION_OVERRIDE mn10300_option_override
118
119 #undef TARGET_ENCODE_SECTION_INFO
120 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
121
122 #undef TARGET_PROMOTE_PROTOTYPES
123 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
124 #undef TARGET_RETURN_IN_MEMORY
125 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
126 #undef TARGET_PASS_BY_REFERENCE
127 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
128 #undef TARGET_CALLEE_COPIES
129 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
130 #undef TARGET_ARG_PARTIAL_BYTES
131 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
132
133 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
134 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
135 #undef TARGET_EXPAND_BUILTIN_VA_START
136 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
137
138 #undef TARGET_CASE_VALUES_THRESHOLD
139 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
140
141 #undef TARGET_LEGITIMATE_ADDRESS_P
142 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
143
144 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
145 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
146 #undef TARGET_TRAMPOLINE_INIT
147 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
148
149 #undef TARGET_FUNCTION_VALUE
150 #define TARGET_FUNCTION_VALUE mn10300_function_value
151 #undef TARGET_LIBCALL_VALUE
152 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
153
154 #undef TARGET_ASM_OUTPUT_MI_THUNK
155 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
156 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
157 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
158
159 struct gcc_target targetm = TARGET_INITIALIZER;
160 \f
161 /* Implement TARGET_HANDLE_OPTION. */
162
163 static bool
164 mn10300_handle_option (size_t code,
165 const char *arg ATTRIBUTE_UNUSED,
166 int value)
167 {
168 switch (code)
169 {
170 case OPT_mam33:
171 mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
172 return true;
173 case OPT_mam33_2:
174 mn10300_processor = (value
175 ? PROCESSOR_AM33_2
176 : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
177 return true;
178 default:
179 return true;
180 }
181 }
182
183 /* Implement TARGET_OPTION_OVERRIDE. */
184
185 static void
186 mn10300_option_override (void)
187 {
188 if (TARGET_AM33)
189 target_flags &= ~MASK_MULT_BUG;
190 }
191
192 static void
193 mn10300_file_start (void)
194 {
195 default_file_start ();
196
197 if (TARGET_AM33_2)
198 fprintf (asm_out_file, "\t.am33_2\n");
199 else if (TARGET_AM33)
200 fprintf (asm_out_file, "\t.am33\n");
201 }
202 \f
203
204 /* Print operand X using operand code CODE to assembly language output file
205 FILE. */
206
207 void
208 print_operand (FILE *file, rtx x, int code)
209 {
210 switch (code)
211 {
212 case 'b':
213 case 'B':
214 if (cc_status.mdep.fpCC)
215 {
216 switch (code == 'b' ? GET_CODE (x)
217 : reverse_condition_maybe_unordered (GET_CODE (x)))
218 {
219 case NE:
220 fprintf (file, "ne");
221 break;
222 case EQ:
223 fprintf (file, "eq");
224 break;
225 case GE:
226 fprintf (file, "ge");
227 break;
228 case GT:
229 fprintf (file, "gt");
230 break;
231 case LE:
232 fprintf (file, "le");
233 break;
234 case LT:
235 fprintf (file, "lt");
236 break;
237 case ORDERED:
238 fprintf (file, "lge");
239 break;
240 case UNORDERED:
241 fprintf (file, "uo");
242 break;
243 case LTGT:
244 fprintf (file, "lg");
245 break;
246 case UNEQ:
247 fprintf (file, "ue");
248 break;
249 case UNGE:
250 fprintf (file, "uge");
251 break;
252 case UNGT:
253 fprintf (file, "ug");
254 break;
255 case UNLE:
256 fprintf (file, "ule");
257 break;
258 case UNLT:
259 fprintf (file, "ul");
260 break;
261 default:
262 gcc_unreachable ();
263 }
264 break;
265 }
266 /* These are normal and reversed branches. */
267 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
268 {
269 case NE:
270 fprintf (file, "ne");
271 break;
272 case EQ:
273 fprintf (file, "eq");
274 break;
275 case GE:
276 fprintf (file, "ge");
277 break;
278 case GT:
279 fprintf (file, "gt");
280 break;
281 case LE:
282 fprintf (file, "le");
283 break;
284 case LT:
285 fprintf (file, "lt");
286 break;
287 case GEU:
288 fprintf (file, "cc");
289 break;
290 case GTU:
291 fprintf (file, "hi");
292 break;
293 case LEU:
294 fprintf (file, "ls");
295 break;
296 case LTU:
297 fprintf (file, "cs");
298 break;
299 default:
300 gcc_unreachable ();
301 }
302 break;
303 case 'C':
304 /* This is used for the operand to a call instruction;
305 if it's a REG, enclose it in parens, else output
306 the operand normally. */
307 if (GET_CODE (x) == REG)
308 {
309 fputc ('(', file);
310 print_operand (file, x, 0);
311 fputc (')', file);
312 }
313 else
314 print_operand (file, x, 0);
315 break;
316
317 case 'D':
318 switch (GET_CODE (x))
319 {
320 case MEM:
321 fputc ('(', file);
322 output_address (XEXP (x, 0));
323 fputc (')', file);
324 break;
325
326 case REG:
327 fprintf (file, "fd%d", REGNO (x) - 18);
328 break;
329
330 default:
331 gcc_unreachable ();
332 }
333 break;
334
335 /* These are the least significant word in a 64bit value. */
336 case 'L':
337 switch (GET_CODE (x))
338 {
339 case MEM:
340 fputc ('(', file);
341 output_address (XEXP (x, 0));
342 fputc (')', file);
343 break;
344
345 case REG:
346 fprintf (file, "%s", reg_names[REGNO (x)]);
347 break;
348
349 case SUBREG:
350 fprintf (file, "%s", reg_names[subreg_regno (x)]);
351 break;
352
353 case CONST_DOUBLE:
354 {
355 long val[2];
356 REAL_VALUE_TYPE rv;
357
358 switch (GET_MODE (x))
359 {
360 case DFmode:
361 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
362 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
363 fprintf (file, "0x%lx", val[0]);
364 break;;
365 case SFmode:
366 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
367 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
368 fprintf (file, "0x%lx", val[0]);
369 break;;
370 case VOIDmode:
371 case DImode:
372 print_operand_address (file,
373 GEN_INT (CONST_DOUBLE_LOW (x)));
374 break;
375 default:
376 break;
377 }
378 break;
379 }
380
381 case CONST_INT:
382 {
383 rtx low, high;
384 split_double (x, &low, &high);
385 fprintf (file, "%ld", (long)INTVAL (low));
386 break;
387 }
388
389 default:
390 gcc_unreachable ();
391 }
392 break;
393
394 /* Similarly, but for the most significant word. */
395 case 'H':
396 switch (GET_CODE (x))
397 {
398 case MEM:
399 fputc ('(', file);
400 x = adjust_address (x, SImode, 4);
401 output_address (XEXP (x, 0));
402 fputc (')', file);
403 break;
404
405 case REG:
406 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
407 break;
408
409 case SUBREG:
410 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
411 break;
412
413 case CONST_DOUBLE:
414 {
415 long val[2];
416 REAL_VALUE_TYPE rv;
417
418 switch (GET_MODE (x))
419 {
420 case DFmode:
421 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
422 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
423 fprintf (file, "0x%lx", val[1]);
424 break;;
425 case SFmode:
426 gcc_unreachable ();
427 case VOIDmode:
428 case DImode:
429 print_operand_address (file,
430 GEN_INT (CONST_DOUBLE_HIGH (x)));
431 break;
432 default:
433 break;
434 }
435 break;
436 }
437
438 case CONST_INT:
439 {
440 rtx low, high;
441 split_double (x, &low, &high);
442 fprintf (file, "%ld", (long)INTVAL (high));
443 break;
444 }
445
446 default:
447 gcc_unreachable ();
448 }
449 break;
450
451 case 'A':
452 fputc ('(', file);
453 if (GET_CODE (XEXP (x, 0)) == REG)
454 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
455 else
456 output_address (XEXP (x, 0));
457 fputc (')', file);
458 break;
459
460 case 'N':
461 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
462 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
463 break;
464
465 case 'U':
466 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
467 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
468 break;
469
470 /* For shift counts. The hardware ignores the upper bits of
471 any immediate, but the assembler will flag an out of range
472 shift count as an error. So we mask off the high bits
473 of the immediate here. */
474 case 'S':
475 if (GET_CODE (x) == CONST_INT)
476 {
477 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
478 break;
479 }
480 /* FALL THROUGH */
481
482 default:
483 switch (GET_CODE (x))
484 {
485 case MEM:
486 fputc ('(', file);
487 output_address (XEXP (x, 0));
488 fputc (')', file);
489 break;
490
491 case PLUS:
492 output_address (x);
493 break;
494
495 case REG:
496 fprintf (file, "%s", reg_names[REGNO (x)]);
497 break;
498
499 case SUBREG:
500 fprintf (file, "%s", reg_names[subreg_regno (x)]);
501 break;
502
503 /* This will only be single precision.... */
504 case CONST_DOUBLE:
505 {
506 unsigned long val;
507 REAL_VALUE_TYPE rv;
508
509 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
510 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
511 fprintf (file, "0x%lx", val);
512 break;
513 }
514
515 case CONST_INT:
516 case SYMBOL_REF:
517 case CONST:
518 case LABEL_REF:
519 case CODE_LABEL:
520 case UNSPEC:
521 print_operand_address (file, x);
522 break;
523 default:
524 gcc_unreachable ();
525 }
526 break;
527 }
528 }
529
530 /* Output assembly language output for the address ADDR to FILE. */
531
532 void
533 print_operand_address (FILE *file, rtx addr)
534 {
535 switch (GET_CODE (addr))
536 {
537 case POST_INC:
538 print_operand_address (file, XEXP (addr, 0));
539 fputc ('+', file);
540 break;
541 case REG:
542 print_operand (file, addr, 0);
543 break;
544 case PLUS:
545 {
546 rtx base, index;
547 if (REG_P (XEXP (addr, 0))
548 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
549 base = XEXP (addr, 0), index = XEXP (addr, 1);
550 else if (REG_P (XEXP (addr, 1))
551 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
552 base = XEXP (addr, 1), index = XEXP (addr, 0);
553 else
554 gcc_unreachable ();
555 print_operand (file, index, 0);
556 fputc (',', file);
557 print_operand (file, base, 0);;
558 break;
559 }
560 case SYMBOL_REF:
561 output_addr_const (file, addr);
562 break;
563 default:
564 output_addr_const (file, addr);
565 break;
566 }
567 }
568
569 /* Count the number of FP registers that have to be saved. */
570 static int
571 fp_regs_to_save (void)
572 {
573 int i, n = 0;
574
575 if (! TARGET_AM33_2)
576 return 0;
577
578 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
579 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
580 ++n;
581
582 return n;
583 }
584
585 /* Print a set of registers in the format required by "movm" and "ret".
586 Register K is saved if bit K of MASK is set. The data and address
587 registers can be stored individually, but the extended registers cannot.
588 We assume that the mask already takes that into account. For instance,
589 bits 14 to 17 must have the same value. */
590
591 void
592 mn10300_print_reg_list (FILE *file, int mask)
593 {
594 int need_comma;
595 int i;
596
597 need_comma = 0;
598 fputc ('[', file);
599
600 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
601 if ((mask & (1 << i)) != 0)
602 {
603 if (need_comma)
604 fputc (',', file);
605 fputs (reg_names [i], file);
606 need_comma = 1;
607 }
608
609 if ((mask & 0x3c000) != 0)
610 {
611 gcc_assert ((mask & 0x3c000) == 0x3c000);
612 if (need_comma)
613 fputc (',', file);
614 fputs ("exreg1", file);
615 need_comma = 1;
616 }
617
618 fputc (']', file);
619 }
620
621 int
622 can_use_return_insn (void)
623 {
624 /* size includes the fixed stack space needed for function calls. */
625 int size = get_frame_size () + crtl->outgoing_args_size;
626
627 /* And space for the return pointer. */
628 size += crtl->outgoing_args_size ? 4 : 0;
629
630 return (reload_completed
631 && size == 0
632 && !df_regs_ever_live_p (2)
633 && !df_regs_ever_live_p (3)
634 && !df_regs_ever_live_p (6)
635 && !df_regs_ever_live_p (7)
636 && !df_regs_ever_live_p (14)
637 && !df_regs_ever_live_p (15)
638 && !df_regs_ever_live_p (16)
639 && !df_regs_ever_live_p (17)
640 && fp_regs_to_save () == 0
641 && !frame_pointer_needed);
642 }
643
644 /* Returns the set of live, callee-saved registers as a bitmask. The
645 callee-saved extended registers cannot be stored individually, so
646 all of them will be included in the mask if any one of them is used. */
647
648 int
649 mn10300_get_live_callee_saved_regs (void)
650 {
651 int mask;
652 int i;
653
654 mask = 0;
655 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
656 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
657 mask |= (1 << i);
658 if ((mask & 0x3c000) != 0)
659 mask |= 0x3c000;
660
661 return mask;
662 }
663
664 /* Generate an instruction that pushes several registers onto the stack.
665 Register K will be saved if bit K in MASK is set. The function does
666 nothing if MASK is zero.
667
668 To be compatible with the "movm" instruction, the lowest-numbered
669 register must be stored in the lowest slot. If MASK is the set
670 { R1,...,RN }, where R1...RN are ordered least first, the generated
671 instruction will have the form:
672
673 (parallel
674 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
675 (set (mem:SI (plus:SI (reg:SI 9)
676 (const_int -1*4)))
677 (reg:SI RN))
678 ...
679 (set (mem:SI (plus:SI (reg:SI 9)
680 (const_int -N*4)))
681 (reg:SI R1))) */
682
683 void
684 mn10300_gen_multiple_store (int mask)
685 {
686 if (mask != 0)
687 {
688 int i;
689 int count;
690 rtx par;
691 int pari;
692
693 /* Count how many registers need to be saved. */
694 count = 0;
695 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
696 if ((mask & (1 << i)) != 0)
697 count += 1;
698
699 /* We need one PARALLEL element to update the stack pointer and
700 an additional element for each register that is stored. */
701 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
702
703 /* Create the instruction that updates the stack pointer. */
704 XVECEXP (par, 0, 0)
705 = gen_rtx_SET (SImode,
706 stack_pointer_rtx,
707 gen_rtx_PLUS (SImode,
708 stack_pointer_rtx,
709 GEN_INT (-count * 4)));
710
711 /* Create each store. */
712 pari = 1;
713 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
714 if ((mask & (1 << i)) != 0)
715 {
716 rtx address = gen_rtx_PLUS (SImode,
717 stack_pointer_rtx,
718 GEN_INT (-pari * 4));
719 XVECEXP(par, 0, pari)
720 = gen_rtx_SET (VOIDmode,
721 gen_rtx_MEM (SImode, address),
722 gen_rtx_REG (SImode, i));
723 pari += 1;
724 }
725
726 par = emit_insn (par);
727 RTX_FRAME_RELATED_P (par) = 1;
728 }
729 }
730
731 void
732 expand_prologue (void)
733 {
734 HOST_WIDE_INT size;
735
736 /* SIZE includes the fixed stack space needed for function calls. */
737 size = get_frame_size () + crtl->outgoing_args_size;
738 size += (crtl->outgoing_args_size ? 4 : 0);
739
740 /* If we use any of the callee-saved registers, save them now. */
741 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
742
743 if (TARGET_AM33_2 && fp_regs_to_save ())
744 {
745 int num_regs_to_save = fp_regs_to_save (), i;
746 HOST_WIDE_INT xsize;
747 enum { save_sp_merge,
748 save_sp_no_merge,
749 save_sp_partial_merge,
750 save_a0_merge,
751 save_a0_no_merge } strategy;
752 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
753 rtx reg;
754 rtx insn;
755
756 /* We have several different strategies to save FP registers.
757 We can store them using SP offsets, which is beneficial if
758 there are just a few registers to save, or we can use `a0' in
759 post-increment mode (`a0' is the only call-clobbered address
760 register that is never used to pass information to a
761 function). Furthermore, if we don't need a frame pointer, we
762 can merge the two SP adds into a single one, but this isn't
763 always beneficial; sometimes we can just split the two adds
764 so that we don't exceed a 16-bit constant size. The code
765 below will select which strategy to use, so as to generate
766 smallest code. Ties are broken in favor or shorter sequences
767 (in terms of number of instructions). */
768
769 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
770 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
771 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
772 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
773 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
774 (((S) >= (L)) ? (SIZE1) * (N) \
775 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
776 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
777 : (ELSE))
778 #define SIZE_FMOV_SP_(S,N) \
779 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
780 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
781 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
782 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
783
784 /* Consider alternative save_sp_merge only if we don't need the
785 frame pointer and size is nonzero. */
786 if (! frame_pointer_needed && size)
787 {
788 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
789 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
790 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
791 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
792
793 if (this_strategy_size < strategy_size)
794 {
795 strategy = save_sp_merge;
796 strategy_size = this_strategy_size;
797 }
798 }
799
800 /* Consider alternative save_sp_no_merge unconditionally. */
801 /* Insn: add -4 * num_regs_to_save, sp. */
802 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
803 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
804 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
805 if (size)
806 {
807 /* Insn: add -size, sp. */
808 this_strategy_size += SIZE_ADD_SP (-size);
809 }
810
811 if (this_strategy_size < strategy_size)
812 {
813 strategy = save_sp_no_merge;
814 strategy_size = this_strategy_size;
815 }
816
817 /* Consider alternative save_sp_partial_merge only if we don't
818 need a frame pointer and size is reasonably large. */
819 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
820 {
821 /* Insn: add -128, sp. */
822 this_strategy_size = SIZE_ADD_SP (-128);
823 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
824 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
825 num_regs_to_save);
826 if (size)
827 {
828 /* Insn: add 128-size, sp. */
829 this_strategy_size += SIZE_ADD_SP (128 - size);
830 }
831
832 if (this_strategy_size < strategy_size)
833 {
834 strategy = save_sp_partial_merge;
835 strategy_size = this_strategy_size;
836 }
837 }
838
839 /* Consider alternative save_a0_merge only if we don't need a
840 frame pointer, size is nonzero and the user hasn't
841 changed the calling conventions of a0. */
842 if (! frame_pointer_needed && size
843 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
844 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
845 {
846 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
847 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
848 /* Insn: mov sp, a0. */
849 this_strategy_size++;
850 if (size)
851 {
852 /* Insn: add size, a0. */
853 this_strategy_size += SIZE_ADD_AX (size);
854 }
855 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
856 this_strategy_size += 3 * num_regs_to_save;
857
858 if (this_strategy_size < strategy_size)
859 {
860 strategy = save_a0_merge;
861 strategy_size = this_strategy_size;
862 }
863 }
864
865 /* Consider alternative save_a0_no_merge if the user hasn't
866 changed the calling conventions of a0. */
867 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
868 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
869 {
870 /* Insn: add -4 * num_regs_to_save, sp. */
871 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
872 /* Insn: mov sp, a0. */
873 this_strategy_size++;
874 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
875 this_strategy_size += 3 * num_regs_to_save;
876 if (size)
877 {
878 /* Insn: add -size, sp. */
879 this_strategy_size += SIZE_ADD_SP (-size);
880 }
881
882 if (this_strategy_size < strategy_size)
883 {
884 strategy = save_a0_no_merge;
885 strategy_size = this_strategy_size;
886 }
887 }
888
889 /* Emit the initial SP add, common to all strategies. */
890 switch (strategy)
891 {
892 case save_sp_no_merge:
893 case save_a0_no_merge:
894 emit_insn (gen_addsi3 (stack_pointer_rtx,
895 stack_pointer_rtx,
896 GEN_INT (-4 * num_regs_to_save)));
897 xsize = 0;
898 break;
899
900 case save_sp_partial_merge:
901 emit_insn (gen_addsi3 (stack_pointer_rtx,
902 stack_pointer_rtx,
903 GEN_INT (-128)));
904 xsize = 128 - 4 * num_regs_to_save;
905 size -= xsize;
906 break;
907
908 case save_sp_merge:
909 case save_a0_merge:
910 emit_insn (gen_addsi3 (stack_pointer_rtx,
911 stack_pointer_rtx,
912 GEN_INT (-(size + 4 * num_regs_to_save))));
913 /* We'll have to adjust FP register saves according to the
914 frame size. */
915 xsize = size;
916 /* Since we've already created the stack frame, don't do it
917 again at the end of the function. */
918 size = 0;
919 break;
920
921 default:
922 gcc_unreachable ();
923 }
924
925 /* Now prepare register a0, if we have decided to use it. */
926 switch (strategy)
927 {
928 case save_sp_merge:
929 case save_sp_no_merge:
930 case save_sp_partial_merge:
931 reg = 0;
932 break;
933
934 case save_a0_merge:
935 case save_a0_no_merge:
936 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
937 emit_insn (gen_movsi (reg, stack_pointer_rtx));
938 if (xsize)
939 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
940 reg = gen_rtx_POST_INC (SImode, reg);
941 break;
942
943 default:
944 gcc_unreachable ();
945 }
946
947 /* Now actually save the FP registers. */
948 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
949 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
950 {
951 rtx addr;
952
953 if (reg)
954 addr = reg;
955 else
956 {
957 /* If we aren't using `a0', use an SP offset. */
958 if (xsize)
959 {
960 addr = gen_rtx_PLUS (SImode,
961 stack_pointer_rtx,
962 GEN_INT (xsize));
963 }
964 else
965 addr = stack_pointer_rtx;
966
967 xsize += 4;
968 }
969
970 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
971 gen_rtx_REG (SImode, i)));
972
973 RTX_FRAME_RELATED_P (insn) = 1;
974 }
975 }
976
977 /* Now put the frame pointer into the frame pointer register. */
978 if (frame_pointer_needed)
979 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
980
981 /* Allocate stack for this frame. */
982 if (size)
983 emit_insn (gen_addsi3 (stack_pointer_rtx,
984 stack_pointer_rtx,
985 GEN_INT (-size)));
986 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
987 emit_insn (gen_GOTaddr2picreg ());
988 }
989
990 void
991 expand_epilogue (void)
992 {
993 HOST_WIDE_INT size;
994
995 /* SIZE includes the fixed stack space needed for function calls. */
996 size = get_frame_size () + crtl->outgoing_args_size;
997 size += (crtl->outgoing_args_size ? 4 : 0);
998
999 if (TARGET_AM33_2 && fp_regs_to_save ())
1000 {
1001 int num_regs_to_save = fp_regs_to_save (), i;
1002 rtx reg = 0;
1003
1004 /* We have several options to restore FP registers. We could
1005 load them from SP offsets, but, if there are enough FP
1006 registers to restore, we win if we use a post-increment
1007 addressing mode. */
1008
1009 /* If we have a frame pointer, it's the best option, because we
1010 already know it has the value we want. */
1011 if (frame_pointer_needed)
1012 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1013 /* Otherwise, we may use `a1', since it's call-clobbered and
1014 it's never used for return values. But only do so if it's
1015 smaller than using SP offsets. */
1016 else
1017 {
1018 enum { restore_sp_post_adjust,
1019 restore_sp_pre_adjust,
1020 restore_sp_partial_adjust,
1021 restore_a1 } strategy;
1022 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1023
1024 /* Consider using sp offsets before adjusting sp. */
1025 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1026 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1027 /* If size is too large, we'll have to adjust SP with an
1028 add. */
1029 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1030 {
1031 /* Insn: add size + 4 * num_regs_to_save, sp. */
1032 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1033 }
1034 /* If we don't have to restore any non-FP registers,
1035 we'll be able to save one byte by using rets. */
1036 if (! REG_SAVE_BYTES)
1037 this_strategy_size--;
1038
1039 if (this_strategy_size < strategy_size)
1040 {
1041 strategy = restore_sp_post_adjust;
1042 strategy_size = this_strategy_size;
1043 }
1044
1045 /* Consider using sp offsets after adjusting sp. */
1046 /* Insn: add size, sp. */
1047 this_strategy_size = SIZE_ADD_SP (size);
1048 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1049 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1050 /* We're going to use ret to release the FP registers
1051 save area, so, no savings. */
1052
1053 if (this_strategy_size < strategy_size)
1054 {
1055 strategy = restore_sp_pre_adjust;
1056 strategy_size = this_strategy_size;
1057 }
1058
1059 /* Consider using sp offsets after partially adjusting sp.
1060 When size is close to 32Kb, we may be able to adjust SP
1061 with an imm16 add instruction while still using fmov
1062 (d8,sp). */
1063 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1064 {
1065 /* Insn: add size + 4 * num_regs_to_save
1066 + REG_SAVE_BYTES - 252,sp. */
1067 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1068 + REG_SAVE_BYTES - 252);
1069 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1070 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1071 - 4 * num_regs_to_save,
1072 num_regs_to_save);
1073 /* We're going to use ret to release the FP registers
1074 save area, so, no savings. */
1075
1076 if (this_strategy_size < strategy_size)
1077 {
1078 strategy = restore_sp_partial_adjust;
1079 strategy_size = this_strategy_size;
1080 }
1081 }
1082
1083 /* Consider using a1 in post-increment mode, as long as the
1084 user hasn't changed the calling conventions of a1. */
1085 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1086 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1087 {
1088 /* Insn: mov sp,a1. */
1089 this_strategy_size = 1;
1090 if (size)
1091 {
1092 /* Insn: add size,a1. */
1093 this_strategy_size += SIZE_ADD_AX (size);
1094 }
1095 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1096 this_strategy_size += 3 * num_regs_to_save;
1097 /* If size is large enough, we may be able to save a
1098 couple of bytes. */
1099 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1100 {
1101 /* Insn: mov a1,sp. */
1102 this_strategy_size += 2;
1103 }
1104 /* If we don't have to restore any non-FP registers,
1105 we'll be able to save one byte by using rets. */
1106 if (! REG_SAVE_BYTES)
1107 this_strategy_size--;
1108
1109 if (this_strategy_size < strategy_size)
1110 {
1111 strategy = restore_a1;
1112 strategy_size = this_strategy_size;
1113 }
1114 }
1115
1116 switch (strategy)
1117 {
1118 case restore_sp_post_adjust:
1119 break;
1120
1121 case restore_sp_pre_adjust:
1122 emit_insn (gen_addsi3 (stack_pointer_rtx,
1123 stack_pointer_rtx,
1124 GEN_INT (size)));
1125 size = 0;
1126 break;
1127
1128 case restore_sp_partial_adjust:
1129 emit_insn (gen_addsi3 (stack_pointer_rtx,
1130 stack_pointer_rtx,
1131 GEN_INT (size + 4 * num_regs_to_save
1132 + REG_SAVE_BYTES - 252)));
1133 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1134 break;
1135
1136 case restore_a1:
1137 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1138 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1139 if (size)
1140 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1141 break;
1142
1143 default:
1144 gcc_unreachable ();
1145 }
1146 }
1147
1148 /* Adjust the selected register, if any, for post-increment. */
1149 if (reg)
1150 reg = gen_rtx_POST_INC (SImode, reg);
1151
1152 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1153 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1154 {
1155 rtx addr;
1156
1157 if (reg)
1158 addr = reg;
1159 else if (size)
1160 {
1161 /* If we aren't using a post-increment register, use an
1162 SP offset. */
1163 addr = gen_rtx_PLUS (SImode,
1164 stack_pointer_rtx,
1165 GEN_INT (size));
1166 }
1167 else
1168 addr = stack_pointer_rtx;
1169
1170 size += 4;
1171
1172 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1173 gen_rtx_MEM (SImode, addr)));
1174 }
1175
1176 /* If we were using the restore_a1 strategy and the number of
1177 bytes to be released won't fit in the `ret' byte, copy `a1'
1178 to `sp', to avoid having to use `add' to adjust it. */
1179 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1180 {
1181 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1182 size = 0;
1183 }
1184 }
1185
1186 /* Maybe cut back the stack, except for the register save area.
1187
1188 If the frame pointer exists, then use the frame pointer to
1189 cut back the stack.
1190
1191 If the stack size + register save area is more than 255 bytes,
1192 then the stack must be cut back here since the size + register
1193 save size is too big for a ret/retf instruction.
1194
1195 Else leave it alone, it will be cut back as part of the
1196 ret/retf instruction, or there wasn't any stack to begin with.
1197
1198 Under no circumstances should the register save area be
1199 deallocated here, that would leave a window where an interrupt
1200 could occur and trash the register save area. */
1201 if (frame_pointer_needed)
1202 {
1203 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1204 size = 0;
1205 }
1206 else if (size + REG_SAVE_BYTES > 255)
1207 {
1208 emit_insn (gen_addsi3 (stack_pointer_rtx,
1209 stack_pointer_rtx,
1210 GEN_INT (size)));
1211 size = 0;
1212 }
1213
1214 /* Adjust the stack and restore callee-saved registers, if any. */
1215 if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1216 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1217 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1218 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1219 || frame_pointer_needed)
1220 emit_jump_insn (gen_return_internal_regs
1221 (GEN_INT (size + REG_SAVE_BYTES)));
1222 else
1223 emit_jump_insn (gen_return_internal ());
1224 }
1225
1226 /* Update the condition code from the insn. */
1227
1228 void
1229 notice_update_cc (rtx body, rtx insn)
1230 {
1231 switch (get_attr_cc (insn))
1232 {
1233 case CC_NONE:
1234 /* Insn does not affect CC at all. */
1235 break;
1236
1237 case CC_NONE_0HIT:
1238 /* Insn does not change CC, but the 0'th operand has been changed. */
1239 if (cc_status.value1 != 0
1240 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1241 cc_status.value1 = 0;
1242 break;
1243
1244 case CC_SET_ZN:
1245 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1246 V,C are unusable. */
1247 CC_STATUS_INIT;
1248 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1249 cc_status.value1 = recog_data.operand[0];
1250 break;
1251
1252 case CC_SET_ZNV:
1253 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1254 C is unusable. */
1255 CC_STATUS_INIT;
1256 cc_status.flags |= CC_NO_CARRY;
1257 cc_status.value1 = recog_data.operand[0];
1258 break;
1259
1260 case CC_COMPARE:
1261 /* The insn is a compare instruction. */
1262 CC_STATUS_INIT;
1263 cc_status.value1 = SET_SRC (body);
1264 if (GET_CODE (cc_status.value1) == COMPARE
1265 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1266 cc_status.mdep.fpCC = 1;
1267 break;
1268
1269 case CC_CLOBBER:
1270 /* Insn doesn't leave CC in a usable state. */
1271 CC_STATUS_INIT;
1272 break;
1273
1274 default:
1275 gcc_unreachable ();
1276 }
1277 }
1278
1279 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1280 This function is for MATCH_PARALLEL and so assumes OP is known to be
1281 parallel. If OP is a multiple store, return a mask indicating which
1282 registers it saves. Return 0 otherwise. */
1283
1284 int
1285 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1286 {
1287 int count;
1288 int mask;
1289 int i;
1290 unsigned int last;
1291 rtx elt;
1292
1293 count = XVECLEN (op, 0);
1294 if (count < 2)
1295 return 0;
1296
1297 /* Check that first instruction has the form (set (sp) (plus A B)) */
1298 elt = XVECEXP (op, 0, 0);
1299 if (GET_CODE (elt) != SET
1300 || GET_CODE (SET_DEST (elt)) != REG
1301 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1302 || GET_CODE (SET_SRC (elt)) != PLUS)
1303 return 0;
1304
1305 /* Check that A is the stack pointer and B is the expected stack size.
1306 For OP to match, each subsequent instruction should push a word onto
1307 the stack. We therefore expect the first instruction to create
1308 COUNT-1 stack slots. */
1309 elt = SET_SRC (elt);
1310 if (GET_CODE (XEXP (elt, 0)) != REG
1311 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1312 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1313 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1314 return 0;
1315
1316 /* Now go through the rest of the vector elements. They must be
1317 ordered so that the first instruction stores the highest-numbered
1318 register to the highest stack slot and that subsequent instructions
1319 store a lower-numbered register to the slot below.
1320
1321 LAST keeps track of the smallest-numbered register stored so far.
1322 MASK is the set of stored registers. */
1323 last = LAST_EXTENDED_REGNUM + 1;
1324 mask = 0;
1325 for (i = 1; i < count; i++)
1326 {
1327 /* Check that element i is a (set (mem M) R) and that R is valid. */
1328 elt = XVECEXP (op, 0, i);
1329 if (GET_CODE (elt) != SET
1330 || GET_CODE (SET_DEST (elt)) != MEM
1331 || GET_CODE (SET_SRC (elt)) != REG
1332 || REGNO (SET_SRC (elt)) >= last)
1333 return 0;
1334
1335 /* R was OK, so provisionally add it to MASK. We return 0 in any
1336 case if the rest of the instruction has a flaw. */
1337 last = REGNO (SET_SRC (elt));
1338 mask |= (1 << last);
1339
1340 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1341 elt = XEXP (SET_DEST (elt), 0);
1342 if (GET_CODE (elt) != PLUS
1343 || GET_CODE (XEXP (elt, 0)) != REG
1344 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1345 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1346 || INTVAL (XEXP (elt, 1)) != -i * 4)
1347 return 0;
1348 }
1349
1350 /* All or none of the callee-saved extended registers must be in the set. */
1351 if ((mask & 0x3c000) != 0
1352 && (mask & 0x3c000) != 0x3c000)
1353 return 0;
1354
1355 return mask;
1356 }
1357
1358 /* What (if any) secondary registers are needed to move IN with mode
1359 MODE into a register in register class RCLASS.
1360
1361 We might be able to simplify this. */
1362 enum reg_class
1363 mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
1364 rtx in)
1365 {
1366 rtx inner = in;
1367
1368 /* Strip off any SUBREG expressions from IN. Basically we want
1369 to know if IN is a pseudo or (subreg (pseudo)) as those can
1370 turn into MEMs during reload. */
1371 while (GET_CODE (inner) == SUBREG)
1372 inner = SUBREG_REG (inner);
1373
1374 /* Memory loads less than a full word wide can't have an
1375 address or stack pointer destination. They must use
1376 a data register as an intermediate register. */
1377 if ((GET_CODE (in) == MEM
1378 || (GET_CODE (inner) == REG
1379 && REGNO (inner) >= FIRST_PSEUDO_REGISTER))
1380 && (mode == QImode || mode == HImode)
1381 && (rclass == ADDRESS_REGS || rclass == SP_REGS
1382 || rclass == SP_OR_ADDRESS_REGS))
1383 {
1384 if (TARGET_AM33)
1385 return DATA_OR_EXTENDED_REGS;
1386 return DATA_REGS;
1387 }
1388
1389 /* We can't directly load sp + const_int into a data register;
1390 we must use an address register as an intermediate. */
1391 if (rclass != SP_REGS
1392 && rclass != ADDRESS_REGS
1393 && rclass != SP_OR_ADDRESS_REGS
1394 && rclass != SP_OR_EXTENDED_REGS
1395 && rclass != ADDRESS_OR_EXTENDED_REGS
1396 && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS
1397 && (in == stack_pointer_rtx
1398 || (GET_CODE (in) == PLUS
1399 && (XEXP (in, 0) == stack_pointer_rtx
1400 || XEXP (in, 1) == stack_pointer_rtx))))
1401 return ADDRESS_REGS;
1402
1403 if (GET_CODE (in) == PLUS
1404 && (XEXP (in, 0) == stack_pointer_rtx
1405 || XEXP (in, 1) == stack_pointer_rtx))
1406 return GENERAL_REGS;
1407
1408 if (TARGET_AM33_2
1409 && rclass == FP_REGS)
1410 {
1411 /* We can't load directly into an FP register from a
1412 constant address. */
1413 if (GET_CODE (in) == MEM
1414 && CONSTANT_ADDRESS_P (XEXP (in, 0)))
1415 return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1416
1417 /* Handle case were a pseudo may not get a hard register
1418 but has an equivalent memory location defined. */
1419 if (GET_CODE (inner) == REG
1420 && REGNO (inner) >= FIRST_PSEUDO_REGISTER
1421 && reg_equiv_mem [REGNO (inner)]
1422 && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
1423 return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1424 }
1425
1426 /* Otherwise assume no secondary reloads are needed. */
1427 return NO_REGS;
1428 }
1429
1430 int
1431 initial_offset (int from, int to)
1432 {
1433 /* The difference between the argument pointer and the frame pointer
1434 is the size of the callee register save area. */
1435 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1436 {
1437 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1438 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1439 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1440 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1441 || fp_regs_to_save ()
1442 || frame_pointer_needed)
1443 return REG_SAVE_BYTES
1444 + 4 * fp_regs_to_save ();
1445 else
1446 return 0;
1447 }
1448
1449 /* The difference between the argument pointer and the stack pointer is
1450 the sum of the size of this function's frame, the callee register save
1451 area, and the fixed stack space needed for function calls (if any). */
1452 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1453 {
1454 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1455 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1456 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1457 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1458 || fp_regs_to_save ()
1459 || frame_pointer_needed)
1460 return (get_frame_size () + REG_SAVE_BYTES
1461 + 4 * fp_regs_to_save ()
1462 + (crtl->outgoing_args_size
1463 ? crtl->outgoing_args_size + 4 : 0));
1464 else
1465 return (get_frame_size ()
1466 + (crtl->outgoing_args_size
1467 ? crtl->outgoing_args_size + 4 : 0));
1468 }
1469
1470 /* The difference between the frame pointer and stack pointer is the sum
1471 of the size of this function's frame and the fixed stack space needed
1472 for function calls (if any). */
1473 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1474 return (get_frame_size ()
1475 + (crtl->outgoing_args_size
1476 ? crtl->outgoing_args_size + 4 : 0));
1477
1478 gcc_unreachable ();
1479 }
1480
1481 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1482
1483 static bool
1484 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1485 {
1486 /* Return values > 8 bytes in length in memory. */
1487 return (int_size_in_bytes (type) > 8
1488 || int_size_in_bytes (type) == 0
1489 || TYPE_MODE (type) == BLKmode);
1490 }
1491
1492 /* Flush the argument registers to the stack for a stdarg function;
1493 return the new argument pointer. */
1494 static rtx
1495 mn10300_builtin_saveregs (void)
1496 {
1497 rtx offset, mem;
1498 tree fntype = TREE_TYPE (current_function_decl);
1499 int argadj = ((!stdarg_p (fntype))
1500 ? UNITS_PER_WORD : 0);
1501 alias_set_type set = get_varargs_alias_set ();
1502
1503 if (argadj)
1504 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
1505 else
1506 offset = crtl->args.arg_offset_rtx;
1507
1508 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1509 set_mem_alias_set (mem, set);
1510 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1511
1512 mem = gen_rtx_MEM (SImode,
1513 plus_constant (crtl->args.internal_arg_pointer, 4));
1514 set_mem_alias_set (mem, set);
1515 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1516
1517 return copy_to_reg (expand_binop (Pmode, add_optab,
1518 crtl->args.internal_arg_pointer,
1519 offset, 0, 0, OPTAB_LIB_WIDEN));
1520 }
1521
1522 static void
1523 mn10300_va_start (tree valist, rtx nextarg)
1524 {
1525 nextarg = expand_builtin_saveregs ();
1526 std_expand_builtin_va_start (valist, nextarg);
1527 }
1528
1529 /* Return true when a parameter should be passed by reference. */
1530
1531 static bool
1532 mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1533 enum machine_mode mode, const_tree type,
1534 bool named ATTRIBUTE_UNUSED)
1535 {
1536 unsigned HOST_WIDE_INT size;
1537
1538 if (type)
1539 size = int_size_in_bytes (type);
1540 else
1541 size = GET_MODE_SIZE (mode);
1542
1543 return (size > 8 || size == 0);
1544 }
1545
1546 /* Return an RTX to represent where a value with mode MODE will be returned
1547 from a function. If the result is NULL_RTX, the argument is pushed. */
1548
1549 rtx
1550 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1551 tree type, int named ATTRIBUTE_UNUSED)
1552 {
1553 rtx result = NULL_RTX;
1554 int size, align;
1555
1556 /* We only support using 2 data registers as argument registers. */
1557 int nregs = 2;
1558
1559 /* Figure out the size of the object to be passed. */
1560 if (mode == BLKmode)
1561 size = int_size_in_bytes (type);
1562 else
1563 size = GET_MODE_SIZE (mode);
1564
1565 /* Figure out the alignment of the object to be passed. */
1566 align = size;
1567
1568 cum->nbytes = (cum->nbytes + 3) & ~3;
1569
1570 /* Don't pass this arg via a register if all the argument registers
1571 are used up. */
1572 if (cum->nbytes > nregs * UNITS_PER_WORD)
1573 return result;
1574
1575 /* Don't pass this arg via a register if it would be split between
1576 registers and memory. */
1577 if (type == NULL_TREE
1578 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1579 return result;
1580
1581 switch (cum->nbytes / UNITS_PER_WORD)
1582 {
1583 case 0:
1584 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1585 break;
1586 case 1:
1587 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1588 break;
1589 default:
1590 break;
1591 }
1592
1593 return result;
1594 }
1595
1596 /* Return the number of bytes of registers to use for an argument passed
1597 partially in registers and partially in memory. */
1598
1599 static int
1600 mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1601 tree type, bool named ATTRIBUTE_UNUSED)
1602 {
1603 int size, align;
1604
1605 /* We only support using 2 data registers as argument registers. */
1606 int nregs = 2;
1607
1608 /* Figure out the size of the object to be passed. */
1609 if (mode == BLKmode)
1610 size = int_size_in_bytes (type);
1611 else
1612 size = GET_MODE_SIZE (mode);
1613
1614 /* Figure out the alignment of the object to be passed. */
1615 align = size;
1616
1617 cum->nbytes = (cum->nbytes + 3) & ~3;
1618
1619 /* Don't pass this arg via a register if all the argument registers
1620 are used up. */
1621 if (cum->nbytes > nregs * UNITS_PER_WORD)
1622 return 0;
1623
1624 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1625 return 0;
1626
1627 /* Don't pass this arg via a register if it would be split between
1628 registers and memory. */
1629 if (type == NULL_TREE
1630 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1631 return 0;
1632
1633 return nregs * UNITS_PER_WORD - cum->nbytes;
1634 }
1635
1636 /* Return the location of the function's value. This will be either
1637 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1638 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1639 we only return the PARALLEL for outgoing values; we do not want
1640 callers relying on this extra copy. */
1641
1642 static rtx
1643 mn10300_function_value (const_tree valtype,
1644 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1645 bool outgoing)
1646 {
1647 rtx rv;
1648 enum machine_mode mode = TYPE_MODE (valtype);
1649
1650 if (! POINTER_TYPE_P (valtype))
1651 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1652 else if (! TARGET_PTR_A0D0 || ! outgoing
1653 || cfun->returns_struct)
1654 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1655
1656 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1657 XVECEXP (rv, 0, 0)
1658 = gen_rtx_EXPR_LIST (VOIDmode,
1659 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1660 GEN_INT (0));
1661
1662 XVECEXP (rv, 0, 1)
1663 = gen_rtx_EXPR_LIST (VOIDmode,
1664 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1665 GEN_INT (0));
1666 return rv;
1667 }
1668
1669 /* Implements TARGET_LIBCALL_VALUE. */
1670
1671 static rtx
1672 mn10300_libcall_value (enum machine_mode mode,
1673 const_rtx fun ATTRIBUTE_UNUSED)
1674 {
1675 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1676 }
1677
1678 /* Implements FUNCTION_VALUE_REGNO_P. */
1679
1680 bool
1681 mn10300_function_value_regno_p (const unsigned int regno)
1682 {
1683 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1684 }
1685
1686 /* Output a tst insn. */
1687 const char *
1688 output_tst (rtx operand, rtx insn)
1689 {
1690 rtx temp;
1691 int past_call = 0;
1692
1693 /* We can save a byte if we can find a register which has the value
1694 zero in it. */
1695 temp = PREV_INSN (insn);
1696 while (optimize && temp)
1697 {
1698 rtx set;
1699
1700 /* We allow the search to go through call insns. We record
1701 the fact that we've past a CALL_INSN and reject matches which
1702 use call clobbered registers. */
1703 if (GET_CODE (temp) == CODE_LABEL
1704 || GET_CODE (temp) == JUMP_INSN
1705 || GET_CODE (temp) == BARRIER)
1706 break;
1707
1708 if (GET_CODE (temp) == CALL_INSN)
1709 past_call = 1;
1710
1711 if (GET_CODE (temp) == NOTE)
1712 {
1713 temp = PREV_INSN (temp);
1714 continue;
1715 }
1716
1717 /* It must be an insn, see if it is a simple set. */
1718 set = single_set (temp);
1719 if (!set)
1720 {
1721 temp = PREV_INSN (temp);
1722 continue;
1723 }
1724
1725 /* Are we setting a data register to zero (this does not win for
1726 address registers)?
1727
1728 If it's a call clobbered register, have we past a call?
1729
1730 Make sure the register we find isn't the same as ourself;
1731 the mn10300 can't encode that.
1732
1733 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1734 so the code to detect calls here isn't doing anything useful. */
1735 if (REG_P (SET_DEST (set))
1736 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1737 && !reg_set_between_p (SET_DEST (set), temp, insn)
1738 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1739 == REGNO_REG_CLASS (REGNO (operand)))
1740 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1741 && REGNO (SET_DEST (set)) != REGNO (operand)
1742 && (!past_call
1743 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1744 {
1745 rtx xoperands[2];
1746 xoperands[0] = operand;
1747 xoperands[1] = SET_DEST (set);
1748
1749 output_asm_insn ("cmp %1,%0", xoperands);
1750 return "";
1751 }
1752
1753 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1754 && REG_P (SET_DEST (set))
1755 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1756 && !reg_set_between_p (SET_DEST (set), temp, insn)
1757 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1758 != REGNO_REG_CLASS (REGNO (operand)))
1759 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1760 && REGNO (SET_DEST (set)) != REGNO (operand)
1761 && (!past_call
1762 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1763 {
1764 rtx xoperands[2];
1765 xoperands[0] = operand;
1766 xoperands[1] = SET_DEST (set);
1767
1768 output_asm_insn ("cmp %1,%0", xoperands);
1769 return "";
1770 }
1771 temp = PREV_INSN (temp);
1772 }
1773 return "cmp 0,%0";
1774 }
1775
1776 int
1777 impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1778 {
1779 if (GET_CODE (op) != PLUS)
1780 return 0;
1781
1782 if (XEXP (op, 0) == stack_pointer_rtx
1783 || XEXP (op, 1) == stack_pointer_rtx)
1784 return 1;
1785
1786 return 0;
1787 }
1788
1789 /* Similarly, but when using a zero_extract pattern for a btst where
1790 the source operand might end up in memory. */
1791 int
1792 mask_ok_for_mem_btst (int len, int bit)
1793 {
1794 unsigned int mask = 0;
1795
1796 while (len > 0)
1797 {
1798 mask |= (1 << bit);
1799 bit++;
1800 len--;
1801 }
1802
1803 /* MASK must bit into an 8bit value. */
1804 return (((mask & 0xff) == mask)
1805 || ((mask & 0xff00) == mask)
1806 || ((mask & 0xff0000) == mask)
1807 || ((mask & 0xff000000) == mask));
1808 }
1809
1810 /* Return 1 if X contains a symbolic expression. We know these
1811 expressions will have one of a few well defined forms, so
1812 we need only check those forms. */
1813 int
1814 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1815 {
1816 switch (GET_CODE (op))
1817 {
1818 case SYMBOL_REF:
1819 case LABEL_REF:
1820 return 1;
1821 case CONST:
1822 op = XEXP (op, 0);
1823 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1824 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1825 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1826 default:
1827 return 0;
1828 }
1829 }
1830
1831 /* Try machine dependent ways of modifying an illegitimate address
1832 to be legitimate. If we find one, return the new valid address.
1833 This macro is used in only one place: `memory_address' in explow.c.
1834
1835 OLDX is the address as it was before break_out_memory_refs was called.
1836 In some cases it is useful to look at this to decide what needs to be done.
1837
1838 Normally it is always safe for this macro to do nothing. It exists to
1839 recognize opportunities to optimize the output.
1840
1841 But on a few ports with segmented architectures and indexed addressing
1842 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1843 rtx
1844 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1845 enum machine_mode mode ATTRIBUTE_UNUSED)
1846 {
1847 if (flag_pic && ! legitimate_pic_operand_p (x))
1848 x = legitimize_pic_address (oldx, NULL_RTX);
1849
1850 /* Uh-oh. We might have an address for x[n-100000]. This needs
1851 special handling to avoid creating an indexed memory address
1852 with x-100000 as the base. */
1853 if (GET_CODE (x) == PLUS
1854 && symbolic_operand (XEXP (x, 1), VOIDmode))
1855 {
1856 /* Ugly. We modify things here so that the address offset specified
1857 by the index expression is computed first, then added to x to form
1858 the entire address. */
1859
1860 rtx regx1, regy1, regy2, y;
1861
1862 /* Strip off any CONST. */
1863 y = XEXP (x, 1);
1864 if (GET_CODE (y) == CONST)
1865 y = XEXP (y, 0);
1866
1867 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1868 {
1869 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1870 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1871 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1872 regx1 = force_reg (Pmode,
1873 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2));
1874 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1875 }
1876 }
1877 return x;
1878 }
1879
1880 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1881 @GOTOFF in `reg'. */
1882 rtx
1883 legitimize_pic_address (rtx orig, rtx reg)
1884 {
1885 if (GET_CODE (orig) == LABEL_REF
1886 || (GET_CODE (orig) == SYMBOL_REF
1887 && (CONSTANT_POOL_ADDRESS_P (orig)
1888 || ! MN10300_GLOBAL_P (orig))))
1889 {
1890 if (reg == 0)
1891 reg = gen_reg_rtx (Pmode);
1892
1893 emit_insn (gen_symGOTOFF2reg (reg, orig));
1894 return reg;
1895 }
1896 else if (GET_CODE (orig) == SYMBOL_REF)
1897 {
1898 if (reg == 0)
1899 reg = gen_reg_rtx (Pmode);
1900
1901 emit_insn (gen_symGOT2reg (reg, orig));
1902 return reg;
1903 }
1904 return orig;
1905 }
1906
1907 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1908 isn't protected by a PIC unspec; nonzero otherwise. */
1909 int
1910 legitimate_pic_operand_p (rtx x)
1911 {
1912 register const char *fmt;
1913 register int i;
1914
1915 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1916 return 0;
1917
1918 if (GET_CODE (x) == UNSPEC
1919 && (XINT (x, 1) == UNSPEC_PIC
1920 || XINT (x, 1) == UNSPEC_GOT
1921 || XINT (x, 1) == UNSPEC_GOTOFF
1922 || XINT (x, 1) == UNSPEC_PLT
1923 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1924 return 1;
1925
1926 fmt = GET_RTX_FORMAT (GET_CODE (x));
1927 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1928 {
1929 if (fmt[i] == 'E')
1930 {
1931 register int j;
1932
1933 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1934 if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1935 return 0;
1936 }
1937 else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1938 return 0;
1939 }
1940
1941 return 1;
1942 }
1943
1944 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1945 legitimate, and FALSE otherwise.
1946
1947 On the mn10300, the value in the address register must be
1948 in the same memory space/segment as the effective address.
1949
1950 This is problematical for reload since it does not understand
1951 that base+index != index+base in a memory reference.
1952
1953 Note it is still possible to use reg+reg addressing modes,
1954 it's just much more difficult. For a discussion of a possible
1955 workaround and solution, see the comments in pa.c before the
1956 function record_unscaled_index_insn_codes. */
1957
1958 bool
1959 mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1960 {
1961 if (CONSTANT_ADDRESS_P (x)
1962 && (! flag_pic || legitimate_pic_operand_p (x)))
1963 return TRUE;
1964
1965 if (RTX_OK_FOR_BASE_P (x, strict))
1966 return TRUE;
1967
1968 if (TARGET_AM33
1969 && GET_CODE (x) == POST_INC
1970 && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1971 && (mode == SImode || mode == SFmode || mode == HImode))
1972 return TRUE;
1973
1974 if (GET_CODE (x) == PLUS)
1975 {
1976 rtx base = 0, index = 0;
1977
1978 if (REG_P (XEXP (x, 0))
1979 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict))
1980 {
1981 base = XEXP (x, 0);
1982 index = XEXP (x, 1);
1983 }
1984
1985 if (REG_P (XEXP (x, 1))
1986 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict))
1987 {
1988 base = XEXP (x, 1);
1989 index = XEXP (x, 0);
1990 }
1991
1992 if (base != 0 && index != 0)
1993 {
1994 if (GET_CODE (index) == CONST_INT)
1995 return TRUE;
1996 if (GET_CODE (index) == CONST
1997 && GET_CODE (XEXP (index, 0)) != PLUS
1998 && (! flag_pic
1999 || legitimate_pic_operand_p (index)))
2000 return TRUE;
2001 }
2002 }
2003
2004 return FALSE;
2005 }
2006
2007 static int
2008 mn10300_address_cost_1 (rtx x, int *unsig)
2009 {
2010 switch (GET_CODE (x))
2011 {
2012 case REG:
2013 switch (REGNO_REG_CLASS (REGNO (x)))
2014 {
2015 case SP_REGS:
2016 *unsig = 1;
2017 return 0;
2018
2019 case ADDRESS_REGS:
2020 return 1;
2021
2022 case DATA_REGS:
2023 case EXTENDED_REGS:
2024 case FP_REGS:
2025 return 3;
2026
2027 case NO_REGS:
2028 return 5;
2029
2030 default:
2031 gcc_unreachable ();
2032 }
2033
2034 case PLUS:
2035 case MINUS:
2036 case ASHIFT:
2037 case AND:
2038 case IOR:
2039 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
2040 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
2041
2042 case EXPR_LIST:
2043 case SUBREG:
2044 case MEM:
2045 return mn10300_address_cost (XEXP (x, 0), !optimize_size);
2046
2047 case ZERO_EXTEND:
2048 *unsig = 1;
2049 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
2050
2051 case CONST_INT:
2052 if (INTVAL (x) == 0)
2053 return 0;
2054 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
2055 return 1;
2056 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
2057 return 3;
2058 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
2059 return 5;
2060 return 7;
2061
2062 case CONST:
2063 case SYMBOL_REF:
2064 case LABEL_REF:
2065 return 8;
2066
2067 default:
2068 gcc_unreachable ();
2069
2070 }
2071 }
2072
2073 static int
2074 mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
2075 {
2076 int s = 0;
2077 return mn10300_address_cost_1 (x, &s);
2078 }
2079
2080 static bool
2081 mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED)
2082 {
2083 switch (code)
2084 {
2085 case CONST_INT:
2086 /* Zeros are extremely cheap. */
2087 if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
2088 *total = 0;
2089 /* If it fits in 8 bits, then it's still relatively cheap. */
2090 else if (INT_8_BITS (INTVAL (x)))
2091 *total = 1;
2092 /* This is the "base" cost, includes constants where either the
2093 upper or lower 16bits are all zeros. */
2094 else if (INT_16_BITS (INTVAL (x))
2095 || (INTVAL (x) & 0xffff) == 0
2096 || (INTVAL (x) & 0xffff0000) == 0)
2097 *total = 2;
2098 else
2099 *total = 4;
2100 return true;
2101
2102 case CONST:
2103 case LABEL_REF:
2104 case SYMBOL_REF:
2105 /* These are more costly than a CONST_INT, but we can relax them,
2106 so they're less costly than a CONST_DOUBLE. */
2107 *total = 6;
2108 return true;
2109
2110 case CONST_DOUBLE:
2111 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2112 so their cost is very high. */
2113 *total = 8;
2114 return true;
2115
2116 case ZERO_EXTRACT:
2117 /* This is cheap, we can use btst. */
2118 if (outer_code == COMPARE)
2119 *total = 0;
2120 return false;
2121
2122 /* ??? This probably needs more work. */
2123 case MOD:
2124 case DIV:
2125 case MULT:
2126 *total = 8;
2127 return true;
2128
2129 default:
2130 return false;
2131 }
2132 }
2133
2134 /* Check whether a constant used to initialize a DImode or DFmode can
2135 use a clr instruction. The code here must be kept in sync with
2136 movdf and movdi. */
2137
2138 bool
2139 mn10300_wide_const_load_uses_clr (rtx operands[2])
2140 {
2141 long val[2];
2142
2143 if (GET_CODE (operands[0]) != REG
2144 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2145 return false;
2146
2147 switch (GET_CODE (operands[1]))
2148 {
2149 case CONST_INT:
2150 {
2151 rtx low, high;
2152 split_double (operands[1], &low, &high);
2153 val[0] = INTVAL (low);
2154 val[1] = INTVAL (high);
2155 }
2156 break;
2157
2158 case CONST_DOUBLE:
2159 if (GET_MODE (operands[1]) == DFmode)
2160 {
2161 REAL_VALUE_TYPE rv;
2162
2163 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2164 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2165 }
2166 else if (GET_MODE (operands[1]) == VOIDmode
2167 || GET_MODE (operands[1]) == DImode)
2168 {
2169 val[0] = CONST_DOUBLE_LOW (operands[1]);
2170 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2171 }
2172 break;
2173
2174 default:
2175 return false;
2176 }
2177
2178 return val[0] == 0 || val[1] == 0;
2179 }
2180 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2181 may access it using GOTOFF instead of GOT. */
2182
2183 static void
2184 mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2185 {
2186 rtx symbol;
2187
2188 if (GET_CODE (rtl) != MEM)
2189 return;
2190 symbol = XEXP (rtl, 0);
2191 if (GET_CODE (symbol) != SYMBOL_REF)
2192 return;
2193
2194 if (flag_pic)
2195 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2196 }
2197
2198 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2199 and readonly data size. So we crank up the case threshold value to
2200 encourage a series of if/else comparisons to implement many small switch
2201 statements. In theory, this value could be increased much more if we
2202 were solely optimizing for space, but we keep it "reasonable" to avoid
2203 serious code efficiency lossage. */
2204
2205 unsigned int mn10300_case_values_threshold (void)
2206 {
2207 return 6;
2208 }
2209
2210 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */
2211
2212 static void
2213 mn10300_asm_trampoline_template (FILE *f)
2214 {
2215 fprintf (f, "\tadd -4,sp\n");
2216 fprintf (f, "\t.long 0x0004fffa\n");
2217 fprintf (f, "\tmov (0,sp),a0\n");
2218 fprintf (f, "\tadd 4,sp\n");
2219 fprintf (f, "\tmov (13,a0),a1\n");
2220 fprintf (f, "\tmov (17,a0),a0\n");
2221 fprintf (f, "\tjmp (a0)\n");
2222 fprintf (f, "\t.long 0\n");
2223 fprintf (f, "\t.long 0\n");
2224 }
2225
2226 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2227
2228 static void
2229 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2230 {
2231 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2232 rtx mem;
2233
2234 emit_block_move (m_tramp, assemble_trampoline_template (),
2235 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2236
2237 mem = adjust_address (m_tramp, SImode, 0x14);
2238 emit_move_insn (mem, chain_value);
2239 mem = adjust_address (m_tramp, SImode, 0x18);
2240 emit_move_insn (mem, fnaddr);
2241 }
2242
2243 /* Output the assembler code for a C++ thunk function.
2244 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2245 is the decl for the target function. DELTA is an immediate constant
2246 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2247 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2248 additionally added to THIS. Finally jump to the entry point of
2249 FUNCTION. */
2250
2251 static void
2252 mn10300_asm_output_mi_thunk (FILE * file,
2253 tree thunk_fndecl ATTRIBUTE_UNUSED,
2254 HOST_WIDE_INT delta,
2255 HOST_WIDE_INT vcall_offset,
2256 tree function)
2257 {
2258 const char * _this;
2259
2260 /* Get the register holding the THIS parameter. Handle the case
2261 where there is a hidden first argument for a returned structure. */
2262 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2263 _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2264 else
2265 _this = reg_names [FIRST_ARGUMENT_REGNUM];
2266
2267 fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2268
2269 if (delta)
2270 fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2271
2272 if (vcall_offset)
2273 {
2274 const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2275
2276 fprintf (file, "\tmov %s, %s\n", _this, scratch);
2277 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2278 fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2279 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2280 fprintf (file, "\tadd %s, %s\n", scratch, _this);
2281 }
2282
2283 fputs ("\tjmp ", file);
2284 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2285 putc ('\n', file);
2286 }
2287
2288 /* Return true if mn10300_output_mi_thunk would be able to output the
2289 assembler code for the thunk function specified by the arguments
2290 it is passed, and false otherwise. */
2291
2292 static bool
2293 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
2294 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
2295 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2296 const_tree function ATTRIBUTE_UNUSED)
2297 {
2298 return true;
2299 }
GCC graphite test results