1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
43 #include "c-family/c-pragma.h" /* ??? */
47 #include "target-def.h"
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
52 A constant operand of some sort.
58 A memory reference with a constant address.
61 A memory reference with a register as its address.
64 Some other kind of memory reference. */
65 enum h8300_operand_class
75 /* For a general two-operand instruction, element [X][Y] gives
76 the length of the opcode fields when the first operand has class
77 (X + 1) and the second has class Y. */
78 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
80 /* Forward declarations. */
81 static const char *byte_reg (rtx
, int);
82 static int h8300_interrupt_function_p (tree
);
83 static int h8300_saveall_function_p (tree
);
84 static int h8300_monitor_function_p (tree
);
85 static int h8300_os_task_function_p (tree
);
86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
87 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
88 static unsigned int compute_saved_regs (void);
89 static void push (int);
90 static void pop (int);
91 static const char *cond_string (enum rtx_code
);
92 static unsigned int h8300_asm_insn_count (const char *);
93 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
94 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
95 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree
);
99 static int h8300_and_costs (rtx
);
100 static int h8300_shift_costs (rtx
);
101 static void h8300_push_pop (int, int, bool, bool);
102 static int h8300_stack_offset_p (rtx
, int);
103 static int h8300_ldm_stm_regno (rtx
, int, int, int);
104 static void h8300_reorg (void);
105 static unsigned int h8300_constant_length (rtx
);
106 static unsigned int h8300_displacement_length (rtx
, int);
107 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
108 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
109 static unsigned int h8300_unary_length (rtx
);
110 static unsigned int h8300_short_immediate_length (rtx
);
111 static unsigned int h8300_bitfield_length (rtx
, rtx
);
112 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
113 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
114 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
115 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 /* CPU_TYPE, says what cpu we're compiling for. */
120 /* True if a #pragma interrupt has been seen for the current function. */
121 static int pragma_interrupt
;
123 /* True if a #pragma saveall has been seen for the current function. */
124 static int pragma_saveall
;
126 static const char *const names_big
[] =
127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
129 static const char *const names_extended
[] =
130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
132 static const char *const names_upper_extended
[] =
133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
135 /* Points to one of the above. */
136 /* ??? The above could be put in an array indexed by CPU_TYPE. */
137 const char * const *h8_reg_names
;
139 /* Various operations needed by the following, indexed by CPU_TYPE. */
141 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
143 /* Value of MOVE_RATIO. */
144 int h8300_move_ratio
;
146 /* See below where shifts are handled for explanation of this enum. */
156 /* Symbols of the various shifts which can be used as indices. */
160 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
163 /* Macros to keep the shift algorithm tables small. */
164 #define INL SHIFT_INLINE
165 #define ROT SHIFT_ROT_AND
166 #define LOP SHIFT_LOOP
167 #define SPC SHIFT_SPECIAL
169 /* The shift algorithms for each machine, mode, shift type, and shift
170 count are defined below. The three tables below correspond to
171 QImode, HImode, and SImode, respectively. Each table is organized
172 by, in the order of indices, machine, shift type, and shift count. */
174 static enum shift_alg shift_alg_qi
[3][3][8] = {
177 /* 0 1 2 3 4 5 6 7 */
178 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
179 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
180 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
186 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
187 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
193 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
194 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
198 static enum shift_alg shift_alg_hi
[3][3][16] = {
201 /* 0 1 2 3 4 5 6 7 */
202 /* 8 9 10 11 12 13 14 15 */
203 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
204 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
205 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
206 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
207 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
208 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
216 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
218 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 static enum shift_alg shift_alg_si
[3][3][32] = {
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 /* 16 17 18 19 20 21 22 23 */
240 /* 24 25 26 27 28 29 30 31 */
241 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
242 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
243 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
244 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
245 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
246 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
247 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
248 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
249 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
251 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
252 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
256 /* 0 1 2 3 4 5 6 7 */
257 /* 8 9 10 11 12 13 14 15 */
258 /* 16 17 18 19 20 21 22 23 */
259 /* 24 25 26 27 28 29 30 31 */
260 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
262 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
263 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
264 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
265 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
266 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
267 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
268 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
270 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
271 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
275 /* 0 1 2 3 4 5 6 7 */
276 /* 8 9 10 11 12 13 14 15 */
277 /* 16 17 18 19 20 21 22 23 */
278 /* 24 25 26 27 28 29 30 31 */
279 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
280 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
281 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
282 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
283 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
284 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
285 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
286 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
287 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
288 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
289 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
290 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
306 /* Implement TARGET_OPTION_OPTIMIZATION. */
309 h8300_option_optimization (int level ATTRIBUTE_UNUSED
,
310 int size ATTRIBUTE_UNUSED
)
312 /* Basic block reordering is only beneficial on targets with cache
313 and/or variable-cycle branches where (cycle count taken != cycle
315 flag_reorder_blocks
= 0;
318 /* Initialize various cpu specific globals at start up. */
321 h8300_option_override (void)
323 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
324 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
325 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
329 cpu_type
= (int) CPU_H8300
;
330 h8_reg_names
= names_big
;
334 /* For this we treat the H8/300H and H8S the same. */
335 cpu_type
= (int) CPU_H8300H
;
336 h8_reg_names
= names_extended
;
338 h8_push_op
= h8_push_ops
[cpu_type
];
339 h8_pop_op
= h8_pop_ops
[cpu_type
];
340 h8_mov_op
= h8_mov_ops
[cpu_type
];
342 if (!TARGET_H8300S
&& TARGET_MAC
)
344 error ("-ms2600 is used without -ms");
345 target_flags
|= MASK_H8300S_1
;
348 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
350 error ("-mn is used without -mh or -ms");
351 target_flags
^= MASK_NORMAL_MODE
;
354 /* Some of the shifts are optimized for speed by default.
355 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
356 If optimizing for size, change shift_alg for those shift to
361 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
362 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
363 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
364 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
366 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
367 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
369 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
370 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
373 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
374 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
376 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
377 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
379 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
380 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
381 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
382 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
385 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
388 /* Work out a value for MOVE_RATIO. */
391 /* Memory-memory moves are quite expensive without the
392 h8sx instructions. */
393 h8300_move_ratio
= 3;
395 else if (flag_omit_frame_pointer
)
397 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
398 sometimes be as short as two individual memory-to-memory moves,
399 but since they use all the call-saved registers, it seems better
400 to allow up to three moves here. */
401 h8300_move_ratio
= 4;
403 else if (optimize_size
)
405 /* In this case we don't use movmd sequences since they tend
406 to be longer than calls to memcpy(). Memory-to-memory
407 moves are cheaper than for !TARGET_H8300SX, so it makes
408 sense to have a slightly higher threshold. */
409 h8300_move_ratio
= 4;
413 /* We use movmd sequences for some moves since it can be quicker
414 than calling memcpy(). The sequences will need to save and
415 restore er6 though, so bump up the cost. */
416 h8300_move_ratio
= 6;
419 /* This target defaults to strict volatile bitfields. */
420 if (flag_strict_volatile_bitfields
< 0)
421 flag_strict_volatile_bitfields
= 1;
424 /* Implement REG_CLASS_FROM_LETTER.
426 Some patterns need to use er6 as a scratch register. This is
427 difficult to arrange since er6 is the frame pointer and usually
430 Such patterns should define two alternatives, one which allows only
431 er6 and one which allows any general register. The former alternative
432 should have a 'd' constraint while the latter should be disparaged and
435 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
436 However, there are cases where they should be NO_REGS:
438 - 'd' should be NO_REGS when reloading a function that uses the
439 frame pointer. In this case, DESTINATION_REGS won't contain any
440 spillable registers, so the first alternative can't be used.
442 - -fno-omit-frame-pointer means that the frame pointer will
443 always be in use. It's therefore better to map 'd' to NO_REGS
444 before reload so that register allocator will pick the second
447 - we would like 'D' to be be NO_REGS when the frame pointer isn't
448 live, but we the frame pointer may turn out to be needed after
449 we start reload, and then we may have already decided we don't
450 have a choice, so we can't do that. Forcing the register
451 allocator to use er6 if possible might produce better code for
452 small functions: it's more efficient to save and restore er6 in
453 the prologue & epilogue than to do it in a define_split.
454 Hopefully disparaging 'D' will have a similar effect, without
455 forcing a reload failure if the frame pointer is found to be
459 h8300_reg_class_from_letter (int c
)
470 if (!flag_omit_frame_pointer
&& !reload_completed
)
472 if (frame_pointer_needed
&& reload_in_progress
)
474 return DESTINATION_REGS
;
477 /* The meaning of a constraint shouldn't change dynamically, so
478 we can't make this NO_REGS. */
489 /* Return the byte register name for a register rtx X. B should be 0
490 if you want a lower byte register. B should be 1 if you want an
491 upper byte register. */
494 byte_reg (rtx x
, int b
)
496 static const char *const names_small
[] = {
497 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
498 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
501 gcc_assert (REG_P (x
));
503 return names_small
[REGNO (x
) * 2 + b
];
506 /* REGNO must be saved/restored across calls if this macro is true. */
508 #define WORD_REG_USED(regno) \
510 /* No need to save registers if this function will not return. */ \
511 && ! TREE_THIS_VOLATILE (current_function_decl) \
512 && (h8300_saveall_function_p (current_function_decl) \
513 /* Save any call saved register that was used. */ \
514 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
515 /* Save the frame pointer if it was used. */ \
516 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
517 /* Save any register used in an interrupt handler. */ \
518 || (h8300_current_function_interrupt_function_p () \
519 && df_regs_ever_live_p (regno)) \
520 /* Save call clobbered registers in non-leaf interrupt \
522 || (h8300_current_function_interrupt_function_p () \
523 && call_used_regs[regno] \
524 && !current_function_is_leaf)))
526 /* We use this to wrap all emitted insns in the prologue. */
528 F (rtx x
, bool set_it
)
531 RTX_FRAME_RELATED_P (x
) = 1;
535 /* Mark all the subexpressions of the PARALLEL rtx PAR as
536 frame-related. Return PAR.
538 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
539 PARALLEL rtx other than the first if they do not have the
540 FRAME_RELATED flag set on them. */
544 int len
= XVECLEN (par
, 0);
547 for (i
= 0; i
< len
; i
++)
548 F (XVECEXP (par
, 0, i
), true);
553 /* Output assembly language to FILE for the operation OP with operand size
554 SIZE to adjust the stack pointer. */
557 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
559 /* If the frame size is 0, we don't have anything to do. */
563 /* H8/300 cannot add/subtract a large constant with a single
564 instruction. If a temporary register is available, load the
565 constant to it and then do the addition. */
568 && !h8300_current_function_interrupt_function_p ()
569 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
571 rtx r3
= gen_rtx_REG (Pmode
, 3);
572 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
573 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
574 stack_pointer_rtx
, r3
)), in_prologue
);
578 /* The stack adjustment made here is further optimized by the
579 splitter. In case of H8/300, the splitter always splits the
580 addition emitted here to make the adjustment interrupt-safe.
581 FIXME: We don't always tag those, because we don't know what
582 the splitter will do. */
585 rtx x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
586 stack_pointer_rtx
, GEN_INT (sign
* size
)));
591 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
592 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
596 /* Round up frame size SIZE. */
599 round_frame_size (HOST_WIDE_INT size
)
601 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
602 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
605 /* Compute which registers to push/pop.
606 Return a bit vector of registers. */
609 compute_saved_regs (void)
611 unsigned int saved_regs
= 0;
614 /* Construct a bit vector of registers to be pushed/popped. */
615 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
617 if (WORD_REG_USED (regno
))
618 saved_regs
|= 1 << regno
;
621 /* Don't push/pop the frame pointer as it is treated separately. */
622 if (frame_pointer_needed
)
623 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
628 /* Emit an insn to push register RN. */
633 rtx reg
= gen_rtx_REG (word_mode
, rn
);
637 x
= gen_push_h8300 (reg
);
638 else if (!TARGET_NORMAL_MODE
)
639 x
= gen_push_h8300hs_advanced (reg
);
641 x
= gen_push_h8300hs_normal (reg
);
642 x
= F (emit_insn (x
), true);
643 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
646 /* Emit an insn to pop register RN. */
651 rtx reg
= gen_rtx_REG (word_mode
, rn
);
655 x
= gen_pop_h8300 (reg
);
656 else if (!TARGET_NORMAL_MODE
)
657 x
= gen_pop_h8300hs_advanced (reg
);
659 x
= gen_pop_h8300hs_normal (reg
);
661 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
664 /* Emit an instruction to push or pop NREGS consecutive registers
665 starting at register REGNO. POP_P selects a pop rather than a
666 push and RETURN_P is true if the instruction should return.
668 It must be possible to do the requested operation in a single
669 instruction. If NREGS == 1 && !RETURN_P, use a normal push
670 or pop insn. Otherwise emit a parallel of the form:
673 [(return) ;; if RETURN_P
674 (save or restore REGNO)
675 (save or restore REGNO + 1)
677 (save or restore REGNO + NREGS - 1)
678 (set sp (plus sp (const_int adjust)))] */
681 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
687 /* See whether we can use a simple push or pop. */
688 if (!return_p
&& nregs
== 1)
697 /* We need one element for the return insn, if present, one for each
698 register, and one for stack adjustment. */
699 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
700 sp
= stack_pointer_rtx
;
703 /* Add the return instruction. */
706 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
710 /* Add the register moves. */
711 for (j
= 0; j
< nregs
; j
++)
717 /* Register REGNO + NREGS - 1 is popped first. Before the
718 stack adjustment, its slot is at address @sp. */
719 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
720 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
724 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
725 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
726 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
728 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
731 /* Add the stack adjustment. */
732 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
733 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
734 gen_rtx_PLUS (Pmode
, sp
, offset
));
736 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
746 /* Return true if X has the value sp + OFFSET. */
749 h8300_stack_offset_p (rtx x
, int offset
)
752 return x
== stack_pointer_rtx
;
754 return (GET_CODE (x
) == PLUS
755 && XEXP (x
, 0) == stack_pointer_rtx
756 && GET_CODE (XEXP (x
, 1)) == CONST_INT
757 && INTVAL (XEXP (x
, 1)) == offset
);
760 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
761 something that may be an ldm or stm instruction. If it fits
762 the required template, return the register it loads or stores,
765 LOAD_P is true if X should be a load, false if it should be a store.
766 NREGS is the number of registers that the whole instruction is expected
767 to load or store. INDEX is the index of the register that X should
768 load or store, relative to the lowest-numbered register. */
771 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
773 int regindex
, memindex
, offset
;
776 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
778 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
780 if (GET_CODE (x
) == SET
781 && GET_CODE (XEXP (x
, regindex
)) == REG
782 && GET_CODE (XEXP (x
, memindex
)) == MEM
783 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
784 return REGNO (XEXP (x
, regindex
));
789 /* Return true if the elements of VEC starting at FIRST describe an
790 ldm or stm instruction (LOAD_P says which). */
793 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
796 int nregs
, i
, regno
, adjust
;
798 /* There must be a stack adjustment, a register move, and at least one
799 other operation (a return or another register move). */
800 if (GET_NUM_ELEM (vec
) < 3)
803 /* Get the range of registers to be pushed or popped. */
804 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
805 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
807 /* Check that the call to h8300_ldm_stm_regno succeeded and
808 that we're only dealing with GPRs. */
809 if (regno
< 0 || regno
+ nregs
> 8)
812 /* 2-register h8s instructions must start with an even-numbered register.
813 3- and 4-register instructions must start with er0 or er4. */
816 if ((regno
& 1) != 0)
818 if (nregs
> 2 && (regno
& 3) != 0)
822 /* Check the other loads or stores. */
823 for (i
= 1; i
< nregs
; i
++)
824 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
828 /* Check the stack adjustment. */
829 last
= RTVEC_ELT (vec
, first
+ nregs
);
830 adjust
= (load_p
? nregs
: -nregs
) * 4;
831 return (GET_CODE (last
) == SET
832 && SET_DEST (last
) == stack_pointer_rtx
833 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
836 /* This is what the stack looks like after the prolog of
837 a function with a frame has been set up:
843 <saved registers> <- sp
845 This is what the stack looks like after the prolog of
846 a function which doesn't have a frame:
851 <saved registers> <- sp
854 /* Generate RTL code for the function prologue. */
857 h8300_expand_prologue (void)
863 /* If the current function has the OS_Task attribute set, then
864 we have a naked prologue. */
865 if (h8300_os_task_function_p (current_function_decl
))
868 if (h8300_monitor_function_p (current_function_decl
))
869 /* My understanding of monitor functions is they act just like
870 interrupt functions, except the prologue must mask
872 emit_insn (gen_monitor_prologue ());
874 if (frame_pointer_needed
)
877 push (HARD_FRAME_POINTER_REGNUM
);
878 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
881 /* Push the rest of the registers in ascending order. */
882 saved_regs
= compute_saved_regs ();
883 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
886 if (saved_regs
& (1 << regno
))
890 /* See how many registers we can push at the same time. */
891 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
892 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
895 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
896 && ((saved_regs
>> regno
) & 0x07) == 0x07)
899 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
900 && ((saved_regs
>> regno
) & 0x03) == 0x03)
904 h8300_push_pop (regno
, n_regs
, false, false);
908 /* Leave room for locals. */
909 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
912 /* Return nonzero if we can use "rts" for the function currently being
916 h8300_can_use_return_insn_p (void)
918 return (reload_completed
919 && !frame_pointer_needed
920 && get_frame_size () == 0
921 && compute_saved_regs () == 0);
924 /* Generate RTL code for the function epilogue. */
927 h8300_expand_epilogue (void)
932 HOST_WIDE_INT frame_size
;
935 if (h8300_os_task_function_p (current_function_decl
))
936 /* OS_Task epilogues are nearly naked -- they just have an
940 frame_size
= round_frame_size (get_frame_size ());
943 /* Deallocate locals. */
944 h8300_emit_stack_adjustment (1, frame_size
, false);
946 /* Pop the saved registers in descending order. */
947 saved_regs
= compute_saved_regs ();
948 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
951 if (saved_regs
& (1 << regno
))
955 /* See how many registers we can pop at the same time. */
956 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
957 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
960 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
961 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
964 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
965 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
969 /* See if this pop would be the last insn before the return.
970 If so, use rte/l or rts/l instead of pop or ldm.l. */
972 && !frame_pointer_needed
974 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
977 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
981 /* Pop frame pointer if we had one. */
982 if (frame_pointer_needed
)
986 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
990 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
993 /* Return nonzero if the current function is an interrupt
997 h8300_current_function_interrupt_function_p (void)
999 return (h8300_interrupt_function_p (current_function_decl
)
1000 || h8300_monitor_function_p (current_function_decl
));
1003 /* Output assembly code for the start of the file. */
1006 h8300_file_start (void)
1008 default_file_start ();
1011 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1012 else if (TARGET_H8300SX
)
1013 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1014 else if (TARGET_H8300S
)
1015 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1018 /* Output assembly language code for the end of file. */
1021 h8300_file_end (void)
1023 fputs ("\t.end\n", asm_out_file
);
1026 /* Split an add of a small constant into two adds/subs insns.
1028 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1029 instead of adds/subs. */
1032 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
1034 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1035 rtx reg
= operands
[0];
1036 HOST_WIDE_INT sign
= 1;
1037 HOST_WIDE_INT amount
;
1038 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1040 /* Force VAL to be positive so that we do not have to consider the
1051 gen_add
= gen_addhi3
;
1055 gen_add
= gen_addsi3
;
1062 /* Try different amounts in descending order. */
1063 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1067 for (; val
>= amount
; val
-= amount
)
1068 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1074 /* Handle machine specific pragmas for compatibility with existing
1075 compilers for the H8/300.
1077 pragma saveall generates prologue/epilogue code which saves and
1078 restores all the registers on function entry.
1080 pragma interrupt saves and restores all registers, and exits with
1081 an rte instruction rather than an rts. A pointer to a function
1082 with this attribute may be safely used in an interrupt vector. */
1085 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1087 pragma_interrupt
= 1;
1091 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1096 /* If the next function argument with MODE and TYPE is to be passed in
1097 a register, return a reg RTX for the hard register in which to pass
1098 the argument. CUM represents the state after the last argument.
1099 If the argument is to be pushed, NULL_RTX is returned. */
1102 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1103 tree type
, int named
)
1105 static const char *const hand_list
[] = {
1124 rtx result
= NULL_RTX
;
1128 /* Never pass unnamed arguments in registers. */
1132 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1133 if (TARGET_QUICKCALL
)
1136 /* If calling hand written assembler, use 4 regs of args. */
1139 const char * const *p
;
1141 fname
= XSTR (cum
->libcall
, 0);
1143 /* See if this libcall is one of the hand coded ones. */
1144 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1155 if (mode
== BLKmode
)
1156 size
= int_size_in_bytes (type
);
1158 size
= GET_MODE_SIZE (mode
);
1160 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1161 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1162 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1168 /* Compute the cost of an and insn. */
1171 h8300_and_costs (rtx x
)
1175 if (GET_MODE (x
) == QImode
)
1178 if (GET_MODE (x
) != HImode
1179 && GET_MODE (x
) != SImode
)
1183 operands
[1] = XEXP (x
, 0);
1184 operands
[2] = XEXP (x
, 1);
1186 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1189 /* Compute the cost of a shift insn. */
1192 h8300_shift_costs (rtx x
)
1196 if (GET_MODE (x
) != QImode
1197 && GET_MODE (x
) != HImode
1198 && GET_MODE (x
) != SImode
)
1203 operands
[2] = XEXP (x
, 1);
1205 return compute_a_shift_length (NULL
, operands
) / 2;
1208 /* Worker function for TARGET_RTX_COSTS. */
1211 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
1213 if (TARGET_H8300SX
&& outer_code
== MEM
)
1215 /* Estimate the number of execution states needed to calculate
1217 if (register_operand (x
, VOIDmode
)
1218 || GET_CODE (x
) == POST_INC
1219 || GET_CODE (x
) == POST_DEC
1223 *total
= COSTS_N_INSNS (1);
1231 HOST_WIDE_INT n
= INTVAL (x
);
1235 /* Constant operands need the same number of processor
1236 states as register operands. Although we could try to
1237 use a size-based cost for !speed, the lack of
1238 of a mode makes the results very unpredictable. */
1242 if (-4 <= n
|| n
<= 4)
1253 *total
= 0 + (outer_code
== SET
);
1257 if (TARGET_H8300H
|| TARGET_H8300S
)
1258 *total
= 0 + (outer_code
== SET
);
1273 /* See comment for CONST_INT. */
1285 if (XEXP (x
, 1) == const0_rtx
)
1290 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1291 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1293 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1296 /* We say that MOD and DIV are so expensive because otherwise we'll
1297 generate some really horrible code for division of a power of two. */
1303 switch (GET_MODE (x
))
1307 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1311 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1317 *total
= COSTS_N_INSNS (12);
1322 switch (GET_MODE (x
))
1326 *total
= COSTS_N_INSNS (2);
1330 *total
= COSTS_N_INSNS (5);
1336 *total
= COSTS_N_INSNS (4);
1342 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1344 *total
= COSTS_N_INSNS (2);
1347 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1349 *total
= COSTS_N_INSNS (1);
1352 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1357 if (GET_MODE (x
) == HImode
)
1364 *total
= COSTS_N_INSNS (1);
1369 /* Documentation for the machine specific operand escapes:
1371 'E' like s but negative.
1372 'F' like t but negative.
1373 'G' constant just the negative
1374 'R' print operand as a byte:8 address if appropriate, else fall back to
1376 'S' print operand as a long word
1377 'T' print operand as a word
1378 'V' find the set bit, and print its number.
1379 'W' find the clear bit, and print its number.
1380 'X' print operand as a byte
1381 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1382 If this operand isn't a register, fall back to 'R' handling.
1384 'c' print the opcode corresponding to rtl
1385 'e' first word of 32-bit value - if reg, then least reg. if mem
1386 then least. if const then most sig word
1387 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1388 then +2. if const then least sig word
1389 'j' print operand as condition code.
1390 'k' print operand as reverse condition code.
1391 'm' convert an integer operand to a size suffix (.b, .w or .l)
1392 'o' print an integer without a leading '#'
1393 's' print as low byte of 16-bit value
1394 't' print as high byte of 16-bit value
1395 'w' print as low byte of 32-bit value
1396 'x' print as 2nd byte of 32-bit value
1397 'y' print as 3rd byte of 32-bit value
1398 'z' print as msb of 32-bit value
1401 /* Return assembly language string which identifies a comparison type. */
1404 cond_string (enum rtx_code code
)
1433 /* Print operand X using operand code CODE to assembly language output file
1437 print_operand (FILE *file
, rtx x
, int code
)
1439 /* This is used for communication between codes V,W,Z and Y. */
1445 switch (GET_CODE (x
))
1448 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1451 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1458 switch (GET_CODE (x
))
1461 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1464 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1471 gcc_assert (GET_CODE (x
) == CONST_INT
);
1472 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1475 if (GET_CODE (x
) == REG
)
1476 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1481 if (GET_CODE (x
) == REG
)
1482 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1487 bitint
= (INTVAL (x
) & 0xffff);
1488 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1489 bitint
= exact_log2 (bitint
& 0xff);
1491 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1492 gcc_assert (bitint
>= 0);
1493 fprintf (file
, "#%d", bitint
);
1496 bitint
= ((~INTVAL (x
)) & 0xffff);
1497 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1498 bitint
= exact_log2 (bitint
& 0xff);
1500 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1501 gcc_assert (bitint
>= 0);
1502 fprintf (file
, "#%d", bitint
);
1506 if (GET_CODE (x
) == REG
)
1507 fprintf (file
, "%s", byte_reg (x
, 0));
1512 gcc_assert (bitint
>= 0);
1513 if (GET_CODE (x
) == REG
)
1514 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1516 print_operand (file
, x
, 'R');
1520 bitint
= INTVAL (x
);
1521 fprintf (file
, "#%d", bitint
& 7);
1524 switch (GET_CODE (x
))
1527 fprintf (file
, "or");
1530 fprintf (file
, "xor");
1533 fprintf (file
, "and");
1540 switch (GET_CODE (x
))
1544 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1546 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1549 print_operand (file
, x
, 0);
1552 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1558 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1559 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1560 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1569 switch (GET_CODE (x
))
1573 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1575 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1578 x
= adjust_address (x
, HImode
, 2);
1579 print_operand (file
, x
, 0);
1582 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1588 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1589 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1590 fprintf (file
, "#%ld", (val
& 0xffff));
1598 fputs (cond_string (GET_CODE (x
)), file
);
1601 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1604 gcc_assert (GET_CODE (x
) == CONST_INT
);
1624 print_operand_address (file
, x
);
1627 if (GET_CODE (x
) == CONST_INT
)
1628 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1630 fprintf (file
, "%s", byte_reg (x
, 0));
1633 if (GET_CODE (x
) == CONST_INT
)
1634 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1636 fprintf (file
, "%s", byte_reg (x
, 1));
1639 if (GET_CODE (x
) == CONST_INT
)
1640 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1642 fprintf (file
, "%s",
1643 byte_reg (x
, TARGET_H8300
? 2 : 0));
1646 if (GET_CODE (x
) == CONST_INT
)
1647 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1649 fprintf (file
, "%s",
1650 byte_reg (x
, TARGET_H8300
? 3 : 1));
1653 if (GET_CODE (x
) == CONST_INT
)
1654 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1656 fprintf (file
, "%s", byte_reg (x
, 0));
1659 if (GET_CODE (x
) == CONST_INT
)
1660 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1662 fprintf (file
, "%s", byte_reg (x
, 1));
1667 switch (GET_CODE (x
))
1670 switch (GET_MODE (x
))
1673 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1674 fprintf (file
, "%s", byte_reg (x
, 0));
1675 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1676 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1680 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1684 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1693 rtx addr
= XEXP (x
, 0);
1695 fprintf (file
, "@");
1696 output_address (addr
);
1698 /* Add a length suffix to constant addresses. Although this
1699 is often unnecessary, it helps to avoid ambiguity in the
1700 syntax of mova. If we wrote an insn like:
1702 mova/w.l @(1,@foo.b),er0
1704 then .b would be considered part of the symbol name.
1705 Adding a length after foo will avoid this. */
1706 if (CONSTANT_P (addr
))
1710 /* Used for mov.b and bit operations. */
1711 if (h8300_eightbit_constant_address_p (addr
))
1713 fprintf (file
, ":8");
1717 /* Fall through. We should not get here if we are
1718 processing bit operations on H8/300 or H8/300H
1719 because 'U' constraint does not allow bit
1720 operations on the tiny area on these machines. */
1725 if (h8300_constant_length (addr
) == 2)
1726 fprintf (file
, ":16");
1728 fprintf (file
, ":32");
1740 fprintf (file
, "#");
1741 print_operand_address (file
, x
);
1747 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1748 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1749 fprintf (file
, "#%ld", val
);
1758 /* Output assembly language output for the address ADDR to FILE. */
1761 print_operand_address (FILE *file
, rtx addr
)
1766 switch (GET_CODE (addr
))
1769 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1773 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1777 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1781 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1785 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1789 fprintf (file
, "(");
1791 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1792 if (GET_CODE (index
) == REG
)
1795 print_operand_address (file
, XEXP (addr
, 1));
1796 fprintf (file
, ",");
1800 print_operand_address (file
, index
);
1804 print_operand (file
, index
, 'X');
1809 print_operand (file
, index
, 'T');
1814 print_operand (file
, index
, 'S');
1818 /* print_operand_address (file, XEXP (addr, 0)); */
1823 print_operand_address (file
, XEXP (addr
, 0));
1824 fprintf (file
, "+");
1825 print_operand_address (file
, XEXP (addr
, 1));
1827 fprintf (file
, ")");
1832 /* Since the H8/300 only has 16-bit pointers, negative values are also
1833 those >= 32768. This happens for example with pointer minus a
1834 constant. We don't want to turn (char *p - 2) into
1835 (char *p + 65534) because loop unrolling can build upon this
1836 (IE: char *p + 131068). */
1837 int n
= INTVAL (addr
);
1839 n
= (int) (short) n
;
1840 fprintf (file
, "%d", n
);
1845 output_addr_const (file
, addr
);
1850 /* Output all insn addresses and their sizes into the assembly language
1851 output file. This is helpful for debugging whether the length attributes
1852 in the md file are correct. This is not meant to be a user selectable
1856 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1857 int num_operands ATTRIBUTE_UNUSED
)
1859 /* This holds the last insn address. */
1860 static int last_insn_address
= 0;
1862 const int uid
= INSN_UID (insn
);
1864 if (TARGET_ADDRESSES
)
1866 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1867 INSN_ADDRESSES (uid
) - last_insn_address
);
1868 last_insn_address
= INSN_ADDRESSES (uid
);
1872 /* Prepare for an SI sized move. */
1875 h8300_expand_movsi (rtx operands
[])
1877 rtx src
= operands
[1];
1878 rtx dst
= operands
[0];
1879 if (!reload_in_progress
&& !reload_completed
)
1881 if (!register_operand (dst
, GET_MODE (dst
)))
1883 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1884 emit_move_insn (tmp
, src
);
1891 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1892 Frame pointer elimination is automatically handled.
1894 For the h8300, if frame pointer elimination is being done, we would like to
1895 convert ap and rp into sp, not fp.
1897 All other eliminations are valid. */
1900 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1902 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1905 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1906 Define the offset between two registers, one to be eliminated, and
1907 the other its replacement, at the start of a routine. */
1910 h8300_initial_elimination_offset (int from
, int to
)
1912 /* The number of bytes that the return address takes on the stack. */
1913 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1915 /* The number of bytes that the saved frame pointer takes on the stack. */
1916 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1918 /* The number of bytes that the saved registers, excluding the frame
1919 pointer, take on the stack. */
1920 int saved_regs_size
= 0;
1922 /* The number of bytes that the locals takes on the stack. */
1923 int frame_size
= round_frame_size (get_frame_size ());
1927 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1928 if (WORD_REG_USED (regno
))
1929 saved_regs_size
+= UNITS_PER_WORD
;
1931 /* Adjust saved_regs_size because the above loop took the frame
1932 pointer int account. */
1933 saved_regs_size
-= fp_size
;
1937 case HARD_FRAME_POINTER_REGNUM
:
1940 case ARG_POINTER_REGNUM
:
1941 return pc_size
+ fp_size
;
1942 case RETURN_ADDRESS_POINTER_REGNUM
:
1944 case FRAME_POINTER_REGNUM
:
1945 return -saved_regs_size
;
1950 case STACK_POINTER_REGNUM
:
1953 case ARG_POINTER_REGNUM
:
1954 return pc_size
+ saved_regs_size
+ frame_size
;
1955 case RETURN_ADDRESS_POINTER_REGNUM
:
1956 return saved_regs_size
+ frame_size
;
1957 case FRAME_POINTER_REGNUM
:
1969 /* Worker function for RETURN_ADDR_RTX. */
1972 h8300_return_addr_rtx (int count
, rtx frame
)
1977 ret
= gen_rtx_MEM (Pmode
,
1978 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1979 else if (flag_omit_frame_pointer
)
1982 ret
= gen_rtx_MEM (Pmode
,
1983 memory_address (Pmode
,
1984 plus_constant (frame
, UNITS_PER_WORD
)));
1985 set_mem_alias_set (ret
, get_frame_alias_set ());
1989 /* Update the condition code from the insn. */
1992 notice_update_cc (rtx body
, rtx insn
)
1996 switch (get_attr_cc (insn
))
1999 /* Insn does not affect CC at all. */
2003 /* Insn does not change CC, but the 0'th operand has been changed. */
2004 if (cc_status
.value1
!= 0
2005 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2006 cc_status
.value1
= 0;
2007 if (cc_status
.value2
!= 0
2008 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2009 cc_status
.value2
= 0;
2013 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2014 The V flag is unusable. The C flag may or may not be known but
2015 that's ok because alter_cond will change tests to use EQ/NE. */
2017 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2018 set
= single_set (insn
);
2019 cc_status
.value1
= SET_SRC (set
);
2020 if (SET_DEST (set
) != cc0_rtx
)
2021 cc_status
.value2
= SET_DEST (set
);
2025 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2026 The C flag may or may not be known but that's ok because
2027 alter_cond will change tests to use EQ/NE. */
2029 cc_status
.flags
|= CC_NO_CARRY
;
2030 set
= single_set (insn
);
2031 cc_status
.value1
= SET_SRC (set
);
2032 if (SET_DEST (set
) != cc0_rtx
)
2034 /* If the destination is STRICT_LOW_PART, strip off
2036 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2037 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2039 cc_status
.value2
= SET_DEST (set
);
2044 /* The insn is a compare instruction. */
2046 cc_status
.value1
= SET_SRC (body
);
2050 /* Insn doesn't leave CC in a usable state. */
2056 /* Given that X occurs in an address of the form (plus X constant),
2057 return the part of X that is expected to be a register. There are
2058 four kinds of addressing mode to recognize:
2065 If SIZE is nonnull, and the address is one of the last three forms,
2066 set *SIZE to the index multiplication factor. Set it to 0 for
2067 plain @(dd,Rn) addresses.
2069 MODE is the mode of the value being accessed. It can be VOIDmode
2070 if the address is known to be valid, but its mode is unknown. */
2073 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
2080 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2083 && (mode
== VOIDmode
2084 || GET_MODE_CLASS (mode
) == MODE_INT
2085 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2087 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2089 /* When accessing byte-sized values, the index can be
2090 a zero-extended QImode or HImode register. */
2091 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2096 /* We're looking for addresses of the form:
2099 or (mult (zero_extend X) I)
2101 where I is the size of the operand being accessed.
2102 The canonical form of the second expression is:
2104 (and (mult (subreg X) I) J)
2106 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2109 if (GET_CODE (x
) == AND
2110 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2112 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2113 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2115 index
= XEXP (x
, 0);
2116 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2124 if (GET_CODE (index
) == MULT
2125 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2126 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2127 return XEXP (index
, 0);
2134 static const h8300_length_table addb_length_table
=
2136 /* #xx Rs @aa @Rs @xx */
2137 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2138 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2139 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2140 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2143 static const h8300_length_table addw_length_table
=
2145 /* #xx Rs @aa @Rs @xx */
2146 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2147 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2148 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2149 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2152 static const h8300_length_table addl_length_table
=
2154 /* #xx Rs @aa @Rs @xx */
2155 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2156 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2157 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2158 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2161 #define logicb_length_table addb_length_table
2162 #define logicw_length_table addw_length_table
2164 static const h8300_length_table logicl_length_table
=
2166 /* #xx Rs @aa @Rs @xx */
2167 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2168 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2169 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2170 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2173 static const h8300_length_table movb_length_table
=
2175 /* #xx Rs @aa @Rs @xx */
2176 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2177 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2178 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2179 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2182 #define movw_length_table movb_length_table
2184 static const h8300_length_table movl_length_table
=
2186 /* #xx Rs @aa @Rs @xx */
2187 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2188 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2189 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2190 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2193 /* Return the size of the given address or displacement constant. */
2196 h8300_constant_length (rtx constant
)
2198 /* Check for (@d:16,Reg). */
2199 if (GET_CODE (constant
) == CONST_INT
2200 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2203 /* Check for (@d:16,Reg) in cases where the displacement is
2204 an absolute address. */
2205 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2211 /* Return the size of a displacement field in address ADDR, which should
2212 have the form (plus X constant). SIZE is the number of bytes being
2216 h8300_displacement_length (rtx addr
, int size
)
2220 offset
= XEXP (addr
, 1);
2222 /* Check for @(d:2,Reg). */
2223 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2224 && GET_CODE (offset
) == CONST_INT
2225 && (INTVAL (offset
) == size
2226 || INTVAL (offset
) == size
* 2
2227 || INTVAL (offset
) == size
* 3))
2230 return h8300_constant_length (offset
);
2233 /* Store the class of operand OP in *OPCLASS and return the length of any
2234 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2235 can be null if only the length is needed. */
2238 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2240 enum h8300_operand_class dummy
;
2245 if (CONSTANT_P (op
))
2247 *opclass
= H8OP_IMMEDIATE
;
2249 /* Byte-sized immediates are stored in the opcode fields. */
2253 /* If this is a 32-bit instruction, see whether the constant
2254 will fit into a 16-bit immediate field. */
2257 && GET_CODE (op
) == CONST_INT
2258 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2263 else if (GET_CODE (op
) == MEM
)
2266 if (CONSTANT_P (op
))
2268 *opclass
= H8OP_MEM_ABSOLUTE
;
2269 return h8300_constant_length (op
);
2271 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2273 *opclass
= H8OP_MEM_COMPLEX
;
2274 return h8300_displacement_length (op
, size
);
2276 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2278 *opclass
= H8OP_MEM_COMPLEX
;
2281 else if (register_operand (op
, VOIDmode
))
2283 *opclass
= H8OP_MEM_BASE
;
2287 gcc_assert (register_operand (op
, VOIDmode
));
2288 *opclass
= H8OP_REGISTER
;
2292 /* Return the length of the instruction described by TABLE given that
2293 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2294 and OP2 must be an h8300_src_operand. */
2297 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2299 enum h8300_operand_class op1_class
, op2_class
;
2300 unsigned int size
, immediate_length
;
2302 size
= GET_MODE_SIZE (GET_MODE (op1
));
2303 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2304 + h8300_classify_operand (op2
, size
, &op2_class
));
2305 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2308 /* Return the length of a unary instruction such as neg or not given that
2309 its operand is OP. */
2312 h8300_unary_length (rtx op
)
2314 enum h8300_operand_class opclass
;
2315 unsigned int size
, operand_length
;
2317 size
= GET_MODE_SIZE (GET_MODE (op
));
2318 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2325 return (size
== 4 ? 6 : 4);
2327 case H8OP_MEM_ABSOLUTE
:
2328 return operand_length
+ (size
== 4 ? 6 : 4);
2330 case H8OP_MEM_COMPLEX
:
2331 return operand_length
+ 6;
2338 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2341 h8300_short_immediate_length (rtx op
)
2343 enum h8300_operand_class opclass
;
2344 unsigned int size
, operand_length
;
2346 size
= GET_MODE_SIZE (GET_MODE (op
));
2347 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2355 case H8OP_MEM_ABSOLUTE
:
2356 case H8OP_MEM_COMPLEX
:
2357 return 4 + operand_length
;
2364 /* Likewise bitfield load and store instructions. */
2367 h8300_bitfield_length (rtx op
, rtx op2
)
2369 enum h8300_operand_class opclass
;
2370 unsigned int size
, operand_length
;
2372 if (GET_CODE (op
) == REG
)
2374 gcc_assert (GET_CODE (op
) != REG
);
2376 size
= GET_MODE_SIZE (GET_MODE (op
));
2377 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2382 case H8OP_MEM_ABSOLUTE
:
2383 case H8OP_MEM_COMPLEX
:
2384 return 4 + operand_length
;
2391 /* Calculate the length of general binary instruction INSN using TABLE. */
2394 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2398 set
= single_set (insn
);
2401 if (BINARY_P (SET_SRC (set
)))
2402 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2403 XEXP (SET_SRC (set
), 1), table
);
2406 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2407 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2408 XEXP (XEXP (SET_SRC (set
), 1), 1),
2413 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2414 memory reference and either (1) it has the form @(d:16,Rn) or
2415 (2) its address has the code given by INC_CODE. */
2418 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2423 if (GET_CODE (op
) != MEM
)
2426 addr
= XEXP (op
, 0);
2427 size
= GET_MODE_SIZE (GET_MODE (op
));
2428 if (size
!= 1 && size
!= 2)
2431 return (GET_CODE (addr
) == inc_code
2432 || (GET_CODE (addr
) == PLUS
2433 && GET_CODE (XEXP (addr
, 0)) == REG
2434 && h8300_displacement_length (addr
, size
) == 2));
2437 /* Calculate the length of move instruction INSN using the given length
2438 table. Although the tables are correct for most cases, there is some
2439 irregularity in the length of mov.b and mov.w. The following forms:
2446 are two bytes shorter than most other "mov Rs, @complex" or
2447 "mov @complex,Rd" combinations. */
2450 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2454 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2455 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2457 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2462 /* Return the length of a mova instruction with the given operands.
2463 DEST is the register destination, SRC is the source address and
2464 OFFSET is the 16-bit or 32-bit displacement. */
2467 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2472 + h8300_constant_length (offset
)
2473 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2474 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2479 /* Compute the length of INSN based on its length_table attribute.
2480 OPERANDS is the array of its operands. */
2483 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2485 switch (get_attr_length_table (insn
))
2487 case LENGTH_TABLE_NONE
:
2490 case LENGTH_TABLE_ADDB
:
2491 return h8300_binary_length (insn
, &addb_length_table
);
2493 case LENGTH_TABLE_ADDW
:
2494 return h8300_binary_length (insn
, &addw_length_table
);
2496 case LENGTH_TABLE_ADDL
:
2497 return h8300_binary_length (insn
, &addl_length_table
);
2499 case LENGTH_TABLE_LOGICB
:
2500 return h8300_binary_length (insn
, &logicb_length_table
);
2502 case LENGTH_TABLE_MOVB
:
2503 return h8300_move_length (operands
, &movb_length_table
);
2505 case LENGTH_TABLE_MOVW
:
2506 return h8300_move_length (operands
, &movw_length_table
);
2508 case LENGTH_TABLE_MOVL
:
2509 return h8300_move_length (operands
, &movl_length_table
);
2511 case LENGTH_TABLE_MOVA
:
2512 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2514 case LENGTH_TABLE_MOVA_ZERO
:
2515 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2517 case LENGTH_TABLE_UNARY
:
2518 return h8300_unary_length (operands
[0]);
2520 case LENGTH_TABLE_MOV_IMM4
:
2521 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2523 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2524 return h8300_short_immediate_length (operands
[0]);
2526 case LENGTH_TABLE_BITFIELD
:
2527 return h8300_bitfield_length (operands
[0], operands
[1]);
2529 case LENGTH_TABLE_BITBRANCH
:
2530 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2537 /* Return true if LHS and RHS are memory references that can be mapped
2538 to the same h8sx assembly operand. LHS appears as the destination of
2539 an instruction and RHS appears as a source.
2541 Three cases are allowed:
2543 - RHS is @+Rn or @-Rn, LHS is @Rn
2544 - RHS is @Rn, LHS is @Rn+ or @Rn-
2545 - RHS and LHS have the same address and neither has side effects. */
2548 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2550 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2552 rhs
= XEXP (rhs
, 0);
2553 lhs
= XEXP (lhs
, 0);
2555 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2556 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2558 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2559 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2561 if (rtx_equal_p (rhs
, lhs
))
2567 /* Return true if OPERANDS[1] can be mapped to the same assembly
2568 operand as OPERANDS[0]. */
2571 h8300_operands_match_p (rtx
*operands
)
2573 if (register_operand (operands
[0], VOIDmode
)
2574 && register_operand (operands
[1], VOIDmode
))
2577 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2583 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2584 region DEST. The two regions do not overlap and have the common
2585 alignment given by ALIGNMENT. Return true on success.
2587 Using movmd for variable-length moves seems to involve some
2588 complex trade-offs. For instance:
2590 - Preparing for a movmd instruction is similar to preparing
2591 for a memcpy. The main difference is that the arguments
2592 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2594 - Since movmd clobbers the frame pointer, we need to save
2595 and restore it somehow when frame_pointer_needed. This can
2596 sometimes make movmd sequences longer than calls to memcpy().
2598 - The counter register is 16 bits, so the instruction is only
2599 suitable for variable-length moves when sizeof (size_t) == 2.
2600 That's only true in normal mode.
2602 - We will often lack static alignment information. Falling back
2603 on movmd.b would likely be slower than calling memcpy(), at least
2606 This function therefore only uses movmd when the length is a
2607 known constant, and only then if -fomit-frame-pointer is in
2608 effect or if we're not optimizing for size.
2610 At the moment the function uses movmd for all in-range constants,
2611 but it might be better to fall back on memcpy() for large moves
2612 if ALIGNMENT == 1. */
2615 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2616 HOST_WIDE_INT alignment
)
2618 if (!flag_omit_frame_pointer
&& optimize_size
)
2621 if (GET_CODE (length
) == CONST_INT
)
2623 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2627 /* Use movmd.l if the alignment allows it, otherwise fall back
2629 factor
= (alignment
>= 2 ? 4 : 1);
2631 /* Make sure the length is within range. We can handle counter
2632 values up to 65536, although HImode truncation will make
2633 the count appear negative in rtl dumps. */
2634 n
= INTVAL (length
);
2635 if (n
<= 0 || n
/ factor
> 65536)
2638 /* Create temporary registers for the source and destination
2639 pointers. Initialize them to the start of each region. */
2640 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2641 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2643 /* Create references to the movmd source and destination blocks. */
2644 first_dest
= replace_equiv_address (dest
, dest_reg
);
2645 first_src
= replace_equiv_address (src
, src_reg
);
2647 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
2648 set_mem_size (first_src
, GEN_INT (n
& -factor
));
2650 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2651 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2653 if ((n
& -factor
) != n
)
2655 /* Move SRC and DEST past the region we just copied.
2656 This is done to update the memory attributes. */
2657 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2658 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2660 /* Replace the addresses with the source and destination
2661 registers, which movmd has left with the right values. */
2662 dest
= replace_equiv_address (dest
, dest_reg
);
2663 src
= replace_equiv_address (src
, src_reg
);
2665 /* Mop up the left-over bytes. */
2667 emit_move_insn (adjust_address (dest
, HImode
, 0),
2668 adjust_address (src
, HImode
, 0));
2670 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2671 adjust_address (src
, QImode
, n
& 2));
2678 /* Move ADDR into er6 after pushing its old value onto the stack. */
2681 h8300_swap_into_er6 (rtx addr
)
2683 push (HARD_FRAME_POINTER_REGNUM
);
2684 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2685 if (REGNO (addr
) == SP_REG
)
2686 emit_move_insn (hard_frame_pointer_rtx
,
2687 plus_constant (hard_frame_pointer_rtx
,
2688 GET_MODE_SIZE (word_mode
)));
2691 /* Move the current value of er6 into ADDR and pop its old value
2695 h8300_swap_out_of_er6 (rtx addr
)
2697 if (REGNO (addr
) != SP_REG
)
2698 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2699 pop (HARD_FRAME_POINTER_REGNUM
);
2702 /* Return the length of mov instruction. */
2705 compute_mov_length (rtx
*operands
)
2707 /* If the mov instruction involves a memory operand, we compute the
2708 length, assuming the largest addressing mode is used, and then
2709 adjust later in the function. Otherwise, we compute and return
2710 the exact length in one step. */
2711 enum machine_mode mode
= GET_MODE (operands
[0]);
2712 rtx dest
= operands
[0];
2713 rtx src
= operands
[1];
2716 if (GET_CODE (src
) == MEM
)
2717 addr
= XEXP (src
, 0);
2718 else if (GET_CODE (dest
) == MEM
)
2719 addr
= XEXP (dest
, 0);
2725 unsigned int base_length
;
2730 if (addr
== NULL_RTX
)
2733 /* The eightbit addressing is available only in QImode, so
2734 go ahead and take care of it. */
2735 if (h8300_eightbit_constant_address_p (addr
))
2742 if (addr
== NULL_RTX
)
2747 if (src
== const0_rtx
)
2757 if (addr
== NULL_RTX
)
2762 if (GET_CODE (src
) == CONST_INT
)
2764 if (src
== const0_rtx
)
2767 if ((INTVAL (src
) & 0xffff) == 0)
2770 if ((INTVAL (src
) & 0xffff) == 0)
2773 if ((INTVAL (src
) & 0xffff)
2774 == ((INTVAL (src
) >> 16) & 0xffff))
2784 if (addr
== NULL_RTX
)
2789 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2802 /* Adjust the length based on the addressing mode used.
2803 Specifically, we subtract the difference between the actual
2804 length and the longest one, which is @(d:16,Rs). For SImode
2805 and SFmode, we double the adjustment because two mov.w are
2806 used to do the job. */
2808 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2809 if (GET_CODE (addr
) == PRE_DEC
2810 || GET_CODE (addr
) == POST_INC
)
2812 if (mode
== QImode
|| mode
== HImode
)
2813 return base_length
- 2;
2815 /* In SImode and SFmode, we use two mov.w instructions, so
2816 double the adjustment. */
2817 return base_length
- 4;
2820 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2821 in SImode and SFmode, the second mov.w involves an address
2822 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2824 if (GET_CODE (addr
) == REG
)
2825 return base_length
- 2;
2831 unsigned int base_length
;
2836 if (addr
== NULL_RTX
)
2839 /* The eightbit addressing is available only in QImode, so
2840 go ahead and take care of it. */
2841 if (h8300_eightbit_constant_address_p (addr
))
2848 if (addr
== NULL_RTX
)
2853 if (src
== const0_rtx
)
2863 if (addr
== NULL_RTX
)
2867 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2873 if (GET_CODE (src
) == CONST_INT
)
2875 int val
= INTVAL (src
);
2880 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2883 switch (val
& 0xffffffff)
2904 if (addr
== NULL_RTX
)
2909 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2922 /* Adjust the length based on the addressing mode used.
2923 Specifically, we subtract the difference between the actual
2924 length and the longest one, which is @(d:24,ERs). */
2926 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2927 if (GET_CODE (addr
) == PRE_DEC
2928 || GET_CODE (addr
) == POST_INC
)
2929 return base_length
- 6;
2931 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2932 if (GET_CODE (addr
) == REG
)
2933 return base_length
- 6;
2935 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2937 if (GET_CODE (addr
) == PLUS
2938 && GET_CODE (XEXP (addr
, 0)) == REG
2939 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2940 && INTVAL (XEXP (addr
, 1)) > -32768
2941 && INTVAL (XEXP (addr
, 1)) < 32767)
2942 return base_length
- 4;
2944 /* @aa:16 is 4 bytes shorter than the longest. */
2945 if (h8300_tiny_constant_address_p (addr
))
2946 return base_length
- 4;
2948 /* @aa:24 is 2 bytes shorter than the longest. */
2949 if (CONSTANT_P (addr
))
2950 return base_length
- 2;
2956 /* Output an addition insn. */
2959 output_plussi (rtx
*operands
)
2961 enum machine_mode mode
= GET_MODE (operands
[0]);
2963 gcc_assert (mode
== SImode
);
2967 if (GET_CODE (operands
[2]) == REG
)
2968 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2970 if (GET_CODE (operands
[2]) == CONST_INT
)
2972 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2974 if ((n
& 0xffffff) == 0)
2975 return "add\t%z2,%z0";
2976 if ((n
& 0xffff) == 0)
2977 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2978 if ((n
& 0xff) == 0)
2979 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2982 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2986 if (GET_CODE (operands
[2]) == CONST_INT
2987 && register_operand (operands
[1], VOIDmode
))
2989 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
2991 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
2992 return "add.l\t%S2,%S0";
2993 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
2994 return "sub.l\t%G2,%S0";
2996 /* See if we can finish with 2 bytes. */
2998 switch ((unsigned int) intval
& 0xffffffff)
3003 return "adds\t%2,%S0";
3008 return "subs\t%G2,%S0";
3012 operands
[2] = GEN_INT (intval
>> 16);
3013 return "inc.w\t%2,%e0";
3017 operands
[2] = GEN_INT (intval
>> 16);
3018 return "dec.w\t%G2,%e0";
3021 /* See if we can finish with 4 bytes. */
3022 if ((intval
& 0xffff) == 0)
3024 operands
[2] = GEN_INT (intval
>> 16);
3025 return "add.w\t%2,%e0";
3029 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3031 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3032 return "sub.l\t%S2,%S0";
3034 return "add.l\t%S2,%S0";
3038 /* ??? It would be much easier to add the h8sx stuff if a single function
3039 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3040 /* Compute the length of an addition insn. */
3043 compute_plussi_length (rtx
*operands
)
3045 enum machine_mode mode
= GET_MODE (operands
[0]);
3047 gcc_assert (mode
== SImode
);
3051 if (GET_CODE (operands
[2]) == REG
)
3054 if (GET_CODE (operands
[2]) == CONST_INT
)
3056 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3058 if ((n
& 0xffffff) == 0)
3060 if ((n
& 0xffff) == 0)
3062 if ((n
& 0xff) == 0)
3070 if (GET_CODE (operands
[2]) == CONST_INT
3071 && register_operand (operands
[1], VOIDmode
))
3073 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3075 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3077 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3080 /* See if we can finish with 2 bytes. */
3082 switch ((unsigned int) intval
& 0xffffffff)
3103 /* See if we can finish with 4 bytes. */
3104 if ((intval
& 0xffff) == 0)
3108 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3109 return h8300_length_from_table (operands
[0],
3110 GEN_INT (-INTVAL (operands
[2])),
3111 &addl_length_table
);
3113 return h8300_length_from_table (operands
[0], operands
[2],
3114 &addl_length_table
);
3119 /* Compute which flag bits are valid after an addition insn. */
3122 compute_plussi_cc (rtx
*operands
)
3124 enum machine_mode mode
= GET_MODE (operands
[0]);
3126 gcc_assert (mode
== SImode
);
3134 if (GET_CODE (operands
[2]) == CONST_INT
3135 && register_operand (operands
[1], VOIDmode
))
3137 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3139 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3141 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3144 /* See if we can finish with 2 bytes. */
3146 switch ((unsigned int) intval
& 0xffffffff)
3151 return CC_NONE_0HIT
;
3156 return CC_NONE_0HIT
;
3167 /* See if we can finish with 4 bytes. */
3168 if ((intval
& 0xffff) == 0)
3176 /* Output a logical insn. */
3179 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3181 /* Figure out the logical op that we need to perform. */
3182 enum rtx_code code
= GET_CODE (operands
[3]);
3183 /* Pretend that every byte is affected if both operands are registers. */
3184 const unsigned HOST_WIDE_INT intval
=
3185 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3186 /* Always use the full instruction if the
3187 first operand is in memory. It is better
3188 to use define_splits to generate the shorter
3189 sequence where valid. */
3190 && register_operand (operands
[1], VOIDmode
)
3191 ? INTVAL (operands
[2]) : 0x55555555);
3192 /* The determinant of the algorithm. If we perform an AND, 0
3193 affects a bit. Otherwise, 1 affects a bit. */
3194 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3195 /* Break up DET into pieces. */
3196 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3197 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3198 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3199 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3200 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3201 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3202 int lower_half_easy_p
= 0;
3203 int upper_half_easy_p
= 0;
3204 /* The name of an insn. */
3226 /* First, see if we can finish with one insn. */
3227 if ((TARGET_H8300H
|| TARGET_H8300S
)
3231 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3232 output_asm_insn (insn_buf
, operands
);
3236 /* Take care of the lower byte. */
3239 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3240 output_asm_insn (insn_buf
, operands
);
3242 /* Take care of the upper byte. */
3245 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3246 output_asm_insn (insn_buf
, operands
);
3251 if (TARGET_H8300H
|| TARGET_H8300S
)
3253 /* Determine if the lower half can be taken care of in no more
3255 lower_half_easy_p
= (b0
== 0
3257 || (code
!= IOR
&& w0
== 0xffff));
3259 /* Determine if the upper half can be taken care of in no more
3261 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3262 || (code
== AND
&& w1
== 0xff00));
3265 /* Check if doing everything with one insn is no worse than
3266 using multiple insns. */
3267 if ((TARGET_H8300H
|| TARGET_H8300S
)
3268 && w0
!= 0 && w1
!= 0
3269 && !(lower_half_easy_p
&& upper_half_easy_p
)
3270 && !(code
== IOR
&& w1
== 0xffff
3271 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3273 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3274 output_asm_insn (insn_buf
, operands
);
3278 /* Take care of the lower and upper words individually. For
3279 each word, we try different methods in the order of
3281 1) the special insn (in case of AND or XOR),
3282 2) the word-wise insn, and
3283 3) The byte-wise insn. */
3285 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3286 output_asm_insn ((code
== AND
)
3287 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3289 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3293 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3294 output_asm_insn (insn_buf
, operands
);
3300 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3301 output_asm_insn (insn_buf
, operands
);
3305 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3306 output_asm_insn (insn_buf
, operands
);
3311 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3312 output_asm_insn ((code
== AND
)
3313 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3315 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3318 && (w0
& 0x8000) != 0)
3320 output_asm_insn ("exts.l\t%S0", operands
);
3322 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3326 output_asm_insn ("extu.w\t%e0", operands
);
3328 else if (TARGET_H8300H
|| TARGET_H8300S
)
3332 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3333 output_asm_insn (insn_buf
, operands
);
3340 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3341 output_asm_insn (insn_buf
, operands
);
3345 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3346 output_asm_insn (insn_buf
, operands
);
3357 /* Compute the length of a logical insn. */
3360 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3362 /* Figure out the logical op that we need to perform. */
3363 enum rtx_code code
= GET_CODE (operands
[3]);
3364 /* Pretend that every byte is affected if both operands are registers. */
3365 const unsigned HOST_WIDE_INT intval
=
3366 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3367 /* Always use the full instruction if the
3368 first operand is in memory. It is better
3369 to use define_splits to generate the shorter
3370 sequence where valid. */
3371 && register_operand (operands
[1], VOIDmode
)
3372 ? INTVAL (operands
[2]) : 0x55555555);
3373 /* The determinant of the algorithm. If we perform an AND, 0
3374 affects a bit. Otherwise, 1 affects a bit. */
3375 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3376 /* Break up DET into pieces. */
3377 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3378 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3379 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3380 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3381 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3382 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3383 int lower_half_easy_p
= 0;
3384 int upper_half_easy_p
= 0;
3386 unsigned int length
= 0;
3391 /* First, see if we can finish with one insn. */
3392 if ((TARGET_H8300H
|| TARGET_H8300S
)
3396 length
= h8300_length_from_table (operands
[1], operands
[2],
3397 &logicw_length_table
);
3401 /* Take care of the lower byte. */
3405 /* Take care of the upper byte. */
3411 if (TARGET_H8300H
|| TARGET_H8300S
)
3413 /* Determine if the lower half can be taken care of in no more
3415 lower_half_easy_p
= (b0
== 0
3417 || (code
!= IOR
&& w0
== 0xffff));
3419 /* Determine if the upper half can be taken care of in no more
3421 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3422 || (code
== AND
&& w1
== 0xff00));
3425 /* Check if doing everything with one insn is no worse than
3426 using multiple insns. */
3427 if ((TARGET_H8300H
|| TARGET_H8300S
)
3428 && w0
!= 0 && w1
!= 0
3429 && !(lower_half_easy_p
&& upper_half_easy_p
)
3430 && !(code
== IOR
&& w1
== 0xffff
3431 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3433 length
= h8300_length_from_table (operands
[1], operands
[2],
3434 &logicl_length_table
);
3438 /* Take care of the lower and upper words individually. For
3439 each word, we try different methods in the order of
3441 1) the special insn (in case of AND or XOR),
3442 2) the word-wise insn, and
3443 3) The byte-wise insn. */
3445 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3449 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3465 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3469 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3472 && (w0
& 0x8000) != 0)
3476 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3482 else if (TARGET_H8300H
|| TARGET_H8300S
)
3503 /* Compute which flag bits are valid after a logical insn. */
3506 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3508 /* Figure out the logical op that we need to perform. */
3509 enum rtx_code code
= GET_CODE (operands
[3]);
3510 /* Pretend that every byte is affected if both operands are registers. */
3511 const unsigned HOST_WIDE_INT intval
=
3512 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3513 /* Always use the full instruction if the
3514 first operand is in memory. It is better
3515 to use define_splits to generate the shorter
3516 sequence where valid. */
3517 && register_operand (operands
[1], VOIDmode
)
3518 ? INTVAL (operands
[2]) : 0x55555555);
3519 /* The determinant of the algorithm. If we perform an AND, 0
3520 affects a bit. Otherwise, 1 affects a bit. */
3521 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3522 /* Break up DET into pieces. */
3523 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3524 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3525 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3526 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3527 int lower_half_easy_p
= 0;
3528 int upper_half_easy_p
= 0;
3529 /* Condition code. */
3530 enum attr_cc cc
= CC_CLOBBER
;
3535 /* First, see if we can finish with one insn. */
3536 if ((TARGET_H8300H
|| TARGET_H8300S
)
3544 if (TARGET_H8300H
|| TARGET_H8300S
)
3546 /* Determine if the lower half can be taken care of in no more
3548 lower_half_easy_p
= (b0
== 0
3550 || (code
!= IOR
&& w0
== 0xffff));
3552 /* Determine if the upper half can be taken care of in no more
3554 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3555 || (code
== AND
&& w1
== 0xff00));
3558 /* Check if doing everything with one insn is no worse than
3559 using multiple insns. */
3560 if ((TARGET_H8300H
|| TARGET_H8300S
)
3561 && w0
!= 0 && w1
!= 0
3562 && !(lower_half_easy_p
&& upper_half_easy_p
)
3563 && !(code
== IOR
&& w1
== 0xffff
3564 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3570 if ((TARGET_H8300H
|| TARGET_H8300S
)
3573 && (w0
& 0x8000) != 0)
3585 /* Expand a conditional branch. */
3588 h8300_expand_branch (rtx operands
[])
3590 enum rtx_code code
= GET_CODE (operands
[0]);
3591 rtx op0
= operands
[1];
3592 rtx op1
= operands
[2];
3593 rtx label
= operands
[3];
3596 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3597 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3599 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3600 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3601 gen_rtx_LABEL_REF (VOIDmode
, label
),
3603 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3607 /* Expand a conditional store. */
3610 h8300_expand_store (rtx operands
[])
3612 rtx dest
= operands
[0];
3613 enum rtx_code code
= GET_CODE (operands
[1]);
3614 rtx op0
= operands
[2];
3615 rtx op1
= operands
[3];
3618 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3619 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3621 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3622 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
3627 We devote a fair bit of code to getting efficient shifts since we
3628 can only shift one bit at a time on the H8/300 and H8/300H and only
3629 one or two bits at a time on the H8S.
3631 All shift code falls into one of the following ways of
3634 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3635 when a straight line shift is about the same size or smaller than
3638 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3639 off the bits we don't need. This is used when only a few of the
3640 bits in the original value will survive in the shifted value.
3642 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3643 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3644 shifts can be added if the shift count is slightly more than 8 or
3645 16. This case also includes other oddballs that are not worth
3648 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3650 For each shift count, we try to use code that has no trade-off
3651 between code size and speed whenever possible.
3653 If the trade-off is unavoidable, we try to be reasonable.
3654 Specifically, the fastest version is one instruction longer than
3655 the shortest version, we take the fastest version. We also provide
3656 the use a way to switch back to the shortest version with -Os.
3658 For the details of the shift algorithms for various shift counts,
3659 refer to shift_alg_[qhs]i. */
3661 /* Classify a shift with the given mode and code. OP is the shift amount. */
3663 enum h8sx_shift_type
3664 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
3666 if (!TARGET_H8300SX
)
3667 return H8SX_SHIFT_NONE
;
3673 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3674 if (GET_CODE (op
) != CONST_INT
)
3675 return H8SX_SHIFT_BINARY
;
3677 /* Reject out-of-range shift amounts. */
3678 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3679 return H8SX_SHIFT_NONE
;
3681 /* Power-of-2 shifts are effectively unary operations. */
3682 if (exact_log2 (INTVAL (op
)) >= 0)
3683 return H8SX_SHIFT_UNARY
;
3685 return H8SX_SHIFT_BINARY
;
3688 if (op
== const1_rtx
|| op
== const2_rtx
)
3689 return H8SX_SHIFT_UNARY
;
3690 return H8SX_SHIFT_NONE
;
3693 if (GET_CODE (op
) == CONST_INT
3694 && (INTVAL (op
) == 1
3696 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3697 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3698 return H8SX_SHIFT_UNARY
;
3699 return H8SX_SHIFT_NONE
;
3702 return H8SX_SHIFT_NONE
;
3706 /* Return the asm template for a single h8sx shift instruction.
3707 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3708 is the source and OPERANDS[3] is the shift. SUFFIX is the
3709 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3710 prefix for the destination operand. */
3713 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3715 static char buffer
[16];
3718 switch (GET_CODE (operands
[3]))
3734 if (INTVAL (operands
[2]) > 2)
3736 /* This is really a right rotate. */
3737 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3738 - INTVAL (operands
[2]));
3746 if (operands
[2] == const1_rtx
)
3747 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3749 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3753 /* Emit code to do shifts. */
3756 expand_a_shift (enum machine_mode mode
, int code
, rtx operands
[])
3758 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3760 case H8SX_SHIFT_BINARY
:
3761 operands
[1] = force_reg (mode
, operands
[1]);
3764 case H8SX_SHIFT_UNARY
:
3767 case H8SX_SHIFT_NONE
:
3771 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3773 /* Need a loop to get all the bits we want - we generate the
3774 code at emit time, but need to allocate a scratch reg now. */
3776 emit_insn (gen_rtx_PARALLEL
3779 gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
3780 gen_rtx_fmt_ee (code
, mode
,
3781 copy_rtx (operands
[0]), operands
[2])),
3782 gen_rtx_CLOBBER (VOIDmode
,
3783 gen_rtx_SCRATCH (QImode
)))));
3787 /* Symbols of the various modes which can be used as indices. */
3791 QIshift
, HIshift
, SIshift
3794 /* For single bit shift insns, record assembler and what bits of the
3795 condition code are valid afterwards (represented as various CC_FOO
3796 bits, 0 means CC isn't left in a usable state). */
3800 const char *const assembler
;
3804 /* Assembler instruction shift table.
3806 These tables are used to look up the basic shifts.
3807 They are indexed by cpu, shift_type, and mode. */
3809 static const struct shift_insn shift_one
[2][3][3] =
3815 { "shll\t%X0", CC_SET_ZNV
},
3816 { "add.w\t%T0,%T0", CC_SET_ZN
},
3817 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3819 /* SHIFT_LSHIFTRT */
3821 { "shlr\t%X0", CC_SET_ZNV
},
3822 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3823 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3825 /* SHIFT_ASHIFTRT */
3827 { "shar\t%X0", CC_SET_ZNV
},
3828 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3829 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3836 { "shll.b\t%X0", CC_SET_ZNV
},
3837 { "shll.w\t%T0", CC_SET_ZNV
},
3838 { "shll.l\t%S0", CC_SET_ZNV
}
3840 /* SHIFT_LSHIFTRT */
3842 { "shlr.b\t%X0", CC_SET_ZNV
},
3843 { "shlr.w\t%T0", CC_SET_ZNV
},
3844 { "shlr.l\t%S0", CC_SET_ZNV
}
3846 /* SHIFT_ASHIFTRT */
3848 { "shar.b\t%X0", CC_SET_ZNV
},
3849 { "shar.w\t%T0", CC_SET_ZNV
},
3850 { "shar.l\t%S0", CC_SET_ZNV
}
3855 static const struct shift_insn shift_two
[3][3] =
3859 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3860 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3861 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3863 /* SHIFT_LSHIFTRT */
3865 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3866 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3867 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3869 /* SHIFT_ASHIFTRT */
3871 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3872 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3873 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3877 /* Rotates are organized by which shift they'll be used in implementing.
3878 There's no need to record whether the cc is valid afterwards because
3879 it is the AND insn that will decide this. */
3881 static const char *const rotate_one
[2][3][3] =
3888 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3891 /* SHIFT_LSHIFTRT */
3894 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3897 /* SHIFT_ASHIFTRT */
3900 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3912 /* SHIFT_LSHIFTRT */
3918 /* SHIFT_ASHIFTRT */
3927 static const char *const rotate_two
[3][3] =
3935 /* SHIFT_LSHIFTRT */
3941 /* SHIFT_ASHIFTRT */
3950 /* Shift algorithm. */
3953 /* The number of bits to be shifted by shift1 and shift2. Valid
3954 when ALG is SHIFT_SPECIAL. */
3955 unsigned int remainder
;
3957 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3958 const char *special
;
3960 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3961 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3964 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3965 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3968 /* CC status for SHIFT_INLINE. */
3971 /* CC status for SHIFT_SPECIAL. */
3975 static void get_shift_alg (enum shift_type
,
3976 enum shift_mode
, unsigned int,
3977 struct shift_info
*);
3979 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3980 best algorithm for doing the shift. The assembler code is stored
3981 in the pointers in INFO. We achieve the maximum efficiency in most
3982 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3983 SImode in particular have a lot of room to optimize.
3985 We first determine the strategy of the shift algorithm by a table
3986 lookup. If that tells us to use a hand crafted assembly code, we
3987 go into the big switch statement to find what that is. Otherwise,
3988 we resort to a generic way, such as inlining. In either case, the
3989 result is returned through INFO. */
3992 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
3993 unsigned int count
, struct shift_info
*info
)
3997 /* Find the target CPU. */
4000 else if (TARGET_H8300H
)
4005 /* Find the shift algorithm. */
4006 info
->alg
= SHIFT_LOOP
;
4010 if (count
< GET_MODE_BITSIZE (QImode
))
4011 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4015 if (count
< GET_MODE_BITSIZE (HImode
))
4016 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4020 if (count
< GET_MODE_BITSIZE (SImode
))
4021 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4028 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4032 info
->remainder
= count
;
4036 /* It is up to the caller to know that looping clobbers cc. */
4037 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4038 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4039 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4043 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4044 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4045 info
->cc_inline
= CC_CLOBBER
;
4049 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4050 info
->remainder
= 0;
4051 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4052 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4053 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4054 info
->cc_special
= CC_CLOBBER
;
4058 /* Here we only deal with SHIFT_SPECIAL. */
4062 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4063 through the entire value. */
4064 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4065 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4075 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4077 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4079 case SHIFT_LSHIFTRT
:
4081 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4083 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4085 case SHIFT_ASHIFTRT
:
4086 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4090 else if ((8 <= count
&& count
<= 13)
4091 || (TARGET_H8300S
&& count
== 14))
4093 info
->remainder
= count
- 8;
4098 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4100 case SHIFT_LSHIFTRT
:
4103 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4104 info
->shift1
= "shlr.b\t%s0";
4105 info
->cc_inline
= CC_SET_ZNV
;
4109 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4110 info
->cc_special
= CC_SET_ZNV
;
4113 case SHIFT_ASHIFTRT
:
4116 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4117 info
->shift1
= "shar.b\t%s0";
4121 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4122 info
->cc_special
= CC_SET_ZNV
;
4127 else if (count
== 14)
4133 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4135 case SHIFT_LSHIFTRT
:
4137 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4139 case SHIFT_ASHIFTRT
:
4141 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4142 else if (TARGET_H8300H
)
4144 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4145 info
->cc_special
= CC_SET_ZNV
;
4147 else /* TARGET_H8300S */
4152 else if (count
== 15)
4157 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4159 case SHIFT_LSHIFTRT
:
4160 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4162 case SHIFT_ASHIFTRT
:
4163 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4170 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4172 info
->remainder
= count
- 8;
4177 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4179 case SHIFT_LSHIFTRT
:
4180 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4181 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4183 case SHIFT_ASHIFTRT
:
4184 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4188 else if (count
== 8 && !TARGET_H8300
)
4193 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4195 case SHIFT_LSHIFTRT
:
4196 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4198 case SHIFT_ASHIFTRT
:
4199 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4203 else if (count
== 15 && TARGET_H8300
)
4209 case SHIFT_LSHIFTRT
:
4210 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4212 case SHIFT_ASHIFTRT
:
4213 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4217 else if (count
== 15 && !TARGET_H8300
)
4222 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4223 info
->cc_special
= CC_SET_ZNV
;
4225 case SHIFT_LSHIFTRT
:
4226 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4227 info
->cc_special
= CC_SET_ZNV
;
4229 case SHIFT_ASHIFTRT
:
4233 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4234 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4235 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4237 info
->remainder
= count
- 16;
4242 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4244 info
->shift1
= "add.w\t%e0,%e0";
4246 case SHIFT_LSHIFTRT
:
4249 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4250 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4254 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4255 info
->cc_special
= CC_SET_ZNV
;
4258 case SHIFT_ASHIFTRT
:
4261 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4262 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4266 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4267 info
->cc_special
= CC_SET_ZNV
;
4272 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4274 info
->remainder
= count
- 24;
4279 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4280 info
->shift1
= "shll.b\t%z0";
4281 info
->cc_inline
= CC_SET_ZNV
;
4283 case SHIFT_LSHIFTRT
:
4284 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4285 info
->shift1
= "shlr.b\t%w0";
4286 info
->cc_inline
= CC_SET_ZNV
;
4288 case SHIFT_ASHIFTRT
:
4289 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4290 info
->shift1
= "shar.b\t%w0";
4291 info
->cc_inline
= CC_SET_ZNV
;
4295 else if ((TARGET_H8300H
&& count
== 24)
4296 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4298 info
->remainder
= count
- 24;
4303 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4305 case SHIFT_LSHIFTRT
:
4306 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4307 info
->cc_special
= CC_SET_ZNV
;
4309 case SHIFT_ASHIFTRT
:
4310 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4311 info
->cc_special
= CC_SET_ZNV
;
4315 else if (!TARGET_H8300
&& count
== 28)
4321 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4323 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4325 case SHIFT_LSHIFTRT
:
4328 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4329 info
->cc_special
= CC_SET_ZNV
;
4332 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4334 case SHIFT_ASHIFTRT
:
4338 else if (!TARGET_H8300
&& count
== 29)
4344 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4346 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4348 case SHIFT_LSHIFTRT
:
4351 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4352 info
->cc_special
= CC_SET_ZNV
;
4356 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4357 info
->cc_special
= CC_SET_ZNV
;
4360 case SHIFT_ASHIFTRT
:
4364 else if (!TARGET_H8300
&& count
== 30)
4370 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4372 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4374 case SHIFT_LSHIFTRT
:
4376 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4378 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4380 case SHIFT_ASHIFTRT
:
4384 else if (count
== 31)
4391 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4393 case SHIFT_LSHIFTRT
:
4394 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4396 case SHIFT_ASHIFTRT
:
4397 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4406 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4407 info
->cc_special
= CC_SET_ZNV
;
4409 case SHIFT_LSHIFTRT
:
4410 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4411 info
->cc_special
= CC_SET_ZNV
;
4413 case SHIFT_ASHIFTRT
:
4414 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4415 info
->cc_special
= CC_SET_ZNV
;
4428 info
->shift2
= NULL
;
4431 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4432 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4435 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4440 if (GET_MODE_BITSIZE (mode
) <= count
)
4443 /* Find out the target CPU. */
4446 else if (TARGET_H8300H
)
4451 /* Find the shift algorithm. */
4455 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4456 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4457 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4461 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4462 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4463 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4467 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4468 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4469 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4476 /* On H8/300H, count == 8 uses a scratch register. */
4477 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4478 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4481 /* Output the assembler code for doing shifts. */
4484 output_a_shift (rtx
*operands
)
4486 static int loopend_lab
;
4487 rtx shift
= operands
[3];
4488 enum machine_mode mode
= GET_MODE (shift
);
4489 enum rtx_code code
= GET_CODE (shift
);
4490 enum shift_type shift_type
;
4491 enum shift_mode shift_mode
;
4492 struct shift_info info
;
4500 shift_mode
= QIshift
;
4503 shift_mode
= HIshift
;
4506 shift_mode
= SIshift
;
4515 shift_type
= SHIFT_ASHIFTRT
;
4518 shift_type
= SHIFT_LSHIFTRT
;
4521 shift_type
= SHIFT_ASHIFT
;
4527 /* This case must be taken care of by one of the two splitters
4528 that convert a variable shift into a loop. */
4529 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4531 n
= INTVAL (operands
[2]);
4533 /* If the count is negative, make it 0. */
4536 /* If the count is too big, truncate it.
4537 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4538 do the intuitive thing. */
4539 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4540 n
= GET_MODE_BITSIZE (mode
);
4542 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4547 output_asm_insn (info
.special
, operands
);
4553 /* Emit two bit shifts first. */
4554 if (info
.shift2
!= NULL
)
4556 for (; n
> 1; n
-= 2)
4557 output_asm_insn (info
.shift2
, operands
);
4560 /* Now emit one bit shifts for any residual. */
4562 output_asm_insn (info
.shift1
, operands
);
4567 int m
= GET_MODE_BITSIZE (mode
) - n
;
4568 const int mask
= (shift_type
== SHIFT_ASHIFT
4569 ? ((1 << m
) - 1) << n
4573 /* Not all possibilities of rotate are supported. They shouldn't
4574 be generated, but let's watch for 'em. */
4575 gcc_assert (info
.shift1
);
4577 /* Emit two bit rotates first. */
4578 if (info
.shift2
!= NULL
)
4580 for (; m
> 1; m
-= 2)
4581 output_asm_insn (info
.shift2
, operands
);
4584 /* Now single bit rotates for any residual. */
4586 output_asm_insn (info
.shift1
, operands
);
4588 /* Now mask off the high bits. */
4592 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4596 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4597 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4604 output_asm_insn (insn_buf
, operands
);
4609 /* A loop to shift by a "large" constant value.
4610 If we have shift-by-2 insns, use them. */
4611 if (info
.shift2
!= NULL
)
4613 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4614 names_big
[REGNO (operands
[4])]);
4615 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4616 output_asm_insn (info
.shift2
, operands
);
4617 output_asm_insn ("add #0xff,%X4", operands
);
4618 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4620 output_asm_insn (info
.shift1
, operands
);
4624 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4625 names_big
[REGNO (operands
[4])]);
4626 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4627 output_asm_insn (info
.shift1
, operands
);
4628 output_asm_insn ("add #0xff,%X4", operands
);
4629 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4638 /* Count the number of assembly instructions in a string TEMPL. */
4641 h8300_asm_insn_count (const char *templ
)
4643 unsigned int count
= 1;
4645 for (; *templ
; templ
++)
4652 /* Compute the length of a shift insn. */
4655 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4657 rtx shift
= operands
[3];
4658 enum machine_mode mode
= GET_MODE (shift
);
4659 enum rtx_code code
= GET_CODE (shift
);
4660 enum shift_type shift_type
;
4661 enum shift_mode shift_mode
;
4662 struct shift_info info
;
4663 unsigned int wlength
= 0;
4668 shift_mode
= QIshift
;
4671 shift_mode
= HIshift
;
4674 shift_mode
= SIshift
;
4683 shift_type
= SHIFT_ASHIFTRT
;
4686 shift_type
= SHIFT_LSHIFTRT
;
4689 shift_type
= SHIFT_ASHIFT
;
4695 if (GET_CODE (operands
[2]) != CONST_INT
)
4697 /* Get the assembler code to do one shift. */
4698 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4700 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4704 int n
= INTVAL (operands
[2]);
4706 /* If the count is negative, make it 0. */
4709 /* If the count is too big, truncate it.
4710 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4711 do the intuitive thing. */
4712 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4713 n
= GET_MODE_BITSIZE (mode
);
4715 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4720 wlength
+= h8300_asm_insn_count (info
.special
);
4722 /* Every assembly instruction used in SHIFT_SPECIAL case
4723 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4724 see xor.l, we just pretend that xor.l counts as two insns
4725 so that the insn length will be computed correctly. */
4726 if (strstr (info
.special
, "xor.l") != NULL
)
4734 if (info
.shift2
!= NULL
)
4736 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4740 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4746 int m
= GET_MODE_BITSIZE (mode
) - n
;
4748 /* Not all possibilities of rotate are supported. They shouldn't
4749 be generated, but let's watch for 'em. */
4750 gcc_assert (info
.shift1
);
4752 if (info
.shift2
!= NULL
)
4754 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4758 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4760 /* Now mask off the high bits. */
4770 gcc_assert (!TARGET_H8300
);
4780 /* A loop to shift by a "large" constant value.
4781 If we have shift-by-2 insns, use them. */
4782 if (info
.shift2
!= NULL
)
4784 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4786 wlength
+= h8300_asm_insn_count (info
.shift1
);
4790 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4800 /* Compute which flag bits are valid after a shift insn. */
4803 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4805 rtx shift
= operands
[3];
4806 enum machine_mode mode
= GET_MODE (shift
);
4807 enum rtx_code code
= GET_CODE (shift
);
4808 enum shift_type shift_type
;
4809 enum shift_mode shift_mode
;
4810 struct shift_info info
;
4816 shift_mode
= QIshift
;
4819 shift_mode
= HIshift
;
4822 shift_mode
= SIshift
;
4831 shift_type
= SHIFT_ASHIFTRT
;
4834 shift_type
= SHIFT_LSHIFTRT
;
4837 shift_type
= SHIFT_ASHIFT
;
4843 /* This case must be taken care of by one of the two splitters
4844 that convert a variable shift into a loop. */
4845 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4847 n
= INTVAL (operands
[2]);
4849 /* If the count is negative, make it 0. */
4852 /* If the count is too big, truncate it.
4853 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4854 do the intuitive thing. */
4855 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4856 n
= GET_MODE_BITSIZE (mode
);
4858 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4863 if (info
.remainder
== 0)
4864 return info
.cc_special
;
4869 return info
.cc_inline
;
4872 /* This case always ends with an and instruction. */
4876 /* A loop to shift by a "large" constant value.
4877 If we have shift-by-2 insns, use them. */
4878 if (info
.shift2
!= NULL
)
4881 return info
.cc_inline
;
4890 /* A rotation by a non-constant will cause a loop to be generated, in
4891 which a rotation by one bit is used. A rotation by a constant,
4892 including the one in the loop, will be taken care of by
4893 output_a_rotate () at the insn emit time. */
4896 expand_a_rotate (rtx operands
[])
4898 rtx dst
= operands
[0];
4899 rtx src
= operands
[1];
4900 rtx rotate_amount
= operands
[2];
4901 enum machine_mode mode
= GET_MODE (dst
);
4903 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4906 /* We rotate in place. */
4907 emit_move_insn (dst
, src
);
4909 if (GET_CODE (rotate_amount
) != CONST_INT
)
4911 rtx counter
= gen_reg_rtx (QImode
);
4912 rtx start_label
= gen_label_rtx ();
4913 rtx end_label
= gen_label_rtx ();
4915 /* If the rotate amount is less than or equal to 0,
4916 we go out of the loop. */
4917 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4918 QImode
, 0, end_label
);
4920 /* Initialize the loop counter. */
4921 emit_move_insn (counter
, rotate_amount
);
4923 emit_label (start_label
);
4925 /* Rotate by one bit. */
4929 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
4932 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
4935 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
4941 /* Decrement the counter by 1. */
4942 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
4944 /* If the loop counter is nonzero, we go back to the beginning
4946 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
4949 emit_label (end_label
);
4953 /* Rotate by AMOUNT bits. */
4957 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
4960 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
4963 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
4973 /* Output a rotate insn. */
4976 output_a_rotate (enum rtx_code code
, rtx
*operands
)
4978 rtx dst
= operands
[0];
4979 rtx rotate_amount
= operands
[2];
4980 enum shift_mode rotate_mode
;
4981 enum shift_type rotate_type
;
4982 const char *insn_buf
;
4985 enum machine_mode mode
= GET_MODE (dst
);
4987 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
4992 rotate_mode
= QIshift
;
4995 rotate_mode
= HIshift
;
4998 rotate_mode
= SIshift
;
5007 rotate_type
= SHIFT_ASHIFT
;
5010 rotate_type
= SHIFT_LSHIFTRT
;
5016 amount
= INTVAL (rotate_amount
);
5018 /* Clean up AMOUNT. */
5021 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5022 amount
= GET_MODE_BITSIZE (mode
);
5024 /* Determine the faster direction. After this phase, amount will be
5025 at most a half of GET_MODE_BITSIZE (mode). */
5026 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5028 /* Flip the direction. */
5029 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5031 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5034 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5035 boost up the rotation. */
5036 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5037 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5038 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5039 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5040 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5045 /* This code works on any family. */
5046 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5047 output_asm_insn (insn_buf
, operands
);
5051 /* This code works on the H8/300H and H8S. */
5052 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5053 output_asm_insn (insn_buf
, operands
);
5060 /* Adjust AMOUNT and flip the direction. */
5061 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5063 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5066 /* Output rotate insns. */
5067 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5070 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5072 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5074 for (; amount
>= bits
; amount
-= bits
)
5075 output_asm_insn (insn_buf
, operands
);
5081 /* Compute the length of a rotate insn. */
5084 compute_a_rotate_length (rtx
*operands
)
5086 rtx src
= operands
[1];
5087 rtx amount_rtx
= operands
[2];
5088 enum machine_mode mode
= GET_MODE (src
);
5090 unsigned int length
= 0;
5092 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5094 amount
= INTVAL (amount_rtx
);
5096 /* Clean up AMOUNT. */
5099 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5100 amount
= GET_MODE_BITSIZE (mode
);
5102 /* Determine the faster direction. After this phase, amount
5103 will be at most a half of GET_MODE_BITSIZE (mode). */
5104 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5105 /* Flip the direction. */
5106 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5108 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5109 boost up the rotation. */
5110 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5111 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5112 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5113 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5114 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5116 /* Adjust AMOUNT and flip the direction. */
5117 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5121 /* We use 2-bit rotations on the H8S. */
5123 amount
= amount
/ 2 + amount
% 2;
5125 /* The H8/300 uses three insns to rotate one bit, taking 6
5127 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5132 /* Fix the operands of a gen_xxx so that it could become a bit
5136 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5138 /* The bit_operand predicate accepts any memory during RTL generation, but
5139 only 'U' memory afterwards, so if this is a MEM operand, we must force
5140 it to be valid for 'U' by reloading the address. */
5143 ? single_zero_operand (operands
[2], QImode
)
5144 : single_one_operand (operands
[2], QImode
))
5146 /* OK to have a memory dest. */
5147 if (GET_CODE (operands
[0]) == MEM
5148 && !OK_FOR_U (operands
[0]))
5150 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5151 copy_to_mode_reg (Pmode
,
5152 XEXP (operands
[0], 0)));
5153 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5157 if (GET_CODE (operands
[1]) == MEM
5158 && !OK_FOR_U (operands
[1]))
5160 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5161 copy_to_mode_reg (Pmode
,
5162 XEXP (operands
[1], 0)));
5163 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5169 /* Dest and src op must be register. */
5171 operands
[1] = force_reg (QImode
, operands
[1]);
5173 rtx res
= gen_reg_rtx (QImode
);
5177 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5180 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5183 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5188 emit_insn (gen_movqi (operands
[0], res
));
5193 /* Return nonzero if FUNC is an interrupt function as specified
5194 by the "interrupt" attribute. */
5197 h8300_interrupt_function_p (tree func
)
5201 if (TREE_CODE (func
) != FUNCTION_DECL
)
5204 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5205 return a
!= NULL_TREE
;
5208 /* Return nonzero if FUNC is a saveall function as specified by the
5209 "saveall" attribute. */
5212 h8300_saveall_function_p (tree func
)
5216 if (TREE_CODE (func
) != FUNCTION_DECL
)
5219 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5220 return a
!= NULL_TREE
;
5223 /* Return nonzero if FUNC is an OS_Task function as specified
5224 by the "OS_Task" attribute. */
5227 h8300_os_task_function_p (tree func
)
5231 if (TREE_CODE (func
) != FUNCTION_DECL
)
5234 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5235 return a
!= NULL_TREE
;
5238 /* Return nonzero if FUNC is a monitor function as specified
5239 by the "monitor" attribute. */
5242 h8300_monitor_function_p (tree func
)
5246 if (TREE_CODE (func
) != FUNCTION_DECL
)
5249 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5250 return a
!= NULL_TREE
;
5253 /* Return nonzero if FUNC is a function that should be called
5254 through the function vector. */
5257 h8300_funcvec_function_p (tree func
)
5261 if (TREE_CODE (func
) != FUNCTION_DECL
)
5264 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5265 return a
!= NULL_TREE
;
5268 /* Return nonzero if DECL is a variable that's in the eight bit
5272 h8300_eightbit_data_p (tree decl
)
5276 if (TREE_CODE (decl
) != VAR_DECL
)
5279 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5280 return a
!= NULL_TREE
;
5283 /* Return nonzero if DECL is a variable that's in the tiny
5287 h8300_tiny_data_p (tree decl
)
5291 if (TREE_CODE (decl
) != VAR_DECL
)
5294 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5295 return a
!= NULL_TREE
;
5298 /* Generate an 'interrupt_handler' attribute for decls. We convert
5299 all the pragmas to corresponding attributes. */
5302 h8300_insert_attributes (tree node
, tree
*attributes
)
5304 if (TREE_CODE (node
) == FUNCTION_DECL
)
5306 if (pragma_interrupt
)
5308 pragma_interrupt
= 0;
5310 /* Add an 'interrupt_handler' attribute. */
5311 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5319 /* Add an 'saveall' attribute. */
5320 *attributes
= tree_cons (get_identifier ("saveall"),
5326 /* Supported attributes:
5328 interrupt_handler: output a prologue and epilogue suitable for an
5331 saveall: output a prologue and epilogue that saves and restores
5332 all registers except the stack pointer.
5334 function_vector: This function should be called through the
5337 eightbit_data: This variable lives in the 8-bit data area and can
5338 be referenced with 8-bit absolute memory addresses.
5340 tiny_data: This variable lives in the tiny data area and can be
5341 referenced with 16-bit absolute memory references. */
5343 static const struct attribute_spec h8300_attribute_table
[] =
5345 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5346 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5347 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5348 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5349 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5350 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5351 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
5352 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
5353 { NULL
, 0, 0, false, false, false, NULL
}
5357 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5358 struct attribute_spec.handler. */
5360 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5361 tree args ATTRIBUTE_UNUSED
,
5362 int flags ATTRIBUTE_UNUSED
,
5365 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5367 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5369 *no_add_attrs
= true;
5375 /* Handle an "eightbit_data" attribute; arguments as in
5376 struct attribute_spec.handler. */
5378 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5379 tree args ATTRIBUTE_UNUSED
,
5380 int flags ATTRIBUTE_UNUSED
,
5385 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5387 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5391 warning (OPT_Wattributes
, "%qE attribute ignored",
5393 *no_add_attrs
= true;
5399 /* Handle an "tiny_data" attribute; arguments as in
5400 struct attribute_spec.handler. */
5402 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5403 tree args ATTRIBUTE_UNUSED
,
5404 int flags ATTRIBUTE_UNUSED
,
5409 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5411 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5415 warning (OPT_Wattributes
, "%qE attribute ignored",
5417 *no_add_attrs
= true;
5423 /* Mark function vectors, and various small data objects. */
5426 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5428 int extra_flags
= 0;
5430 default_encode_section_info (decl
, rtl
, first
);
5432 if (TREE_CODE (decl
) == FUNCTION_DECL
5433 && h8300_funcvec_function_p (decl
))
5434 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5435 else if (TREE_CODE (decl
) == VAR_DECL
5436 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5438 if (h8300_eightbit_data_p (decl
))
5439 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5440 else if (first
&& h8300_tiny_data_p (decl
))
5441 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5445 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5448 /* Output a single-bit extraction. */
5451 output_simode_bld (int bild
, rtx operands
[])
5455 /* Clear the destination register. */
5456 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5458 /* Now output the bit load or bit inverse load, and store it in
5461 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5463 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5465 output_asm_insn ("bst\t#0,%w0", operands
);
5469 /* Determine if we can clear the destination first. */
5470 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5471 && REGNO (operands
[0]) != REGNO (operands
[1]));
5474 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5476 /* Output the bit load or bit inverse load. */
5478 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5480 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5483 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5485 /* Perform the bit store. */
5486 output_asm_insn ("rotxl.l\t%S0", operands
);
5493 /* Delayed-branch scheduling is more effective if we have some idea
5494 how long each instruction will be. Use a shorten_branches pass
5495 to get an initial estimate. */
5500 if (flag_delayed_branch
)
5501 shorten_branches (get_insns ());
5504 #ifndef OBJECT_FORMAT_ELF
5506 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5509 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5510 fprintf (asm_out_file
, "\t.section %s\n", name
);
5512 #endif /* ! OBJECT_FORMAT_ELF */
5514 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5515 which is a special case of the 'R' operand. */
5518 h8300_eightbit_constant_address_p (rtx x
)
5520 /* The ranges of the 8-bit area. */
5521 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5522 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5523 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5524 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5525 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5526 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5528 unsigned HOST_WIDE_INT addr
;
5530 /* We accept symbols declared with eightbit_data. */
5531 if (GET_CODE (x
) == SYMBOL_REF
)
5532 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5534 if (GET_CODE (x
) != CONST_INT
)
5540 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5541 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5542 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5545 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5546 on H8/300H and H8S. */
5549 h8300_tiny_constant_address_p (rtx x
)
5551 /* The ranges of the 16-bit area. */
5552 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5553 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5554 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5555 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5556 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5557 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5558 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5559 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5561 unsigned HOST_WIDE_INT addr
;
5563 switch (GET_CODE (x
))
5566 /* In the normal mode, any symbol fits in the 16-bit absolute
5567 address range. We also accept symbols declared with
5569 return (TARGET_NORMAL_MODE
5570 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5574 return (TARGET_NORMAL_MODE
5576 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5578 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5581 return TARGET_NORMAL_MODE
;
5589 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5590 locations that can be accessed as a 16-bit word. */
5593 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5595 HOST_WIDE_INT offset1
, offset2
;
5603 else if (GET_CODE (addr1
) == PLUS
5604 && REG_P (XEXP (addr1
, 0))
5605 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5607 reg1
= XEXP (addr1
, 0);
5608 offset1
= INTVAL (XEXP (addr1
, 1));
5618 else if (GET_CODE (addr2
) == PLUS
5619 && REG_P (XEXP (addr2
, 0))
5620 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5622 reg2
= XEXP (addr2
, 0);
5623 offset2
= INTVAL (XEXP (addr2
, 1));
5628 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5629 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5631 && offset1
+ 1 == offset2
)
5637 /* Return nonzero if we have the same comparison insn as I3 two insns
5638 before I3. I3 is assumed to be a comparison insn. */
5641 same_cmp_preceding_p (rtx i3
)
5645 /* Make sure we have a sequence of three insns. */
5646 i2
= prev_nonnote_insn (i3
);
5649 i1
= prev_nonnote_insn (i2
);
5653 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5654 && any_condjump_p (i2
) && onlyjump_p (i2
));
5657 /* Return nonzero if we have the same comparison insn as I1 two insns
5658 after I1. I1 is assumed to be a comparison insn. */
5661 same_cmp_following_p (rtx i1
)
5665 /* Make sure we have a sequence of three insns. */
5666 i2
= next_nonnote_insn (i1
);
5669 i3
= next_nonnote_insn (i2
);
5673 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5674 && any_condjump_p (i2
) && onlyjump_p (i2
));
5677 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5678 (or pops) N registers. OPERANDS are assumed to be an array of
5682 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5687 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5688 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5689 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5691 return ((REGNO (operands
[0]) == 0
5692 && REGNO (operands
[1]) == 1
5693 && REGNO (operands
[2]) == 2)
5694 || (REGNO (operands
[0]) == 4
5695 && REGNO (operands
[1]) == 5
5696 && REGNO (operands
[2]) == 6));
5699 return (REGNO (operands
[0]) == 0
5700 && REGNO (operands
[1]) == 1
5701 && REGNO (operands
[2]) == 2
5702 && REGNO (operands
[3]) == 3);
5708 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5711 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5712 unsigned int new_reg
)
5714 /* Interrupt functions can only use registers that have already been
5715 saved by the prologue, even if they would normally be
5718 if (h8300_current_function_interrupt_function_p ()
5719 && !df_regs_ever_live_p (new_reg
))
5725 /* Returns true if register REGNO is safe to be allocated as a scratch
5726 register in the current function. */
5729 h8300_hard_regno_scratch_ok (unsigned int regno
)
5731 if (h8300_current_function_interrupt_function_p ()
5732 && ! WORD_REG_USED (regno
))
5739 /* Return nonzero if X is a legitimate constant. */
5742 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
5747 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5750 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5752 /* Strip off SUBREG if any. */
5753 if (GET_CODE (x
) == SUBREG
)
5758 ? REG_OK_FOR_BASE_STRICT_P (x
)
5759 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5762 /* Return nozero if X is a legitimate address. On the H8/300, a
5763 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5764 CONSTANT_ADDRESS. */
5767 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
5769 /* The register indirect addresses like @er0 is always valid. */
5770 if (h8300_rtx_ok_for_base_p (x
, strict
))
5773 if (CONSTANT_ADDRESS_P (x
))
5777 && ( GET_CODE (x
) == PRE_INC
5778 || GET_CODE (x
) == PRE_DEC
5779 || GET_CODE (x
) == POST_INC
5780 || GET_CODE (x
) == POST_DEC
)
5781 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5784 if (GET_CODE (x
) == PLUS
5785 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5786 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5793 /* Worker function for HARD_REGNO_NREGS.
5795 We pretend the MAC register is 32bits -- we don't have any data
5796 types on the H8 series to handle more than 32bits. */
5799 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5801 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5804 /* Worker function for HARD_REGNO_MODE_OK. */
5807 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5810 /* If an even reg, then anything goes. Otherwise the mode must be
5812 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5814 /* MAC register can only be of SImode. Otherwise, anything
5816 return regno
== MAC_REG
? mode
== SImode
: 1;
5819 /* Perform target dependent optabs initialization. */
5821 h8300_init_libfuncs (void)
5823 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5824 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5825 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5826 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5827 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5830 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5833 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5835 return (TYPE_MODE (type
) == BLKmode
5836 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5839 /* We emit the entire trampoline here. Depending on the pointer size,
5840 we use a different trampoline.
5844 1 0000 7903xxxx mov.w #0x1234,r3
5845 2 0004 5A00xxxx jmp @0x1234
5850 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5851 3 0006 5Axxxxxx jmp @0x123456
5856 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
5858 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5861 if (Pmode
== HImode
)
5863 mem
= adjust_address (m_tramp
, HImode
, 0);
5864 emit_move_insn (mem
, GEN_INT (0x7903));
5865 mem
= adjust_address (m_tramp
, Pmode
, 2);
5866 emit_move_insn (mem
, cxt
);
5867 mem
= adjust_address (m_tramp
, HImode
, 4);
5868 emit_move_insn (mem
, GEN_INT (0x5a00));
5869 mem
= adjust_address (m_tramp
, Pmode
, 6);
5870 emit_move_insn (mem
, fnaddr
);
5876 mem
= adjust_address (m_tramp
, HImode
, 0);
5877 emit_move_insn (mem
, GEN_INT (0x7a03));
5878 mem
= adjust_address (m_tramp
, Pmode
, 2);
5879 emit_move_insn (mem
, cxt
);
5881 tem
= copy_to_reg (fnaddr
);
5882 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
5883 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
5884 mem
= adjust_address (m_tramp
, SImode
, 6);
5885 emit_move_insn (mem
, tem
);
5889 /* Initialize the GCC target structure. */
5890 #undef TARGET_ATTRIBUTE_TABLE
5891 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5893 #undef TARGET_ASM_ALIGNED_HI_OP
5894 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5896 #undef TARGET_ASM_FILE_START
5897 #define TARGET_ASM_FILE_START h8300_file_start
5898 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5899 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5901 #undef TARGET_ASM_FILE_END
5902 #define TARGET_ASM_FILE_END h8300_file_end
5904 #undef TARGET_ENCODE_SECTION_INFO
5905 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5907 #undef TARGET_INSERT_ATTRIBUTES
5908 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5910 #undef TARGET_RTX_COSTS
5911 #define TARGET_RTX_COSTS h8300_rtx_costs
5913 #undef TARGET_INIT_LIBFUNCS
5914 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5916 #undef TARGET_RETURN_IN_MEMORY
5917 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5919 #undef TARGET_MACHINE_DEPENDENT_REORG
5920 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5922 #undef TARGET_HARD_REGNO_SCRATCH_OK
5923 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5925 #undef TARGET_LEGITIMATE_ADDRESS_P
5926 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5928 #undef TARGET_DEFAULT_TARGET_FLAGS
5929 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5931 #undef TARGET_CAN_ELIMINATE
5932 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5934 #undef TARGET_TRAMPOLINE_INIT
5935 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5937 #undef TARGET_OPTION_OVERRIDE
5938 #define TARGET_OPTION_OVERRIDE h8300_option_override
5940 #undef TARGET_OPTION_OPTIMIZATION
5941 #define TARGET_OPTION_OPTIMIZATION h8300_option_optimization
5943 struct gcc_target targetm
= TARGET_INITIALIZER
;