| blob | 9b739a6c95bf4fcb07205e35de201f4a2b7bb80b |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
59 #ifndef CHECK_STACK_LIMIT
60 #define CHECK_STACK_LIMIT (-1)
61 #endif
63 /* Return index of given mode in mult and division cost tables. */
64 #define MODE_INDEX(mode) \
65 ((mode) == QImode ? 0 \
66 : (mode) == HImode ? 1 \
67 : (mode) == SImode ? 2 \
68 : (mode) == DImode ? 3 \
69 : 4)
71 /* Processor costs (relative to an add) */
72 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
73 #define COSTS_N_BYTES(N) ((N) * 2)
75 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
77 const
100 in QImode, HImode and SImode.
101 Relative to reg-reg move (2). */
105 in SFmode, DFmode and XFmode */
107 in SFmode, DFmode and XFmode */
110 in SImode and DImode */
112 in SImode and DImode */
115 in SImode, DImode and TImode */
117 in SImode, DImode and TImode */
145 };
147 /* Processor costs (relative to an add) */
148 static const
171 in QImode, HImode and SImode.
172 Relative to reg-reg move (2). */
176 in SFmode, DFmode and XFmode */
178 in SFmode, DFmode and XFmode */
181 in SImode and DImode */
183 in SImode and DImode */
186 in SImode, DImode and TImode */
188 in SImode, DImode and TImode */
202 DUMMY_STRINGOP_ALGS},
204 DUMMY_STRINGOP_ALGS},
216 };
218 static const
241 in QImode, HImode and SImode.
242 Relative to reg-reg move (2). */
246 in SFmode, DFmode and XFmode */
248 in SFmode, DFmode and XFmode */
251 in SImode and DImode */
253 in SImode and DImode */
256 in SImode, DImode and TImode */
258 in SImode, DImode and TImode */
261 shared for code and data, so 4kB is
262 not really precise. */
274 DUMMY_STRINGOP_ALGS},
276 DUMMY_STRINGOP_ALGS},
288 };
290 static const
313 in QImode, HImode and SImode.
314 Relative to reg-reg move (2). */
318 in SFmode, DFmode and XFmode */
320 in SFmode, DFmode and XFmode */
323 in SImode and DImode */
325 in SImode and DImode */
328 in SImode, DImode and TImode */
330 in SImode, DImode and TImode */
344 DUMMY_STRINGOP_ALGS},
346 DUMMY_STRINGOP_ALGS},
358 };
360 static const
383 in QImode, HImode and SImode.
384 Relative to reg-reg move (2). */
388 in SFmode, DFmode and XFmode */
390 in SFmode, DFmode and XFmode */
393 in SImode and DImode */
395 in SImode and DImode */
398 in SImode, DImode and TImode */
400 in SImode, DImode and TImode */
413 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
414 the alignment). For small blocks inline loop is still a noticeable win, for bigger
415 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
416 more expensive startup time in CPU, but after 4K the difference is down in the noise.
417 */
420 DUMMY_STRINGOP_ALGS},
423 DUMMY_STRINGOP_ALGS},
435 };
437 static const
460 in QImode, HImode and SImode.
461 Relative to reg-reg move (2). */
465 in SFmode, DFmode and XFmode */
467 in SFmode, DFmode and XFmode */
471 in SImode and DImode */
473 in SImode and DImode */
476 in SImode, DImode and TImode */
478 in SImode, DImode and TImode */
492 DUMMY_STRINGOP_ALGS},
494 DUMMY_STRINGOP_ALGS},
506 };
508 static const
531 in QImode, HImode and SImode.
532 Relative to reg-reg move (2). */
536 in SFmode, DFmode and XFmode */
538 in SFmode, DFmode and XFmode */
541 in SImode and DImode */
543 in SImode and DImode */
546 in SImode, DImode and TImode */
548 in SImode, DImode and TImode */
552 have integrated l2 cache, but
553 optimizing for k6 is not important
554 enough to worry about that. */
565 DUMMY_STRINGOP_ALGS},
567 DUMMY_STRINGOP_ALGS},
579 };
581 static const
604 in QImode, HImode and SImode.
605 Relative to reg-reg move (2). */
609 in SFmode, DFmode and XFmode */
611 in SFmode, DFmode and XFmode */
614 in SImode and DImode */
616 in SImode and DImode */
619 in SImode, DImode and TImode */
621 in SImode, DImode and TImode */
634 /* For some reason, Athlon deals better with REP prefix (relative to loops)
635 compared to K8. Alignment becomes important after 8 bytes for memcpy and
636 128 bytes for memset. */
638 DUMMY_STRINGOP_ALGS},
640 DUMMY_STRINGOP_ALGS},
652 };
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
699 /* New AMD processors never drop prefetches; if they cannot be performed
700 immediately, they are queued. We set number of simultaneous prefetches
701 to a large constant to reflect this (it probably is not a good idea not
702 to limit number of prefetches at all, as their execution also takes some
703 time). */
712 /* K8 has optimized REP instruction for medium sized blocks, but for very small
713 blocks it is better to use loop. For large blocks, libcall can do
714 nontemporary accesses and beat inline considerably. */
731 };
755 in QImode, HImode and SImode.
756 Relative to reg-reg move (2). */
760 in SFmode, DFmode and XFmode */
762 in SFmode, DFmode and XFmode */
765 in SImode and DImode */
767 in SImode and DImode */
770 in SImode, DImode and TImode */
772 in SImode, DImode and TImode */
774 /* On K8
775 MOVD reg64, xmmreg Double FSTORE 4
776 MOVD reg32, xmmreg Double FSTORE 4
777 On AMDFAM10
778 MOVD reg64, xmmreg Double FADD 3
779 1/1 1/1
780 MOVD reg32, xmmreg Double FADD 3
781 1/1 1/1 */
785 /* New AMD processors never drop prefetches; if they cannot be performed
786 immediately, they are queued. We set number of simultaneous prefetches
787 to a large constant to reflect this (it probably is not a good idea not
788 to limit number of prefetches at all, as their execution also takes some
789 time). */
799 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
800 very small blocks it is better to use loop. For large blocks, libcall can
801 do nontemporary accesses and beat inline considerably. */
818 };
820 static const
843 in QImode, HImode and SImode.
844 Relative to reg-reg move (2). */
848 in SFmode, DFmode and XFmode */
850 in SFmode, DFmode and XFmode */
853 in SImode and DImode */
855 in SImode and DImode */
858 in SImode, DImode and TImode */
860 in SImode, DImode and TImode */
874 DUMMY_STRINGOP_ALGS},
877 DUMMY_STRINGOP_ALGS},
889 };
891 static const
914 in QImode, HImode and SImode.
915 Relative to reg-reg move (2). */
919 in SFmode, DFmode and XFmode */
921 in SFmode, DFmode and XFmode */
924 in SImode and DImode */
926 in SImode and DImode */
929 in SImode, DImode and TImode */
931 in SImode, DImode and TImode */
962 };
964 static const
987 in QImode, HImode and SImode.
988 Relative to reg-reg move (2). */
992 in SFmode, DFmode and XFmode */
994 in SFmode, DFmode and XFmode */
997 in SImode and DImode */
999 in SImode and DImode */
1002 in SImode, DImode and TImode */
1004 in SImode, DImode and TImode */
1035 };
1037 static const
1060 in QImode, HImode and SImode.
1061 Relative to reg-reg move (2). */
1065 in SFmode, DFmode and XFmode */
1067 in SFmode, DFmode and XFmode */
1070 in SImode and DImode */
1072 in SImode and DImode */
1075 in SImode, DImode and TImode */
1077 in SImode, DImode and TImode */
1108 };
1110 /* Generic64 should produce code tuned for Nocona and K8. */
1111 static const
1114 /* On all chips taken into consideration lea is 2 cycles and more. With
1115 this cost however our current implementation of synth_mult results in
1116 use of unnecessary temporary registers causing regression on several
1117 SPECfp benchmarks. */
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1143 in SFmode, DFmode and XFmode */
1145 in SFmode, DFmode and XFmode */
1148 in SImode and DImode */
1150 in SImode and DImode */
1153 in SImode, DImode and TImode */
1155 in SImode, DImode and TImode */
1161 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1162 is increased to perhaps more appropriate value of 5. */
1185 };
1187 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1188 static const
1211 in QImode, HImode and SImode.
1212 Relative to reg-reg move (2). */
1216 in SFmode, DFmode and XFmode */
1218 in SFmode, DFmode and XFmode */
1221 in SImode and DImode */
1223 in SImode and DImode */
1226 in SImode, DImode and TImode */
1228 in SImode, DImode and TImode */
1242 DUMMY_STRINGOP_ALGS},
1244 DUMMY_STRINGOP_ALGS},
1256 };
1260 /* Processor feature/optimization bitmasks. */
1261 #define m_386 (1<<PROCESSOR_I386)
1262 #define m_486 (1<<PROCESSOR_I486)
1263 #define m_PENT (1<<PROCESSOR_PENTIUM)
1264 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1265 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1266 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1267 #define m_CORE2 (1<<PROCESSOR_CORE2)
1268 #define m_ATOM (1<<PROCESSOR_ATOM)
1270 #define m_GEODE (1<<PROCESSOR_GEODE)
1271 #define m_K6 (1<<PROCESSOR_K6)
1272 #define m_K6_GEODE (m_K6 | m_GEODE)
1273 #define m_K8 (1<<PROCESSOR_K8)
1274 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1275 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1276 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1277 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1279 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1280 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1282 /* Generic instruction choice should be common subset of supported CPUs
1283 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1284 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1286 /* Feature tests against the various tunings. */
1289 /* Feature tests against the various tunings used to create ix86_tune_features
1290 based on the processor mask. */
1292 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1293 negatively, so enabling for Generic64 seems like good code size
1294 tradeoff. We can't enable it for 32bit generic because it does not
1295 work well with PPro base chips. */
1298 /* X86_TUNE_PUSH_MEMORY */
1302 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1305 /* X86_TUNE_UNROLL_STRLEN */
1309 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1312 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1313 on simulation result. But after P4 was made, no performance benefit
1314 was observed with branch hints. It also increases the code size.
1315 As a result, icc never generates branch hints. */
1318 /* X86_TUNE_DOUBLE_WITH_ADD */
1321 /* X86_TUNE_USE_SAHF */
1325 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1326 partial dependencies. */
1330 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1331 register stalls on Generic32 compilation setting as well. However
1332 in current implementation the partial register stalls are not eliminated
1333 very well - they can be introduced via subregs synthesized by combine
1334 and can happen in caller/callee saving sequences. Because this option
1335 pays back little on PPro based chips and is in conflict with partial reg
1336 dependencies used by Athlon/P4 based chips, it is better to leave it off
1337 for generic32 for now. */
1338 m_PPRO,
1340 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1343 /* X86_TUNE_USE_HIMODE_FIOP */
1346 /* X86_TUNE_USE_SIMODE_FIOP */
1349 /* X86_TUNE_USE_MOV0 */
1350 m_K6,
1352 /* X86_TUNE_USE_CLTD */
1355 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1356 m_PENT4,
1358 /* X86_TUNE_SPLIT_LONG_MOVES */
1359 m_PPRO,
1361 /* X86_TUNE_READ_MODIFY_WRITE */
1364 /* X86_TUNE_READ_MODIFY */
1367 /* X86_TUNE_PROMOTE_QIMODE */
1371 /* X86_TUNE_FAST_PREFIX */
1374 /* X86_TUNE_SINGLE_STRINGOP */
1377 /* X86_TUNE_QIMODE_MATH */
1380 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1381 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1382 might be considered for Generic32 if our scheme for avoiding partial
1383 stalls was more effective. */
1386 /* X86_TUNE_PROMOTE_QI_REGS */
1389 /* X86_TUNE_PROMOTE_HI_REGS */
1390 m_PPRO,
1392 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1396 /* X86_TUNE_ADD_ESP_8 */
1400 /* X86_TUNE_SUB_ESP_4 */
1404 /* X86_TUNE_SUB_ESP_8 */
1408 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1409 for DFmode copies */
1413 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1416 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1417 conflict here in between PPro/Pentium4 based chips that thread 128bit
1418 SSE registers as single units versus K8 based chips that divide SSE
1419 registers to two 64bit halves. This knob promotes all store destinations
1420 to be 128bit to allow register renaming on 128bit SSE units, but usually
1421 results in one extra microop on 64bit SSE units. Experimental results
1422 shows that disabling this option on P4 brings over 20% SPECfp regression,
1423 while enabling it on K8 brings roughly 2.4% regression that can be partly
1424 masked by careful scheduling of moves. */
1428 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1429 m_AMDFAM10,
1431 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1432 are resolved on SSE register parts instead of whole registers, so we may
1433 maintain just lower part of scalar values in proper format leaving the
1434 upper part undefined. */
1435 m_ATHLON_K8,
1437 /* X86_TUNE_SSE_TYPELESS_STORES */
1438 m_AMD_MULTIPLE,
1440 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1443 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1446 /* X86_TUNE_PROLOGUE_USING_MOVE */
1449 /* X86_TUNE_EPILOGUE_USING_MOVE */
1452 /* X86_TUNE_SHIFT1 */
1455 /* X86_TUNE_USE_FFREEP */
1456 m_AMD_MULTIPLE,
1458 /* X86_TUNE_INTER_UNIT_MOVES */
1461 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1464 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1465 than 4 branch instructions in the 16 byte window. */
1469 /* X86_TUNE_SCHEDULE */
1473 /* X86_TUNE_USE_BT */
1476 /* X86_TUNE_USE_INCDEC */
1479 /* X86_TUNE_PAD_RETURNS */
1482 /* X86_TUNE_EXT_80387_CONSTANTS */
1486 /* X86_TUNE_SHORTEN_X87_SSE */
1489 /* X86_TUNE_AVOID_VECTOR_DECODE */
1492 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1493 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1496 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1497 vector path on AMD machines. */
1500 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1501 machines. */
1504 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1505 than a MOV. */
1506 m_PENT,
1508 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1509 but one byte longer. */
1510 m_PENT,
1512 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1513 operand that cannot be represented using a modRM byte. The XOR
1514 replacement is long decoded, so this split helps here as well. */
1515 m_K6,
1517 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1518 from FP to FP. */
1521 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1522 from integer to FP. */
1523 m_AMDFAM10,
1525 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1526 with a subsequent conditional jump instruction into a single
1527 compare-and-branch uop. */
1528 m_CORE2,
1530 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1531 will impact LEA instruction selection. */
1532 m_ATOM,
1533 };
1535 /* Feature tests against the various architecture variations. */
1538 /* Feature tests against the various architecture variations, used to create
1539 ix86_arch_features based on the processor mask. */
1541 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1544 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1547 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1550 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1553 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1555 };
1557 static const unsigned int x86_accumulate_outgoing_args
1561 static const unsigned int x86_arch_always_fancy_math_387
1567 /* In case the average insn count for single function invocation is
1568 lower than this constant, emit fast (but longer) prologue and
1569 epilogue code. */
1570 #define FAST_PROLOGUE_INSN_COUNT 20
1572 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1577 /* Array of the smallest class containing reg number REGNO, indexed by
1578 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 {
1582 /* ax, dx, cx, bx */
1584 /* si, di, bp, sp */
1586 /* FP registers */
1589 /* arg pointer */
1590 NON_Q_REGS,
1591 /* flags, fpsr, fpcr, frame */
1593 /* SSE registers */
1596 /* MMX registers */
1599 /* REX registers */
1602 /* SSE REX registers */
1605 };
1607 /* The "default" register map used in 32bit mode. */
1610 {
1618 };
1620 /* The "default" register map used in 64bit mode. */
1623 {
1631 };
1633 /* Define the register numbers to be used in Dwarf debugging information.
1634 The SVR4 reference port C compiler uses the following register numbers
1635 in its Dwarf output code:
1636 0 for %eax (gcc regno = 0)
1637 1 for %ecx (gcc regno = 2)
1638 2 for %edx (gcc regno = 1)
1639 3 for %ebx (gcc regno = 3)
1640 4 for %esp (gcc regno = 7)
1641 5 for %ebp (gcc regno = 6)
1642 6 for %esi (gcc regno = 4)
1643 7 for %edi (gcc regno = 5)
1644 The following three DWARF register numbers are never generated by
1645 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1646 believes these numbers have these meanings.
1647 8 for %eip (no gcc equivalent)
1648 9 for %eflags (gcc regno = 17)
1649 10 for %trapno (no gcc equivalent)
1650 It is not at all clear how we should number the FP stack registers
1651 for the x86 architecture. If the version of SDB on x86/svr4 were
1652 a bit less brain dead with respect to floating-point then we would
1653 have a precedent to follow with respect to DWARF register numbers
1654 for x86 FP registers, but the SDB on x86/svr4 is so completely
1655 broken with respect to FP registers that it is hardly worth thinking
1656 of it as something to strive for compatibility with.
1657 The version of x86/svr4 SDB I have at the moment does (partially)
1658 seem to believe that DWARF register number 11 is associated with
1659 the x86 register %st(0), but that's about all. Higher DWARF
1660 register numbers don't seem to be associated with anything in
1661 particular, and even for DWARF regno 11, SDB only seems to under-
1662 stand that it should say that a variable lives in %st(0) (when
1663 asked via an `=' command) if we said it was in DWARF regno 11,
1664 but SDB still prints garbage when asked for the value of the
1665 variable in question (via a `/' command).
1666 (Also note that the labels SDB prints for various FP stack regs
1667 when doing an `x' command are all wrong.)
1668 Note that these problems generally don't affect the native SVR4
1669 C compiler because it doesn't allow the use of -O with -g and
1670 because when it is *not* optimizing, it allocates a memory
1671 location for each floating-point variable, and the memory
1672 location is what gets described in the DWARF AT_location
1673 attribute for the variable in question.
1674 Regardless of the severe mental illness of the x86/svr4 SDB, we
1675 do something sensible here and we use the following DWARF
1676 register numbers. Note that these are all stack-top-relative
1677 numbers.
1678 11 for %st(0) (gcc regno = 8)
1679 12 for %st(1) (gcc regno = 9)
1680 13 for %st(2) (gcc regno = 10)
1681 14 for %st(3) (gcc regno = 11)
1682 15 for %st(4) (gcc regno = 12)
1683 16 for %st(5) (gcc regno = 13)
1684 17 for %st(6) (gcc regno = 14)
1685 18 for %st(7) (gcc regno = 15)
1686 */
1688 {
1696 };
1698 /* Test and compare insns in i386.md store the information needed to
1699 generate branch and scc insns here. */
1704 /* Define parameter passing and return registers. */
1707 {
1709 };
1712 {
1714 };
1717 {
1719 };
1721 /* Define the structure for the machine field in struct function. */
1726 rtx rtl;
1728 };
1730 /* Structure describing stack frame layout.
1731 Stack grows downward:
1733 [arguments]
1734 <- ARG_POINTER
1735 saved pc
1737 saved frame pointer if frame_pointer_needed
1738 <- HARD_FRAME_POINTER
1739 [saved regs]
1741 [padding0]
1743 [saved SSE regs]
1745 [padding1] \
1746 )
1747 [va_arg registers] (
1748 > to_allocate <- FRAME_POINTER
1749 [frame] (
1750 )
1751 [padding2] /
1752 */
1753 struct ix86_frame
1754 {
1760 HOST_WIDE_INT frame;
1765 HOST_WIDE_INT to_allocate;
1766 /* The offsets relative to ARG_POINTER. */
1767 HOST_WIDE_INT frame_pointer_offset;
1768 HOST_WIDE_INT hard_frame_pointer_offset;
1769 HOST_WIDE_INT stack_pointer_offset;
1771 /* When save_regs_using_mov is set, emit prologue using
1772 move instead of push instructions. */
1774 };
1776 /* Code model option. */
1778 /* Asm dialect. */
1780 /* TLS dialects. */
1783 /* Which unit we are generating floating point math for. */
1786 /* Which cpu are we scheduling for. */
1789 /* Which cpu are we optimizing for. */
1792 /* Which instruction set architecture to use. */
1795 /* true if sse prefetch instruction is not NOOP. */
1798 /* ix86_regparm_string as a number */
1801 /* -mstackrealign option */
1815 /* Preferred alignment for stack boundary in bits. */
1818 /* Alignment for incoming stack boundary in bits specified at
1819 command line. */
1822 /* Default alignment for incoming stack boundary in bits. */
1825 /* Alignment for incoming stack boundary in bits. */
1828 /* The abi used by target. */
1831 /* Values 1-5: see jump.c */
1834 /* Calling abi specific va_list type nodes. */
1838 /* Variables which are this size or smaller are put in the data/bss
1839 or ldata/lbss sections. */
1843 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1847 /* Fence to use after loop using movnt. */
1848 tree x86_mfence;
1850 /* Register class used for passing given 64bit part of the argument.
1851 These represent classes as documented by the PS ABI, with the exception
1852 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1853 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1855 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1856 whenever possible (upper half does contain padding). */
1857 enum x86_64_reg_class
1858 {
1859 X86_64_NO_CLASS,
1860 X86_64_INTEGER_CLASS,
1861 X86_64_INTEGERSI_CLASS,
1862 X86_64_SSE_CLASS,
1863 X86_64_SSESF_CLASS,
1864 X86_64_SSEDF_CLASS,
1865 X86_64_SSEUP_CLASS,
1866 X86_64_X87_CLASS,
1867 X86_64_X87UP_CLASS,
1868 X86_64_COMPLEX_X87_CLASS,
1869 X86_64_MEMORY_CLASS
1870 };
1872 #define MAX_CLASSES 4
1874 /* Table of constants used by fldpi, fldln2, etc.... */
1878 \f
1889 enum ix86_function_specific_strings
1890 {
1891 IX86_FUNCTION_SPECIFIC_ARCH,
1892 IX86_FUNCTION_SPECIFIC_TUNE,
1893 IX86_FUNCTION_SPECIFIC_FPMATH,
1894 IX86_FUNCTION_SPECIFIC_MAX
1895 };
1912 \f
1913 /* The svr4 ABI for the i386 says that records and unions are returned
1914 in memory. */
1915 #ifndef DEFAULT_PCC_STRUCT_RETURN
1916 #define DEFAULT_PCC_STRUCT_RETURN 1
1917 #endif
1919 /* Whether -mtune= or -march= were specified */
1923 /* Bit flags that specify the ISA we are compiling for. */
1926 /* A mask of ix86_isa_flags that includes bit X if X
1927 was set or cleared on the command line. */
1930 /* Define a set of ISAs which are available when a given ISA is
1931 enabled. MMX and SSE ISAs are handled separately. */
1933 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1934 #define OPTION_MASK_ISA_3DNOW_SET \
1935 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1937 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1938 #define OPTION_MASK_ISA_SSE2_SET \
1939 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1940 #define OPTION_MASK_ISA_SSE3_SET \
1941 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1942 #define OPTION_MASK_ISA_SSSE3_SET \
1943 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1944 #define OPTION_MASK_ISA_SSE4_1_SET \
1945 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1946 #define OPTION_MASK_ISA_SSE4_2_SET \
1947 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1948 #define OPTION_MASK_ISA_AVX_SET \
1949 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1950 #define OPTION_MASK_ISA_FMA_SET \
1951 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1953 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1954 as -msse4.2. */
1955 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1957 #define OPTION_MASK_ISA_SSE4A_SET \
1958 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1959 #define OPTION_MASK_ISA_FMA4_SET \
1960 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1961 | OPTION_MASK_ISA_AVX_SET)
1962 #define OPTION_MASK_ISA_XOP_SET \
1963 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
1964 #define OPTION_MASK_ISA_LWP_SET \
1965 OPTION_MASK_ISA_LWP
1967 /* AES and PCLMUL need SSE2 because they use xmm registers */
1968 #define OPTION_MASK_ISA_AES_SET \
1969 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1970 #define OPTION_MASK_ISA_PCLMUL_SET \
1971 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1973 #define OPTION_MASK_ISA_ABM_SET \
1974 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1976 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1977 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1978 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1979 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1980 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1982 /* Define a set of ISAs which aren't available when a given ISA is
1983 disabled. MMX and SSE ISAs are handled separately. */
1985 #define OPTION_MASK_ISA_MMX_UNSET \
1986 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1987 #define OPTION_MASK_ISA_3DNOW_UNSET \
1988 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1989 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1991 #define OPTION_MASK_ISA_SSE_UNSET \
1992 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1993 #define OPTION_MASK_ISA_SSE2_UNSET \
1994 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1995 #define OPTION_MASK_ISA_SSE3_UNSET \
1996 (OPTION_MASK_ISA_SSE3 \
1997 | OPTION_MASK_ISA_SSSE3_UNSET \
1998 | OPTION_MASK_ISA_SSE4A_UNSET )
1999 #define OPTION_MASK_ISA_SSSE3_UNSET \
2000 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2001 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2002 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2003 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2004 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2005 #define OPTION_MASK_ISA_AVX_UNSET \
2006 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2007 | OPTION_MASK_ISA_FMA4_UNSET)
2008 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2010 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2011 as -mno-sse4.1. */
2012 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2014 #define OPTION_MASK_ISA_SSE4A_UNSET \
2015 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2017 #define OPTION_MASK_ISA_FMA4_UNSET \
2018 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2019 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2020 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2022 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2023 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2024 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2025 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2026 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2027 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2028 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2029 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2031 /* Vectorization library interface and handlers. */
2036 /* Processor target table, indexed by processor number */
2037 struct ptt
2038 {
2045 };
2048 {
2064 };
2067 {
2089 "amdfam10"
2090 };
2091 \f
2092 /* Implement TARGET_HANDLE_OPTION. */
2094 static bool
2096 {
2098 {
2101 {
2104 }
2105 else
2106 {
2109 }
2114 {
2117 }
2118 else
2119 {
2122 }
2130 {
2133 }
2134 else
2135 {
2138 }
2143 {
2146 }
2147 else
2148 {
2151 }
2156 {
2159 }
2160 else
2161 {
2164 }
2169 {
2172 }
2173 else
2174 {
2177 }
2182 {
2185 }
2186 else
2187 {
2190 }
2195 {
2198 }
2199 else
2200 {
2203 }
2208 {
2211 }
2212 else
2213 {
2216 }
2221 {
2224 }
2225 else
2226 {
2229 }
2244 {
2247 }
2248 else
2249 {
2252 }
2257 {
2260 }
2261 else
2262 {
2265 }
2270 {
2273 }
2274 else
2275 {
2278 }
2283 {
2286 }
2287 else
2288 {
2291 }
2296 {
2299 }
2300 else
2301 {
2304 }
2309 {
2312 }
2313 else
2314 {
2317 }
2322 {
2325 }
2326 else
2327 {
2330 }
2335 {
2338 }
2339 else
2340 {
2343 }
2348 {
2351 }
2352 else
2353 {
2356 }
2361 {
2364 }
2365 else
2366 {
2369 }
2374 {
2377 }
2378 else
2379 {
2382 }
2387 {
2390 }
2391 else
2392 {
2395 }
2400 }
2401 }
2402 \f
2403 /* Return a string the documents the current -m options. The caller is
2404 responsible for freeing the string. */
2409 {
2410 struct ix86_target_opts
2411 {
2414 };
2416 /* This table is ordered so that options like -msse4.2 that imply
2417 preceding options while match those first. */
2419 {
2440 };
2442 /* Flag options. */
2444 {
2465 };
2481 /* Add -march= option. */
2483 {
2486 }
2488 /* Add -mtune= option. */
2490 {
2493 }
2495 /* Pick out the options in isa options. */
2497 {
2499 {
2502 }
2503 }
2506 {
2509 }
2511 /* Add flag options. */
2513 {
2515 {
2518 }
2519 }
2522 {
2525 }
2527 /* Add -fpmath= option. */
2529 {
2532 }
2534 /* Any options? */
2540 /* Size the string. */
2544 {
2549 }
2551 /* Build the string. */
2556 {
2563 {
2565 line_len++;
2568 {
2572 }
2573 }
2577 {
2581 }
2582 }
2588 }
2590 /* Function that is callable from the debugger to print the current
2591 options. */
2592 void
2594 {
2600 {
2603 }
2604 else
2608 }
2609 \f
2610 /* Sometimes certain combinations of command options do not make
2611 sense on a particular target machine. You can define a macro
2612 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2613 defined, is executed once just after all the command options have
2614 been parsed.
2616 Don't use this macro to turn on various extra optimizations for
2617 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2619 void
2621 {
2628 /* Comes from final.c -- no real reason to change it. */
2629 #define MAX_CODE_ALIGN 16
2631 enum pta_flags
2632 {
2657 };
2659 static struct pta
2660 {
2665 }
2667 {
2749 };
2753 /* Set up prefix/suffix so the error messages refer to either the command
2754 line argument, or the attribute(target). */
2756 {
2760 }
2761 else
2762 {
2766 }
2768 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2769 SUBTARGET_OVERRIDE_OPTIONS;
2770 #endif
2772 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2773 SUBSUBTARGET_OVERRIDE_OPTIONS;
2774 #endif
2776 /* -fPIC is the default for x86_64. */
2780 /* Set the default values for switches whose default depends on TARGET_64BIT
2781 in case they weren't overwritten by command line options. */
2783 {
2784 /* Mach-O doesn't support omitting the frame pointer for now. */
2791 }
2792 else
2793 {
2800 }
2802 /* Need to check -mtune=generic first. */
2804 {
2807 /* As special support for cross compilers we read -mtune=native
2808 as -mtune=generic. With native compilers we won't see the
2809 -mtune=native, as it was changed by the driver. */
2811 {
2814 else
2816 }
2817 /* If this call is for setting the option attribute, allow the
2818 generic32/generic64 that was previously set. */
2822 ;
2826 }
2827 else
2828 {
2832 {
2835 }
2837 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2838 need to use a sensible tune option. */
2842 {
2845 else
2847 }
2848 }
2850 {
2859 /* rep; movq isn't available in 32-bit code. */
2867 else
2870 }
2878 else
2888 /* Validate -mabi= value. */
2890 {
2895 else
2898 }
2899 else
2903 {
2916 else
2919 }
2920 else
2921 {
2922 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2923 use of rip-relative addressing. This eliminates fixups that
2924 would otherwise be needed if this object is to be placed in a
2925 DLL, and is essentially just as efficient as direct addressing. */
2930 else
2932 }
2934 {
2940 else
2943 }
2953 {
2956 /* Default cpu tuning to the architecture. */
3033 }
3045 {
3049 {
3051 {
3059 }
3060 else
3063 }
3064 /* Intel CPUs have always interpreted SSE prefetch instructions as
3065 NOPs; so, we can enable SSE prefetch instructions even when
3066 -mtune (rather than -march) points us to a processor that has them.
3067 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3068 higher processors. */
3073 }
3084 else
3087 /* Arrange to set up i386_stack_locals for all functions. */
3090 /* Validate -mregparm= value. */
3092 {
3099 else
3101 }
3105 /* If the user has provided any of the -malign-* options,
3106 warn and use that value only if -falign-* is not set.
3107 Remove this code in GCC 3.2 or later. */
3109 {
3113 {
3118 else
3120 }
3121 }
3124 {
3128 {
3133 else
3135 }
3136 }
3139 {
3143 {
3148 else
3150 }
3151 }
3153 /* Default align_* from the processor table. */
3155 {
3158 }
3160 {
3163 }
3165 {
3167 }
3169 /* Validate -mbranch-cost= value, or provide default. */
3172 {
3176 else
3178 }
3180 {
3184 else
3186 }
3189 {
3196 else
3199 }
3202 {
3206 }
3209 {
3212 /* Enable by default the SSE and MMX builtins. Do allow the user to
3213 explicitly disable any of these. In particular, disabling SSE and
3214 MMX for kernel code is extremely useful. */
3216 ix86_isa_flags
3222 }
3223 else
3224 {
3228 ix86_isa_flags
3231 /* i386 ABI does not specify red zone. It still makes sense to use it
3232 when programmer takes care to stack from being destroyed. */
3235 }
3237 /* Keep nonleaf frame pointers. */
3243 /* If we're doing fast math, we don't care about comparison order
3244 wrt NaNs. This lets us use a shorter comparison sequence. */
3248 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3249 since the insns won't need emulation. */
3253 /* Likewise, if the target doesn't have a 387, or we've specified
3254 software floating point, don't use 387 inline intrinsics. */
3258 /* Turn on MMX builtins for -msse. */
3260 {
3263 }
3265 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3269 /* Validate -mpreferred-stack-boundary= value or default it to
3270 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3273 {
3278 else
3280 }
3282 /* Set the default value for -mstackrealign. */
3288 /* Validate -mincoming-stack-boundary= value or default it to
3289 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3292 {
3297 else
3298 {
3300 ix86_incoming_stack_boundary
3302 }
3303 }
3305 /* Accept -msseregparm only if at least SSE support is enabled. */
3312 {
3316 {
3318 {
3321 }
3322 else
3324 }
3330 {
3332 {
3335 }
3337 {
3340 }
3341 else
3343 }
3344 else
3347 }
3349 /* If the i387 is disabled, then do not return values in it. */
3353 /* Use external vectorized library in vectorizing intrinsics. */
3355 {
3360 else
3364 }
3371 /* ??? Unwind info is not correct around the CFG unless either a frame
3372 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3373 unwind info generation to be aware of the CFG and propagating states
3374 around edges. */
3377 && flag_omit_frame_pointer
3379 {
3385 }
3387 /* If stack probes are required, the space used for large function
3388 arguments on the stack must also be probed, so enable
3389 -maccumulate-outgoing-args so this happens in the prologue. */
3392 {
3397 }
3399 /* For sane SSE instruction set generation we need fcomi instruction.
3400 It is safe to enable all CMOVE instructions. */
3404 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3405 {
3411 }
3413 /* When scheduling description is not available, disable scheduler pass
3414 so it won't slow down the compilation and make x87 code slower. */
3428 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3429 can be optimized to ap = __builtin_next_arg (0). */
3434 {
3443 }
3444 else
3445 {
3454 }
3456 #ifdef USE_IX86_CLD
3457 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3460 #endif
3462 /* Save the initial options in case the user does function specific options */
3464 target_option_default_node = target_option_current_node
3466 }
3468 /* Update register usage after having seen the compiler flags. */
3470 void
3472 {
3477 {
3482 }
3484 /* The PIC register, if it exists, is fixed. */
3489 /* The MS_ABI changes the set of call-used registers. */
3491 {
3498 }
3500 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3501 other call-clobbered regs for 64-bit. */
3503 {
3510 }
3512 /* If MMX is disabled, squash the registers. */
3518 /* If SSE is disabled, squash the registers. */
3524 /* If the FPU is disabled, squash the registers. */
3530 /* If 32-bit, squash the 64-bit registers. */
3532 {
3537 }
3538 }
3540 \f
3541 /* Save the current options */
3543 static void
3545 {
3556 /* The fields are char but the variables are not; make sure the
3557 values fit in the fields. */
3563 }
3565 /* Restore the current options */
3567 static void
3569 {
3585 /* Recreate the arch feature tests if the arch changed */
3587 {
3592 }
3594 /* Recreate the tune optimization tests */
3596 {
3601 }
3602 }
3604 /* Print the current options */
3606 static void
3609 {
3634 {
3637 }
3638 }
3640 \f
3641 /* Inner function to process the attribute((target(...))), take an argument and
3642 set the current options from the argument. If we have a list, recursively go
3643 over the list. */
3645 static bool
3647 {
3651 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3652 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3653 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3654 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3656 enum ix86_opt_type
3657 {
3658 ix86_opt_unknown,
3659 ix86_opt_yes,
3660 ix86_opt_no,
3661 ix86_opt_str,
3662 ix86_opt_isa
3663 };
3665 static const struct
3666 {
3673 /* isa options */
3693 /* string options */
3698 /* flag options */
3700 OPT_mcld,
3701 MASK_CLD),
3704 OPT_mfancy_math_387,
3705 MASK_NO_FANCY_MATH_387),
3708 OPT_mieee_fp,
3709 MASK_IEEE_FP),
3712 OPT_minline_all_stringops,
3713 MASK_INLINE_ALL_STRINGOPS),
3716 OPT_minline_stringops_dynamically,
3717 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3720 OPT_mno_align_stringops,
3721 MASK_NO_ALIGN_STRINGOPS),
3724 OPT_mrecip,
3725 MASK_RECIP),
3727 };
3729 /* If this is a list, recurse to get the options. */
3731 {
3740 }
3745 /* Handle multiple arguments separated by commas. */
3749 {
3763 {
3767 }
3768 else
3769 {
3772 }
3774 /* Recognize no-xxx. */
3776 {
3780 }
3781 else
3784 /* Find the option. */
3788 {
3794 {
3799 }
3800 }
3802 /* Process the option. */
3804 {
3807 }
3813 {
3819 else
3821 }
3824 {
3826 {
3829 }
3830 else
3832 }
3834 else
3836 }
3839 }
3841 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3843 tree
3845 {
3857 /* Process each of the options on the chain. */
3861 /* If the changed options are different from the default, rerun override_options,
3862 and then save the options away. The string options are are attribute options,
3863 and will be undone when we copy the save structure. */
3869 {
3870 /* If we are using the default tune= or arch=, undo the string assigned,
3871 and use the default. */
3882 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3888 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3891 /* Add any builtin functions with the new isa if any. */
3894 /* Save the current options unless we are validating options for
3895 #pragma. */
3902 /* Free up memory allocated to hold the strings */
3906 }
3909 }
3911 /* Hook to validate attribute((target("string"))). */
3913 static bool
3916 tree args,
3918 {
3925 /* If the function changed the optimization levels as well as setting target
3926 options, start with the optimizations specified. */
3930 /* The target attributes may also change some optimization flags, so update
3931 the optimization options if necessary. */
3940 {
3945 }
3953 }
3955 \f
3956 /* Hook to determine if one function can safely inline another. */
3958 static bool
3960 {
3965 /* If callee has no option attributes, then it is ok to inline. */
3969 /* If caller has no option attributes, but callee does then it is not ok to
3970 inline. */
3974 else
3975 {
3979 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3980 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3981 function. */
3986 /* See if we have the same non-isa options. */
3990 /* See if arch, tune, etc. are the same. */
4003 else
4005 }
4008 }
4010 \f
4011 /* Remember the last target of ix86_set_current_function. */
4014 /* Establish appropriate back-end context for processing the function
4015 FNDECL. The argument might be NULL to indicate processing at top
4016 level, outside of any function scope. */
4017 static void
4019 {
4020 /* Only change the context if the function changes. This hook is called
4021 several times in the course of compiling a function, and we don't want to
4022 slow things down too much or call target_reinit when it isn't safe. */
4024 {
4025 tree old_tree = (ix86_previous_fndecl
4029 tree new_tree = (fndecl
4035 ;
4038 {
4041 }
4044 {
4050 }
4051 }
4052 }
4054 \f
4055 /* Return true if this goes in large data/bss. */
4057 static bool
4059 {
4063 /* Functions are never large data. */
4068 {
4074 }
4075 else
4076 {
4079 /* If this is an incomplete type with size 0, then we can't put it
4080 in data because it might be too big when completed. */
4083 }
4086 }
4088 /* Switch to the appropriate section for output of DECL.
4089 DECL is either a `VAR_DECL' node or a constant of some sort.
4090 RELOC indicates whether forming the initial value of DECL requires
4091 link-time relocations. */
4094 ATTRIBUTE_UNUSED;
4099 {
4102 {
4106 {
4140 /* We don't split these for medium model. Place them into
4141 default sections and hope for best. */
4146 }
4148 {
4149 /* We might get called with string constants, but get_named_section
4150 doesn't like them as they are not DECLs. Also, we need to set
4151 flags in that case. */
4155 }
4156 }
4158 }
4160 /* Build up a unique section name, expressed as a
4161 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4162 RELOC indicates whether the initial value of EXP requires
4163 link-time relocations. */
4165 static void ATTRIBUTE_UNUSED
4167 {
4170 {
4172 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4176 {
4200 /* We don't split these for medium model. Place them into
4201 default sections and hope for best. */
4209 }
4211 {
4218 /* If we're using one_only, then there needs to be a .gnu.linkonce
4219 prefix to the section name. */
4226 }
4227 }
4229 }
4231 #ifdef COMMON_ASM_OP
4232 /* This says how to output assembler code to declare an
4233 uninitialized external linkage data object.
4235 For medium model x86-64 we need to use .largecomm opcode for
4236 large objects. */
4237 void
4241 {
4245 else
4250 }
4251 #endif
4253 /* Utility function for targets to use in implementing
4254 ASM_OUTPUT_ALIGNED_BSS. */
4256 void
4260 {
4264 else
4267 #ifdef ASM_DECLARE_OBJECT_NAME
4270 #else
4271 /* Standard thing is just output label for the object. */
4275 }
4276 \f
4277 void
4279 {
4280 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4281 make the problem with not enough registers even worse. */
4282 #ifdef INSN_SCHEDULING
4285 #endif
4288 /* The Darwin libraries never set errno, so we might as well
4289 avoid calling them when that's the only reason we would. */
4292 /* The default values of these switches depend on the TARGET_64BIT
4293 that is not known at this moment. Mark these values with 2 and
4294 let user the to override these. In case there is no command line option
4295 specifying them, we will set the defaults in override_options. */
4301 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4302 SUBTARGET_OPTIMIZATION_OPTIONS;
4303 #endif
4304 }
4305 \f
4306 /* Decide whether we can make a sibling call to a function. DECL is the
4307 declaration of the function being targeted by the call and EXP is the
4308 CALL_EXPR representing the call. */
4310 static bool
4312 {
4316 /* If we are generating position-independent code, we cannot sibcall
4317 optimize any indirect call, or a direct call to a global function,
4318 as the PLT requires %ebx be live. */
4322 /* If we need to align the outgoing stack, then sibcalling would
4323 unalign the stack, which may break the called function. */
4329 {
4332 }
4333 else
4334 {
4335 /* We're looking at the CALL_EXPR, we need the type of the function. */
4340 }
4342 /* Check that the return value locations are the same. Like
4343 if we are returning floats on the 80387 register stack, we cannot
4344 make a sibcall from a function that doesn't return a float to a
4345 function that does or, conversely, from a function that does return
4346 a float to a function that doesn't; the necessary stack adjustment
4347 would not be executed. This is also the place we notice
4348 differences in the return value ABI. Note that it is ok for one
4349 of the functions to have void return type as long as the return
4350 value of the other is passed in a register. */
4355 {
4358 }
4360 ;
4365 {
4366 /* The SYSV ABI has more call-clobbered registers;
4367 disallow sibcalls from MS to SYSV. */
4371 }
4372 else
4373 {
4374 /* If this call is indirect, we'll need to be able to use a
4375 call-clobbered register for the address of the target function.
4376 Make sure that all such registers are not used for passing
4377 parameters. Note that DLLIMPORT functions are indirect. */
4380 {
4382 {
4383 /* ??? Need to count the actual number of registers to be used,
4384 not the possible number of registers. Fix later. */
4386 }
4387 }
4388 }
4390 /* Otherwise okay. That also includes certain types of indirect calls. */
4392 }
4394 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4395 calling convention attributes;
4396 arguments as in struct attribute_spec.handler. */
4398 static tree
4400 tree args,
4403 {
4408 {
4410 name);
4413 }
4415 /* Can combine regparm with all attributes but fastcall. */
4417 {
4418 tree cst;
4421 {
4423 }
4427 {
4430 name);
4432 }
4434 {
4438 }
4441 }
4444 {
4445 /* Do not warn when emulating the MS ABI. */
4449 name);
4452 }
4454 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4456 {
4458 {
4460 }
4462 {
4464 }
4466 {
4468 }
4469 }
4471 /* Can combine stdcall with fastcall (redundant), regparm and
4472 sseregparm. */
4474 {
4476 {
4478 }
4480 {
4482 }
4483 }
4485 /* Can combine cdecl with regparm and sseregparm. */
4487 {
4489 {
4491 }
4493 {
4495 }
4496 }
4498 /* Can combine sseregparm with all attributes. */
4501 }
4503 /* Return 0 if the attributes for two types are incompatible, 1 if they
4504 are compatible, and 2 if they are nearly compatible (which causes a
4505 warning to be generated). */
4507 static int
4509 {
4510 /* Check for mismatch of non-default calling convention. */
4517 /* Check for mismatched fastcall/regparm types. */
4524 /* Check for mismatched sseregparm types. */
4529 /* Check for mismatched return types (cdecl vs stdcall). */
4535 }
4536 \f
4537 /* Return the regparm value for a function with the indicated TYPE and DECL.
4538 DECL may be NULL when calling function indirectly
4539 or considering a libcall. */
4541 static int
4543 {
4544 tree attr;
4554 {
4557 }
4562 /* Use register calling convention for local functions when possible. */
4565 && optimize
4567 {
4568 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4571 {
4574 /* Make sure no regparm register is taken by a
4575 fixed register variable. */
4580 /* We don't want to use regparm(3) for nested functions as
4581 these use a static chain pointer in the third argument. */
4585 /* Each fixed register usage increases register pressure,
4586 so less registers should be used for argument passing.
4587 This functionality can be overriden by an explicit
4588 regparm value. */
4591 globals++;
4593 local_regparm
4598 }
4599 }
4602 }
4604 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4605 DFmode (2) arguments in SSE registers for a function with the
4606 indicated TYPE and DECL. DECL may be NULL when calling function
4607 indirectly or considering a libcall. Otherwise return 0. */
4609 static int
4611 {
4614 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4615 by the sseregparm attribute. */
4618 {
4620 {
4622 {
4626 else
4629 }
4631 }
4634 }
4636 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4637 (and DFmode for SSE2) arguments in SSE registers. */
4639 {
4640 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4644 }
4647 }
4649 /* Return true if EAX is live at the start of the function. Used by
4650 ix86_expand_prologue to determine if we need special help before
4651 calling allocate_stack_worker. */
4653 static bool
4655 {
4656 /* Cheat. Don't bother working forward from ix86_function_regparm
4657 to the function type to whether an actual argument is located in
4658 eax. Instead just look at cfg info, which is still close enough
4659 to correct at this point. This gives false positives for broken
4660 functions that might use uninitialized data that happens to be
4661 allocated in eax, but who cares? */
4663 }
4665 /* Value is the number of bytes of arguments automatically
4666 popped when returning from a subroutine call.
4667 FUNDECL is the declaration node of the function (as a tree),
4668 FUNTYPE is the data type of the function (as a tree),
4669 or for a library call it is an identifier node for the subroutine name.
4670 SIZE is the number of bytes of arguments passed on the stack.
4672 On the 80386, the RTD insn may be used to pop them if the number
4673 of args is fixed, but if the number is variable then the caller
4674 must pop them all. RTD can't be used for library calls now
4675 because the library is compiled with the Unix compiler.
4676 Use of RTD is a selectable option, since it is incompatible with
4677 standard Unix calling sequences. If the option is not selected,
4678 the caller must always pop the args.
4680 The attribute stdcall is equivalent to RTD on a per module basis. */
4682 int
4684 {
4687 /* None of the 64-bit ABIs pop arguments. */
4693 /* Cdecl functions override -mrtd, and never pop the stack. */
4695 {
4696 /* Stdcall and fastcall functions will pop the stack if not
4697 variable args. */
4704 }
4706 /* Lose any fake structure return argument if it is passed on the stack. */
4709 {
4713 }
4716 }
4717 \f
4718 /* Argument support functions. */
4720 /* Return true when register may be used to pass function parameters. */
4721 bool
4723 {
4728 {
4732 else
4738 }
4741 {
4744 }
4745 else
4746 {
4750 }
4752 /* TODO: The function should depend on current function ABI but
4753 builtins.c would need updating then. Therefore we use the
4754 default ABI. */
4756 /* RAX is used as hidden argument to va_arg functions. */
4762 else
4769 }
4771 /* Return if we do not know how to pass TYPE solely in registers. */
4773 static bool
4775 {
4779 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4780 The layout_type routine is crafty and tries to trick us into passing
4781 currently unsupported vector types on the stack by using TImode. */
4784 }
4786 /* It returns the size, in bytes, of the area reserved for arguments passed
4787 in registers for the function represented by fndecl dependent to the used
4788 abi format. */
4789 int
4791 {
4795 else
4800 }
4802 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4803 call abi used. */
4804 enum calling_abi
4806 {
4808 {
4811 {
4814 }
4818 }
4820 }
4822 static bool
4824 {
4826 {
4828 {
4830 {
4833 }
4836 }
4837 }
4839 }
4841 static enum calling_abi
4843 {
4847 }
4849 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4850 call abi used. */
4851 enum calling_abi
4853 {
4857 }
4859 /* regclass.c */
4862 /* Implementation of call abi switching target hook. Specific to FNDECL
4863 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4864 for more details. */
4865 void
4867 {
4870 else
4872 }
4874 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4875 re-initialization of init_regs each time we switch function context since
4876 this is needed only during RTL expansion. */
4877 static void
4879 {
4883 }
4885 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4886 for a call to a function whose data type is FNTYPE.
4887 For a library call, FNTYPE is 0. */
4889 void
4893 tree fndecl)
4894 {
4900 else
4902 /* Set up the number of registers to use for passing arguments. */
4909 {
4913 }
4915 {
4918 {
4921 ? X86_64_SSE_REGPARM_MAX
4923 }
4924 }
4931 /* Because type might mismatch in between caller and callee, we need to
4932 use actual type of function for local calls.
4933 FIXME: cgraph_analyze can be told to actually record if function uses
4934 va_start so for local functions maybe_vaarg can be made aggressive
4935 helping K&R code.
4936 FIXME: once typesytem is fixed, we won't need this code anymore. */
4944 {
4945 /* If there are variable arguments, then we won't pass anything
4946 in registers in 32-bit mode. */
4948 {
4956 }
4958 /* Use ecx and edx registers if function has fastcall attribute,
4959 else look for regparm information. */
4961 {
4963 {
4966 }
4967 else
4969 }
4971 /* Set up the number of SSE registers used for passing SFmode
4972 and DFmode arguments. Warn for mismatching ABI. */
4974 }
4975 }
4977 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4978 But in the case of vector types, it is some vector mode.
4980 When we have only some of our vector isa extensions enabled, then there
4981 are some modes for which vector_mode_supported_p is false. For these
4982 modes, the generic vector support in gcc will choose some non-vector mode
4983 in order to implement the type. By computing the natural mode, we'll
4984 select the proper ABI location for the operand and not depend on whatever
4985 the middle-end decides to do with these vector types.
4987 The midde-end can't deal with the vector types > 16 bytes. In this
4988 case, we return the original mode and warn ABI change if CUM isn't
4989 NULL. */
4991 static enum machine_mode
4993 {
4997 {
5000 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5002 {
5007 else
5010 /* Get the mode which has this inner mode and number of units. */
5014 {
5016 {
5020 && !warnedavx
5022 {
5026 }
5028 }
5029 else
5031 }
5034 }
5035 }
5038 }
5040 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5041 this may not agree with the mode that the type system has chosen for the
5042 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5043 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5045 static rtx
5048 {
5049 rtx tmp;
5053 else
5054 {
5058 }
5061 }
5063 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5064 of this code is to classify each 8bytes of incoming argument by the register
5065 class and assign registers accordingly. */
5067 /* Return the union class of CLASS1 and CLASS2.
5068 See the x86-64 PS ABI for details. */
5070 static enum x86_64_reg_class
5072 {
5073 /* Rule #1: If both classes are equal, this is the resulting class. */
5077 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5078 the other class. */
5084 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5088 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5096 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5097 MEMORY is used. */
5106 /* Rule #6: Otherwise class SSE is used. */
5108 }
5110 /* Classify the argument of type TYPE and mode MODE.
5111 CLASSES will be filled by the register class used to pass each word
5112 of the operand. The number of words is returned. In case the parameter
5113 should be passed in memory, 0 is returned. As a special case for zero
5114 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5116 BIT_OFFSET is used internally for handling records and specifies offset
5117 of the offset in bits modulo 256 to avoid overflow cases.
5119 See the x86-64 PS ABI for details.
5120 */
5122 static int
5125 {
5126 HOST_WIDE_INT bytes =
5130 /* Variable sized entities are always passed/returned in memory. */
5139 {
5141 tree field;
5144 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5151 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5152 signalize memory class, so handle it as special case. */
5154 {
5157 }
5159 /* Classify each field of record and merge classes. */
5161 {
5163 /* And now merge the fields of structure. */
5165 {
5167 {
5173 /* Bitfields are always classified as integer. Handle them
5174 early, since later code would consider them to be
5175 misaligned integers. */
5177 {
5185 }
5186 else
5187 {
5192 /* Flexible array member is ignored. */
5199 {
5203 {
5206 "The ABI of passing struct with"
5207 " a flexible array member has"
5209 }
5211 }
5213 subclasses,
5222 }
5223 }
5224 }
5228 /* Arrays are handled as small records. */
5229 {
5236 /* The partial classes are now full classes. */
5247 }
5250 /* Unions are similar to RECORD_TYPE but offset is always 0.
5251 */
5253 {
5255 {
5263 bit_offset);
5268 }
5269 }
5274 }
5277 {
5278 /* When size > 16 bytes, if the first one isn't
5279 X86_64_SSE_CLASS or any other ones aren't
5280 X86_64_SSEUP_CLASS, everything should be passed in
5281 memory. */
5288 }
5290 /* Final merger cleanup. */
5292 {
5293 /* If one class is MEMORY, everything should be passed in
5294 memory. */
5298 /* The X86_64_SSEUP_CLASS should be always preceded by
5299 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5303 {
5304 /* The first one should never be X86_64_SSEUP_CLASS. */
5307 }
5309 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5310 everything should be passed in memory. */
5313 {
5316 /* The first one should never be X86_64_X87UP_CLASS. */
5319 {
5322 "The ABI of passing union with long double"
5324 }
5326 }
5327 }
5329 }
5331 /* Compute alignment needed. We align all types to natural boundaries with
5332 exception of XFmode that is aligned to 64bits. */
5334 {
5343 /* Misaligned fields are always returned in memory. */
5346 }
5348 /* for V1xx modes, just use the base mode */
5353 /* Classification of atomic types. */
5355 {
5371 {
5375 {
5378 }
5380 {
5383 }
5385 {
5389 }
5391 {
5394 }
5395 else
5397 }
5404 /* OImode shouldn't be used directly. */
5411 else
5429 else
5430 {
5434 {
5437 "The ABI of passing structure with complex float"
5439 }
5442 }
5451 /* This modes is larger than 16 bytes. */
5493 else
5497 }
5498 }
5500 /* Examine the argument and return set number of register required in each
5501 class. Return 0 iff parameter should be passed in memory. */
5502 static int
5505 {
5515 {
5537 }
5539 }
5541 /* Construct container for the argument used by GCC interface. See
5542 FUNCTION_ARG for the detailed description. */
5544 static rtx
5548 {
5549 /* The following variables hold the static issued_error state. */
5563 rtx ret;
5574 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5575 some less clueful developer tries to use floating-point anyway. */
5577 {
5579 {
5581 {
5584 }
5585 }
5587 {
5590 }
5592 }
5594 /* Likewise, error if the ABI requires us to return values in the
5595 x87 registers and the user specified -mno-80387. */
5601 {
5603 {
5606 }
5608 }
5610 /* First construct simple cases. Avoid SCmode, since we want to use
5611 single register to pass this type. */
5614 {
5629 /* Zero sized array, struct or class. */
5633 }
5654 /* Otherwise figure out the entries of the PARALLEL. */
5656 {
5660 {
5665 /* Merge TImodes on aligned occasions here too. */
5670 else
5672 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5678 intreg++;
5685 sse_regno++;
5692 sse_regno++;
5697 {
5703 {
5705 i++;
5706 }
5707 else
5720 }
5725 sse_regno++;
5729 }
5730 }
5732 /* Empty aligned struct, union or class. */
5740 }
5742 /* Update the data in CUM to advance over an argument of mode MODE
5743 and data type TYPE. (TYPE is null for libcalls where that information
5744 may not be available.) */
5746 static void
5749 {
5751 {
5758 /* FALLTHRU */
5769 {
5772 }
5776 /* OImode shouldn't be used directly. */
5785 /* FALLTHRU */
5801 {
5806 {
5809 }
5810 }
5819 {
5824 {
5827 }
5828 }
5830 }
5831 }
5833 static void
5836 {
5839 /* Unnamed 256bit vector mode parameters are passed on stack. */
5846 {
5851 }
5852 else
5854 }
5856 static void
5858 HOST_WIDE_INT words)
5859 {
5860 /* Otherwise, this should be passed indirect. */
5865 {
5868 }
5869 }
5871 void
5874 {
5879 else
5890 else
5892 }
5894 /* Define where to put the arguments to a function.
5895 Value is zero to push the argument on the stack,
5896 or a hard register in which to store the argument.
5898 MODE is the argument's machine mode.
5899 TYPE is the data type of the argument (as a tree).
5900 This is null for libcalls where that information may
5901 not be available.
5902 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5903 the preceding args and about the function being called.
5904 NAMED is nonzero if this argument is a named parameter
5905 (otherwise it is an extra parameter matching an ellipsis). */
5907 static rtx
5911 {
5914 /* Avoid the AL settings for the Unix64 ABI. */
5919 {
5926 /* FALLTHRU */
5932 {
5935 /* Fastcall allocates the first two DWORD (SImode) or
5936 smaller arguments to ECX and EDX if it isn't an
5937 aggregate type . */
5939 {
5945 /* ECX not EAX is the first allocated register. */
5948 }
5950 }
5959 /* FALLTHRU */
5961 /* In 32bit, we pass TImode in xmm registers. */
5969 {
5971 {
5975 }
5979 }
5983 /* OImode shouldn't be used directly. */
5993 {
5997 }
6006 {
6008 {
6012 }
6016 }
6018 }
6021 }
6023 static rtx
6026 {
6027 /* Handle a hidden AL argument containing number of registers
6028 for varargs x86-64 functions. */
6033 ? SSE_REGPARM_MAX
6035 ? X86_64_SSE_REGPARM_MAX
6041 {
6051 /* Unnamed 256bit vector mode parameters are passed on stack. */
6055 }
6061 }
6063 static rtx
6066 HOST_WIDE_INT bytes)
6067 {
6070 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6071 We use value of -2 to specify that current function call is MSABI. */
6075 /* If we've run out of registers, it goes on the stack. */
6081 /* Only floating point modes are passed in anything but integer regs. */
6083 {
6086 else
6087 {
6090 /* Unnamed floating parameters are passed in both the
6091 SSE and integer registers. */
6097 }
6098 }
6099 /* Handle aggregated types passed in register. */
6101 {
6106 }
6109 }
6111 rtx
6114 {
6120 else
6124 /* To simplify the code below, represent vector types with a vector mode
6125 even if MMX/SSE are not active. */
6133 else
6135 }
6137 /* A C expression that indicates when an argument must be passed by
6138 reference. If nonzero for an argument, a copy of that argument is
6139 made in memory and a pointer to the argument is passed instead of
6140 the argument itself. The pointer is passed in whatever way is
6141 appropriate for passing a pointer to that type. */
6143 static bool
6147 {
6148 /* See Windows x64 Software Convention. */
6150 {
6153 {
6154 /* Arrays are passed by reference. */
6159 {
6160 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6161 are passed by reference. */
6163 }
6164 }
6166 /* __m128 is passed by reference. */
6172 }
6173 }
6178 }
6180 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6181 ABI. */
6182 static bool
6184 {
6196 {
6197 /* Walk the aggregates recursively. */
6199 {
6203 {
6204 tree field;
6206 /* Walk all the structure fields. */
6208 {
6212 }
6214 }
6217 /* Just for use if some languages passes arrays by value. */
6224 }
6225 }
6227 }
6229 /* Gives the alignment boundary, in bits, of an argument with the
6230 specified mode and type. */
6232 int
6234 {
6237 {
6238 /* Since canonical type is used for call, we convert it to
6239 canonical type if needed. */
6243 }
6244 else
6248 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6249 natural boundaries. */
6251 {
6252 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6253 make an exception for SSE modes since these require 128bit
6254 alignment.
6256 The handling here differs from field_alignment. ICC aligns MMX
6257 arguments to 4 byte boundaries, while structure fields are aligned
6258 to 8 byte boundaries. */
6260 {
6263 }
6264 else
6265 {
6268 }
6269 }
6273 }
6275 /* Return true if N is a possible register number of function value. */
6277 bool
6279 {
6281 {
6286 /* TODO: The function should depend on current function ABI but
6287 builtins.c would need updating then. Therefore we use the
6288 default ABI. */
6300 }
6303 }
6305 /* Define how to find the value returned by a function.
6306 VALTYPE is the data type of the value (as a tree).
6307 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6308 otherwise, FUNC is 0. */
6310 static rtx
6313 {
6316 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6317 we normally prevent this case when mmx is not available. However
6318 some ABIs may require the result to be returned like DImode. */
6322 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6323 we prevent this case when sse is not available. However some ABIs
6324 may require the result to be returned like integer TImode. */
6329 /* 32-byte vector modes in %ymm0. */
6333 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6336 else
6337 /* Most things go in %eax. */
6340 /* Override FP return register with %xmm0 for local functions when
6341 SSE math is enabled or for functions with sseregparm attribute. */
6343 {
6348 }
6350 /* OImode shouldn't be used directly. */
6354 }
6356 static rtx
6358 const_tree valtype)
6359 {
6360 rtx ret;
6362 /* Handle libcalls, which don't provide a type node. */
6364 {
6366 {
6383 }
6384 }
6390 /* For zero sized structures, construct_container returns NULL, but we
6391 need to keep rest of compiler happy by returning meaningful value. */
6396 }
6398 static rtx
6400 {
6404 {
6406 {
6419 }
6420 }
6422 }
6424 static rtx
6427 {
6439 else
6441 }
6443 static rtx
6446 {
6452 }
6454 rtx
6456 {
6458 }
6460 /* Return true iff type is returned in memory. */
6462 static int ATTRIBUTE_UNUSED
6464 {
6465 HOST_WIDE_INT size;
6476 {
6477 /* User-created vectors small enough to fit in EAX. */
6481 /* MMX/3dNow values are returned in MM0,
6482 except when it doesn't exits. */
6486 /* SSE values are returned in XMM0, except when it doesn't exist. */
6490 /* AVX values are returned in YMM0, except when it doesn't exist. */
6493 }
6501 /* OImode shouldn't be used directly. */
6505 }
6507 static int ATTRIBUTE_UNUSED
6509 {
6512 }
6514 static int ATTRIBUTE_UNUSED
6516 {
6519 /* __m128 is returned in xmm0. */
6524 /* Otherwise, the size must be exactly in [1248]. */
6526 }
6528 static bool
6530 {
6531 #ifdef SUBTARGET_RETURN_IN_MEMORY
6533 #else
6537 {
6540 else
6542 }
6543 else
6545 #endif
6546 }
6548 /* Return false iff TYPE is returned in memory. This version is used
6549 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6550 but differs notably in that when MMX is available, 8-byte vectors
6551 are returned in memory, rather than in MMX registers. */
6553 bool
6555 {
6568 {
6569 /* Return in memory only if MMX registers *are* available. This
6570 seems backwards, but it is consistent with the existing
6571 Solaris x86 ABI. */
6576 }
6583 }
6585 /* When returning SSE vector types, we have a choice of either
6586 (1) being abi incompatible with a -march switch, or
6587 (2) generating an error.
6588 Given no good solution, I think the safest thing is one warning.
6589 The user won't be able to use -Werror, but....
6591 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6592 called in response to actually generating a caller or callee that
6593 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6594 via aggregate_value_p for general type probing from tree-ssa. */
6596 static rtx
6598 {
6602 {
6603 /* Look at the return type of the function, not the function type. */
6607 {
6610 {
6614 }
6615 }
6618 {
6620 {
6624 }
6625 }
6626 }
6629 }
6631 \f
6632 /* Create the va_list data type. */
6634 /* Returns the calling convention specific va_list date type.
6635 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6637 static tree
6639 {
6642 /* For i386 we use plain pointer to argument area. */
6652 unsigned_type_node);
6655 unsigned_type_node);
6658 ptr_type_node);
6661 ptr_type_node);
6680 /* The correct type is an array type of one element. */
6682 }
6684 /* Setup the builtin va_list data type and for 64-bit the additional
6685 calling convention specific va_list data types. */
6687 static tree
6689 {
6692 /* Initialize abi specific va_list builtin types. */
6694 {
6695 tree t;
6697 {
6702 }
6703 else
6704 {
6709 }
6711 {
6716 }
6717 else
6718 {
6723 }
6724 }
6727 }
6729 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6731 static void
6733 {
6735 rtx label;
6736 rtx label_ref;
6737 rtx tmp_reg;
6738 rtx nsse_reg;
6739 alias_set_type set;
6747 /* GPR size of varargs save area. */
6750 else
6753 /* FPR size of varargs save area. We don't need it if we don't pass
6754 anything in SSE registers. */
6757 else
6767 i < regparm
6769 i++)
6770 {
6777 }
6780 {
6781 /* Now emit code to save SSE registers. The AX parameter contains number
6782 of SSE parameter registers used to call this function. We use
6783 sse_prologue_save insn template that produces computed jump across
6784 SSE saves. We need some preparation work to get this working. */
6789 /* Compute address to jump to :
6790 label - eax*4 + nnamed_sse_arguments*4 Or
6791 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6799 /* vmovaps is one byte longer than movaps. */
6803 nsse_reg)));
6806 emit_move_insn
6810 label_ref,
6813 else
6817 /* Compute address of memory block we save into. We always use pointer
6818 pointing 127 bytes after first byte to store - this is needed to keep
6819 instruction size limited by 4 bytes (5 bytes for AVX) with one
6820 byte displacement. */
6830 /* And finally do the dirty job! */
6833 }
6834 }
6836 static void
6838 {
6843 {
6854 }
6855 }
6857 static void
6861 {
6862 CUMULATIVE_ARGS next_cum;
6863 tree fntype;
6865 /* This argument doesn't appear to be used anymore. Which is good,
6866 because the old code here didn't suppress rtl generation. */
6874 /* For varargs, we do not want to skip the dummy va_dcl argument.
6875 For stdargs, we do want to skip the last named argument. */
6882 else
6884 }
6886 /* Checks if TYPE is of kind va_list char *. */
6888 static bool
6890 {
6891 tree canonic;
6893 /* For 32-bit it is always true. */
6899 }
6901 /* Implement va_start. */
6903 static void
6905 {
6909 tree type;
6911 /* Only 64bit target needs something special. */
6913 {
6916 }
6929 /* Count number of gp and fp argument registers used. */
6935 {
6941 }
6944 {
6950 }
6952 /* Find the overflow area. */
6963 {
6964 /* Find the register save area.
6965 Prologue of the function save it right above stack frame. */
6974 }
6975 }
6977 /* Implement va_arg. */
6979 static tree
6982 {
6989 rtx container;
6991 tree ptrtype;
6995 /* Only 64bit target needs something special. */
7019 {
7026 /* Unnamed 256bit vector mode parameters are passed on stack. */
7028 {
7031 }
7039 }
7041 /* Pull the value out of the saved registers. */
7046 {
7060 /* In case we are passing structure, verify that it is consecutive block
7061 on the register save area. If not we need to do moves. */
7063 {
7064 /* Verify that all registers are strictly consecutive */
7066 {
7070 {
7075 }
7076 }
7077 else
7078 {
7082 {
7087 }
7088 }
7089 }
7091 {
7094 }
7095 else
7096 {
7099 }
7101 /* First ensure that we fit completely in registers. */
7103 {
7110 }
7112 {
7120 }
7122 /* Compute index to start of area used for integer regs. */
7124 {
7125 /* int_addr = gpr + sav; */
7129 }
7131 {
7132 /* sse_addr = fpr + sav; */
7136 }
7138 {
7142 /* addr = &temp; */
7147 {
7160 {
7163 }
7164 else
7165 {
7168 }
7180 }
7181 }
7184 {
7188 }
7191 {
7195 }
7200 }
7202 /* ... otherwise out of the overflow area. */
7204 /* When we align parameter on stack for caller, if the parameter
7205 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7206 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7207 here with caller. */
7212 /* Care for on-stack alignment if needed. */
7216 else
7217 {
7225 }
7242 }
7243 \f
7244 /* Return nonzero if OPNUM's MEM should be matched
7245 in movabs* patterns. */
7247 int
7249 {
7261 }
7262 \f
7263 /* Initialize the table of extra 80387 mathematical constants. */
7265 static void
7267 {
7269 {
7275 };
7279 {
7281 /* Ensure each constant is rounded to XFmode precision. */
7284 }
7287 }
7289 /* Return true if the constant is something that can be loaded with
7290 a special instruction. */
7292 int
7294 {
7297 REAL_VALUE_TYPE r;
7309 /* For XFmode constants, try to find a special 80387 instruction when
7310 optimizing for size or on those CPUs that benefit from them. */
7313 {
7322 }
7324 /* Load of the constant -0.0 or -1.0 will be split as
7325 fldz;fchs or fld1;fchs sequence. */
7332 }
7334 /* Return the opcode of the special instruction to be used to load
7335 the constant X. */
7339 {
7341 {
7361 }
7362 }
7364 /* Return the CONST_DOUBLE representing the 80387 constant that is
7365 loaded by the specified special instruction. The argument IDX
7366 matches the return value from standard_80387_constant_p. */
7368 rtx
7370 {
7377 {
7388 }
7391 XFmode);
7392 }
7394 /* Return 1 if X is all 0s and 2 if x is all 1s
7395 in supported SSE vector mode. */
7397 int
7399 {
7406 {
7415 }
7418 }
7420 /* Return the opcode of the special instruction to be used to load
7421 the constant X. */
7425 {
7427 {
7430 {
7445 }
7450 }
7452 }
7454 /* Returns 1 if OP contains a symbol reference */
7456 int
7458 {
7467 {
7469 {
7475 }
7479 }
7482 }
7484 /* Return 1 if it is appropriate to emit `ret' instructions in the
7485 body of a function. Do this only if the epilogue is simple, needing a
7486 couple of insns. Prior to reloading, we can't tell how many registers
7487 must be saved, so return 0 then. Return 0 if there is no frame
7488 marker to de-allocate. */
7490 int
7492 {
7498 /* Don't allow more than 32 pop, since that's all we can do
7499 with one instruction. */
7507 }
7508 \f
7509 /* Value should be nonzero if functions must have frame pointers.
7510 Zero means the frame pointer need not be set up (and parms may
7511 be accessed via the stack pointer) in functions that seem suitable. */
7513 static bool
7515 {
7516 /* If we accessed previous frames, then the generated code expects
7517 to be able to access the saved ebp value in our frame. */
7521 /* Several x86 os'es need a frame pointer for other reasons,
7522 usually pertaining to setjmp. */
7526 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7527 the frame pointer by default. Turn it back on now if we've not
7528 got a leaf function. */
7530 && (!current_function_is_leaf
7538 }
7540 /* Record that the current function accesses previous call frames. */
7542 void
7544 {
7546 }
7547 \f
7548 #ifndef USE_HIDDEN_LINKONCE
7549 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7550 # define USE_HIDDEN_LINKONCE 1
7551 # else
7552 # define USE_HIDDEN_LINKONCE 0
7553 # endif
7554 #endif
7558 /* Fills in the label name that should be used for a pc thunk for
7559 the given register. */
7561 static void
7563 {
7568 else
7570 }
7573 /* This function generates code for -fpic that loads %ebx with
7574 the return address of the caller and then returns. */
7576 void
7578 {
7583 {
7591 #if TARGET_MACHO
7593 {
7601 }
7602 else
7603 #endif
7605 {
7606 tree decl;
7610 error_mark_node);
7623 }
7624 else
7625 {
7628 }
7634 }
7638 }
7640 /* Emit code for the SET_GOT patterns. */
7644 {
7650 {
7651 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7656 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7657 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7658 an unadorned address. */
7663 }
7668 {
7673 else
7676 #if TARGET_MACHO
7677 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7678 is what will be referenced by the Mach-O PIC subsystem. */
7681 #endif
7688 }
7689 else
7690 {
7698 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7699 is what will be referenced by the Mach-O PIC subsystem. */
7700 #if TARGET_MACHO
7703 else
7706 #endif
7707 }
7714 else
7718 }
7720 /* Generate an "push" pattern for input ARG. */
7722 static rtx
7724 {
7731 stack_pointer_rtx)),
7732 arg);
7733 }
7735 /* Return >= 0 if there is an unused call-clobbered register available
7736 for the entire function. */
7738 static unsigned int
7740 {
7743 {
7745 /* Can't use the same register for both PIC and DRAP. */
7748 else
7753 }
7756 }
7758 /* Return 1 if we need to save REGNO. */
7759 static int
7761 {
7768 {
7772 }
7775 {
7778 {
7784 }
7785 }
7794 }
7796 /* Return number of saved general prupose registers. */
7798 static int
7800 {
7806 nregs ++;
7808 }
7810 /* Return number of saved SSE registrers. */
7812 static int
7814 {
7822 nregs ++;
7824 }
7826 /* Given FROM and TO register numbers, say whether this elimination is
7827 allowed. If stack alignment is needed, we can only replace argument
7828 pointer with hard frame pointer, or replace frame pointer with stack
7829 pointer. Otherwise, frame pointer elimination is automatically
7830 handled and all other eliminations are valid. */
7832 static bool
7834 {
7840 else
7842 }
7844 /* Return the offset between two registers, one to be eliminated, and the other
7845 its replacement, at the start of a routine. */
7847 HOST_WIDE_INT
7849 {
7858 else
7859 {
7867 }
7868 }
7870 /* In a dynamically-aligned function, we can't know the offset from
7871 stack pointer to frame pointer, so we must ensure that setjmp
7872 eliminates fp against the hard fp (%ebp) rather than trying to
7873 index from %esp up to the top of the frame across a gap that is
7874 of unknown (at compile-time) size. */
7875 static rtx
7877 {
7879 }
7881 /* Fill structure ix86_frame about frame of currently computed function. */
7883 static void
7885 {
7887 HOST_WIDE_INT offset;
7897 /* MS ABI seem to require stack alignment to be always 16 except for function
7898 prologues. */
7900 {
7905 }
7911 /* During reload iteration the amount of registers saved can change.
7912 Recompute the value as needed. Do not recompute when amount of registers
7913 didn't change as reload does multiple calls to the function and does not
7914 expect the decision to change within single iteration. */
7917 {
7921 /* The fast prologue uses move instead of push to save registers. This
7922 is significantly longer, but also executes faster as modern hardware
7923 can execute the moves in parallel, but can't do that for push/pop.
7925 Be careful about choosing what prologue to emit: When function takes
7926 many instructions to execute we may use slow version as well as in
7927 case function is known to be outside hot spot (this is known with
7928 feedback only). Weight the size of function by number of registers
7929 to save as it is cheap to use one or two push instructions but very
7930 slow to use many of them. */
7934 || (flag_branch_probabilities
7937 else
7940 }
7944 else
7947 /* Skip return address. */
7950 /* Skip pushed static chain. */
7954 /* Skip saved base pointer. */
7960 /* Set offset to aligned because the realigned frame starts from
7961 here. */
7965 /* Register save area */
7968 /* Align SSE reg save area. */
7971 else
7974 /* SSE register save area. */
7977 /* Va-arg area */
7981 /* Align start of frame for local function. */
7987 /* Frame pointer points here. */
7992 /* Add outgoing arguments area. Can be skipped if we eliminated
7993 all the function calls as dead code.
7994 Skipping is however impossible when function calls alloca. Alloca
7995 expander assumes that last crtl->outgoing_args_size
7996 of stack frame are unused. */
8000 {
8003 }
8004 else
8007 /* Align stack boundary. Only needed if we're calling another function
8008 or using alloca. */
8013 else
8018 /* We've reached end of stack frame. */
8021 /* Size prologue needs to allocate. */
8031 && current_function_sp_is_unchanging
8032 && current_function_is_leaf
8034 {
8040 }
8041 else
8045 }
8047 /* Emit code to save registers in the prologue. */
8049 static void
8051 {
8053 rtx insn;
8057 {
8060 }
8061 }
8063 /* Emit code to save registers using MOV insns. First register
8064 is restored from POINTER + OFFSET. */
8065 static void
8067 {
8069 rtx insn;
8073 {
8079 }
8080 }
8082 /* Emit code to save registers using MOV insns. First register
8083 is restored from POINTER + OFFSET. */
8084 static void
8086 {
8088 rtx insn;
8089 rtx mem;
8093 {
8099 }
8100 }
8104 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8105 manipulation insn. Don't add it if the previously
8106 saved value will be left untouched within stack red-zone till return,
8107 as unwinders can find the same value in the register and
8108 on the stack. */
8110 static void
8112 {
8114 && !TARGET_64BIT_MS_ABI
8120 {
8123 }
8124 else
8125 queued_cfa_restores
8127 }
8129 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8131 static void
8133 {
8134 rtx last;
8138 ;
8143 }
8145 /* Expand prologue or epilogue stack adjustment.
8146 The pattern exist to put a dependency on all ebp-based memory accesses.
8147 STYLE should be negative if instructions should be marked as frame related,
8148 zero if %r11 register is live and cannot be freely used and positive
8149 otherwise. */
8151 static void
8154 {
8155 rtx insn;
8161 else
8162 {
8163 rtx r11;
8164 /* r11 is used by indirect sibcall return as well, set before the
8165 epilogue and used after the epilogue. ATM indirect sibcall
8166 shouldn't be used together with huge frame sizes in one
8167 function because of the frame_size check in sibcall.c. */
8174 offset));
8175 }
8181 {
8182 rtx r;
8192 }
8195 }
8197 /* Find an available register to be used as dynamic realign argument
8198 pointer regsiter. Such a register will be written in prologue and
8199 used in begin of body, so it must not be
8200 1. parameter passing register.
8201 2. GOT pointer.
8202 We reuse static-chain register if it is available. Otherwise, we
8203 use DI for i386 and R13 for x86-64. We chose R13 since it has
8204 shorter encoding.
8206 Return: the regno of chosen register. */
8208 static unsigned int
8210 {
8214 {
8215 /* Use R13 for nested function or function need static chain.
8216 Since function with tail call may use any caller-saved
8217 registers in epilogue, DRAP must not use caller-saved
8218 register in such case. */
8223 }
8224 else
8225 {
8226 /* Use DI for nested function or function need static chain.
8227 Since function with tail call may use any caller-saved
8228 registers in epilogue, DRAP must not use caller-saved
8229 register in such case. */
8233 /* Reuse static chain register if it isn't used for parameter
8234 passing. */
8239 else
8241 }
8242 }
8244 /* Return minimum incoming stack alignment. */
8246 static unsigned int
8248 {
8251 /* Prefer the one specified at command line. */
8254 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8255 if -mstackrealign is used, it isn't used for sibcall check and
8256 estimated stack alignment is 128bit. */
8258 && !TARGET_64BIT
8259 && ix86_force_align_arg_pointer
8262 else
8265 /* Incoming stack alignment can be changed on individual functions
8266 via force_align_arg_pointer attribute. We use the smallest
8267 incoming stack boundary. */
8273 /* The incoming stack frame has to be aligned at least at
8274 parm_stack_boundary. */
8278 /* Stack at entrance of main is aligned by runtime. We use the
8279 smallest incoming stack boundary. */
8287 }
8289 /* Update incoming stack boundary and estimated stack alignment. */
8291 static void
8293 {
8294 ix86_incoming_stack_boundary
8297 /* x86_64 vararg needs 16byte stack alignment for register save
8298 area. */
8303 }
8305 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8306 needed or an rtx for DRAP otherwise. */
8308 static rtx
8310 {
8315 {
8316 /* Assign DRAP to vDRAP and returns vDRAP */
8318 rtx drap_vreg;
8319 rtx arg_ptr;
8333 }
8334 else
8336 }
8338 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8340 static rtx
8342 {
8344 }
8346 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8347 to be generated in correct form. */
8348 static void
8350 {
8351 /* Check if stack realign is really needed after reload, and
8352 stores result in cfun */
8353 unsigned int incoming_stack_boundary
8357 < (current_function_is_leaf
8362 {
8363 /* After stack_realign_needed is finalized, we can't no longer
8364 change it. */
8366 }
8367 else
8368 {
8371 }
8372 }
8374 /* Expand the prologue into a bunch of separate insns. */
8376 void
8378 {
8379 rtx insn;
8382 HOST_WIDE_INT allocate;
8387 /* DRAP should not coexist with stack_realign_fp */
8390 /* Initialize CFA state for before the prologue. */
8397 {
8400 /* Make sure the function starts with
8401 8b ff movl.s %edi,%edi
8402 55 push %ebp
8403 8b ec movl.s %esp,%ebp
8405 This matches the hookable function prologue in Win32 API
8406 functions in Microsoft Windows XP Service Pack 2 and newer.
8407 Wine uses this to enable Windows apps to hook the Win32 API
8408 functions provided by Wine. */
8413 stack_pointer_rtx));
8417 {
8418 /* The push %ebp and movl.s %esp, %ebp already set up
8419 the frame pointer. No need to do this again. */
8425 }
8426 else
8427 /* If the frame pointer is not needed, pop %ebp again. This
8428 could be optimized for cases where ebp needs to be backed up
8429 for some other reason. If stack realignment is needed, pop
8430 the base pointer again, align the stack, and later regenerate
8431 the frame pointer setup. The frame pointer generated by the
8432 hook prologue is not aligned, so it can't be used. */
8434 }
8436 /* The first insn of a function that accepts its static chain on the
8437 stack is to push the register that would be filled in by a direct
8438 call. This insn will be skipped by the trampoline. */
8440 {
8441 rtx t;
8446 /* We don't want to interpret this push insn as a register save,
8447 only as a stack adjustment. The real copy of the register as
8448 a save will be done later, if needed. */
8453 }
8455 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8456 of DRAP is needed and stack realignment is really needed after reload */
8458 {
8470 /* Grab the argument pointer. */
8474 /* Only need to push parameter pointer reg if it is caller
8475 saved reg */
8477 {
8478 /* Push arg pointer reg */
8481 }
8487 /* Align the stack. */
8489 stack_pointer_rtx,
8493 /* Replicate the return address on the stack so that return
8494 address can be reached via (argp - 1) slot. This is needed
8495 to implement macro RETURN_ADDR_RTX and intrinsic function
8496 expand_builtin_return_addr etc. */
8502 }
8504 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8505 slower on all targets. Also sdb doesn't like it. */
8508 {
8517 }
8520 {
8524 /* Align the stack. */
8526 stack_pointer_rtx,
8529 }
8535 else
8538 /* When using red zone we may start register saving before allocating
8539 the stack frame saving one cycle of the prologue. However I will
8540 avoid doing this if I am going to have to probe the stack since
8541 at least on x86_64 the stack probe can turn into a call that clobbers
8542 a red zone location */
8547 ? hard_frame_pointer_rtx
8552 ;
8557 else
8558 {
8559 /* Only valid for Win32. */
8562 rtx t;
8568 else
8572 {
8575 }
8581 else
8586 {
8592 }
8595 {
8598 allocate
8601 else
8604 }
8605 }
8610 {
8615 frame.to_allocate
8617 else
8620 }
8626 else
8636 {
8643 }
8646 {
8648 {
8650 {
8660 }
8661 else
8663 }
8664 else
8666 }
8668 /* In the pic_reg_used case, make sure that the got load isn't deleted
8669 when mcount needs it. Blockage to avoid call movement across mcount
8670 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8671 note. */
8676 {
8677 /* vDRAP is setup but after reload it turns out stack realign
8678 isn't necessary, here we will emit prologue to setup DRAP
8679 without stack realign adjustment */
8680 rtx x;
8687 }
8689 /* Prevent instructions from being scheduled into register save push
8690 sequence when access to the redzone area is done through frame pointer.
8691 The offset between the frame pointer and the stack pointer is calculated
8692 relative to the value of the stack pointer at the end of the function
8693 prologue, and moving instructions that access redzone area via frame
8694 pointer inside push sequence violates this assumption. */
8698 /* Emit cld instruction if stringops are used in the function. */
8701 }
8703 /* Emit code to restore REG using a POP insn. */
8705 static void
8707 {
8712 {
8713 /* Previously we'd represented the CFA as an expression
8714 like *(%ebp - 8). We've just popped that value from
8715 the stack, which means we need to reset the CFA to
8716 the drap register. This will remain until we restore
8717 the stack pointer. */
8721 }
8724 {
8729 }
8731 /* When the frame pointer is the CFA, and we pop it, we are
8732 swapping back to the stack pointer as the CFA. This happens
8733 for stack frames that don't allocate other data, so we assume
8734 the stack pointer is now pointing at the return address, i.e.
8735 the function entry state, which makes the offset be 1 word. */
8738 {
8746 }
8749 }
8751 /* Emit code to restore saved registers using POP insns. */
8753 static void
8755 {
8760 {
8762 red_offset);
8764 }
8765 }
8767 /* Emit code and notes for the LEAVE instruction. */
8769 static void
8771 {
8777 {
8785 }
8786 }
8788 /* Emit code to restore saved registers using MOV insns. First register
8789 is restored from POINTER + OFFSET. */
8790 static void
8792 HOST_WIDE_INT red_offset,
8794 {
8797 rtx insn;
8801 {
8804 /* Ensure that adjust_address won't be forced to produce pointer
8805 out of range allowed by x86-64 instruction set. */
8807 {
8808 rtx r11;
8815 }
8822 {
8823 /* Previously we'd represented the CFA as an expression
8824 like *(%ebp - 8). We've just popped that value from
8825 the stack, which means we need to reset the CFA to
8826 the drap register. This will remain until we restore
8827 the stack pointer. */
8830 }
8831 else
8835 }
8836 }
8838 /* Emit code to restore saved registers using MOV insns. First register
8839 is restored from POINTER + OFFSET. */
8840 static void
8842 HOST_WIDE_INT red_offset,
8844 {
8847 rtx mem;
8851 {
8854 /* Ensure that adjust_address won't be forced to produce pointer
8855 out of range allowed by x86-64 instruction set. */
8857 {
8858 rtx r11;
8865 }
8874 }
8875 }
8877 /* Restore function stack, frame, and registers. */
8879 void
8881 {
8890 /* When stack is realigned, SP must be valid. */
8891 sp_valid = (!frame_pointer_needed
8892 || current_function_sp_is_unchanging
8897 /* See the comment about red zone and frame
8898 pointer usage in ix86_expand_prologue. */
8905 /* Calculate start of saved registers relative to ebp. Special care
8906 must be taken for the normal return case of a function using
8907 eh_return: the eax and edx registers are marked as saved, but not
8908 restored along this path. */
8915 /* Calculate start of saved registers relative to esp on entry of the
8916 function. When realigning stack, this needs to be the most negative
8917 value possible at runtime. */
8930 /* If we're only restoring one register and sp is not valid then
8931 using a move instruction to restore the register since it's
8932 less work than reloading sp and popping the register.
8934 The default code result in stack adjustment using add/lea instruction,
8935 while this code results in LEAVE instruction (or discrete equivalent),
8936 so it is profitable in some other cases as well. Especially when there
8937 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8938 and there is exactly one register to pop. This heuristic may need some
8939 tuning in future. */
8941 || (TARGET_EPILOGUE_USING_MOVE
8951 {
8952 /* Restore registers. We can use ebp or esp to address the memory
8953 locations. If both are available, default to ebp, since offsets
8954 are known to be small. Only exception is esp pointing directly
8955 to the end of block of saved registers, where we may simplify
8956 addressing mode.
8958 If we are realigning stack with bp and sp, regs restore can't
8959 be addressed by bp. sp must be used instead. */
8964 {
8969 frame.to_allocate
8972 red_offset
8975 }
8976 else
8977 {
8982 offset
8985 red_offset
8988 }
8992 /* eh_return epilogues need %ecx added to the stack pointer. */
8994 {
8997 /* Stack align doesn't work with eh_return. */
8999 /* Neither does regparm nested functions. */
9003 {
9011 /* Note that we use SA as a temporary CFA, as the return
9012 address is at the proper place relative to it. We
9013 pretend this happens at the FP restore insn because
9014 prior to this insn the FP would be stored at the wrong
9015 offset relative to SA, and after this insn we have no
9016 other reasonable register to use for the CFA. We don't
9017 bother resetting the CFA to the SP for the duration of
9018 the return insn. */
9029 }
9030 else
9031 {
9042 {
9046 UNITS_PER_WORD));
9048 }
9049 }
9050 }
9058 /* If not an i386, mov & pop is faster than "leave". */
9062 else
9063 {
9065 hard_frame_pointer_rtx,
9069 }
9070 }
9071 else
9072 {
9073 /* First step is to deallocate the stack frame so that we can
9074 pop the registers.
9076 If we realign stack with frame pointer, then stack pointer
9077 won't be able to recover via lea $offset(%bp), %sp, because
9078 there is a padding area between bp and sp for realign.
9079 "add $to_allocate, %sp" must be used instead. */
9081 {
9085 hard_frame_pointer_rtx,
9094 }
9096 {
9105 }
9112 {
9113 /* Leave results in shorter dependency chains on CPUs that are
9114 able to grok it fast. */
9117 else
9118 {
9119 /* For stack realigned really happens, recover stack
9120 pointer to hard frame pointer is a must, if not using
9121 leave. */
9124 hard_frame_pointer_rtx,
9127 red_offset);
9128 }
9129 }
9130 }
9133 {
9135 rtx insn;
9158 }
9160 /* Remove the saved static chain from the stack. The use of ECX is
9161 merely as a scratch register, not as the actual static chain. */
9163 {
9176 }
9178 /* Sibcall epilogues don't want a return instruction. */
9180 {
9183 }
9186 {
9189 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9190 address, do explicit add, and jump indirectly to the caller. */
9193 {
9195 rtx insn;
9197 /* There is no "pascal" calling convention in any 64bit ABI. */
9212 }
9213 else
9215 }
9216 else
9219 /* Restore the state back to the state from the prologue,
9220 so that it's correct for the next epilogue. */
9222 }
9224 /* Reset from the function's potential modifications. */
9226 static void
9228 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9229 {
9232 #if TARGET_MACHO
9233 /* Mach-O doesn't support labels at the end of objects, so if
9234 it looks like we might want one, insert a NOP. */
9235 {
9246 }
9247 #endif
9249 }
9250 \f
9251 /* Extract the parts of an RTL expression that is a valid memory address
9252 for an instruction. Return 0 if the structure of the address is
9253 grossly off. Return -1 if the address contains ASHIFT, so it is not
9254 strictly valid, but still used for computing length of lea instruction. */
9256 int
9258 {
9269 {
9274 do
9275 {
9280 }
9287 {
9290 {
9300 && TARGET_TLS_DIRECT_SEG_REFS
9303 else
9313 else
9328 }
9329 }
9330 }
9332 {
9335 }
9337 {
9338 rtx tmp;
9340 /* We're called for lea too, which implements ashift on occasion. */
9350 }
9351 else
9354 /* Extract the integral value of scale. */
9356 {
9360 }
9365 /* Avoid useless 0 displacement. */
9369 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9374 {
9375 rtx tmp;
9378 }
9380 /* Special case: %ebp cannot be encoded as a base without a displacement.
9381 Similarly %r13. */
9383 && base_reg
9392 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9393 Avoid this by transforming to [%esi+0].
9394 Reload calls address legitimization without cfun defined, so we need
9395 to test cfun for being non-NULL. */
9402 /* Special case: encode reg+reg instead of reg*2. */
9406 /* Special case: scaling cannot be encoded without base or displacement. */
9417 }
9418 \f
9419 /* Return cost of the memory address x.
9420 For i386, it is better to use a complex address than let gcc copy
9421 the address into a reg and make a new pseudo. But not if the address
9422 requires to two regs - that would mean more pseudos with longer
9423 lifetimes. */
9424 static int
9426 {
9438 /* Attempt to minimize number of registers in the address. */
9444 cost++;
9451 cost++;
9453 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9454 since it's predecode logic can't detect the length of instructions
9455 and it degenerates to vector decoded. Increase cost of such
9456 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9457 to split such addresses or even refuse such addresses at all.
9459 Following addressing modes are affected:
9460 [base+scale*index]
9461 [scale*index+disp]
9462 [base+index]
9464 The first and last case may be avoidable by explicitly coding the zero in
9465 memory address, but I don't have AMD-K6 machine handy to check this
9466 theory. */
9475 }
9476 \f
9477 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9478 this is used for to form addresses to local data when -fPIC is in
9479 use. */
9481 static bool
9483 {
9486 }
9488 /* Determine if a given RTX is a valid constant. We already know this
9489 satisfies CONSTANT_P. */
9491 bool
9493 {
9495 {
9500 {
9504 }
9509 /* Only some unspecs are valid as "constants". */
9512 {
9528 }
9530 /* We must have drilled down to a symbol. */
9535 /* FALLTHRU */
9538 /* TLS symbols are never valid. */
9542 /* DLLIMPORT symbols are never valid. */
9561 }
9563 /* Otherwise we handle everything else in the move patterns. */
9565 }
9567 /* Determine if it's legal to put X into the constant pool. This
9568 is not possible for the address of thread-local symbols, which
9569 is checked above. */
9571 static bool
9573 {
9574 /* We can always put integral constants and vectors in memory. */
9576 {
9584 }
9586 }
9589 /* Nonzero if the constant value X is a legitimate general operand
9590 when generating PIC code. It is given that flag_pic is on and
9591 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9593 bool
9595 {
9596 rtx inner;
9599 {
9606 /* Only some unspecs are valid as "constants". */
9609 {
9622 }
9623 /* FALLTHRU */
9631 }
9632 }
9634 /* Determine if a given CONST RTX is a valid memory displacement
9635 in PIC mode. */
9637 int
9639 {
9642 /* In 64bit mode we can allow direct addresses of symbols and labels
9643 when they are not dynamic symbols. */
9645 {
9649 {
9666 /* FALLTHRU */
9669 /* TLS references should always be enclosed in UNSPEC. */
9679 }
9680 }
9686 {
9687 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9688 of GOT tables. We should not need these anyway. */
9699 }
9703 {
9708 }
9717 {
9721 /* We need to check for both symbols and labels because VxWorks loads
9722 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9723 details. */
9727 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9728 While ABI specify also 32bit relocation but we don't produce it in
9729 small PIC model at all. */
9751 }
9754 }
9756 /* Recognizes RTL expressions that are valid memory addresses for an
9757 instruction. The MODE argument is the machine mode for the MEM
9758 expression that wants to use this address.
9760 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9761 convert common non-canonical forms to canonical form so that they will
9762 be recognized. */
9764 static bool
9767 {
9770 HOST_WIDE_INT scale;
9773 /* Decomposition failed. */
9781 /* Validate base register.
9783 Don't allow SUBREG's that span more than a word here. It can lead to spill
9784 failures when the base is one word out of a two word structure, which is
9785 represented internally as a DImode int. */
9788 {
9789 rtx reg;
9798 else
9799 /* Base is not a register. */
9803 /* Base is not in Pmode. */
9808 /* Base is not valid. */
9810 }
9812 /* Validate index register.
9814 Don't allow SUBREG's that span more than a word here -- same as above. */
9817 {
9818 rtx reg;
9827 else
9828 /* Index is not a register. */
9832 /* Index is not in Pmode. */
9837 /* Index is not valid. */
9839 }
9841 /* Validate scale factor. */
9843 {
9845 /* Scale without index. */
9849 /* Scale is not a valid multiplier. */
9851 }
9853 /* Validate displacement. */
9855 {
9860 {
9861 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9862 used. While ABI specify also 32bit relocations, we don't produce
9863 them at all and use IP relative instead. */
9870 /* 64bit address unspec. */
9885 /* Invalid address unspec. */
9887 }
9890 && (flag_pic
9891 || (TARGET_MACHO
9892 #if TARGET_MACHO
9893 && MACHOPIC_INDIRECT
9895 #endif
9896 )))
9897 {
9899 is_legitimate_pic:
9901 {
9902 /* foo@dtpoff(%rX) is ok. */
9909 /* Non-constant pic memory reference. */
9911 }
9913 /* Displacement is an invalid pic construct. */
9916 /* This code used to verify that a symbolic pic displacement
9917 includes the pic_offset_table_rtx register.
9919 While this is good idea, unfortunately these constructs may
9920 be created by "adds using lea" optimization for incorrect
9921 code like:
9923 int a;
9924 int foo(int i)
9925 {
9926 return *(&a+i);
9927 }
9929 This code is nonsensical, but results in addressing
9930 GOT table with pic_offset_table_rtx base. We can't
9931 just refuse it easily, since it gets matched by
9932 "addsi3" pattern, that later gets split to lea in the
9933 case output register differs from input. While this
9934 can be handled by separate addsi pattern for this case
9935 that never results in lea, this seems to be easier and
9936 correct fix for crash to disable this test. */
9937 }
9944 /* Displacement is not constant. */
9948 /* Displacement is out of range. */
9950 }
9952 /* Everything looks valid. */
9954 }
9956 /* Determine if a given RTX is a valid constant address. */
9958 bool
9960 {
9962 }
9963 \f
9964 /* Return a unique alias set for the GOT. */
9966 static alias_set_type
9968 {
9973 }
9975 /* Return a legitimate reference for ORIG (an address) using the
9976 register REG. If REG is 0, a new pseudo is generated.
9978 There are two types of references that must be handled:
9980 1. Global data references must load the address from the GOT, via
9981 the PIC reg. An insn is emitted to do this load, and the reg is
9982 returned.
9984 2. Static data references, constant pool addresses, and code labels
9985 compute the address as an offset from the GOT, whose base is in
9986 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9987 differentiate them from global data objects. The returned
9988 address is the PIC reg + an unspec constant.
9990 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9991 reg also appears in the address. */
9993 static rtx
9995 {
9998 rtx base;
10000 #if TARGET_MACHO
10002 {
10005 /* Use the generic Mach-O PIC machinery. */
10007 }
10008 #endif
10015 {
10016 rtx tmpreg;
10017 /* This symbol may be referenced via a displacement from the PIC
10018 base address (@GOTOFF). */
10025 {
10027 UNSPEC_GOTOFF);
10029 }
10030 else
10035 else
10040 {
10044 }
10046 }
10048 {
10049 /* This symbol may be referenced via a displacement from the PIC
10050 base address (@GOTOFF). */
10057 {
10059 UNSPEC_GOTOFF);
10061 }
10062 else
10068 {
10071 }
10072 }
10074 /* We can't use @GOTOFF for text labels on VxWorks;
10075 see gotoff_operand. */
10077 {
10079 {
10085 {
10088 }
10089 }
10092 {
10100 /* Use directly gen_movsi, otherwise the address is loaded
10101 into register for CSE. We don't want to CSE this addresses,
10102 instead we CSE addresses from the GOT table, so skip this. */
10105 }
10106 else
10107 {
10108 /* This symbol must be referenced via a load from the
10109 Global Offset Table (@GOT). */
10125 }
10126 }
10127 else
10128 {
10131 {
10133 {
10136 }
10137 else
10139 }
10141 {
10144 /* We must match stuff we generate before. Assume the only
10145 unspecs that can get here are ours. Not that we could do
10146 anything with them anyway.... */
10152 }
10154 {
10157 /* Check first to see if this is a constant offset from a @GOTOFF
10158 symbol reference. */
10161 {
10163 {
10167 UNSPEC_GOTOFF);
10173 {
10176 }
10177 }
10178 else
10179 {
10182 {
10186 }
10187 }
10188 }
10189 else
10190 {
10197 else
10198 {
10200 {
10203 }
10205 }
10206 }
10207 }
10208 }
10210 }
10211 \f
10212 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10214 static rtx
10216 {
10228 }
10230 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10231 false if we expect this to be used for a memory address and true if
10232 we expect to load the address into a register. */
10234 static rtx
10236 {
10241 {
10247 {
10257 }
10260 else
10264 {
10268 }
10276 {
10288 }
10291 else
10295 {
10300 }
10308 {
10312 }
10318 {
10321 }
10323 {
10328 }
10330 {
10334 }
10335 else
10336 {
10339 }
10349 {
10353 }
10354 else
10355 {
10359 }
10369 {
10372 }
10373 else
10374 {
10378 }
10383 }
10386 }
10388 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10389 to symbol DECL. */
10392 htab_t dllimport_map;
10394 static tree
10396 {
10403 tree to;
10404 rtx rtl;
10448 }
10450 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10451 true if we require the result be a register. */
10453 static rtx
10455 {
10456 tree imp_decl;
10457 rtx x;
10466 }
10468 /* Try machine-dependent ways of modifying an illegitimate address
10469 to be legitimate. If we find one, return the new, valid address.
10470 This macro is used in only one place: `memory_address' in explow.c.
10472 OLDX is the address as it was before break_out_memory_refs was called.
10473 In some cases it is useful to look at this to decide what needs to be done.
10475 It is always safe for this macro to do nothing. It exists to recognize
10476 opportunities to optimize the output.
10478 For the 80386, we handle X+REG by loading X into a register R and
10479 using R+REG. R will go in a general reg and indexing will be used.
10480 However, if REG is a broken-out memory address or multiplication,
10481 nothing needs to be done because REG can certainly go in a general reg.
10483 When -fpic is used, special handling is needed for symbolic references.
10484 See comments by legitimize_pic_address in i386.c for details. */
10486 static rtx
10489 {
10500 {
10504 }
10507 {
10514 {
10517 }
10518 }
10523 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10527 {
10532 }
10535 {
10536 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10541 {
10547 }
10552 {
10558 }
10560 /* Put multiply first if it isn't already. */
10562 {
10567 }
10569 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10570 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10571 created by virtual register instantiation, register elimination, and
10572 similar optimizations. */
10574 {
10580 }
10582 /* Canonicalize
10583 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10584 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10589 {
10590 rtx constant;
10594 {
10597 }
10599 {
10602 }
10603 else
10607 {
10613 }
10614 }
10620 {
10623 }
10626 {
10629 }
10637 {
10640 }
10646 {
10654 }
10657 {
10665 }
10666 }
10669 }
10670 \f
10671 /* Print an integer constant expression in assembler syntax. Addition
10672 and subtraction are the only arithmetic that may appear in these
10673 expressions. FILE is the stdio stream to write to, X is the rtx, and
10674 CODE is the operand print code from the output string. */
10676 static void
10678 {
10682 {
10691 else
10692 {
10695 /* Mark the decl as referenced so that cgraph will
10696 output the function. */
10700 #if TARGET_MACHO
10704 #endif
10706 }
10714 /* FALLTHRU */
10725 /* This used to output parentheses around the expression,
10726 but that does not work on the 386 (either ATT or BSD assembler). */
10732 {
10733 /* We can use %d if the number is <32 bits and positive. */
10738 else
10740 }
10741 else
10742 /* We can't handle floating point constants;
10743 PRINT_OPERAND must handle them. */
10748 /* Some assemblers need integer constants to appear first. */
10750 {
10754 }
10755 else
10756 {
10761 }
10778 {
10793 /* FIXME: This might be @TPOFF in Sun ld too. */
10802 else
10812 else
10818 #if TARGET_MACHO
10823 #endif
10827 }
10832 }
10833 }
10835 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10836 We need to emit DTP-relative relocations. */
10838 static void ATTRIBUTE_UNUSED
10840 {
10845 {
10853 }
10854 }
10856 /* Return true if X is a representation of the PIC register. This copes
10857 with calls from ix86_find_base_term, where the register might have
10858 been replaced by a cselib value. */
10860 static bool
10862 {
10866 else
10868 }
10870 /* In the name of slightly smaller debug output, and to cater to
10871 general assembler lossage, recognize PIC+GOTOFF and turn it back
10872 into a direct symbol reference.
10874 On Darwin, this is necessary to avoid a crash, because Darwin
10875 has a different PIC label for each routine but the DWARF debugging
10876 information is not associated with any particular routine, so it's
10877 necessary to remove references to the PIC label from RTL stored by
10878 the DWARF output code. */
10880 static rtx
10882 {
10884 /* reg_addend is NULL or a multiple of some register. */
10886 /* const_addend is NULL or a const_int. */
10888 /* This is the result, or NULL. */
10897 {
10904 }
10911 /* %ebx + GOT/GOTOFF */
10912 ;
10914 {
10915 /* %ebx + %reg * scale + GOT/GOTOFF */
10921 else
10927 }
10928 else
10934 {
10937 }
10956 }
10958 /* If X is a machine specific address (i.e. a symbol or label being
10959 referenced as a displacement from the GOT implemented using an
10960 UNSPEC), then return the base term. Otherwise return X. */
10962 rtx
10964 {
10965 rtx term;
10968 {
10981 }
10984 }
10985 \f
10986 static void
10989 {
10993 {
10996 }
11001 {
11004 {
11023 }
11027 {
11046 }
11053 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11054 Those same assemblers have the same but opposite lossage on cmov. */
11059 else
11064 {
11077 }
11085 {
11098 }
11101 /* ??? As above. */
11110 /* ??? As above. */
11115 else
11126 }
11128 }
11130 /* Print the name of register X to FILE based on its machine mode and number.
11131 If CODE is 'w', pretend the mode is HImode.
11132 If CODE is 'b', pretend the mode is QImode.
11133 If CODE is 'k', pretend the mode is SImode.
11134 If CODE is 'q', pretend the mode is DImode.
11135 If CODE is 'x', pretend the mode is V4SFmode.
11136 If CODE is 't', pretend the mode is V8SFmode.
11137 If CODE is 'h', pretend the reg is the 'high' byte register.
11138 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11139 If CODE is 'd', duplicate the operand for AVX instruction.
11140 */
11142 void
11144 {
11159 {
11163 }
11181 else
11184 /* Irritatingly, AMD extended registers use different naming convention
11185 from the normal registers. */
11187 {
11190 {
11209 }
11211 }
11215 {
11218 {
11221 }
11222 /* FALLTHRU */
11228 /* FALLTHRU */
11231 normal:
11246 {
11251 }
11255 }
11259 {
11262 else
11264 }
11265 }
11267 /* Locate some local-dynamic symbol still in use by this function
11268 so that we can print its name in some tls_local_dynamic_base
11269 pattern. */
11271 static int
11273 {
11278 {
11281 }
11284 }
11288 {
11289 rtx insn;
11300 }
11302 /* Meaning of CODE:
11303 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11304 C -- print opcode suffix for set/cmov insn.
11305 c -- like C, but print reversed condition
11306 E,e -- likewise, but for compare-and-branch fused insn.
11307 F,f -- likewise, but for floating-point.
11308 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11309 otherwise nothing
11310 R -- print the prefix for register names.
11311 z -- print the opcode suffix for the size of the current operand.
11312 Z -- likewise, with special suffixes for x87 instructions.
11313 * -- print a star (in certain assembler syntax)
11314 A -- print an absolute memory reference.
11315 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11316 s -- print a shift double count, followed by the assemblers argument
11317 delimiter.
11318 b -- print the QImode name of the register for the indicated operand.
11319 %b0 would print %al if operands[0] is reg 0.
11320 w -- likewise, print the HImode name of the register.
11321 k -- likewise, print the SImode name of the register.
11322 q -- likewise, print the DImode name of the register.
11323 x -- likewise, print the V4SFmode name of the register.
11324 t -- likewise, print the V8SFmode name of the register.
11325 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11326 y -- print "st(0)" instead of "st" as a register.
11327 d -- print duplicated register operand for AVX instruction.
11328 D -- print condition for SSE cmp instruction.
11329 P -- if PIC, print an @PLT suffix.
11330 X -- don't print any sort of PIC '@' suffix for a symbol.
11331 & -- print some in-use local-dynamic symbol name.
11332 H -- print a memory address offset by 8; used for sse high-parts
11333 Y -- print condition for XOP pcom* instruction.
11334 + -- print a branch hint as 'cs' or 'ds' prefix
11335 ; -- print a semicolon (after prefixes due to bug in older gas).
11336 */
11338 void
11340 {
11342 {
11344 {
11351 {
11356 else
11359 }
11363 {
11369 /* Intel syntax. For absolute addresses, registers should not
11370 be surrounded by braces. */
11372 {
11377 }
11382 }
11420 {
11421 /* Opcodes don't get size suffixes if using Intel opcodes. */
11426 {
11444 output_operand_lossage
11447 }
11448 }
11451 warning
11453 /* FALLTHRU */
11456 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11461 {
11463 {
11465 #ifdef HAVE_AS_IX86_FILDS
11467 #endif
11475 #ifdef HAVE_AS_IX86_FILDQ
11477 #else
11479 #endif
11484 }
11485 }
11487 {
11488 /* 387 opcodes don't get size suffixes
11489 if the operands are registers. */
11494 {
11510 }
11511 }
11512 else
11513 {
11514 output_operand_lossage
11517 }
11519 output_operand_lossage
11538 {
11541 }
11545 /* Little bit of braindamage here. The SSE compare instructions
11546 does use completely different names for the comparisons that the
11547 fp conditional moves. */
11549 {
11551 {
11598 }
11599 }
11600 else
11601 {
11603 {
11638 }
11639 }
11642 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11644 {
11646 {
11653 }
11655 }
11656 #endif
11660 {
11662 "condition code, invalid operand code "
11665 }
11670 {
11672 "condition code, invalid operand code "
11675 }
11676 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11679 #endif
11683 /* Like above, but reverse condition */
11685 /* Check to see if argument to %c is really a constant
11686 and not a condition code which needs to be reversed. */
11688 {
11690 "condition code, invalid operand "
11693 }
11698 {
11700 "condition code, invalid operand "
11703 }
11704 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11707 #endif
11720 /* It doesn't actually matter what mode we use here, as we're
11721 only going to use this for printing. */
11726 {
11727 rtx x;
11735 {
11740 {
11744 /* Emit hints only in the case default branch prediction
11745 heuristics would fail. */
11747 {
11748 /* We use 3e (DS) prefix for taken branches and
11749 2e (CS) prefix for not taken branches. */
11752 else
11754 }
11755 }
11756 }
11758 }
11762 {
11813 }
11817 #if TARGET_MACHO
11819 #else
11821 #endif
11826 }
11827 }
11833 {
11834 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11837 {
11840 {
11849 else
11855 }
11857 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11867 }
11870 /* Avoid (%rip) for call operands. */
11876 else
11878 }
11881 {
11882 REAL_VALUE_TYPE r;
11891 }
11893 /* These float cases don't actually occur as immediate operands. */
11895 {
11900 }
11904 {
11909 }
11911 else
11912 {
11913 /* We have patterns that allow zero sets of memory, for instance.
11914 In 64-bit mode, we should probably support all 8-byte vectors,
11915 since we can in fact encode that into an immediate. */
11917 {
11920 }
11923 {
11925 {
11928 }
11931 {
11934 else
11936 }
11937 }
11942 else
11944 }
11945 }
11946 \f
11947 /* Print a memory operand whose address is ADDR. */
11949 void
11951 {
11965 {
11976 }
11978 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11980 {
11992 }
11994 {
11995 /* Displacement only requires special attention. */
11998 {
12002 }
12005 else
12007 }
12008 else
12009 {
12011 {
12013 {
12018 else
12020 }
12026 {
12031 }
12033 }
12034 else
12035 {
12039 {
12040 /* Pull out the offset of a symbol; print any symbol itself. */
12044 {
12048 }
12056 else
12058 }
12062 {
12065 {
12069 }
12070 }
12073 else
12077 {
12082 }
12084 }
12085 }
12086 }
12088 bool
12090 {
12091 rtx op;
12098 {
12101 /* FIXME: This might be @TPOFF in Sun ld. */
12112 else
12124 else
12131 #if TARGET_MACHO
12137 #endif
12141 }
12144 }
12145 \f
12146 /* Split one or more DImode RTL references into pairs of SImode
12147 references. The RTL can be REG, offsettable MEM, integer constant, or
12148 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12149 split and "num" is its length. lo_half and hi_half are output arrays
12150 that parallel "operands". */
12152 void
12154 {
12156 {
12159 /* simplify_subreg refuse to split volatile memory addresses,
12160 but we still have to handle it. */
12162 {
12165 }
12166 else
12167 {
12174 }
12175 }
12176 }
12177 /* Split one or more TImode RTL references into pairs of DImode
12178 references. The RTL can be REG, offsettable MEM, integer constant, or
12179 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12180 split and "num" is its length. lo_half and hi_half are output arrays
12181 that parallel "operands". */
12183 void
12185 {
12187 {
12190 /* simplify_subreg refuse to split volatile memory addresses, but we
12191 still have to handle it. */
12193 {
12196 }
12197 else
12198 {
12201 }
12202 }
12203 }
12204 \f
12205 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12206 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12207 is the expression of the binary operation. The output may either be
12208 emitted here, or returned to the caller, like all output_* functions.
12210 There is no guarantee that the operands are the same mode, as they
12211 might be within FLOAT or FLOAT_EXTEND expressions. */
12213 #ifndef SYSV386_COMPAT
12214 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12215 wants to fix the assemblers because that causes incompatibility
12216 with gcc. No-one wants to fix gcc because that causes
12217 incompatibility with assemblers... You can use the option of
12218 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12219 #define SYSV386_COMPAT 1
12220 #endif
12224 {
12230 #ifdef ENABLE_CHECKING
12231 /* Even if we do not want to check the inputs, this documents input
12232 constraints. Which helps in understanding the following code. */
12242 else
12244 #endif
12247 {
12252 else
12261 else
12270 else
12279 else
12286 }
12289 {
12291 {
12295 else
12297 }
12298 else
12299 {
12303 else
12305 }
12307 }
12311 {
12315 {
12319 }
12321 /* know operands[0] == operands[1]. */
12324 {
12327 }
12330 {
12332 /* How is it that we are storing to a dead operand[2]?
12333 Well, presumably operands[1] is dead too. We can't
12334 store the result to st(0) as st(0) gets popped on this
12335 instruction. Instead store to operands[2] (which I
12336 think has to be st(1)). st(1) will be popped later.
12337 gcc <= 2.8.1 didn't have this check and generated
12338 assembly code that the Unixware assembler rejected. */
12340 else
12343 }
12347 else
12354 {
12357 }
12360 {
12363 }
12366 {
12367 #if SYSV386_COMPAT
12368 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12369 derived assemblers, confusingly reverse the direction of
12370 the operation for fsub{r} and fdiv{r} when the
12371 destination register is not st(0). The Intel assembler
12372 doesn't have this brain damage. Read !SYSV386_COMPAT to
12373 figure out what the hardware really does. */
12376 else
12378 #else
12380 /* As above for fmul/fadd, we can't store to st(0). */
12382 else
12384 #endif
12386 }
12389 {
12390 #if SYSV386_COMPAT
12393 else
12395 #else
12398 else
12400 #endif
12402 }
12405 {
12408 else
12411 }
12413 {
12414 #if SYSV386_COMPAT
12416 #else
12418 #endif
12419 }
12420 else
12421 {
12422 #if SYSV386_COMPAT
12424 #else
12426 #endif
12427 }
12432 }
12436 }
12438 /* Return needed mode for entity in optimize_mode_switching pass. */
12440 int
12442 {
12445 /* The mode UNINITIALIZED is used to store control word after a
12446 function call or ASM pattern. The mode ANY specify that function
12447 has no requirements on the control word and make no changes in the
12448 bits we are interested in. */
12462 {
12485 }
12488 }
12490 /* Output code to initialize control word copies used by trunc?f?i and
12491 rounding patterns. CURRENT_MODE is set to current control word,
12492 while NEW_MODE is set to new control word. */
12494 void
12496 {
12498 rtx new_mode;
12509 {
12511 {
12513 /* round toward zero (truncate) */
12519 /* round down toward -oo */
12526 /* round up toward +oo */
12533 /* mask precision exception for nearbyint() */
12540 }
12541 }
12542 else
12543 {
12545 {
12547 /* round toward zero (truncate) */
12553 /* round down toward -oo */
12559 /* round up toward +oo */
12565 /* mask precision exception for nearbyint() */
12572 }
12573 }
12579 }
12581 /* Output code for INSN to convert a float to a signed int. OPERANDS
12582 are the insn operands. The output may be [HSD]Imode and the input
12583 operand may be [SDX]Fmode. */
12587 {
12592 /* Jump through a hoop or two for DImode, since the hardware has no
12593 non-popping instruction. We used to do this a different way, but
12594 that was somewhat fragile and broke with post-reload splitters. */
12604 else
12605 {
12610 else
12614 }
12617 }
12619 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12620 have the values zero or one, indicates the ffreep insn's operand
12621 from the OPERANDS array. */
12625 {
12627 #ifdef HAVE_AS_IX86_FFREEP
12629 #else
12630 {
12640 }
12641 #endif
12644 }
12647 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12648 should be used. UNORDERED_P is true when fucom should be used. */
12652 {
12658 {
12661 }
12662 else
12663 {
12666 }
12669 {
12678 else
12680 else
12683 else
12685 }
12692 {
12694 {
12697 }
12698 else
12700 }
12703 && stack_top_dies
12706 {
12707 /* If both the top of the 387 stack dies, and the other operand
12708 is also a stack register that dies, then this must be a
12709 `fcompp' float compare */
12712 {
12713 /* There is no double popping fcomi variant. Fortunately,
12714 eflags is immune from the fstp's cc clobbering. */
12717 else
12720 }
12721 else
12722 {
12725 else
12727 }
12728 }
12729 else
12730 {
12731 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12734 {
12742 NULL,
12743 NULL,
12750 NULL,
12751 NULL,
12752 NULL,
12753 NULL
12754 };
12769 }
12770 }
12772 void
12774 {
12777 #ifdef ASM_QUAD
12780 #else
12782 #endif
12785 }
12787 void
12789 {
12792 #ifdef ASM_QUAD
12795 #else
12797 #endif
12798 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12804 #if TARGET_MACHO
12806 {
12810 }
12811 #endif
12812 else
12815 }
12816 \f
12817 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12818 for the target. */
12820 void
12822 {
12823 rtx tmp;
12825 /* We play register width games, which are only valid after reload. */
12828 /* Avoid HImode and its attendant prefix byte. */
12833 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12835 {
12838 }
12841 }
12843 /* X is an unchanging MEM. If it is a constant pool reference, return
12844 the constant pool rtx, else NULL. */
12846 rtx
12848 {
12855 }
12857 void
12859 {
12867 {
12870 {
12875 }
12879 }
12883 {
12896 {
12902 }
12903 }
12906 {
12908 {
12909 #if TARGET_MACHO
12911 {
12912 rtx temp = ((reload_in_progress
12919 }
12924 #endif
12925 }
12926 else
12927 {
12931 {
12936 }
12937 }
12938 }
12939 else
12940 {
12951 /* Force large constants in 64bit compilation into register
12952 to get them CSEed. */
12964 {
12965 /* If we are loading a floating point constant to a register,
12966 force the value to memory now, since we'll get better code
12967 out the back end. */
12971 {
12976 }
12977 }
12978 }
12981 }
12983 void
12985 {
12989 /* Force constants other than zero into memory. We do not know how
12990 the instructions used to build constants modify the upper 64 bits
12991 of the register, once we have that information we may be able
12992 to handle some of them more efficiently. */
13001 /* We need to check memory alignment for SSE mode since attribute
13002 can make operands unaligned. */
13007 {
13010 /* ix86_expand_vector_move_misalign() does not like constants ... */
13016 /* ... nor both arguments in memory. */
13024 }
13026 /* Make operand1 a register if it isn't already. */
13030 {
13033 }
13036 }
13038 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13039 straight to ix86_expand_vector_move. */
13040 /* Code generation for scalar reg-reg moves of single and double precision data:
13041 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13042 movaps reg, reg
13043 else
13044 movss reg, reg
13045 if (x86_sse_partial_reg_dependency == true)
13046 movapd reg, reg
13047 else
13048 movsd reg, reg
13050 Code generation for scalar loads of double precision data:
13051 if (x86_sse_split_regs == true)
13052 movlpd mem, reg (gas syntax)
13053 else
13054 movsd mem, reg
13056 Code generation for unaligned packed loads of single precision data
13057 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13058 if (x86_sse_unaligned_move_optimal)
13059 movups mem, reg
13061 if (x86_sse_partial_reg_dependency == true)
13062 {
13063 xorps reg, reg
13064 movlps mem, reg
13065 movhps mem+8, reg
13066 }
13067 else
13068 {
13069 movlps mem, reg
13070 movhps mem+8, reg
13071 }
13073 Code generation for unaligned packed loads of double precision data
13074 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13075 if (x86_sse_unaligned_move_optimal)
13076 movupd mem, reg
13078 if (x86_sse_split_regs == true)
13079 {
13080 movlpd mem, reg
13081 movhpd mem+8, reg
13082 }
13083 else
13084 {
13085 movsd mem, reg
13086 movhpd mem+8, reg
13087 }
13088 */
13090 void
13092 {
13099 {
13101 {
13105 {
13118 }
13125 {
13140 }
13145 }
13148 }
13151 {
13152 /* If we're optimizing for size, movups is the smallest. */
13154 {
13159 }
13161 /* ??? If we have typed data, then it would appear that using
13162 movdqu is the only way to get unaligned data loaded with
13163 integer type. */
13165 {
13170 }
13173 {
13174 rtx zero;
13177 {
13182 }
13184 /* When SSE registers are split into halves, we can avoid
13185 writing to the top half twice. */
13187 {
13190 }
13191 else
13192 {
13193 /* ??? Not sure about the best option for the Intel chips.
13194 The following would seem to satisfy; the register is
13195 entirely cleared, breaking the dependency chain. We
13196 then store to the upper half, with a dependency depth
13197 of one. A rumor has it that Intel recommends two movsd
13198 followed by an unpacklpd, but this is unconfirmed. And
13199 given that the dependency depth of the unpacklpd would
13200 still be one, I'm not sure why this would be better. */
13202 }
13208 }
13209 else
13210 {
13212 {
13217 }
13221 else
13230 }
13231 }
13233 {
13234 /* If we're optimizing for size, movups is the smallest. */
13236 {
13241 }
13243 /* ??? Similar to above, only less clear because of quote
13244 typeless stores unquote. */
13247 {
13252 }
13255 {
13260 }
13261 else
13262 {
13269 }
13270 }
13271 else
13273 }
13275 /* Expand a push in MODE. This is some mode for which we do not support
13276 proper push instructions, at least from the registers that we expect
13277 the value to live in. */
13279 void
13281 {
13282 rtx tmp;
13292 /* When we push an operand onto stack, it has to be aligned at least
13293 at the function argument boundary. However since we don't have
13294 the argument type, we can't determine the actual argument
13295 boundary. */
13297 }
13299 /* Helper function of ix86_fixup_binary_operands to canonicalize
13300 operand order. Returns true if the operands should be swapped. */
13302 static bool
13304 rtx operands[])
13305 {
13310 /* If the operation is not commutative, we can't do anything. */
13314 /* Highest priority is that src1 should match dst. */
13320 /* Next highest priority is that immediate constants come second. */
13326 /* Lowest priority is that memory references should come second. */
13333 }
13336 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13337 destination to use for the operation. If different from the true
13338 destination in operands[0], a copy operation will be required. */
13340 rtx
13342 rtx operands[])
13343 {
13348 /* Canonicalize operand order. */
13350 {
13351 rtx temp;
13353 /* It is invalid to swap operands of different modes. */
13359 }
13361 /* Both source operands cannot be in memory. */
13363 {
13364 /* Optimization: Only read from memory once. */
13366 {
13369 }
13370 else
13372 }
13374 /* If the destination is memory, and we do not have matching source
13375 operands, do things in registers. */
13379 /* Source 1 cannot be a constant. */
13383 /* Source 1 cannot be a non-matching memory. */
13387 /* In order for the multiply-add patterns to get matched, we need
13388 to aid combine by forcing all operands into registers to start. */
13390 {
13395 }
13400 }
13402 /* Similarly, but assume that the destination has already been
13403 set up properly. */
13405 void
13408 {
13411 }
13413 /* Attempt to expand a binary operator. Make the expansion closer to the
13414 actual machine, then just general_operand, which will allow 3 separate
13415 memory references (one output, two input) in a single insn. */
13417 void
13419 rtx operands[])
13420 {
13427 /* Emit the instruction. */
13431 {
13432 /* Reload doesn't know about the flags register, and doesn't know that
13433 it doesn't want to clobber it. We can only do this with PLUS. */
13436 }
13437 else
13438 {
13441 }
13443 /* Fix up the destination if needed. */
13446 }
13448 /* Return TRUE or FALSE depending on whether the binary operator meets the
13449 appropriate constraints. */
13451 int
13454 {
13459 /* Both source operands cannot be in memory. */
13463 /* Canonicalize operand order for commutative operators. */
13465 {
13469 }
13471 /* If the destination is memory, we must have a matching source operand. */
13475 /* Source 1 cannot be a constant. */
13479 /* Source 1 cannot be a non-matching memory. */
13484 }
13486 /* Attempt to expand a unary operator. Make the expansion closer to the
13487 actual machine, then just general_operand, which will allow 2 separate
13488 memory references (one output, one input) in a single insn. */
13490 void
13492 rtx operands[])
13493 {
13500 /* If the destination is memory, and we do not have matching source
13501 operands, do things in registers. */
13504 {
13507 else
13509 }
13511 /* When source operand is memory, destination must match. */
13515 /* Emit the instruction. */
13519 {
13520 /* Reload doesn't know about the flags register, and doesn't know that
13521 it doesn't want to clobber it. */
13524 }
13525 else
13526 {
13529 }
13531 /* Fix up the destination if needed. */
13534 }
13536 #define LEA_SEARCH_THRESHOLD 12
13538 /* Search backward for non-agu definition of register number REGNO1
13539 or register number REGNO2 in INSN's basic block until
13540 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13541 2. Reach BB boundary, or
13542 3. Reach agu definition.
13543 Returns the distance between the non-agu definition point and INSN.
13544 If no definition point, returns -1. */
13546 static int
13548 rtx insn)
13549 {
13556 {
13559 {
13561 {
13562 distance++;
13568 {
13572 }
13573 }
13577 }
13578 }
13581 {
13582 edge e;
13583 edge_iterator ei;
13588 {
13591 }
13594 {
13599 {
13601 {
13602 distance++;
13608 {
13612 }
13613 }
13615 }
13616 }
13617 }
13621 done:
13622 /* get_attr_type may modify recog data. We want to make sure
13623 that recog data is valid for instruction INSN, on which
13624 distance_non_agu_define is called. INSN is unchanged here. */
13627 }
13629 /* Return the distance between INSN and the next insn that uses
13630 register number REGNO0 in memory address. Return -1 if no such
13631 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13633 static int
13635 {
13642 {
13645 {
13647 {
13648 distance++;
13654 {
13655 /* Return DISTANCE if OP0 is used in memory
13656 address in NEXT. */
13658 }
13664 {
13665 /* Return -1 if OP0 is set in NEXT. */
13667 }
13668 }
13672 }
13673 }
13676 {
13677 edge e;
13678 edge_iterator ei;
13683 {
13686 }
13689 {
13694 {
13696 {
13697 distance++;
13703 {
13704 /* Return DISTANCE if OP0 is used in memory
13705 address in NEXT. */
13707 }
13713 {
13714 /* Return -1 if OP0 is set in NEXT. */
13716 }
13718 }
13720 }
13721 }
13722 }
13725 }
13727 /* Define this macro to tune LEA priority vs ADD, it take effect when
13728 there is a dilemma of choicing LEA or ADD
13729 Negative value: ADD is more preferred than LEA
13730 Zero: Netrual
13731 Positive value: LEA is more preferred than ADD*/
13732 #define IX86_LEA_PRIORITY 2
13734 /* Return true if it is ok to optimize an ADD operation to LEA
13735 operation to avoid flag register consumation. For the processors
13736 like ATOM, if the destination register of LEA holds an actual
13737 address which will be used soon, LEA is better and otherwise ADD
13738 is better. */
13740 bool
13743 {
13753 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13756 else
13757 {
13763 /* If this insn has both backward non-agu dependence and forward
13764 agu dependence, the one with short distance take effect. */
13771 }
13772 }
13774 /* Return true if destination reg of SET_BODY is shift count of
13775 USE_BODY. */
13777 static bool
13779 {
13780 rtx set_dest;
13781 rtx shift_rtx;
13784 /* Retrieve destination of SET_BODY. */
13786 {
13795 use_body))
13800 }
13802 /* Retrieve shift count of USE_BODY. */
13804 {
13816 }
13824 {
13827 /* Return true if shift count is dest of SET_BODY. */
13831 }
13834 }
13836 /* Return true if destination reg of SET_INSN is shift count of
13837 USE_INSN. */
13839 bool
13841 {
13844 }
13846 /* Return TRUE or FALSE depending on whether the unary operator meets the
13847 appropriate constraints. */
13849 int
13853 {
13854 /* If one of operands is memory, source and destination must match. */
13860 }
13862 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
13863 are ok, keeping in mind the possible movddup alternative. */
13865 bool
13867 {
13873 }
13875 /* Post-reload splitter for converting an SF or DFmode value in an
13876 SSE register into an unsigned SImode. */
13878 void
13880 {
13891 /* Load up the value into the low element. We must ensure that the other
13892 elements are valid floats -- zero is the easiest such value. */
13894 {
13897 else
13899 }
13900 else
13901 {
13906 else
13908 }
13928 else
13933 }
13935 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13936 Expects the 64-bit DImode to be supplied in a pair of integral
13937 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13938 -mfpmath=sse, !optimize_size only. */
13940 void
13942 {
13946 rtx x;
13952 {
13955 }
13956 else
13957 {
13961 }
13969 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13972 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13973 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13974 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13975 (0x1.0p84 + double(fp_value_hi_xmm)).
13976 Note these exponents differ by 32. */
13980 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13981 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13990 /* Add the upper and lower DFmode values together. */
13993 else
13994 {
13998 }
14001 }
14003 /* Not used, but eases macroization of patterns. */
14004 void
14006 rtx input ATTRIBUTE_UNUSED)
14007 {
14009 }
14011 /* Convert an unsigned SImode value into a DFmode. Only currently used
14012 for SSE, but applicable anywhere. */
14014 void
14016 {
14017 REAL_VALUE_TYPE TWO31r;
14032 }
14034 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14035 32-bit mode; otherwise we have a direct convert instruction. */
14037 void
14039 {
14040 REAL_VALUE_TYPE TWO32r;
14058 }
14060 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14061 For x86_32, -mfpmath=sse, !optimize_size only. */
14062 void
14064 {
14065 REAL_VALUE_TYPE ONE16r;
14084 }
14086 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14087 then replicate the value for all elements of the vector
14088 register. */
14090 rtx
14092 {
14093 rtvec v;
14095 {
14109 else
14117 else
14123 }
14124 }
14126 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14127 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14128 for an SSE register. If VECT is true, then replicate the mask for
14129 all elements of the vector register. If INVERT is true, then create
14130 a mask excluding the sign bit. */
14132 rtx
14134 {
14138 rtx v;
14139 rtx mask;
14141 /* Find the sign bit, sign extended to 2*HWI. */
14143 {
14157 else
14165 {
14168 }
14169 else
14170 {
14171 rtvec vec;
14177 {
14180 }
14181 else
14191 }
14196 }
14201 /* Force this value into the low part of a fp vector constant. */
14210 }
14212 /* Generate code for floating point ABS or NEG. */
14214 void
14216 rtx operands[])
14217 {
14224 {
14227 }
14233 /* NEG and ABS performed with SSE use bitwise mask operations.
14234 Create the appropriate mask now. */
14237 else
14244 {
14248 }
14249 else
14250 {
14254 {
14259 }
14260 else
14262 }
14263 }
14265 /* Expand a copysign operation. Special case operand 0 being a constant. */
14267 void
14269 {
14280 {
14287 {
14294 else
14295 {
14299 }
14300 }
14310 else
14314 }
14315 else
14316 {
14326 else
14330 }
14331 }
14333 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14334 be a constant, and so has already been expanded into a vector constant. */
14336 void
14338 {
14354 {
14357 }
14358 }
14360 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14361 so we have to do two masks. */
14363 void
14365 {
14380 {
14381 /* Shouldn't happen often (it's useless, obviously), but when it does
14382 we'd generate incorrect code if we continue below. */
14385 }
14388 {
14399 }
14400 else
14401 {
14403 {
14405 }
14407 {
14411 }
14415 {
14418 }
14420 {
14425 }
14427 }
14431 }
14433 /* Return TRUE or FALSE depending on whether the first SET in INSN
14434 has source and destination with matching CC modes, and that the
14435 CC mode is at least as constrained as REQ_MODE. */
14437 int
14439 {
14440 rtx set;
14451 {
14461 /* FALLTHRU */
14465 /* FALLTHRU */
14469 /* FALLTHRU */
14479 }
14482 }
14484 /* Generate insn patterns to do an integer compare of OPERANDS. */
14486 static rtx
14488 {
14495 /* This is very simple, but making the interface the same as in the
14496 FP case makes the rest of the code easier. */
14500 /* Return the test that should be put into the flags user, i.e.
14501 the bcc, scc, or cmov instruction. */
14503 }
14505 /* Figure out whether to use ordered or unordered fp comparisons.
14506 Return the appropriate mode to use. */
14508 enum machine_mode
14510 {
14511 /* ??? In order to make all comparisons reversible, we do all comparisons
14512 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14513 all forms trapping and nontrapping comparisons, we can make inequality
14514 comparisons trapping again, since it results in better code when using
14515 FCOM based compares. */
14517 }
14519 enum machine_mode
14521 {
14525 {
14528 }
14531 {
14532 /* Only zero flag is needed. */
14536 /* Codes needing carry flag. */
14539 /* Detect overflow checks. They need just the carry flag. */
14543 else
14547 /* Detect overflow checks. They need just the carry flag. */
14551 else
14553 /* Codes possibly doable only with sign flag when
14554 comparing against zero. */
14559 else
14560 /* For other cases Carry flag is not required. */
14562 /* Codes doable only with sign flag when comparing
14563 against zero, but we miss jump instruction for it
14564 so we need to use relational tests against overflow
14565 that thus needs to be zero. */
14570 else
14572 /* strcmp pattern do (use flags) and combine may ask us for proper
14573 mode. */
14578 }
14579 }
14581 /* Return the fixed registers used for condition codes. */
14583 static bool
14585 {
14589 }
14591 /* If two condition code modes are compatible, return a condition code
14592 mode which is compatible with both. Otherwise, return
14593 VOIDmode. */
14595 static enum machine_mode
14597 {
14609 {
14623 {
14637 }
14641 /* These are only compatible with themselves, which we already
14642 checked above. */
14644 }
14645 }
14648 /* Return a comparison we can do and that it is equivalent to
14649 swap_condition (code) apart possibly from orderedness.
14650 But, never change orderedness if TARGET_IEEE_FP, returning
14651 UNKNOWN in that case if necessary. */
14653 static enum rtx_code
14655 {
14657 {
14668 }
14669 }
14671 /* Return cost of comparison CODE using the best strategy for performance.
14672 All following functions do use number of instructions as a cost metrics.
14673 In future this should be tweaked to compute bytes for optimize_size and
14674 take into account performance of various instructions on various CPUs. */
14676 static int
14678 {
14681 /* The cost of code using bit-twiddling on %ah. */
14683 {
14706 }
14709 {
14716 }
14717 }
14719 /* Return strategy to use for floating-point. We assume that fcomi is always
14720 preferrable where available, since that is also true when looking at size
14721 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14723 enum ix86_fpcmp_strategy
14725 {
14726 /* Do fcomi/sahf based test when profitable. */
14735 }
14737 /* Swap, force into registers, or otherwise massage the two operands
14738 to a fp comparison. The operands are updated in place; the new
14739 comparison code is returned. */
14741 static enum rtx_code
14743 {
14749 /* All of the unordered compare instructions only work on registers.
14750 The same is true of the fcomi compare instructions. The XFmode
14751 compare instructions require registers except when comparing
14752 against zero or when converting operand 1 from fixed point to
14753 floating point. */
14762 {
14765 }
14766 else
14767 {
14768 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14769 things around if they appear profitable, otherwise force op0
14770 into a register. */
14776 {
14779 {
14780 rtx tmp;
14783 }
14784 }
14790 {
14795 {
14798 }
14799 else
14801 }
14802 }
14804 /* Try to rearrange the comparison to make it cheaper. */
14808 {
14809 rtx tmp;
14814 }
14819 }
14821 /* Convert comparison codes we use to represent FP comparison to integer
14822 code that will result in proper branch. Return UNKNOWN if no such code
14823 is available. */
14825 enum rtx_code
14827 {
14829 {
14852 }
14853 }
14855 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14857 static rtx
14859 {
14866 /* Do fcomi/sahf based test when profitable. */
14868 {
14873 tmp);
14881 tmp);
14890 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14897 /* In the unordered case, we have to check C2 for NaN's, which
14898 doesn't happen to work out to anything nice combination-wise.
14899 So do some bit twiddling on the value we've got in AH to come
14900 up with an appropriate set of condition codes. */
14904 {
14908 {
14911 }
14912 else
14913 {
14919 }
14924 {
14929 }
14930 else
14931 {
14934 }
14939 {
14942 }
14943 else
14944 {
14948 }
14953 {
14959 }
14960 else
14961 {
14964 }
14969 {
14974 }
14975 else
14976 {
14979 }
14984 {
14989 }
14990 else
14991 {
14994 }
15008 }
15013 }
15015 /* Return the test that should be put into the flags user, i.e.
15016 the bcc, scc, or cmov instruction. */
15019 const0_rtx);
15020 }
15022 rtx
15024 {
15033 {
15036 }
15037 else
15041 }
15043 void
15045 {
15046 rtx tmp;
15049 {
15056 simple:
15060 pc_rtx);
15068 /* Expand DImode branch into multiple compare+branch. */
15069 {
15075 {
15080 }
15082 {
15086 }
15087 else
15088 {
15092 }
15094 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15095 avoid two branches. This costs one extra insn, so disable when
15096 optimizing for size. */
15101 {
15121 }
15123 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15124 op1 is a constant and the low word is zero, then we can just
15125 examine the high word. Similarly for low word -1 and
15126 less-or-equal-than or greater-than. */
15130 {
15133 {
15138 }
15142 {
15147 }
15151 }
15153 /* Otherwise, we need two or three jumps. */
15162 {
15176 }
15178 /*
15179 * a < b =>
15180 * if (hi(a) < hi(b)) goto true;
15181 * if (hi(a) > hi(b)) goto false;
15182 * if (lo(a) < lo(b)) goto true;
15183 * false:
15184 */
15201 }
15204 /* If we have already emitted a compare insn, go straight to simple.
15205 ix86_expand_compare won't emit anything if ix86_compare_emitted
15206 is non NULL. */
15209 }
15210 }
15212 /* Split branch based on floating point condition. */
15213 void
15216 {
15217 rtx condition;
15218 rtx i;
15221 {
15226 }
15229 tmp);
15231 /* Remove pushed operand from stack. */
15241 }
15243 void
15245 {
15246 rtx ret;
15253 }
15255 /* Expand comparison setting or clearing carry flag. Return true when
15256 successful and set pop for the operation. */
15257 static bool
15259 {
15263 /* Do not handle DImode compares that go through special path. */
15268 {
15273 /* Shortcut: following common codes never translate
15274 into carry flag compares. */
15279 /* These comparisons require zero flag; swap operands so they won't. */
15282 {
15287 }
15289 /* Try to expand the comparison and verify that we end up with
15290 carry flag based comparison. This fails to be true only when
15291 we decide to expand comparison using arithmetic that is not
15292 too common scenario. */
15301 else
15310 }
15316 {
15321 /* Convert a==0 into (unsigned)a<1. */
15330 /* Convert a>b into b<a or a>=b-1. */
15334 {
15336 /* Bail out on overflow. We still can swap operands but that
15337 would force loading of the constant into register. */
15342 }
15343 else
15344 {
15349 }
15352 /* Convert a>=0 into (unsigned)a<0x80000000. */
15370 }
15371 /* Swapping operands may cause constant to appear as first operand. */
15373 {
15377 }
15383 }
15385 int
15387 {
15406 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15407 HImode insns, we'd be swallowed in word prefix ops. */
15413 {
15417 HOST_WIDE_INT diff;
15420 /* Sign bit compares are better done using shifts than we do by using
15421 sbb. */
15425 {
15426 /* Detect overlap between destination and compare sources. */
15430 {
15431 rtx flags;
15441 {
15443 compare_code
15445 }
15447 /* To simplify rest of code, restrict to the GEU case. */
15449 {
15455 }
15456 else
15457 {
15460 reverse_condition_maybe_unordered
15462 else
15465 }
15474 else
15478 }
15479 else
15480 {
15483 else
15484 {
15489 }
15492 }
15495 {
15496 /*
15497 * cmpl op0,op1
15498 * sbbl dest,dest
15499 * [addl dest, ct]
15500 *
15501 * Size 5 - 8.
15502 */
15507 }
15509 {
15510 /*
15511 * cmpl op0,op1
15512 * sbbl dest,dest
15513 * orl $ct, dest
15514 *
15515 * Size 8.
15516 */
15520 }
15522 {
15523 /*
15524 * cmpl op0,op1
15525 * sbbl dest,dest
15526 * notl dest
15527 * [addl dest, cf]
15528 *
15529 * Size 8 - 11.
15530 */
15536 }
15537 else
15538 {
15539 /*
15540 * cmpl op0,op1
15541 * sbbl dest,dest
15542 * [notl dest]
15543 * andl cf - ct, dest
15544 * [addl dest, ct]
15545 *
15546 * Size 8 - 11.
15547 */
15550 {
15554 }
15564 }
15570 }
15573 {
15576 HOST_WIDE_INT tmp;
15581 {
15584 /* We may be reversing unordered compare to normal compare, that
15585 is not valid in general (we may convert non-trapping condition
15586 to trapping one), however on i386 we currently emit all
15587 comparisons unordered. */
15590 }
15591 else
15592 {
15595 }
15596 }
15601 {
15606 {
15611 }
15612 }
15614 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15618 {
15619 /* If lea code below could be used, only optimize
15620 if it results in a 2 insn sequence. */
15626 {
15627 /*
15628 * notl op1 (if necessary)
15629 * sarl $31, op1
15630 * orl cf, op1
15631 */
15633 {
15637 }
15649 }
15650 }
15658 {
15659 /*
15660 * xorl dest,dest
15661 * cmpl op1,op2
15662 * setcc dest
15663 * lea cf(dest*(ct-cf)),dest
15664 *
15665 * Size 14.
15666 *
15667 * This also catches the degenerate setcc-only case.
15668 */
15670 rtx tmp;
15677 /* On x86_64 the lea instruction operates on Pmode, so we need
15678 to get arithmetics done in proper mode to match. */
15681 else
15682 {
15683 rtx out1;
15686 nops++;
15688 {
15690 nops++;
15691 }
15692 }
15694 {
15696 nops++;
15697 }
15699 {
15702 else
15704 }
15709 }
15711 /*
15712 * General case: Jumpful:
15713 * xorl dest,dest cmpl op1, op2
15714 * cmpl op1, op2 movl ct, dest
15715 * setcc dest jcc 1f
15716 * decl dest movl cf, dest
15717 * andl (cf-ct),dest 1:
15718 * addl ct,dest
15719 *
15720 * Size 20. Size 14.
15721 *
15722 * This is reasonably steep, but branch mispredict costs are
15723 * high on modern cpus, so consider failing only if optimizing
15724 * for space.
15725 */
15730 {
15732 {
15739 {
15742 /* We may be reversing unordered compare to normal compare,
15743 that is not valid in general (we may convert non-trapping
15744 condition to trapping one), however on i386 we currently
15745 emit all comparisons unordered. */
15747 }
15748 else
15749 {
15753 }
15754 }
15757 {
15758 /* notl op1 (if needed)
15759 sarl $31, op1
15760 andl (cf-ct), op1
15761 addl ct, op1
15763 For x < 0 (resp. x <= -1) there will be no notl,
15764 so if possible swap the constants to get rid of the
15765 complement.
15766 True/false will be -1/0 while code below (store flag
15767 followed by decrement) is 0/-1, so the constants need
15768 to be exchanged once more. */
15771 {
15774 }
15775 else
15776 {
15780 }
15784 }
15785 else
15786 {
15792 }
15804 }
15805 }
15808 {
15809 /* Try a few things more with specific constants and a variable. */
15811 optab op;
15817 /* If one of the two operands is an interesting constant, load a
15818 constant with the above and mask it in with a logical operation. */
15821 {
15827 else
15829 }
15831 {
15837 else
15839 }
15840 else
15847 /* Recurse to get the constant loaded. */
15851 /* Mask in the interesting variable. */
15853 OPTAB_WIDEN);
15858 }
15860 /*
15861 * For comparison with above,
15862 *
15863 * movl cf,dest
15864 * movl ct,tmp
15865 * cmpl op1,op2
15866 * cmovcc tmp,dest
15867 *
15868 * Size 15.
15869 */
15892 }
15894 /* Swap, force into registers, or otherwise massage the two operands
15895 to an sse comparison with a mask result. Thus we differ a bit from
15896 ix86_prepare_fp_compare_args which expects to produce a flags result.
15898 The DEST operand exists to help determine whether to commute commutative
15899 operators. The POP0/POP1 operands are updated in place. The new
15900 comparison code is returned, or UNKNOWN if not implementable. */
15902 static enum rtx_code
15905 {
15906 rtx tmp;
15909 {
15912 /* We have no LTGT as an operator. We could implement it with
15913 NE & ORDERED, but this requires an extra temporary. It's
15914 not clear that it's worth it. */
15921 /* These are supported directly. */
15928 /* For commutative operators, try to canonicalize the destination
15929 operand to be first in the comparison - this helps reload to
15930 avoid extra moves. */
15933 /* FALLTHRU */
15939 /* These are not supported directly. Swap the comparison operands
15940 to transform into something that is supported. */
15949 }
15952 }
15954 /* Detect conditional moves that exactly match min/max operational
15955 semantics. Note that this is IEEE safe, as long as we don't
15956 interchange the operands.
15958 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15959 and TRUE if the operation is successful and instructions are emitted. */
15961 static bool
15964 {
15967 rtx tmp;
15970 ;
15972 {
15976 }
15977 else
15984 else
15989 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15990 but MODE may be a vector mode and thus not appropriate. */
15992 {
15994 rtvec v;
15999 }
16000 else
16001 {
16004 }
16008 }
16010 /* Expand an sse vector comparison. Return the register with the result. */
16012 static rtx
16015 {
16017 rtx x;
16032 }
16034 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16035 operations. This is used for both scalar and vector conditional moves. */
16037 static void
16039 {
16044 {
16048 }
16050 {
16055 }
16057 {
16060 op_true,
16061 op_false));
16063 }
16064 else
16065 {
16072 else
16084 }
16085 }
16087 /* Expand a floating-point conditional move. Return true if successful. */
16089 int
16091 {
16099 {
16102 /* Since we've no cmove for sse registers, don't force bad register
16103 allocation just to gain access to it. Deny movcc when the
16104 comparison mode doesn't match the move mode. */
16126 }
16128 /* The floating point conditional move instructions don't directly
16129 support conditions resulting from a signed integer comparison. */
16133 {
16140 }
16147 }
16149 /* Expand a floating-point vector conditional move; a vcond operation
16150 rather than a movcc operation. */
16152 bool
16154 {
16156 rtx cmp;
16171 }
16173 /* Expand a signed/unsigned integral vector conditional move. */
16175 bool
16177 {
16186 /* XOP supports all of the comparisons on all vector int types. */
16188 {
16189 /* Canonicalize the comparison to EQ, GT, GTU. */
16191 {
16208 /* FALLTHRU */
16218 }
16220 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16222 {
16224 {
16226 /* SSE4.1 supports EQ. */
16233 /* SSE4.2 supports GT/GTU. */
16240 }
16241 }
16243 /* Unsigned parallel compare is not supported by the hardware. Play some
16244 tricks to turn this into a signed comparison against 0. */
16246 {
16250 {
16253 {
16256 /* Perform a parallel modulo subtraction. */
16259 ? gen_subv4si3
16262 /* Extract the original sign bit of op0. */
16267 ? gen_andv4si3
16270 /* XOR it back into the result of the subtraction. This results
16271 in the sign bit set iff we saw unsigned underflow. */
16274 ? gen_xorv4si3
16278 }
16283 /* Perform a parallel unsigned saturating subtraction. */
16294 }
16298 }
16299 }
16307 }
16309 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16310 true if we should do zero extension, else sign extension. HIGH_P is
16311 true if we want the N/2 high elements, else the low elements. */
16313 void
16315 {
16321 {
16325 else
16331 else
16337 else
16342 }
16348 else
16353 }
16355 /* This function performs the same task as ix86_expand_sse_unpack,
16356 but with SSE4.1 instructions. */
16358 void
16360 {
16366 {
16370 else
16376 else
16382 else
16387 }
16391 {
16392 /* Shift higher 8 bytes to lower 8 bytes. */
16397 }
16398 else
16402 }
16404 /* Expand conditional increment or decrement using adb/sbb instructions.
16405 The default case using setcc followed by the conditional move can be
16406 done by generic code. */
16407 int
16409 {
16411 rtx flags;
16413 rtx compare_op;
16432 {
16435 }
16438 {
16442 reverse_condition_maybe_unordered
16444 else
16446 }
16450 /* Construct either adc or sbb insn. */
16452 {
16454 {
16469 }
16470 }
16471 else
16472 {
16474 {
16489 }
16490 }
16494 }
16497 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16498 works for floating pointer parameters and nonoffsetable memories.
16499 For pushes, it returns just stack offsets; the values will be saved
16500 in the right order. Maximally three parts are generated. */
16502 static int
16504 {
16509 else
16515 /* Optimize constant pool reference to immediates. This is used by fp
16516 moves, that force all constants to memory to allow combining. */
16518 {
16522 }
16525 {
16526 /* The only non-offsetable memories we handle are pushes. */
16535 }
16538 {
16540 /* Caution: if we looked through a constant pool memory above,
16541 the operand may actually have a different mode now. That's
16542 ok, since we want to pun this all the way back to an integer. */
16546 }
16549 {
16552 else
16553 {
16557 {
16561 }
16563 {
16568 }
16570 {
16571 REAL_VALUE_TYPE r;
16576 {
16591 }
16594 }
16595 else
16597 }
16598 }
16599 else
16600 {
16604 {
16607 {
16611 }
16613 {
16617 }
16619 {
16620 REAL_VALUE_TYPE r;
16626 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16629 = gen_int_mode
16632 DImode);
16633 else
16640 = gen_int_mode
16643 DImode);
16644 else
16646 }
16647 else
16649 }
16650 }
16653 }
16655 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16656 Return false when normal moves are needed; true when all required
16657 insns have been emitted. Operands 2-4 contain the input values
16658 int the correct order; operands 5-7 contain the output values. */
16660 void
16662 {
16670 /* The DFmode expanders may ask us to move double.
16671 For 64bit target this is single move. By hiding the fact
16672 here we simplify i386.md splitters. */
16674 {
16675 /* Optimize constant pool reference to immediates. This is used by
16676 fp moves, that force all constants to memory to allow combining. */
16683 {
16686 }
16687 else
16692 }
16694 /* The only non-offsettable memory we handle is push. */
16697 else
16704 /* When emitting push, take care for source operands on the stack. */
16707 {
16710 /* Compensate for the stack decrement by 4. */
16715 /* src_base refers to the stack pointer and is
16716 automatically decreased by emitted push. */
16720 }
16722 /* We need to do copy in the right order in case an address register
16723 of the source overlaps the destination. */
16725 {
16726 rtx tmp;
16729 {
16733 collisions++;
16734 }
16736 /* Collision in the middle part can be handled by reordering. */
16738 {
16741 }
16745 {
16747 {
16750 }
16751 else
16752 {
16755 }
16756 }
16758 /* If there are more collisions, we can't handle it by reordering.
16759 Do an lea to the last part and use only one colliding move. */
16761 {
16762 rtx base;
16768 /* Handle the case when the last part isn't valid for lea.
16769 Happens in 64-bit mode storing the 12-byte XFmode. */
16776 {
16779 }
16780 }
16781 }
16784 {
16786 {
16788 {
16793 }
16795 {
16798 }
16799 }
16800 else
16801 {
16802 /* In 64bit mode we don't have 32bit push available. In case this is
16803 register, it is OK - we will just use larger counterpart. We also
16804 retype memory - these comes from attempt to avoid REX prefix on
16805 moving of second half of TFmode value. */
16807 {
16809 {
16820 }
16824 }
16825 }
16829 }
16831 /* Choose correct order to not overwrite the source before it is copied. */
16841 {
16843 {
16846 }
16847 }
16848 else
16849 {
16851 {
16854 }
16855 }
16857 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16859 {
16868 }
16874 }
16876 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16877 left shift by a constant, either using a single shift or
16878 a sequence of add instructions. */
16880 static void
16882 {
16884 {
16886 ? gen_addsi3
16888 }
16891 {
16894 {
16896 ? gen_addsi3
16898 }
16899 }
16900 else
16902 ? gen_ashlsi3
16904 }
16906 void
16908 {
16914 {
16919 {
16925 }
16926 else
16927 {
16931 ? gen_x86_shld
16934 }
16936 }
16941 {
16942 /* Assuming we've chosen a QImode capable registers, then 1 << N
16943 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16945 {
16961 }
16963 /* Otherwise, we can get the same results by manually performing
16964 a bit extract operation on bit 5/6, and then performing the two
16965 shifts. The two methods of getting 0/1 into low/high are exactly
16966 the same size. Avoiding the shift in the bit extract case helps
16967 pentium4 a bit; no one else seems to care much either way. */
16968 else
16969 {
16970 rtx x;
16974 else
16979 ? gen_lshrsi3
16983 ? gen_andsi3
16987 ? gen_xorsi3
16989 }
16992 ? gen_ashlsi3
16995 ? gen_ashlsi3
16998 }
17001 {
17002 /* For -1 << N, we can avoid the shld instruction, because we
17003 know that we're shifting 0...31/63 ones into a -1. */
17007 else
17009 }
17010 else
17011 {
17017 ? gen_x86_shld
17019 }
17024 {
17027 ? gen_x86_shift_adj_1
17029 scratch));
17030 }
17031 else
17033 ? gen_x86_shift_adj_2
17035 }
17037 void
17039 {
17045 {
17050 {
17053 ? gen_ashrsi3
17058 }
17060 {
17064 ? gen_ashrsi3
17069 ? gen_ashrsi3
17072 }
17073 else
17074 {
17078 ? gen_x86_shrd
17081 ? gen_ashrsi3
17083 }
17084 }
17085 else
17086 {
17093 ? gen_x86_shrd
17096 ? gen_ashrsi3
17100 {
17103 ? gen_ashrsi3
17107 ? gen_x86_shift_adj_1
17109 scratch));
17110 }
17111 else
17113 ? gen_x86_shift_adj_3
17115 }
17116 }
17118 void
17120 {
17126 {
17131 {
17137 ? gen_lshrsi3
17140 }
17141 else
17142 {
17146 ? gen_x86_shrd
17149 ? gen_lshrsi3
17151 }
17152 }
17153 else
17154 {
17161 ? gen_x86_shrd
17164 ? gen_lshrsi3
17167 /* Heh. By reversing the arguments, we can reuse this pattern. */
17169 {
17172 ? gen_x86_shift_adj_1
17174 scratch));
17175 }
17176 else
17178 ? gen_x86_shift_adj_2
17180 }
17181 }
17183 /* Predict just emitted jump instruction to be taken with probability PROB. */
17184 static void
17186 {
17190 }
17192 /* Helper function for the string operations below. Dest VARIABLE whether
17193 it is aligned to VALUE bytes. If true, jump to the label. */
17194 static rtx
17196 {
17201 else
17207 else
17210 }
17212 /* Adjust COUNTER by the VALUE. */
17213 static void
17215 {
17218 else
17220 }
17222 /* Zero extend possibly SImode EXP to Pmode register. */
17223 rtx
17225 {
17226 rtx r;
17234 }
17236 /* Divide COUNTREG by SCALE. */
17237 static rtx
17239 {
17240 rtx sc;
17252 }
17254 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17255 DImode for constant loop counts. */
17257 static enum machine_mode
17259 {
17267 }
17269 /* When SRCPTR is non-NULL, output simple loop to move memory
17270 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17271 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17272 equivalent loop to set memory by VALUE (supposed to be in MODE).
17274 The size is rounded down to whole number of chunk size moved at once.
17275 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17278 static void
17283 {
17288 rtx size;
17289 rtx x_addr;
17290 rtx y_addr;
17299 /* Those two should combine. */
17301 {
17305 }
17315 {
17319 /* When unrolling for chips that reorder memory reads and writes,
17320 we can save registers by using single temporary.
17321 Also using 4 temporaries is overkill in 32bit mode. */
17323 {
17325 {
17327 {
17328 destmem =
17330 srcmem =
17332 }
17334 }
17335 }
17336 else
17337 {
17341 {
17344 {
17345 srcmem =
17347 }
17349 }
17351 {
17353 {
17354 destmem =
17356 }
17358 }
17359 }
17360 }
17361 else
17363 {
17365 destmem =
17368 }
17378 {
17384 else
17386 }
17387 else
17395 {
17400 }
17402 }
17404 /* Output "rep; mov" instruction.
17405 Arguments have same meaning as for previous function */
17406 static void
17409 rtx count,
17411 {
17412 rtx destexp;
17413 rtx srcexp;
17414 rtx countreg;
17416 /* If the size is known, it is shorter to use rep movs. */
17427 {
17434 }
17435 else
17436 {
17439 }
17441 {
17448 }
17449 else
17450 {
17455 }
17458 }
17460 /* Output "rep; stos" instruction.
17461 Arguments have same meaning as for previous function */
17462 static void
17465 rtx orig_value)
17466 {
17467 rtx destexp;
17468 rtx countreg;
17475 {
17479 }
17480 else
17483 {
17488 }
17492 }
17494 static void
17497 {
17501 }
17503 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17504 static void
17507 {
17510 {
17515 {
17517 {
17520 }
17521 else
17524 }
17526 {
17529 else
17530 {
17533 }
17535 }
17537 {
17540 }
17542 {
17545 }
17547 {
17550 }
17552 }
17554 {
17560 }
17562 /* When there are stringops, we can cheaply increase dest and src pointers.
17563 Otherwise we save code size by maintaining offset (zero is readily
17564 available from preceding rep operation) and using x86 addressing modes.
17565 */
17567 {
17569 {
17576 }
17578 {
17585 }
17587 {
17594 }
17595 }
17596 else
17597 {
17599 rtx tmp;
17602 {
17613 }
17615 {
17628 }
17630 {
17639 }
17640 }
17641 }
17643 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17644 static void
17647 {
17648 count =
17654 }
17656 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17657 static void
17659 {
17660 rtx dest;
17663 {
17668 {
17670 {
17675 }
17676 else
17679 }
17681 {
17683 {
17686 }
17687 else
17688 {
17693 }
17695 }
17697 {
17701 }
17703 {
17707 }
17709 {
17713 }
17715 }
17717 {
17720 }
17722 {
17725 {
17729 }
17730 else
17731 {
17737 }
17740 }
17742 {
17745 {
17748 }
17749 else
17750 {
17754 }
17757 }
17759 {
17765 }
17767 {
17773 }
17775 {
17781 }
17782 }
17784 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17785 DESIRED_ALIGNMENT. */
17786 static void
17790 {
17792 {
17800 }
17802 {
17810 }
17812 {
17820 }
17822 }
17824 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17825 ALIGN_BYTES is how many bytes need to be copied. */
17826 static rtx
17829 {
17839 {
17844 }
17846 {
17857 }
17859 {
17865 {
17873 }
17876 }
17882 {
17894 }
17901 }
17903 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17904 DESIRED_ALIGNMENT. */
17905 static void
17908 {
17910 {
17917 }
17919 {
17926 }
17928 {
17935 }
17937 }
17939 /* Set enough from DST to align DST known to by aligned by ALIGN to
17940 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17941 static rtx
17944 {
17948 {
17953 }
17955 {
17962 }
17964 {
17971 }
17978 }
17980 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17981 static enum stringop_alg
17984 {
17987 /* Algorithms using the rep prefix want at least edi and ecx;
17988 additionally, memset wants eax and memcpy wants esi. Don't
17989 consider such algorithms if the user has appropriated those
17990 registers for their own purposes. */
17992 || (memset
17995 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17996 || (alg != rep_prefix_1_byte \
17997 && alg != rep_prefix_4_byte \
17998 && alg != rep_prefix_8_byte))
18001 /* Even if the string operation call is cold, we still might spend a lot
18002 of time processing large blocks. */
18007 else
18015 else
18019 /* rep; movq or rep; movl is the smallest variant. */
18021 {
18024 else
18026 }
18027 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
18028 */
18032 {
18036 {
18037 /* We get here if the algorithms that were not libcall-based
18038 were rep-prefix based and we are unable to use rep prefixes
18039 based on global register usage. Break out of the loop and
18040 use the heuristic below. */
18044 {
18049 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18050 last non-libcall inline algorithm. */
18052 {
18053 /* When the current size is best to be copied by a libcall,
18054 but we are still forced to inline, run the heuristic below
18055 that will pick code for medium sized blocks. */
18059 }
18062 }
18063 }
18065 }
18066 /* When asked to inline the call anyway, try to pick meaningful choice.
18067 We look for maximal size of block that is faster to copy by hand and
18068 take blocks of at most of that size guessing that average size will
18069 be roughly half of the block.
18071 If this turns out to be bad, we might simply specify the preferred
18072 choice in ix86_costs. */
18075 {
18082 {
18089 }
18090 /* If there aren't any usable algorithms, then recursing on
18091 smaller sizes isn't going to find anything. Just return the
18092 simple byte-at-a-time copy loop. */
18094 {
18095 /* Pick something reasonable. */
18099 }
18108 }
18110 #undef ALG_USABLE_P
18111 }
18113 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18114 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18115 static int
18119 {
18122 {
18133 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18134 copying whole cacheline at once. */
18137 else
18141 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18142 copying whole cacheline at once. */
18145 else
18153 }
18162 }
18164 /* Return the smallest power of 2 greater than VAL. */
18165 static int
18167 {
18172 }
18174 /* Expand string move (memcpy) operation. Use i386 string operations when
18175 profitable. expand_setmem contains similar code. The code depends upon
18176 architecture, block size and alignment, but always has the same
18177 overall structure:
18179 1) Prologue guard: Conditional that jumps up to epilogues for small
18180 blocks that can be handled by epilogue alone. This is faster but
18181 also needed for correctness, since prologue assume the block is larger
18182 than the desired alignment.
18184 Optional dynamic check for size and libcall for large
18185 blocks is emitted here too, with -minline-stringops-dynamically.
18187 2) Prologue: copy first few bytes in order to get destination aligned
18188 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18189 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18190 We emit either a jump tree on power of two sized blocks, or a byte loop.
18192 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18193 with specified algorithm.
18195 4) Epilogue: code copying tail of the block that is too small to be
18196 handled by main body (or up to size guarded by prologue guard). */
18198 int
18201 {
18202 rtx destreg;
18203 rtx srcreg;
18205 rtx tmp;
18218 /* i386 can do misaligned access on reasonably increased cost. */
18222 /* ALIGN is the minimum of destination and source alignment, but we care here
18223 just about destination alignment. */
18232 /* Make sure we don't need to care about overflow later on. */
18236 /* Step 0: Decide on preferred algorithm, desired alignment and
18237 size of chunks to be copied by main loop. */
18253 {
18278 }
18282 /* Step 1: Prologue guard. */
18284 /* Alignment code needs count to be in register. */
18286 {
18289 {
18290 align_bytes
18294 else
18296 }
18299 }
18302 /* Ensure that alignment prologue won't copy past end of block. */
18304 {
18306 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18307 Make sure it is power of 2. */
18311 {
18313 {
18314 /* If main algorithm works on QImode, no epilogue is needed.
18315 For small sizes just don't align anything. */
18318 else
18320 }
18321 }
18322 else
18323 {
18330 else
18332 }
18333 }
18335 /* Emit code to decide on runtime whether library call or inline should be
18336 used. */
18338 {
18340 {
18342 {
18346 }
18347 }
18348 else
18349 {
18358 }
18359 }
18361 /* Step 2: Alignment prologue. */
18364 {
18366 {
18367 /* Except for the first move in epilogue, we no longer know
18368 constant offset in aliasing info. It don't seems to worth
18369 the pain to maintain it for the first move, so throw away
18370 the info early. */
18374 desired_align);
18375 }
18376 else
18377 {
18378 /* If we know how many bytes need to be stored before dst is
18379 sufficiently aligned, maintain aliasing info accurately. */
18384 }
18390 {
18391 /* It is possible that we copied enough so the main loop will not
18392 execute. */
18402 else
18404 }
18405 }
18407 {
18412 }
18416 /* Step 3: Main loop. */
18419 {
18432 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18433 registers for 4 temporaries anyway. */
18436 expected_size);
18440 DImode);
18444 SImode);
18448 QImode);
18450 }
18451 /* Adjust properly the offset of src and dest memory for aliasing. */
18453 {
18458 }
18459 else
18460 {
18463 }
18465 /* Step 4: Epilogue to copy the remaining bytes. */
18466 epilogue:
18468 {
18469 /* When the main loop is done, COUNT_EXP might hold original count,
18470 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18471 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18472 bytes. Compensate if needed. */
18475 {
18476 tmp =
18479 OPTAB_DIRECT);
18482 }
18485 }
18489 epilogue_size_needed);
18493 }
18495 /* Helper function for memcpy. For QImode value 0xXY produce
18496 0xXYXYXYXY of wide specified by MODE. This is essentially
18497 a * 0x10101010, but we can do slightly better than
18498 synth_mult by unwinding the sequence by hand on CPUs with
18499 slow multiply. */
18500 static rtx
18502 {
18504 rtx tmp;
18511 {
18519 }
18528 nops--;
18533 {
18537 OPTAB_DIRECT);
18538 }
18539 else
18540 {
18546 else
18548 else
18549 {
18552 reg =
18554 }
18564 }
18565 }
18567 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18568 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18569 alignment from ALIGN to DESIRED_ALIGN. */
18570 static rtx
18572 {
18573 rtx promoted_val;
18582 else
18586 }
18588 /* Expand string clear operation (bzero). Use i386 string operations when
18589 profitable. See expand_movmem comment for explanation of individual
18590 steps performed. */
18591 int
18594 {
18595 rtx destreg;
18597 rtx tmp;
18612 /* i386 can do misaligned access on reasonably increased cost. */
18621 /* Make sure we don't need to care about overflow later on. */
18625 /* Step 0: Decide on preferred algorithm, desired alignment and
18626 size of chunks to be copied by main loop. */
18641 {
18666 }
18669 /* Step 1: Prologue guard. */
18671 /* Alignment code needs count to be in register. */
18673 {
18676 {
18677 align_bytes
18681 else
18683 }
18685 {
18690 }
18691 }
18692 /* Do the cheap promotion to allow better CSE across the
18693 main loop and epilogue (ie one load of the big constant in the
18694 front of all code. */
18698 /* Ensure that alignment prologue won't copy past end of block. */
18700 {
18702 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18703 Make sure it is power of 2. */
18706 /* To improve performance of small blocks, we jump around the VAL
18707 promoting mode. This mean that if the promoted VAL is not constant,
18708 we might not use it in the epilogue and have to use byte
18709 loop variant. */
18713 {
18715 {
18716 /* If main algorithm works on QImode, no epilogue is needed.
18717 For small sizes just don't align anything. */
18720 else
18722 }
18723 }
18724 else
18725 {
18732 else
18734 }
18735 }
18737 {
18746 }
18748 /* Step 2: Alignment prologue. */
18750 /* Do the expensive promotion once we branched off the small blocks. */
18757 {
18759 {
18760 /* Except for the first move in epilogue, we no longer know
18761 constant offset in aliasing info. It don't seems to worth
18762 the pain to maintain it for the first move, so throw away
18763 the info early. */
18766 desired_align);
18767 }
18768 else
18769 {
18770 /* If we know how many bytes need to be stored before dst is
18771 sufficiently aligned, maintain aliasing info accurately. */
18776 }
18782 {
18783 /* It is possible that we copied enough so the main loop will not
18784 execute. */
18794 else
18796 }
18797 }
18799 {
18805 }
18809 /* Step 3: Main loop. */
18812 {
18840 }
18841 /* Adjust properly the offset of src and dest memory for aliasing. */
18845 else
18848 /* Step 4: Epilogue to copy the remaining bytes. */
18851 {
18852 /* When the main loop is done, COUNT_EXP might hold original count,
18853 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18854 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18855 bytes. Compensate if needed. */
18858 {
18859 tmp =
18862 OPTAB_DIRECT);
18865 }
18868 }
18869 epilogue:
18871 {
18874 epilogue_size_needed);
18875 else
18877 epilogue_size_needed);
18878 }
18882 }
18884 /* Expand the appropriate insns for doing strlen if not just doing
18885 repnz; scasb
18887 out = result, initialized with the start address
18888 align_rtx = alignment of the address.
18889 scratch = scratch register, initialized with the startaddress when
18890 not aligned, otherwise undefined
18892 This is just the body. It needs the initializations mentioned above and
18893 some address computing at the end. These things are done in i386.md. */
18895 static void
18897 {
18899 rtx tmp;
18904 rtx mem;
18907 rtx cmp;
18913 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18915 /* Is there a known alignment and is it less than 4? */
18917 {
18920 /* Is there a known alignment and is it not 2? */
18922 {
18926 /* Leave just the 3 lower bits. */
18936 }
18937 else
18938 {
18939 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18940 check if is aligned to 4 - byte. */
18947 }
18951 /* Now compare the bytes. */
18953 /* Compare the first n unaligned byte on a byte per byte basis. */
18957 /* Increment the address. */
18960 /* Not needed with an alignment of 2 */
18962 {
18966 end_0_label);
18971 }
18974 end_0_label);
18977 }
18979 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18980 align this loop. It gives only huge programs, but does not help to
18981 speed up. */
18988 /* This formula yields a nonzero result iff one of the bytes is zero.
18989 This saves three branches inside loop and many cycles. */
18997 align_4_label);
19000 {
19006 /* If zero is not in the first two bytes, move two bytes forward. */
19012 reg,
19013 tmpreg)));
19014 /* Emit lea manually to avoid clobbering of flags. */
19022 reg2,
19023 out)));
19024 }
19025 else
19026 {
19028 /* Is zero in the first two bytes? */
19035 pc_rtx);
19039 /* Not in the first two. Move two bytes forward. */
19045 }
19047 /* Avoid branch in fixing the byte. */
19055 }
19057 /* Expand strlen. */
19059 int
19061 {
19064 /* The generic case of strlen expander is long. Avoid it's
19065 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19068 && !TARGET_INLINE_ALL_STRINGOPS
19078 {
19079 /* Well it seems that some optimizer does not combine a call like
19080 foo(strlen(bar), strlen(bar));
19081 when the move and the subtraction is done here. It does calculate
19082 the length just once when these instructions are done inside of
19083 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19084 often used and I use one fewer register for the lifetime of
19085 output_strlen_unroll() this is better. */
19091 /* strlensi_unroll_1 returns the address of the zero at the end of
19092 the string, like memchr(), so compute the length by subtracting
19093 the start address. */
19095 }
19096 else
19097 {
19098 rtx unspec;
19100 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19113 /* If .md starts supporting :P, this can be done in .md. */
19119 }
19121 }
19123 /* For given symbol (function) construct code to compute address of it's PLT
19124 entry in large x86-64 PIC model. */
19125 rtx
19127 {
19137 }
19139 void
19141 rtx callarg2,
19143 {
19151 {
19152 #if TARGET_MACHO
19155 #endif
19156 }
19157 else
19158 {
19159 /* Static functions and indirect calls don't need the pic register. */
19164 }
19167 {
19171 }
19181 {
19184 }
19190 {
19194 }
19198 {
19199 /* We need to represent that SI and DI registers are clobbered
19200 by SYSV calls. */
19206 };
19210 UNSPEC_MS_TO_SYSV_CALL);
19217 gen_rtx_REG
19225 }
19230 }
19232 \f
19233 /* Clear stack slot assignments remembered from previous functions.
19234 This is called from INIT_EXPANDERS once before RTL is emitted for each
19235 function. */
19239 {
19248 }
19250 /* Return a MEM corresponding to a stack slot with mode MODE.
19251 Allocate a new slot if necessary.
19253 The RTL for a function can have several slots available: N is
19254 which slot to use. */
19256 rtx
19258 {
19263 /* Virtual slot is valid only before vregs are instantiated. */
19279 }
19281 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19284 rtx
19286 {
19289 {
19291 (TARGET_ANY_GNU_TLS
19295 }
19298 }
19300 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19303 rtx
19305 {
19308 {
19313 }
19316 }
19317 \f
19318 /* Calculate the length of the memory address in the instruction
19319 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19321 int
19323 {
19348 /* Rule of thumb:
19349 - esp as the base always wants an index,
19350 - ebp as the base always wants a displacement,
19351 - r12 as the base always wants an index,
19352 - r13 as the base always wants a displacement. */
19354 /* Register Indirect. */
19356 {
19357 /* esp (for its index) and ebp (for its displacement) need
19358 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19359 code. */
19368 }
19370 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19371 is not disp32, but disp32(%rip), so for disp32
19372 SIB byte is needed, unless print_operand_address
19373 optimizes it into disp32(%rip) or (%rip) is implied
19374 by UNSPEC. */
19376 {
19379 {
19395 }
19396 }
19398 else
19399 {
19400 /* Find the length of the displacement constant. */
19402 {
19405 else
19407 }
19408 /* ebp always wants a displacement. Similarly r13. */
19413 /* An index requires the two-byte modrm form.... */
19415 /* ...like esp (or r12), which always wants an index. */
19421 }
19424 {
19431 }
19434 }
19436 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19437 is set, expect that insn have 8bit immediate alternative. */
19438 int
19440 {
19446 {
19451 {
19454 {
19466 }
19468 {
19471 }
19472 }
19474 {
19484 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19490 }
19491 }
19493 }
19494 /* Compute default value for "length_address" attribute. */
19495 int
19497 {
19501 {
19511 {
19516 }
19519 }
19524 {
19527 {
19532 constraints++;
19535 ;
19536 /* Skip ignored operands. */
19539 }
19541 }
19543 }
19545 /* Compute default value for "length_vex" attribute. It includes
19546 2 or 3 byte VEX prefix and 1 opcode byte. */
19548 int
19551 {
19554 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19555 byte VEX prefix. */
19559 /* We can always use 2 byte VEX prefix in 32bit. */
19567 {
19568 /* REX.W bit uses 3 byte VEX prefix. */
19572 }
19573 else
19574 {
19575 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19579 }
19582 }
19583 \f
19584 /* Return the maximum number of instructions a cpu can issue. */
19586 static int
19588 {
19590 {
19611 }
19612 }
19614 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19615 by DEP_INSN and nothing set by DEP_INSN. */
19617 static int
19619 {
19622 /* Simplify the test for uninteresting insns. */
19630 {
19633 }
19638 {
19641 }
19642 else
19648 /* This test is true if the dependent insn reads the flags but
19649 not any other potentially set register. */
19657 }
19659 /* Return true iff USE_INSN has a memory address with operands set by
19660 SET_INSN. */
19662 bool
19664 {
19669 {
19672 }
19674 }
19676 static int
19678 {
19684 /* Anti and output dependencies have zero cost on all CPUs. */
19690 /* If we can't recognize the insns, we can't really do anything. */
19698 {
19700 /* Address Generation Interlock adds a cycle of latency. */
19702 {
19713 }
19717 /* ??? Compares pair with jump/setcc. */
19721 /* Floating point stores require value to be ready one cycle earlier. */
19731 /* INT->FP conversion is expensive. */
19735 /* There is one cycle extra latency between an FP op and a store. */
19743 /* Show ability of reorder buffer to hide latency of load by executing
19744 in parallel with previous instruction in case
19745 previous instruction is not needed to compute the address. */
19748 {
19749 /* Claim moves to take one cycle, as core can issue one load
19750 at time and the next load can start cycle later. */
19755 cost--;
19756 }
19762 /* The esp dependency is resolved before the instruction is really
19763 finished. */
19768 /* INT->FP conversion is expensive. */
19772 /* Show ability of reorder buffer to hide latency of load by executing
19773 in parallel with previous instruction in case
19774 previous instruction is not needed to compute the address. */
19777 {
19778 /* Claim moves to take one cycle, as core can issue one load
19779 at time and the next load can start cycle later. */
19785 else
19787 }
19798 /* Show ability of reorder buffer to hide latency of load by executing
19799 in parallel with previous instruction in case
19800 previous instruction is not needed to compute the address. */
19803 {
19807 /* Because of the difference between the length of integer and
19808 floating unit pipeline preparation stages, the memory operands
19809 for floating point are cheaper.
19811 ??? For Athlon it the difference is most probably 2. */
19814 else
19819 else
19821 }
19825 }
19828 }
19830 /* How many alternative schedules to try. This should be as wide as the
19831 scheduling freedom in the DFA, but no wider. Making this value too
19832 large results extra work for the scheduler. */
19834 static int
19836 {
19838 {
19848 }
19849 }
19851 \f
19852 /* Compute the alignment given to a constant that is being placed in memory.
19853 EXP is the constant and ALIGN is the alignment that the object would
19854 ordinarily have.
19855 The value of this function is used instead of that alignment to align
19856 the object. */
19858 int
19860 {
19863 {
19868 }
19874 }
19876 /* Compute the alignment for a static variable.
19877 TYPE is the data type, and ALIGN is the alignment that
19878 the object would ordinarily have. The value of this function is used
19879 instead of that alignment to align the object. */
19881 int
19883 {
19894 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19895 to 16byte boundary. */
19897 {
19904 }
19907 {
19912 }
19914 {
19921 }
19926 {
19931 }
19934 {
19939 }
19942 }
19944 /* Compute the alignment for a local variable or a stack slot. EXP is
19945 the data type or decl itself, MODE is the widest mode available and
19946 ALIGN is the alignment that the object would ordinarily have. The
19947 value of this macro is used instead of that alignment to align the
19948 object. */
19950 unsigned int
19953 {
19957 {
19960 }
19961 else
19962 {
19965 }
19967 /* Don't do dynamic stack realignment for long long objects with
19968 -mpreferred-stack-boundary=2. */
19977 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19978 register in MODE. We will return the largest alignment of XF
19979 and DF. */
19981 {
19985 }
19987 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19988 to 16byte boundary. */
19990 {
19997 }
19999 {
20004 }
20006 {
20012 }
20017 {
20022 }
20025 {
20031 }
20033 }
20035 /* Compute the minimum required alignment for dynamic stack realignment
20036 purposes for a local variable, parameter or a stack slot. EXP is
20037 the data type or decl itself, MODE is its mode and ALIGN is the
20038 alignment that the object would ordinarily have. */
20040 unsigned int
20043 {
20050 {
20053 }
20054 else
20055 {
20058 }
20060 /* Don't do dynamic stack realignment for long long objects with
20061 -mpreferred-stack-boundary=2. */
20068 }
20069 \f
20070 /* Find a location for the static chain incoming to a nested function.
20071 This is a register, unless all free registers are used by arguments. */
20073 static rtx
20075 {
20082 {
20083 /* We always use R10 in 64-bit mode. */
20085 }
20086 else
20087 {
20088 tree fntype;
20089 /* By default in 32-bit mode we use ECX to pass the static chain. */
20094 {
20095 /* Fastcall functions use ecx/edx for arguments, which leaves
20096 us with EAX for the static chain. */
20098 }
20100 {
20101 /* For regparm 3, we have no free call-clobbered registers in
20102 which to store the static chain. In order to implement this,
20103 we have the trampoline push the static chain to the stack.
20104 However, we can't push a value below the return address when
20105 we call the nested function directly, so we have to use an
20106 alternate entry point. For this we use ESI, and have the
20107 alternate entry point push ESI, so that things appear the
20108 same once we're executing the nested function. */
20110 {
20115 }
20117 }
20118 }
20121 }
20123 /* Emit RTL insns to initialize the variable parts of a trampoline.
20124 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20125 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20126 to be passed to the target function. */
20128 static void
20130 {
20136 {
20140 /* Depending on the static chain location, either load a register
20141 with a constant, or push the constant to the stack. All of the
20142 instructions are the same size. */
20145 {
20150 else
20152 }
20153 else
20162 /* Compute offset from the end of the jmp to the target function.
20163 In the case in which the trampoline stores the static chain on
20164 the stack, we need to skip the first insn which pushes the
20165 (call-saved) register static chain; this push is 1 byte. */
20176 }
20177 else
20178 {
20181 /* Load the function address to r11. Try to load address using
20182 the shorter movl instead of movabs. We may want to support
20183 movq for kernel mode, but kernel does not use trampolines at
20184 the moment. */
20186 {
20195 }
20196 else
20197 {
20204 }
20206 /* Load static chain using movabs to r10. */
20214 /* Jump to r11; the last (unused) byte is a nop, only there to
20215 pad the write out to a single 32-bit store. */
20221 }
20223 #ifdef ENABLE_EXECUTE_STACK
20224 #ifdef CHECK_EXECUTE_STACK_ENABLED
20226 #endif
20229 #endif
20230 }
20231 \f
20232 /* The following file contains several enumerations and data structures
20233 built from the definitions in i386-builtin-types.def. */
20237 /* Table for the ix86 builtin non-function types. */
20240 /* Retrieve an element from the above table, building some of
20241 the types lazily. */
20243 static tree
20245 {
20257 {
20265 }
20266 else
20267 {
20273 else
20281 }
20285 }
20287 /* Table for the ix86 builtin function types. */
20290 /* Retrieve an element from the above table, building some of
20291 the types lazily. */
20293 static tree
20295 {
20296 tree type;
20305 {
20313 {
20316 }
20319 }
20320 else
20321 {
20327 }
20331 }
20334 /* Codes for all the SSE/MMX builtins. */
20335 enum ix86_builtins
20336 {
20337 IX86_BUILTIN_ADDPS,
20338 IX86_BUILTIN_ADDSS,
20339 IX86_BUILTIN_DIVPS,
20340 IX86_BUILTIN_DIVSS,
20341 IX86_BUILTIN_MULPS,
20342 IX86_BUILTIN_MULSS,
20343 IX86_BUILTIN_SUBPS,
20344 IX86_BUILTIN_SUBSS,
20346 IX86_BUILTIN_CMPEQPS,
20347 IX86_BUILTIN_CMPLTPS,
20348 IX86_BUILTIN_CMPLEPS,
20349 IX86_BUILTIN_CMPGTPS,
20350 IX86_BUILTIN_CMPGEPS,
20351 IX86_BUILTIN_CMPNEQPS,
20352 IX86_BUILTIN_CMPNLTPS,
20353 IX86_BUILTIN_CMPNLEPS,
20354 IX86_BUILTIN_CMPNGTPS,
20355 IX86_BUILTIN_CMPNGEPS,
20356 IX86_BUILTIN_CMPORDPS,
20357 IX86_BUILTIN_CMPUNORDPS,
20358 IX86_BUILTIN_CMPEQSS,
20359 IX86_BUILTIN_CMPLTSS,
20360 IX86_BUILTIN_CMPLESS,
20361 IX86_BUILTIN_CMPNEQSS,
20362 IX86_BUILTIN_CMPNLTSS,
20363 IX86_BUILTIN_CMPNLESS,
20364 IX86_BUILTIN_CMPNGTSS,
20365 IX86_BUILTIN_CMPNGESS,
20366 IX86_BUILTIN_CMPORDSS,
20367 IX86_BUILTIN_CMPUNORDSS,
20369 IX86_BUILTIN_COMIEQSS,
20370 IX86_BUILTIN_COMILTSS,
20371 IX86_BUILTIN_COMILESS,
20372 IX86_BUILTIN_COMIGTSS,
20373 IX86_BUILTIN_COMIGESS,
20374 IX86_BUILTIN_COMINEQSS,
20375 IX86_BUILTIN_UCOMIEQSS,
20376 IX86_BUILTIN_UCOMILTSS,
20377 IX86_BUILTIN_UCOMILESS,
20378 IX86_BUILTIN_UCOMIGTSS,
20379 IX86_BUILTIN_UCOMIGESS,
20380 IX86_BUILTIN_UCOMINEQSS,
20382 IX86_BUILTIN_CVTPI2PS,
20383 IX86_BUILTIN_CVTPS2PI,
20384 IX86_BUILTIN_CVTSI2SS,
20385 IX86_BUILTIN_CVTSI642SS,
20386 IX86_BUILTIN_CVTSS2SI,
20387 IX86_BUILTIN_CVTSS2SI64,
20388 IX86_BUILTIN_CVTTPS2PI,
20389 IX86_BUILTIN_CVTTSS2SI,
20390 IX86_BUILTIN_CVTTSS2SI64,
20392 IX86_BUILTIN_MAXPS,
20393 IX86_BUILTIN_MAXSS,
20394 IX86_BUILTIN_MINPS,
20395 IX86_BUILTIN_MINSS,
20397 IX86_BUILTIN_LOADUPS,
20398 IX86_BUILTIN_STOREUPS,
20399 IX86_BUILTIN_MOVSS,
20401 IX86_BUILTIN_MOVHLPS,
20402 IX86_BUILTIN_MOVLHPS,
20403 IX86_BUILTIN_LOADHPS,
20404 IX86_BUILTIN_LOADLPS,
20405 IX86_BUILTIN_STOREHPS,
20406 IX86_BUILTIN_STORELPS,
20408 IX86_BUILTIN_MASKMOVQ,
20409 IX86_BUILTIN_MOVMSKPS,
20410 IX86_BUILTIN_PMOVMSKB,
20412 IX86_BUILTIN_MOVNTPS,
20413 IX86_BUILTIN_MOVNTQ,
20415 IX86_BUILTIN_LOADDQU,
20416 IX86_BUILTIN_STOREDQU,
20418 IX86_BUILTIN_PACKSSWB,
20419 IX86_BUILTIN_PACKSSDW,
20420 IX86_BUILTIN_PACKUSWB,
20422 IX86_BUILTIN_PADDB,
20423 IX86_BUILTIN_PADDW,
20424 IX86_BUILTIN_PADDD,
20425 IX86_BUILTIN_PADDQ,
20426 IX86_BUILTIN_PADDSB,
20427 IX86_BUILTIN_PADDSW,
20428 IX86_BUILTIN_PADDUSB,
20429 IX86_BUILTIN_PADDUSW,
20430 IX86_BUILTIN_PSUBB,
20431 IX86_BUILTIN_PSUBW,
20432 IX86_BUILTIN_PSUBD,
20433 IX86_BUILTIN_PSUBQ,
20434 IX86_BUILTIN_PSUBSB,
20435 IX86_BUILTIN_PSUBSW,
20436 IX86_BUILTIN_PSUBUSB,
20437 IX86_BUILTIN_PSUBUSW,
20439 IX86_BUILTIN_PAND,
20440 IX86_BUILTIN_PANDN,
20441 IX86_BUILTIN_POR,
20442 IX86_BUILTIN_PXOR,
20444 IX86_BUILTIN_PAVGB,
20445 IX86_BUILTIN_PAVGW,
20447 IX86_BUILTIN_PCMPEQB,
20448 IX86_BUILTIN_PCMPEQW,
20449 IX86_BUILTIN_PCMPEQD,
20450 IX86_BUILTIN_PCMPGTB,
20451 IX86_BUILTIN_PCMPGTW,
20452 IX86_BUILTIN_PCMPGTD,
20454 IX86_BUILTIN_PMADDWD,
20456 IX86_BUILTIN_PMAXSW,
20457 IX86_BUILTIN_PMAXUB,
20458 IX86_BUILTIN_PMINSW,
20459 IX86_BUILTIN_PMINUB,
20461 IX86_BUILTIN_PMULHUW,
20462 IX86_BUILTIN_PMULHW,
20463 IX86_BUILTIN_PMULLW,
20465 IX86_BUILTIN_PSADBW,
20466 IX86_BUILTIN_PSHUFW,
20468 IX86_BUILTIN_PSLLW,
20469 IX86_BUILTIN_PSLLD,
20470 IX86_BUILTIN_PSLLQ,
20471 IX86_BUILTIN_PSRAW,
20472 IX86_BUILTIN_PSRAD,
20473 IX86_BUILTIN_PSRLW,
20474 IX86_BUILTIN_PSRLD,
20475 IX86_BUILTIN_PSRLQ,
20476 IX86_BUILTIN_PSLLWI,
20477 IX86_BUILTIN_PSLLDI,
20478 IX86_BUILTIN_PSLLQI,
20479 IX86_BUILTIN_PSRAWI,
20480 IX86_BUILTIN_PSRADI,
20481 IX86_BUILTIN_PSRLWI,
20482 IX86_BUILTIN_PSRLDI,
20483 IX86_BUILTIN_PSRLQI,
20485 IX86_BUILTIN_PUNPCKHBW,
20486 IX86_BUILTIN_PUNPCKHWD,
20487 IX86_BUILTIN_PUNPCKHDQ,
20488 IX86_BUILTIN_PUNPCKLBW,
20489 IX86_BUILTIN_PUNPCKLWD,
20490 IX86_BUILTIN_PUNPCKLDQ,
20492 IX86_BUILTIN_SHUFPS,
20494 IX86_BUILTIN_RCPPS,
20495 IX86_BUILTIN_RCPSS,
20496 IX86_BUILTIN_RSQRTPS,
20497 IX86_BUILTIN_RSQRTPS_NR,
20498 IX86_BUILTIN_RSQRTSS,
20499 IX86_BUILTIN_RSQRTF,
20500 IX86_BUILTIN_SQRTPS,
20501 IX86_BUILTIN_SQRTPS_NR,
20502 IX86_BUILTIN_SQRTSS,
20504 IX86_BUILTIN_UNPCKHPS,
20505 IX86_BUILTIN_UNPCKLPS,
20507 IX86_BUILTIN_ANDPS,
20508 IX86_BUILTIN_ANDNPS,
20509 IX86_BUILTIN_ORPS,
20510 IX86_BUILTIN_XORPS,
20512 IX86_BUILTIN_EMMS,
20513 IX86_BUILTIN_LDMXCSR,
20514 IX86_BUILTIN_STMXCSR,
20515 IX86_BUILTIN_SFENCE,
20517 /* 3DNow! Original */
20518 IX86_BUILTIN_FEMMS,
20519 IX86_BUILTIN_PAVGUSB,
20520 IX86_BUILTIN_PF2ID,
20521 IX86_BUILTIN_PFACC,
20522 IX86_BUILTIN_PFADD,
20523 IX86_BUILTIN_PFCMPEQ,
20524 IX86_BUILTIN_PFCMPGE,
20525 IX86_BUILTIN_PFCMPGT,
20526 IX86_BUILTIN_PFMAX,
20527 IX86_BUILTIN_PFMIN,
20528 IX86_BUILTIN_PFMUL,
20529 IX86_BUILTIN_PFRCP,
20530 IX86_BUILTIN_PFRCPIT1,
20531 IX86_BUILTIN_PFRCPIT2,
20532 IX86_BUILTIN_PFRSQIT1,
20533 IX86_BUILTIN_PFRSQRT,
20534 IX86_BUILTIN_PFSUB,
20535 IX86_BUILTIN_PFSUBR,
20536 IX86_BUILTIN_PI2FD,
20537 IX86_BUILTIN_PMULHRW,
20539 /* 3DNow! Athlon Extensions */
20540 IX86_BUILTIN_PF2IW,
20541 IX86_BUILTIN_PFNACC,
20542 IX86_BUILTIN_PFPNACC,
20543 IX86_BUILTIN_PI2FW,
20544 IX86_BUILTIN_PSWAPDSI,
20545 IX86_BUILTIN_PSWAPDSF,
20547 /* SSE2 */
20548 IX86_BUILTIN_ADDPD,
20549 IX86_BUILTIN_ADDSD,
20550 IX86_BUILTIN_DIVPD,
20551 IX86_BUILTIN_DIVSD,
20552 IX86_BUILTIN_MULPD,
20553 IX86_BUILTIN_MULSD,
20554 IX86_BUILTIN_SUBPD,
20555 IX86_BUILTIN_SUBSD,
20557 IX86_BUILTIN_CMPEQPD,
20558 IX86_BUILTIN_CMPLTPD,
20559 IX86_BUILTIN_CMPLEPD,
20560 IX86_BUILTIN_CMPGTPD,
20561 IX86_BUILTIN_CMPGEPD,
20562 IX86_BUILTIN_CMPNEQPD,
20563 IX86_BUILTIN_CMPNLTPD,
20564 IX86_BUILTIN_CMPNLEPD,
20565 IX86_BUILTIN_CMPNGTPD,
20566 IX86_BUILTIN_CMPNGEPD,
20567 IX86_BUILTIN_CMPORDPD,
20568 IX86_BUILTIN_CMPUNORDPD,
20569 IX86_BUILTIN_CMPEQSD,
20570 IX86_BUILTIN_CMPLTSD,
20571 IX86_BUILTIN_CMPLESD,
20572 IX86_BUILTIN_CMPNEQSD,
20573 IX86_BUILTIN_CMPNLTSD,
20574 IX86_BUILTIN_CMPNLESD,
20575 IX86_BUILTIN_CMPORDSD,
20576 IX86_BUILTIN_CMPUNORDSD,
20578 IX86_BUILTIN_COMIEQSD,
20579 IX86_BUILTIN_COMILTSD,
20580 IX86_BUILTIN_COMILESD,
20581 IX86_BUILTIN_COMIGTSD,
20582 IX86_BUILTIN_COMIGESD,
20583 IX86_BUILTIN_COMINEQSD,
20584 IX86_BUILTIN_UCOMIEQSD,
20585 IX86_BUILTIN_UCOMILTSD,
20586 IX86_BUILTIN_UCOMILESD,
20587 IX86_BUILTIN_UCOMIGTSD,
20588 IX86_BUILTIN_UCOMIGESD,
20589 IX86_BUILTIN_UCOMINEQSD,
20591 IX86_BUILTIN_MAXPD,
20592 IX86_BUILTIN_MAXSD,
20593 IX86_BUILTIN_MINPD,
20594 IX86_BUILTIN_MINSD,
20596 IX86_BUILTIN_ANDPD,
20597 IX86_BUILTIN_ANDNPD,
20598 IX86_BUILTIN_ORPD,
20599 IX86_BUILTIN_XORPD,
20601 IX86_BUILTIN_SQRTPD,
20602 IX86_BUILTIN_SQRTSD,
20604 IX86_BUILTIN_UNPCKHPD,
20605 IX86_BUILTIN_UNPCKLPD,
20607 IX86_BUILTIN_SHUFPD,
20609 IX86_BUILTIN_LOADUPD,
20610 IX86_BUILTIN_STOREUPD,
20611 IX86_BUILTIN_MOVSD,
20613 IX86_BUILTIN_LOADHPD,
20614 IX86_BUILTIN_LOADLPD,
20616 IX86_BUILTIN_CVTDQ2PD,
20617 IX86_BUILTIN_CVTDQ2PS,
20619 IX86_BUILTIN_CVTPD2DQ,
20620 IX86_BUILTIN_CVTPD2PI,
20621 IX86_BUILTIN_CVTPD2PS,
20622 IX86_BUILTIN_CVTTPD2DQ,
20623 IX86_BUILTIN_CVTTPD2PI,
20625 IX86_BUILTIN_CVTPI2PD,
20626 IX86_BUILTIN_CVTSI2SD,
20627 IX86_BUILTIN_CVTSI642SD,
20629 IX86_BUILTIN_CVTSD2SI,
20630 IX86_BUILTIN_CVTSD2SI64,
20631 IX86_BUILTIN_CVTSD2SS,
20632 IX86_BUILTIN_CVTSS2SD,
20633 IX86_BUILTIN_CVTTSD2SI,
20634 IX86_BUILTIN_CVTTSD2SI64,
20636 IX86_BUILTIN_CVTPS2DQ,
20637 IX86_BUILTIN_CVTPS2PD,
20638 IX86_BUILTIN_CVTTPS2DQ,
20640 IX86_BUILTIN_MOVNTI,
20641 IX86_BUILTIN_MOVNTPD,
20642 IX86_BUILTIN_MOVNTDQ,
20644 IX86_BUILTIN_MOVQ128,
20646 /* SSE2 MMX */
20647 IX86_BUILTIN_MASKMOVDQU,
20648 IX86_BUILTIN_MOVMSKPD,
20649 IX86_BUILTIN_PMOVMSKB128,
20651 IX86_BUILTIN_PACKSSWB128,
20652 IX86_BUILTIN_PACKSSDW128,
20653 IX86_BUILTIN_PACKUSWB128,
20655 IX86_BUILTIN_PADDB128,
20656 IX86_BUILTIN_PADDW128,
20657 IX86_BUILTIN_PADDD128,
20658 IX86_BUILTIN_PADDQ128,
20659 IX86_BUILTIN_PADDSB128,
20660 IX86_BUILTIN_PADDSW128,
20661 IX86_BUILTIN_PADDUSB128,
20662 IX86_BUILTIN_PADDUSW128,
20663 IX86_BUILTIN_PSUBB128,
20664 IX86_BUILTIN_PSUBW128,
20665 IX86_BUILTIN_PSUBD128,
20666 IX86_BUILTIN_PSUBQ128,
20667 IX86_BUILTIN_PSUBSB128,
20668 IX86_BUILTIN_PSUBSW128,
20669 IX86_BUILTIN_PSUBUSB128,
20670 IX86_BUILTIN_PSUBUSW128,
20672 IX86_BUILTIN_PAND128,
20673 IX86_BUILTIN_PANDN128,
20674 IX86_BUILTIN_POR128,
20675 IX86_BUILTIN_PXOR128,
20677 IX86_BUILTIN_PAVGB128,
20678 IX86_BUILTIN_PAVGW128,
20680 IX86_BUILTIN_PCMPEQB128,
20681 IX86_BUILTIN_PCMPEQW128,
20682 IX86_BUILTIN_PCMPEQD128,
20683 IX86_BUILTIN_PCMPGTB128,
20684 IX86_BUILTIN_PCMPGTW128,
20685 IX86_BUILTIN_PCMPGTD128,
20687 IX86_BUILTIN_PMADDWD128,
20689 IX86_BUILTIN_PMAXSW128,
20690 IX86_BUILTIN_PMAXUB128,
20691 IX86_BUILTIN_PMINSW128,
20692 IX86_BUILTIN_PMINUB128,
20694 IX86_BUILTIN_PMULUDQ,
20695 IX86_BUILTIN_PMULUDQ128,
20696 IX86_BUILTIN_PMULHUW128,
20697 IX86_BUILTIN_PMULHW128,
20698 IX86_BUILTIN_PMULLW128,
20700 IX86_BUILTIN_PSADBW128,
20701 IX86_BUILTIN_PSHUFHW,
20702 IX86_BUILTIN_PSHUFLW,
20703 IX86_BUILTIN_PSHUFD,
20705 IX86_BUILTIN_PSLLDQI128,
20706 IX86_BUILTIN_PSLLWI128,
20707 IX86_BUILTIN_PSLLDI128,
20708 IX86_BUILTIN_PSLLQI128,
20709 IX86_BUILTIN_PSRAWI128,
20710 IX86_BUILTIN_PSRADI128,
20711 IX86_BUILTIN_PSRLDQI128,
20712 IX86_BUILTIN_PSRLWI128,
20713 IX86_BUILTIN_PSRLDI128,
20714 IX86_BUILTIN_PSRLQI128,
20716 IX86_BUILTIN_PSLLDQ128,
20717 IX86_BUILTIN_PSLLW128,
20718 IX86_BUILTIN_PSLLD128,
20719 IX86_BUILTIN_PSLLQ128,
20720 IX86_BUILTIN_PSRAW128,
20721 IX86_BUILTIN_PSRAD128,
20722 IX86_BUILTIN_PSRLW128,
20723 IX86_BUILTIN_PSRLD128,
20724 IX86_BUILTIN_PSRLQ128,
20726 IX86_BUILTIN_PUNPCKHBW128,
20727 IX86_BUILTIN_PUNPCKHWD128,
20728 IX86_BUILTIN_PUNPCKHDQ128,
20729 IX86_BUILTIN_PUNPCKHQDQ128,
20730 IX86_BUILTIN_PUNPCKLBW128,
20731 IX86_BUILTIN_PUNPCKLWD128,
20732 IX86_BUILTIN_PUNPCKLDQ128,
20733 IX86_BUILTIN_PUNPCKLQDQ128,
20735 IX86_BUILTIN_CLFLUSH,
20736 IX86_BUILTIN_MFENCE,
20737 IX86_BUILTIN_LFENCE,
20739 IX86_BUILTIN_BSRSI,
20740 IX86_BUILTIN_BSRDI,
20741 IX86_BUILTIN_RDPMC,
20742 IX86_BUILTIN_RDTSC,
20743 IX86_BUILTIN_RDTSCP,
20744 IX86_BUILTIN_ROLQI,
20745 IX86_BUILTIN_ROLHI,
20746 IX86_BUILTIN_RORQI,
20747 IX86_BUILTIN_RORHI,
20749 /* SSE3. */
20750 IX86_BUILTIN_ADDSUBPS,
20751 IX86_BUILTIN_HADDPS,
20752 IX86_BUILTIN_HSUBPS,
20753 IX86_BUILTIN_MOVSHDUP,
20754 IX86_BUILTIN_MOVSLDUP,
20755 IX86_BUILTIN_ADDSUBPD,
20756 IX86_BUILTIN_HADDPD,
20757 IX86_BUILTIN_HSUBPD,
20758 IX86_BUILTIN_LDDQU,
20760 IX86_BUILTIN_MONITOR,
20761 IX86_BUILTIN_MWAIT,
20763 /* SSSE3. */
20764 IX86_BUILTIN_PHADDW,
20765 IX86_BUILTIN_PHADDD,
20766 IX86_BUILTIN_PHADDSW,
20767 IX86_BUILTIN_PHSUBW,
20768 IX86_BUILTIN_PHSUBD,
20769 IX86_BUILTIN_PHSUBSW,
20770 IX86_BUILTIN_PMADDUBSW,
20771 IX86_BUILTIN_PMULHRSW,
20772 IX86_BUILTIN_PSHUFB,
20773 IX86_BUILTIN_PSIGNB,
20774 IX86_BUILTIN_PSIGNW,
20775 IX86_BUILTIN_PSIGND,
20776 IX86_BUILTIN_PALIGNR,
20777 IX86_BUILTIN_PABSB,
20778 IX86_BUILTIN_PABSW,
20779 IX86_BUILTIN_PABSD,
20781 IX86_BUILTIN_PHADDW128,
20782 IX86_BUILTIN_PHADDD128,
20783 IX86_BUILTIN_PHADDSW128,
20784 IX86_BUILTIN_PHSUBW128,
20785 IX86_BUILTIN_PHSUBD128,
20786 IX86_BUILTIN_PHSUBSW128,
20787 IX86_BUILTIN_PMADDUBSW128,
20788 IX86_BUILTIN_PMULHRSW128,
20789 IX86_BUILTIN_PSHUFB128,
20790 IX86_BUILTIN_PSIGNB128,
20791 IX86_BUILTIN_PSIGNW128,
20792 IX86_BUILTIN_PSIGND128,
20793 IX86_BUILTIN_PALIGNR128,
20794 IX86_BUILTIN_PABSB128,
20795 IX86_BUILTIN_PABSW128,
20796 IX86_BUILTIN_PABSD128,
20798 /* AMDFAM10 - SSE4A New Instructions. */
20799 IX86_BUILTIN_MOVNTSD,
20800 IX86_BUILTIN_MOVNTSS,
20801 IX86_BUILTIN_EXTRQI,
20802 IX86_BUILTIN_EXTRQ,
20803 IX86_BUILTIN_INSERTQI,
20804 IX86_BUILTIN_INSERTQ,
20806 /* SSE4.1. */
20807 IX86_BUILTIN_BLENDPD,
20808 IX86_BUILTIN_BLENDPS,
20809 IX86_BUILTIN_BLENDVPD,
20810 IX86_BUILTIN_BLENDVPS,
20811 IX86_BUILTIN_PBLENDVB128,
20812 IX86_BUILTIN_PBLENDW128,
20814 IX86_BUILTIN_DPPD,
20815 IX86_BUILTIN_DPPS,
20817 IX86_BUILTIN_INSERTPS128,
20819 IX86_BUILTIN_MOVNTDQA,
20820 IX86_BUILTIN_MPSADBW128,
20821 IX86_BUILTIN_PACKUSDW128,
20822 IX86_BUILTIN_PCMPEQQ,
20823 IX86_BUILTIN_PHMINPOSUW128,
20825 IX86_BUILTIN_PMAXSB128,
20826 IX86_BUILTIN_PMAXSD128,
20827 IX86_BUILTIN_PMAXUD128,
20828 IX86_BUILTIN_PMAXUW128,
20830 IX86_BUILTIN_PMINSB128,
20831 IX86_BUILTIN_PMINSD128,
20832 IX86_BUILTIN_PMINUD128,
20833 IX86_BUILTIN_PMINUW128,
20835 IX86_BUILTIN_PMOVSXBW128,
20836 IX86_BUILTIN_PMOVSXBD128,
20837 IX86_BUILTIN_PMOVSXBQ128,
20838 IX86_BUILTIN_PMOVSXWD128,
20839 IX86_BUILTIN_PMOVSXWQ128,
20840 IX86_BUILTIN_PMOVSXDQ128,
20842 IX86_BUILTIN_PMOVZXBW128,
20843 IX86_BUILTIN_PMOVZXBD128,
20844 IX86_BUILTIN_PMOVZXBQ128,
20845 IX86_BUILTIN_PMOVZXWD128,
20846 IX86_BUILTIN_PMOVZXWQ128,
20847 IX86_BUILTIN_PMOVZXDQ128,
20849 IX86_BUILTIN_PMULDQ128,
20850 IX86_BUILTIN_PMULLD128,
20852 IX86_BUILTIN_ROUNDPD,
20853 IX86_BUILTIN_ROUNDPS,
20854 IX86_BUILTIN_ROUNDSD,
20855 IX86_BUILTIN_ROUNDSS,
20857 IX86_BUILTIN_PTESTZ,
20858 IX86_BUILTIN_PTESTC,
20859 IX86_BUILTIN_PTESTNZC,
20861 IX86_BUILTIN_VEC_INIT_V2SI,
20862 IX86_BUILTIN_VEC_INIT_V4HI,
20863 IX86_BUILTIN_VEC_INIT_V8QI,
20864 IX86_BUILTIN_VEC_EXT_V2DF,
20865 IX86_BUILTIN_VEC_EXT_V2DI,
20866 IX86_BUILTIN_VEC_EXT_V4SF,
20867 IX86_BUILTIN_VEC_EXT_V4SI,
20868 IX86_BUILTIN_VEC_EXT_V8HI,
20869 IX86_BUILTIN_VEC_EXT_V2SI,
20870 IX86_BUILTIN_VEC_EXT_V4HI,
20871 IX86_BUILTIN_VEC_EXT_V16QI,
20872 IX86_BUILTIN_VEC_SET_V2DI,
20873 IX86_BUILTIN_VEC_SET_V4SF,
20874 IX86_BUILTIN_VEC_SET_V4SI,
20875 IX86_BUILTIN_VEC_SET_V8HI,
20876 IX86_BUILTIN_VEC_SET_V4HI,
20877 IX86_BUILTIN_VEC_SET_V16QI,
20879 IX86_BUILTIN_VEC_PACK_SFIX,
20881 /* SSE4.2. */
20882 IX86_BUILTIN_CRC32QI,
20883 IX86_BUILTIN_CRC32HI,
20884 IX86_BUILTIN_CRC32SI,
20885 IX86_BUILTIN_CRC32DI,
20887 IX86_BUILTIN_PCMPESTRI128,
20888 IX86_BUILTIN_PCMPESTRM128,
20889 IX86_BUILTIN_PCMPESTRA128,
20890 IX86_BUILTIN_PCMPESTRC128,
20891 IX86_BUILTIN_PCMPESTRO128,
20892 IX86_BUILTIN_PCMPESTRS128,
20893 IX86_BUILTIN_PCMPESTRZ128,
20894 IX86_BUILTIN_PCMPISTRI128,
20895 IX86_BUILTIN_PCMPISTRM128,
20896 IX86_BUILTIN_PCMPISTRA128,
20897 IX86_BUILTIN_PCMPISTRC128,
20898 IX86_BUILTIN_PCMPISTRO128,
20899 IX86_BUILTIN_PCMPISTRS128,
20900 IX86_BUILTIN_PCMPISTRZ128,
20902 IX86_BUILTIN_PCMPGTQ,
20904 /* AES instructions */
20905 IX86_BUILTIN_AESENC128,
20906 IX86_BUILTIN_AESENCLAST128,
20907 IX86_BUILTIN_AESDEC128,
20908 IX86_BUILTIN_AESDECLAST128,
20909 IX86_BUILTIN_AESIMC128,
20910 IX86_BUILTIN_AESKEYGENASSIST128,
20912 /* PCLMUL instruction */
20913 IX86_BUILTIN_PCLMULQDQ128,
20915 /* AVX */
20916 IX86_BUILTIN_ADDPD256,
20917 IX86_BUILTIN_ADDPS256,
20918 IX86_BUILTIN_ADDSUBPD256,
20919 IX86_BUILTIN_ADDSUBPS256,
20920 IX86_BUILTIN_ANDPD256,
20921 IX86_BUILTIN_ANDPS256,
20922 IX86_BUILTIN_ANDNPD256,
20923 IX86_BUILTIN_ANDNPS256,
20924 IX86_BUILTIN_BLENDPD256,
20925 IX86_BUILTIN_BLENDPS256,
20926 IX86_BUILTIN_BLENDVPD256,
20927 IX86_BUILTIN_BLENDVPS256,
20928 IX86_BUILTIN_DIVPD256,
20929 IX86_BUILTIN_DIVPS256,
20930 IX86_BUILTIN_DPPS256,
20931 IX86_BUILTIN_HADDPD256,
20932 IX86_BUILTIN_HADDPS256,
20933 IX86_BUILTIN_HSUBPD256,
20934 IX86_BUILTIN_HSUBPS256,
20935 IX86_BUILTIN_MAXPD256,
20936 IX86_BUILTIN_MAXPS256,
20937 IX86_BUILTIN_MINPD256,
20938 IX86_BUILTIN_MINPS256,
20939 IX86_BUILTIN_MULPD256,
20940 IX86_BUILTIN_MULPS256,
20941 IX86_BUILTIN_ORPD256,
20942 IX86_BUILTIN_ORPS256,
20943 IX86_BUILTIN_SHUFPD256,
20944 IX86_BUILTIN_SHUFPS256,
20945 IX86_BUILTIN_SUBPD256,
20946 IX86_BUILTIN_SUBPS256,
20947 IX86_BUILTIN_XORPD256,
20948 IX86_BUILTIN_XORPS256,
20949 IX86_BUILTIN_CMPSD,
20950 IX86_BUILTIN_CMPSS,
20951 IX86_BUILTIN_CMPPD,
20952 IX86_BUILTIN_CMPPS,
20953 IX86_BUILTIN_CMPPD256,
20954 IX86_BUILTIN_CMPPS256,
20955 IX86_BUILTIN_CVTDQ2PD256,
20956 IX86_BUILTIN_CVTDQ2PS256,
20957 IX86_BUILTIN_CVTPD2PS256,
20958 IX86_BUILTIN_CVTPS2DQ256,
20959 IX86_BUILTIN_CVTPS2PD256,
20960 IX86_BUILTIN_CVTTPD2DQ256,
20961 IX86_BUILTIN_CVTPD2DQ256,
20962 IX86_BUILTIN_CVTTPS2DQ256,
20963 IX86_BUILTIN_EXTRACTF128PD256,
20964 IX86_BUILTIN_EXTRACTF128PS256,
20965 IX86_BUILTIN_EXTRACTF128SI256,
20966 IX86_BUILTIN_VZEROALL,
20967 IX86_BUILTIN_VZEROUPPER,
20968 IX86_BUILTIN_VPERMILVARPD,
20969 IX86_BUILTIN_VPERMILVARPS,
20970 IX86_BUILTIN_VPERMILVARPD256,
20971 IX86_BUILTIN_VPERMILVARPS256,
20972 IX86_BUILTIN_VPERMILPD,
20973 IX86_BUILTIN_VPERMILPS,
20974 IX86_BUILTIN_VPERMILPD256,
20975 IX86_BUILTIN_VPERMILPS256,
20976 IX86_BUILTIN_VPERM2F128PD256,
20977 IX86_BUILTIN_VPERM2F128PS256,
20978 IX86_BUILTIN_VPERM2F128SI256,
20979 IX86_BUILTIN_VBROADCASTSS,
20980 IX86_BUILTIN_VBROADCASTSD256,
20981 IX86_BUILTIN_VBROADCASTSS256,
20982 IX86_BUILTIN_VBROADCASTPD256,
20983 IX86_BUILTIN_VBROADCASTPS256,
20984 IX86_BUILTIN_VINSERTF128PD256,
20985 IX86_BUILTIN_VINSERTF128PS256,
20986 IX86_BUILTIN_VINSERTF128SI256,
20987 IX86_BUILTIN_LOADUPD256,
20988 IX86_BUILTIN_LOADUPS256,
20989 IX86_BUILTIN_STOREUPD256,
20990 IX86_BUILTIN_STOREUPS256,
20991 IX86_BUILTIN_LDDQU256,
20992 IX86_BUILTIN_MOVNTDQ256,
20993 IX86_BUILTIN_MOVNTPD256,
20994 IX86_BUILTIN_MOVNTPS256,
20995 IX86_BUILTIN_LOADDQU256,
20996 IX86_BUILTIN_STOREDQU256,
20997 IX86_BUILTIN_MASKLOADPD,
20998 IX86_BUILTIN_MASKLOADPS,
20999 IX86_BUILTIN_MASKSTOREPD,
21000 IX86_BUILTIN_MASKSTOREPS,
21001 IX86_BUILTIN_MASKLOADPD256,
21002 IX86_BUILTIN_MASKLOADPS256,
21003 IX86_BUILTIN_MASKSTOREPD256,
21004 IX86_BUILTIN_MASKSTOREPS256,
21005 IX86_BUILTIN_MOVSHDUP256,
21006 IX86_BUILTIN_MOVSLDUP256,
21007 IX86_BUILTIN_MOVDDUP256,
21009 IX86_BUILTIN_SQRTPD256,
21010 IX86_BUILTIN_SQRTPS256,
21011 IX86_BUILTIN_SQRTPS_NR256,
21012 IX86_BUILTIN_RSQRTPS256,
21013 IX86_BUILTIN_RSQRTPS_NR256,
21015 IX86_BUILTIN_RCPPS256,
21017 IX86_BUILTIN_ROUNDPD256,
21018 IX86_BUILTIN_ROUNDPS256,
21020 IX86_BUILTIN_UNPCKHPD256,
21021 IX86_BUILTIN_UNPCKLPD256,
21022 IX86_BUILTIN_UNPCKHPS256,
21023 IX86_BUILTIN_UNPCKLPS256,
21025 IX86_BUILTIN_SI256_SI,
21026 IX86_BUILTIN_PS256_PS,
21027 IX86_BUILTIN_PD256_PD,
21028 IX86_BUILTIN_SI_SI256,
21029 IX86_BUILTIN_PS_PS256,
21030 IX86_BUILTIN_PD_PD256,
21032 IX86_BUILTIN_VTESTZPD,
21033 IX86_BUILTIN_VTESTCPD,
21034 IX86_BUILTIN_VTESTNZCPD,
21035 IX86_BUILTIN_VTESTZPS,
21036 IX86_BUILTIN_VTESTCPS,
21037 IX86_BUILTIN_VTESTNZCPS,
21038 IX86_BUILTIN_VTESTZPD256,
21039 IX86_BUILTIN_VTESTCPD256,
21040 IX86_BUILTIN_VTESTNZCPD256,
21041 IX86_BUILTIN_VTESTZPS256,
21042 IX86_BUILTIN_VTESTCPS256,
21043 IX86_BUILTIN_VTESTNZCPS256,
21044 IX86_BUILTIN_PTESTZ256,
21045 IX86_BUILTIN_PTESTC256,
21046 IX86_BUILTIN_PTESTNZC256,
21048 IX86_BUILTIN_MOVMSKPD256,
21049 IX86_BUILTIN_MOVMSKPS256,
21051 /* TFmode support builtins. */
21052 IX86_BUILTIN_INFQ,
21053 IX86_BUILTIN_HUGE_VALQ,
21054 IX86_BUILTIN_FABSQ,
21055 IX86_BUILTIN_COPYSIGNQ,
21057 /* Vectorizer support builtins. */
21058 IX86_BUILTIN_CPYSGNPS,
21059 IX86_BUILTIN_CPYSGNPD,
21061 IX86_BUILTIN_CVTUDQ2PS,
21063 IX86_BUILTIN_VEC_PERM_V2DF,
21064 IX86_BUILTIN_VEC_PERM_V4SF,
21065 IX86_BUILTIN_VEC_PERM_V2DI,
21066 IX86_BUILTIN_VEC_PERM_V4SI,
21067 IX86_BUILTIN_VEC_PERM_V8HI,
21068 IX86_BUILTIN_VEC_PERM_V16QI,
21069 IX86_BUILTIN_VEC_PERM_V2DI_U,
21070 IX86_BUILTIN_VEC_PERM_V4SI_U,
21071 IX86_BUILTIN_VEC_PERM_V8HI_U,
21072 IX86_BUILTIN_VEC_PERM_V16QI_U,
21073 IX86_BUILTIN_VEC_PERM_V4DF,
21074 IX86_BUILTIN_VEC_PERM_V8SF,
21076 /* FMA4 and XOP instructions. */
21077 IX86_BUILTIN_VFMADDSS,
21078 IX86_BUILTIN_VFMADDSD,
21079 IX86_BUILTIN_VFMADDPS,
21080 IX86_BUILTIN_VFMADDPD,
21081 IX86_BUILTIN_VFMSUBSS,
21082 IX86_BUILTIN_VFMSUBSD,
21083 IX86_BUILTIN_VFMSUBPS,
21084 IX86_BUILTIN_VFMSUBPD,
21085 IX86_BUILTIN_VFMADDSUBPS,
21086 IX86_BUILTIN_VFMADDSUBPD,
21087 IX86_BUILTIN_VFMSUBADDPS,
21088 IX86_BUILTIN_VFMSUBADDPD,
21089 IX86_BUILTIN_VFNMADDSS,
21090 IX86_BUILTIN_VFNMADDSD,
21091 IX86_BUILTIN_VFNMADDPS,
21092 IX86_BUILTIN_VFNMADDPD,
21093 IX86_BUILTIN_VFNMSUBSS,
21094 IX86_BUILTIN_VFNMSUBSD,
21095 IX86_BUILTIN_VFNMSUBPS,
21096 IX86_BUILTIN_VFNMSUBPD,
21097 IX86_BUILTIN_VFMADDPS256,
21098 IX86_BUILTIN_VFMADDPD256,
21099 IX86_BUILTIN_VFMSUBPS256,
21100 IX86_BUILTIN_VFMSUBPD256,
21101 IX86_BUILTIN_VFMADDSUBPS256,
21102 IX86_BUILTIN_VFMADDSUBPD256,
21103 IX86_BUILTIN_VFMSUBADDPS256,
21104 IX86_BUILTIN_VFMSUBADDPD256,
21105 IX86_BUILTIN_VFNMADDPS256,
21106 IX86_BUILTIN_VFNMADDPD256,
21107 IX86_BUILTIN_VFNMSUBPS256,
21108 IX86_BUILTIN_VFNMSUBPD256,
21110 IX86_BUILTIN_VPCMOV,
21111 IX86_BUILTIN_VPCMOV_V2DI,
21112 IX86_BUILTIN_VPCMOV_V4SI,
21113 IX86_BUILTIN_VPCMOV_V8HI,
21114 IX86_BUILTIN_VPCMOV_V16QI,
21115 IX86_BUILTIN_VPCMOV_V4SF,
21116 IX86_BUILTIN_VPCMOV_V2DF,
21117 IX86_BUILTIN_VPCMOV256,
21118 IX86_BUILTIN_VPCMOV_V4DI256,
21119 IX86_BUILTIN_VPCMOV_V8SI256,
21120 IX86_BUILTIN_VPCMOV_V16HI256,
21121 IX86_BUILTIN_VPCMOV_V32QI256,
21122 IX86_BUILTIN_VPCMOV_V8SF256,
21123 IX86_BUILTIN_VPCMOV_V4DF256,
21125 IX86_BUILTIN_VPPERM,
21127 IX86_BUILTIN_VPMACSSWW,
21128 IX86_BUILTIN_VPMACSWW,
21129 IX86_BUILTIN_VPMACSSWD,
21130 IX86_BUILTIN_VPMACSWD,
21131 IX86_BUILTIN_VPMACSSDD,
21132 IX86_BUILTIN_VPMACSDD,
21133 IX86_BUILTIN_VPMACSSDQL,
21134 IX86_BUILTIN_VPMACSSDQH,
21135 IX86_BUILTIN_VPMACSDQL,
21136 IX86_BUILTIN_VPMACSDQH,
21137 IX86_BUILTIN_VPMADCSSWD,
21138 IX86_BUILTIN_VPMADCSWD,
21140 IX86_BUILTIN_VPHADDBW,
21141 IX86_BUILTIN_VPHADDBD,
21142 IX86_BUILTIN_VPHADDBQ,
21143 IX86_BUILTIN_VPHADDWD,
21144 IX86_BUILTIN_VPHADDWQ,
21145 IX86_BUILTIN_VPHADDDQ,
21146 IX86_BUILTIN_VPHADDUBW,
21147 IX86_BUILTIN_VPHADDUBD,
21148 IX86_BUILTIN_VPHADDUBQ,
21149 IX86_BUILTIN_VPHADDUWD,
21150 IX86_BUILTIN_VPHADDUWQ,
21151 IX86_BUILTIN_VPHADDUDQ,
21152 IX86_BUILTIN_VPHSUBBW,
21153 IX86_BUILTIN_VPHSUBWD,
21154 IX86_BUILTIN_VPHSUBDQ,
21156 IX86_BUILTIN_VPROTB,
21157 IX86_BUILTIN_VPROTW,
21158 IX86_BUILTIN_VPROTD,
21159 IX86_BUILTIN_VPROTQ,
21160 IX86_BUILTIN_VPROTB_IMM,
21161 IX86_BUILTIN_VPROTW_IMM,
21162 IX86_BUILTIN_VPROTD_IMM,
21163 IX86_BUILTIN_VPROTQ_IMM,
21165 IX86_BUILTIN_VPSHLB,
21166 IX86_BUILTIN_VPSHLW,
21167 IX86_BUILTIN_VPSHLD,
21168 IX86_BUILTIN_VPSHLQ,
21169 IX86_BUILTIN_VPSHAB,
21170 IX86_BUILTIN_VPSHAW,
21171 IX86_BUILTIN_VPSHAD,
21172 IX86_BUILTIN_VPSHAQ,
21174 IX86_BUILTIN_VFRCZSS,
21175 IX86_BUILTIN_VFRCZSD,
21176 IX86_BUILTIN_VFRCZPS,
21177 IX86_BUILTIN_VFRCZPD,
21178 IX86_BUILTIN_VFRCZPS256,
21179 IX86_BUILTIN_VFRCZPD256,
21181 IX86_BUILTIN_VPCOMEQUB,
21182 IX86_BUILTIN_VPCOMNEUB,
21183 IX86_BUILTIN_VPCOMLTUB,
21184 IX86_BUILTIN_VPCOMLEUB,
21185 IX86_BUILTIN_VPCOMGTUB,
21186 IX86_BUILTIN_VPCOMGEUB,
21187 IX86_BUILTIN_VPCOMFALSEUB,
21188 IX86_BUILTIN_VPCOMTRUEUB,
21190 IX86_BUILTIN_VPCOMEQUW,
21191 IX86_BUILTIN_VPCOMNEUW,
21192 IX86_BUILTIN_VPCOMLTUW,
21193 IX86_BUILTIN_VPCOMLEUW,
21194 IX86_BUILTIN_VPCOMGTUW,
21195 IX86_BUILTIN_VPCOMGEUW,
21196 IX86_BUILTIN_VPCOMFALSEUW,
21197 IX86_BUILTIN_VPCOMTRUEUW,
21199 IX86_BUILTIN_VPCOMEQUD,
21200 IX86_BUILTIN_VPCOMNEUD,
21201 IX86_BUILTIN_VPCOMLTUD,
21202 IX86_BUILTIN_VPCOMLEUD,
21203 IX86_BUILTIN_VPCOMGTUD,
21204 IX86_BUILTIN_VPCOMGEUD,
21205 IX86_BUILTIN_VPCOMFALSEUD,
21206 IX86_BUILTIN_VPCOMTRUEUD,
21208 IX86_BUILTIN_VPCOMEQUQ,
21209 IX86_BUILTIN_VPCOMNEUQ,
21210 IX86_BUILTIN_VPCOMLTUQ,
21211 IX86_BUILTIN_VPCOMLEUQ,
21212 IX86_BUILTIN_VPCOMGTUQ,
21213 IX86_BUILTIN_VPCOMGEUQ,
21214 IX86_BUILTIN_VPCOMFALSEUQ,
21215 IX86_BUILTIN_VPCOMTRUEUQ,
21217 IX86_BUILTIN_VPCOMEQB,
21218 IX86_BUILTIN_VPCOMNEB,
21219 IX86_BUILTIN_VPCOMLTB,
21220 IX86_BUILTIN_VPCOMLEB,
21221 IX86_BUILTIN_VPCOMGTB,
21222 IX86_BUILTIN_VPCOMGEB,
21223 IX86_BUILTIN_VPCOMFALSEB,
21224 IX86_BUILTIN_VPCOMTRUEB,
21226 IX86_BUILTIN_VPCOMEQW,
21227 IX86_BUILTIN_VPCOMNEW,
21228 IX86_BUILTIN_VPCOMLTW,
21229 IX86_BUILTIN_VPCOMLEW,
21230 IX86_BUILTIN_VPCOMGTW,
21231 IX86_BUILTIN_VPCOMGEW,
21232 IX86_BUILTIN_VPCOMFALSEW,
21233 IX86_BUILTIN_VPCOMTRUEW,
21235 IX86_BUILTIN_VPCOMEQD,
21236 IX86_BUILTIN_VPCOMNED,
21237 IX86_BUILTIN_VPCOMLTD,
21238 IX86_BUILTIN_VPCOMLED,
21239 IX86_BUILTIN_VPCOMGTD,
21240 IX86_BUILTIN_VPCOMGED,
21241 IX86_BUILTIN_VPCOMFALSED,
21242 IX86_BUILTIN_VPCOMTRUED,
21244 IX86_BUILTIN_VPCOMEQQ,
21245 IX86_BUILTIN_VPCOMNEQ,
21246 IX86_BUILTIN_VPCOMLTQ,
21247 IX86_BUILTIN_VPCOMLEQ,
21248 IX86_BUILTIN_VPCOMGTQ,
21249 IX86_BUILTIN_VPCOMGEQ,
21250 IX86_BUILTIN_VPCOMFALSEQ,
21251 IX86_BUILTIN_VPCOMTRUEQ,
21253 /* LWP instructions. */
21254 IX86_BUILTIN_LLWPCB,
21255 IX86_BUILTIN_SLWPCB,
21256 IX86_BUILTIN_LWPVAL32,
21257 IX86_BUILTIN_LWPVAL64,
21258 IX86_BUILTIN_LWPINS32,
21259 IX86_BUILTIN_LWPINS64,
21261 IX86_BUILTIN_CLZS,
21263 IX86_BUILTIN_MAX
21264 };
21266 /* Table for the ix86 builtin decls. */
21269 /* Table of all of the builtin functions that are possible with different ISA's
21270 but are waiting to be built until a function is declared to use that
21271 ISA. */
21278 };
21283 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21284 of which isa_flags to use in the ix86_builtins_isa array. Stores the
21285 function decl in the ix86_builtins array. Returns the function decl or
21286 NULL_TREE, if the builtin was not added.
21288 If the front end has a special hook for builtin functions, delay adding
21289 builtin functions that aren't in the current ISA until the ISA is changed
21290 with function specific optimization. Doing so, can save about 300K for the
21291 default compiler. When the builtin is expanded, check at that time whether
21292 it is valid.
21294 If the front end doesn't have a special hook, record all builtins, even if
21295 it isn't an instruction set in the current ISA in case the user uses
21296 function specific options for a different ISA, so that we don't get scope
21297 errors if a builtin is added in the middle of a function scope. */
21302 {
21306 {
21314 {
21320 }
21321 else
21322 {
21328 }
21329 }
21332 }
21334 /* Like def_builtin, but also marks the function decl "const". */
21339 {
21343 else
21347 }
21349 /* Add any new builtin functions for a given ISA that may not have been
21350 declared. This saves a bit of space compared to adding all of the
21351 declarations to the tree, even if we didn't use them. */
21353 static void
21355 {
21359 {
21362 {
21365 /* Don't define the builtin again. */
21371 NULL_TREE);
21376 }
21377 }
21378 }
21380 /* Bits for builtin_description.flag. */
21382 /* Set when we don't support the comparison natively, and should
21383 swap_comparison in order to support it. */
21384 #define BUILTIN_DESC_SWAP_OPERANDS 1
21386 struct builtin_description
21387 {
21394 };
21397 {
21398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21407 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21422 };
21425 {
21426 /* SSE4.2 */
21427 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21428 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21429 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21430 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21431 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21432 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21433 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21434 };
21437 {
21438 /* SSE4.2 */
21439 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21440 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21441 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21442 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21443 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21444 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21445 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21446 };
21448 /* Special builtins with variable number of arguments. */
21450 {
21451 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21452 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21454 /* MMX */
21455 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21457 /* 3DNow! */
21458 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21460 /* SSE */
21461 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21462 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21463 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21465 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21466 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21467 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21468 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21470 /* SSE or 3DNow!A */
21471 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21472 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
21474 /* SSE2 */
21475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21488 /* SSE3 */
21489 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21491 /* SSE4.1 */
21492 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21494 /* SSE4A */
21495 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21496 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21498 /* AVX */
21499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21502 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21503 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21504 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21529 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
21530 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
21531 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21532 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21533 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21534 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21536 };
21538 /* Builtins with variable number of arguments. */
21540 {
21541 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21542 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21543 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21544 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21545 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21546 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21547 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21549 /* MMX */
21550 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21551 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21552 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21553 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21554 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21555 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21557 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21558 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21559 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21560 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21561 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21562 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21563 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21564 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21566 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21567 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21569 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21570 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21571 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21572 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21574 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21575 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21576 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21577 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21578 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21579 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21581 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21582 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21583 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21584 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21585 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21586 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21588 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21589 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21590 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21592 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21594 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21595 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21596 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21597 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21598 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21599 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21601 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21602 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21603 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21604 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21605 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21606 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21608 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21609 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21610 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21611 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21613 /* 3DNow! */
21614 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21615 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21616 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21617 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21619 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21620 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21621 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21622 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21623 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21624 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21625 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21626 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21627 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21628 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21629 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21630 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21631 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21632 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21633 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21635 /* 3DNow!A */
21636 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21637 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21638 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21639 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21640 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21641 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21643 /* SSE */
21644 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21645 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21646 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21647 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21648 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21649 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21650 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21651 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21652 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21653 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21654 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21655 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21657 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21659 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21660 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21661 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21662 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21663 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21664 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21665 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21666 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21668 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21669 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21670 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21671 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21672 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21673 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21674 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21675 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21676 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21677 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21678 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21679 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21680 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21681 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21682 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21683 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21684 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21685 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21686 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21687 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21688 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21689 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21691 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21692 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21693 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21694 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21696 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21697 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21698 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21699 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21701 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21703 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21704 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21705 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21706 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21707 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21709 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21710 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21711 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21713 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21715 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21716 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21717 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21719 /* SSE MMX or 3Dnow!A */
21720 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21721 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21722 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21724 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21725 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21726 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21727 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21729 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21730 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21732 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21734 /* SSE2 */
21735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21737 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
21738 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
21739 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
21740 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
21741 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
21742 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21743 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
21744 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
21745 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
21746 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
21747 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
21748 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
21750 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21751 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21753 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21754 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21755 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21757 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21758 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21759 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21767 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21768 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21774 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21775 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21776 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21777 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21786 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21787 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21789 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21790 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21791 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21792 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21793 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21794 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21795 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21796 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21797 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21798 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21799 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21800 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21801 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21802 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21805 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21809 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21811 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21812 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21814 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21817 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21818 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21820 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21822 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21823 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21824 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21825 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21826 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21827 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21828 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21829 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21840 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21841 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21843 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21845 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21846 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21858 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21859 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21860 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21863 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21864 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21865 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21866 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21867 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21868 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21869 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21870 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21876 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21879 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21880 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21885 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
21890 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21891 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21892 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21893 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21894 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21895 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
21898 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21899 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21900 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21901 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21902 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21903 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21905 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21906 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21907 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21908 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21916 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21917 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21919 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21921 /* SSE2 MMX */
21922 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21923 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21925 /* SSE3 */
21926 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21927 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21929 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21930 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21931 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21932 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21933 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21934 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21936 /* SSSE3 */
21937 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21938 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21939 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21940 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21941 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21942 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21944 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21945 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21946 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21947 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21948 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21949 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21950 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21951 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21952 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21953 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21954 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21955 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21956 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21957 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21958 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21959 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21960 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21961 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21962 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21963 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21964 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21965 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21966 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21967 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21969 /* SSSE3. */
21970 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
21971 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
21973 /* SSE4.1 */
21974 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21975 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21976 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21977 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21978 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21979 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21980 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21981 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21982 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21983 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21985 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21986 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21987 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21988 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21989 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21990 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21991 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21992 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21993 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21994 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21995 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21996 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21997 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21999 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22000 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22001 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22002 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22003 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22004 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22005 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22006 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22007 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22008 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22009 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22010 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22012 /* SSE4.1 */
22013 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22014 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22015 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22016 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22018 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22019 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22020 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22022 /* SSE4.2 */
22023 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22024 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22025 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22026 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22027 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22029 /* SSE4A */
22030 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22031 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22032 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22033 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22035 /* AES */
22036 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22037 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22039 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22040 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22041 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22042 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22044 /* PCLMUL */
22045 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22047 /* AVX */
22048 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22049 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22052 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22053 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22054 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22056 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22062 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22063 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22064 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22065 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22066 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22067 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22068 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22069 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22070 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22071 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22072 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22073 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22084 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22085 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22086 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22087 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22088 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22089 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22090 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22091 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22092 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22093 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22094 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22095 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22096 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22097 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22098 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22099 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22100 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22101 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22102 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22103 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22104 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22105 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22106 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22107 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22108 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22109 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22112 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22113 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22115 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22116 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22117 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22119 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22120 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22121 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22122 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22123 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22139 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22142 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22148 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22149 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22150 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22153 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22154 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22155 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22161 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
22162 };
22164 /* FMA4 and XOP. */
22165 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
22166 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
22167 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
22168 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
22169 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
22170 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
22171 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
22172 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
22173 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
22174 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
22175 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
22176 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
22177 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
22178 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
22179 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
22180 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
22181 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
22182 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
22183 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
22184 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
22185 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
22186 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
22187 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
22188 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
22189 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
22190 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
22191 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
22192 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
22193 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
22194 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
22195 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
22196 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
22197 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
22198 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
22199 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
22200 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
22201 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
22202 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
22203 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
22204 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
22205 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
22206 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
22207 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
22208 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
22209 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
22210 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
22211 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
22212 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
22215 {
22216 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22217 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22218 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22219 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22220 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22221 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22222 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22223 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22225 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22226 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22227 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22228 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22229 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22230 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22231 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22232 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22234 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22235 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22236 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22237 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22239 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22240 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22241 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22242 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22244 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22245 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22246 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22247 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22249 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22250 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22251 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22252 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22256 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22265 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22266 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22272 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22273 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22274 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22276 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22279 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22281 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22282 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22289 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22290 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22295 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22297 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22298 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22299 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22300 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22303 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22305 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22306 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22359 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22407 };
22409 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22410 in the current target ISA to allow the user to compile particular modules
22411 with different target specific options that differ from the command line
22412 options. */
22413 static void
22415 {
22420 /* Add all special builtins with variable number of operands. */
22424 {
22430 }
22432 /* Add all builtins with variable number of operands. */
22436 {
22442 }
22444 /* pcmpestr[im] insns. */
22448 {
22451 else
22454 }
22456 /* pcmpistr[im] insns. */
22460 {
22463 else
22466 }
22468 /* comi/ucomi insns. */
22470 {
22473 else
22476 }
22478 /* SSE */
22484 /* SSE or 3DNow!A */
22487 IX86_BUILTIN_MASKMOVQ);
22489 /* SSE2 */
22498 /* SSE3. */
22504 /* AES */
22518 /* PCLMUL */
22522 /* MMX access to the vec_init patterns. */
22527 V4HI_FTYPE_HI_HI_HI_HI,
22528 IX86_BUILTIN_VEC_INIT_V4HI);
22531 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
22532 IX86_BUILTIN_VEC_INIT_V8QI);
22534 /* Access to the vec_extract patterns. */
22556 /* Access to the vec_set patterns. */
22577 /* Add FMA4 multi-arg argument instructions */
22579 {
22585 }
22586 }
22588 /* Internal method for ix86_init_builtins. */
22590 static void
22592 {
22604 sysv_va_ref =
22607 fnvoid_va_end_ms =
22609 fnvoid_va_start_ms =
22611 fnvoid_va_end_sysv =
22613 fnvoid_va_start_sysv =
22615 NULL_TREE);
22616 fnvoid_va_copy_ms =
22618 NULL_TREE);
22619 fnvoid_va_copy_sysv =
22635 }
22637 static void
22639 {
22642 /* The __float80 type. */
22645 {
22646 /* The __float80 type. */
22651 }
22654 /* The __float128 type. */
22660 /* This macro is built by i386-builtin-types.awk. */
22661 DEFINE_BUILTIN_PRIMITIVE_TYPES;
22662 }
22664 static void
22666 {
22667 tree t;
22671 /* TFmode support builtins. */
22677 /* We will expand them to normal call if SSE2 isn't available since
22678 they are used by libgcc. */
22695 }
22697 /* Return the ix86 builtin for CODE. */
22699 static tree
22701 {
22706 }
22708 /* Errors in the source file can cause expand_expr to return const0_rtx
22709 where we expect a vector. To avoid crashing, use one of the vector
22710 clear instructions. */
22711 static rtx
22713 {
22717 }
22719 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
22721 static rtx
22723 {
22724 rtx pat;
22744 {
22748 }
22762 }
22764 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
22766 static rtx
22770 {
22771 rtx pat;
22779 rtx op;
22786 {
22858 }
22868 {
22875 {
22877 {
22880 }
22881 }
22882 else
22883 {
22887 /* If we aren't optimizing, only allow one memory operand to be
22888 generated. */
22890 num_memory++;
22898 }
22902 }
22905 {
22916 else
22917 {
22923 }
22932 }
22939 }
22941 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
22942 insns with vec_merge. */
22944 static rtx
22946 rtx target)
22947 {
22948 rtx pat;
22975 }
22977 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
22979 static rtx
22982 {
22983 rtx pat;
22988 rtx op2;
22999 /* Swap operands if we have a comparison that isn't available in
23000 hardware. */
23002 {
23007 }
23027 }
23029 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23031 static rtx
23033 rtx target)
23034 {
23035 rtx pat;
23049 /* Swap operands if we have a comparison that isn't available in
23050 hardware. */
23052 {
23056 }
23077 const0_rtx)));
23080 }
23082 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23084 static rtx
23086 rtx target)
23087 {
23088 rtx pat;
23121 const0_rtx)));
23124 }
23126 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23128 static rtx
23131 {
23132 rtx pat;
23170 {
23173 }
23176 {
23185 }
23187 {
23196 }
23197 else
23198 {
23205 }
23213 {
23218 emit_insn
23222 FLAGS_REG),
23223 const0_rtx)));
23225 }
23226 else
23228 }
23231 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23233 static rtx
23236 {
23237 rtx pat;
23265 {
23268 }
23271 {
23280 }
23282 {
23291 }
23292 else
23293 {
23300 }
23308 {
23313 emit_insn
23317 FLAGS_REG),
23318 const0_rtx)));
23320 }
23321 else
23323 }
23325 /* Subroutine of ix86_expand_builtin to take care of insns with
23326 variable number of operands. */
23328 static rtx
23331 {
23336 struct
23337 {
23338 rtx op;
23350 {
23554 }
23559 {
23562 }
23565 {
23572 }
23573 else
23574 {
23577 }
23580 {
23587 {
23588 /* SIMD shift insns take either an 8-bit immediate or
23589 register as count. But builtin functions take int as
23590 count. If count doesn't match, we put it in register. */
23592 {
23596 }
23597 }
23599 {
23602 {
23640 {
23643 {
23646 }
23652 }
23654 }
23655 }
23656 else
23657 {
23661 /* If we aren't optimizing, only allow one memory operand to
23662 be generated. */
23664 num_memory++;
23667 {
23670 }
23671 else
23672 {
23675 }
23676 }
23680 }
23683 {
23700 }
23707 }
23709 /* Subroutine of ix86_expand_builtin to take care of special insns
23710 with variable number of operands. */
23712 static rtx
23715 {
23716 tree arg;
23719 struct
23720 {
23721 rtx op;
23731 {
23768 /* Reserve memory operand for target. */
23791 /* Reserve memory operand for target. */
23805 }
23810 {
23816 }
23817 else
23818 {
23825 }
23828 {
23837 {
23840 {
23851 }
23852 }
23853 else
23854 {
23856 {
23857 /* This must be the memory operand. */
23861 }
23862 else
23863 {
23864 /* This must be register. */
23871 }
23872 }
23876 }
23879 {
23894 }
23900 }
23902 /* Return the integer constant in ARG. Constrain it to be in the range
23903 of the subparts of VEC_TYPE; issue an error if not. */
23905 static int
23907 {
23912 {
23915 }
23918 }
23920 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
23921 ix86_expand_vector_init. We DO have language-level syntax for this, in
23922 the form of (type){ init-list }. Except that since we can't place emms
23923 instructions from inside the compiler, we can't allow the use of MMX
23924 registers unless the user explicitly asks for it. So we do *not* define
23925 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
23926 we have builtins invoked by mmintrin.h that gives us license to emit
23927 these sorts of instructions. */
23929 static rtx
23931 {
23941 {
23944 }
23951 }
23953 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
23954 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
23955 had a language-level syntax for referencing vector elements. */
23957 static rtx
23959 {
23963 rtx op0;
23983 }
23985 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
23986 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
23987 a language-level syntax for referencing vector elements. */
23989 static rtx
23991 {
24015 /* OP0 is the source of these builtin functions and shouldn't be
24016 modified. Create a copy, use it and return it as target. */
24022 }
24024 /* Expand an expression EXP that calls a built-in function,
24025 with result going to TARGET if that's convenient
24026 (and in mode MODE if that's convenient).
24027 SUBTARGET may be used as the target for computing one of EXP's operands.
24028 IGNORE is nonzero if the value is to be ignored. */
24030 static rtx
24034 {
24044 /* Determine whether the builtin function is available under the current ISA.
24045 Originally the builtin was not created if it wasn't applicable to the
24046 current ISA based on the command line switches. With function specific
24047 options, we need to check in the context of the function making the call
24048 whether it is supported. */
24051 {
24057 else
24058 {
24062 }
24064 }
24067 {
24071 ? CODE_FOR_mmx_maskmovq
24073 /* Note the arg order is different from the operand order. */
24188 {
24189 REAL_VALUE_TYPE inf;
24190 rtx tmp;
24202 }
24223 }
24236 {
24240 /* Emit a normal call if SSE2 isn't available. */
24244 }
24269 }
24271 /* Returns a function decl for a vectorized version of the builtin function
24272 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24273 if it is not available. */
24275 static tree
24277 tree type_in)
24278 {
24292 {
24330 ;
24331 }
24333 /* Dispatch to a handler for a vectorization library. */
24336 type_in);
24339 }
24341 /* Handler for an SVML-style interface to
24342 a library with vectorized intrinsics. */
24344 static tree
24346 {
24354 /* The SVML is suitable for unsafe math only. */
24367 {
24414 }
24423 {
24426 }
24427 else
24430 /* Convert to uppercase. */
24436 arity++;
24440 else
24443 /* Build a function declaration for the vectorized function. */
24452 }
24454 /* Handler for an ACML-style interface to
24455 a library with vectorized intrinsics. */
24457 static tree
24459 {
24467 /* The ACML is 64bits only and suitable for unsafe math only as
24468 it does not correctly support parts of IEEE with the required
24469 precision such as denormals. */
24483 {
24513 }
24521 arity++;
24525 else
24528 /* Build a function declaration for the vectorized function. */
24537 }
24540 /* Returns a decl of a function that implements conversion of an integer vector
24541 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24542 side of the conversion.
24543 Return NULL_TREE if it is not available. */
24545 static tree
24547 {
24552 {
24555 {
24562 }
24566 {
24569 ? NULL_TREE
24573 }
24577 }
24578 }
24580 /* Returns a code for a target-specific builtin that implements
24581 reciprocal of the function, or NULL_TREE if not available. */
24583 static tree
24586 {
24593 /* Machine dependent builtins. */
24595 {
24596 /* Vectorized version of sqrt to rsqrt conversion. */
24602 }
24603 else
24604 /* Normal builtins. */
24606 {
24607 /* Sqrt to rsqrt conversion. */
24613 }
24614 }
24615 \f
24616 /* Helper for avx_vpermilps256_operand et al. This is also used by
24617 the expansion functions to turn the parallel back into a mask.
24618 The return value is 0 for no match and the imm8+1 for a match. */
24620 int
24622 {
24630 /* Validate that all of the elements are constants, and not totally
24631 out of range. Copy the data into an integral array to make the
24632 subsequent checks easier. */
24634 {
24644 }
24647 {
24649 /* In the 256-bit DFmode case, we can only move elements within
24650 a 128-bit lane. */
24652 {
24656 }
24658 {
24662 }
24666 /* In the 256-bit SFmode case, we have full freedom of movement
24667 within the low 128-bit lane, but the high 128-bit lane must
24668 mirror the exact same pattern. */
24673 /* FALLTHRU */
24677 /* In the 128-bit case, we've full freedom in the placement of
24678 the elements from the source operand. */
24685 }
24687 /* Make sure success has a non-zero value by adding one. */
24689 }
24691 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
24692 the expansion functions to turn the parallel back into a mask.
24693 The return value is 0 for no match and the imm8+1 for a match. */
24695 int
24697 {
24705 /* Validate that all of the elements are constants, and not totally
24706 out of range. Copy the data into an integral array to make the
24707 subsequent checks easier. */
24709 {
24719 }
24721 /* Validate that the halves of the permute are halves. */
24729 /* Reconstruct the mask. */
24731 {
24737 }
24739 /* Make sure success has a non-zero value by adding one. */
24741 }
24742 \f
24744 /* Store OPERAND to the memory after reload is completed. This means
24745 that we can't easily use assign_stack_local. */
24746 rtx
24748 {
24749 rtx result;
24753 {
24756 stack_pointer_rtx,
24759 }
24761 {
24763 {
24767 /* FALLTHRU */
24773 stack_pointer_rtx)),
24774 operand));
24778 }
24780 }
24781 else
24782 {
24784 {
24786 {
24793 stack_pointer_rtx)),
24799 stack_pointer_rtx)),
24801 }
24804 /* Store HImodes as SImodes. */
24806 /* FALLTHRU */
24812 stack_pointer_rtx)),
24813 operand));
24817 }
24819 }
24821 }
24823 /* Free operand from the memory. */
24824 void
24826 {
24828 {
24833 else
24835 /* Use LEA to deallocate stack space. In peephole2 it will be converted
24836 to pop or add instruction if registers are available. */
24840 }
24841 }
24843 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
24844 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
24845 same. */
24848 {
24851 };
24854 };
24857 }
24859 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
24860 QImode must go into class Q_REGS.
24861 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
24862 movdf to do mem-to-mem moves through integer regs. */
24863 enum reg_class
24865 {
24868 /* We're only allowed to return a subclass of CLASS. Many of the
24869 following checks fail for NO_REGS, so eliminate that early. */
24873 /* All classes can load zeros. */
24877 /* Force constants into memory if we are loading a (nonzero) constant into
24878 an MMX or SSE register. This is because there are no MMX/SSE instructions
24879 to load from a constant. */
24884 /* Prefer SSE regs only, if we can use them for math. */
24888 /* Floating-point constants need more complex checks. */
24890 {
24891 /* General regs can load everything. */
24895 /* Floats can load 0 and 1 plus some others. Note that we eliminated
24896 zero above. We only want to wind up preferring 80387 registers if
24897 we plan on doing computation with them. */
24900 {
24901 /* Limit class to non-sse. */
24910 }
24913 }
24915 /* Generally when we see PLUS here, it's the function invariant
24916 (plus soft-fp const_int). Which can only be computed into general
24917 regs. */
24921 /* QImode constants are easy to load, but non-constant QImode data
24922 must go into Q_REGS. */
24924 {
24930 }
24933 }
24935 /* Discourage putting floating-point values in SSE registers unless
24936 SSE math is being used, and likewise for the 387 registers. */
24937 enum reg_class
24939 {
24942 /* Restrict the output reload class to the register bank that we are doing
24943 math on. If we would like not to return a subset of CLASS, reject this
24944 alternative: if reload cannot do this, it will still use its choice. */
24950 {
24955 else
24957 }
24960 }
24962 static enum reg_class
24966 {
24967 /* QImode spills from non-QI registers require
24968 intermediate register on 32bit targets. */
24973 {
24978 else
24984 /* Return Q_REGS if the operand is in memory. */
24987 }
24990 }
24992 /* If we are copying between general and FP registers, we need a memory
24993 location. The same is true for SSE and MMX registers.
24995 To optimize register_move_cost performance, allow inline variant.
24997 The macro can't work reliably when one of the CLASSES is class containing
24998 registers from multiple units (SSE, MMX, integer). We avoid this by never
24999 combining those units in single alternative in the machine description.
25000 Ensure that this constraint holds to avoid unexpected surprises.
25002 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25003 enforce these sanity checks. */
25008 {
25015 {
25018 }
25023 /* ??? This is a lie. We do have moves between mmx/general, and for
25024 mmx/sse2. But by saying we need secondary memory we discourage the
25025 register allocator from using the mmx registers unless needed. */
25030 {
25031 /* SSE1 doesn't have any direct moves from other classes. */
25035 /* If the target says that inter-unit moves are more expensive
25036 than moving through memory, then don't generate them. */
25040 /* Between SSE and general, we have moves no larger than word size. */
25043 }
25046 }
25048 int
25051 {
25053 }
25055 /* Return true if the registers in CLASS cannot represent the change from
25056 modes FROM to TO. */
25058 bool
25061 {
25065 /* x87 registers can't do subreg at all, as all values are reformatted
25066 to extended precision. */
25071 {
25072 /* Vector registers do not support QI or HImode loads. If we don't
25073 disallow a change to these modes, reload will assume it's ok to
25074 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25075 the vec_dupv4hi pattern. */
25079 /* Vector registers do not support subreg with nonzero offsets, which
25080 are otherwise valid for integer registers. Since we can't see
25081 whether we have a nonzero offset from here, prohibit all
25082 nonparadoxical subregs changing size. */
25085 }
25088 }
25090 /* Return the cost of moving data of mode M between a
25091 register and memory. A value of 2 is the default; this cost is
25092 relative to those in `REGISTER_MOVE_COST'.
25094 This function is used extensively by register_move_cost that is used to
25095 build tables at startup. Make it inline in this case.
25096 When IN is 2, return maximum of in and out move cost.
25098 If moving between registers and memory is more expensive than
25099 between two registers, you should define this macro to express the
25100 relative cost.
25102 Model also increased moving costs of QImode registers in non
25103 Q_REGS classes.
25104 */
25108 {
25111 {
25114 {
25126 }
25130 }
25132 {
25135 {
25147 }
25151 }
25153 {
25156 {
25165 }
25169 }
25171 {
25174 {
25180 else
25185 }
25186 else
25187 {
25192 else
25194 }
25201 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25208 else
25212 }
25213 }
25215 int
25217 {
25219 }
25222 /* Return the cost of moving data from a register in class CLASS1 to
25223 one in class CLASS2.
25225 It is not required that the cost always equal 2 when FROM is the same as TO;
25226 on some machines it is expensive to move between registers if they are not
25227 general registers. */
25229 int
25232 {
25233 /* In case we require secondary memory, compute cost of the store followed
25234 by load. In order to avoid bad register allocation choices, we need
25235 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25238 {
25244 /* In case of copying from general_purpose_register we may emit multiple
25245 stores followed by single load causing memory size mismatch stall.
25246 Count this as arbitrarily high cost of 20. */
25250 /* In the case of FP/MMX moves, the registers actually overlap, and we
25251 have to switch modes in order to treat them differently. */
25257 }
25259 /* Moves between SSE/MMX and integer unit are expensive. */
25263 /* ??? By keeping returned value relatively high, we limit the number
25264 of moves between integer and MMX/SSE registers for all targets.
25265 Additionally, high value prevents problem with x86_modes_tieable_p(),
25266 where integer modes in MMX/SSE registers are not tieable
25267 because of missing QImode and HImode moves to, from or between
25268 MMX/SSE registers. */
25278 }
25280 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25282 bool
25284 {
25285 /* Flags and only flags can only hold CCmode values. */
25295 {
25296 /* We implement the move patterns for all vector modes into and
25297 out of SSE registers, even when no operation instructions
25298 are available. OImode move is available only when AVX is
25299 enabled. */
25306 }
25308 {
25309 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25310 so if the register is available at all, then we can move data of
25311 the given mode into or out of it. */
25314 }
25317 {
25318 /* Take care for QImode values - they can be in non-QI regs,
25319 but then they do cause partial register stalls. */
25325 }
25326 /* We handle both integer and floats in the general purpose registers. */
25333 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25334 on to use that value in smaller contexts, this can easily force a
25335 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25336 supporting DImode, allow it. */
25341 }
25343 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25344 tieable integer mode. */
25346 static bool
25348 {
25350 {
25363 }
25364 }
25366 /* Return true if MODE1 is accessible in a register that can hold MODE2
25367 without copying. That is, all register classes that can hold MODE2
25368 can also hold MODE1. */
25370 bool
25372 {
25380 /* MODE2 being XFmode implies fp stack or general regs, which means we
25381 can tie any smaller floating point modes to it. Note that we do not
25382 tie this with TFmode. */
25386 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25387 that we can tie it with SFmode. */
25391 /* If MODE2 is only appropriate for an SSE register, then tie with
25392 any other mode acceptable to SSE registers. */
25398 /* If MODE2 is appropriate for an MMX register, then tie
25399 with any other mode acceptable to MMX registers. */
25406 }
25408 /* Compute a (partial) cost for rtx X. Return true if the complete
25409 cost has been computed, and false if subexpressions should be
25410 scanned. In either case, *TOTAL contains the cost result. */
25412 static bool
25414 {
25420 {
25430 && (!TARGET_64BIT
25435 else
25442 else
25444 {
25453 /* Start with (MEM (SYMBOL_REF)), since that's where
25454 it'll probably end up. Add a penalty for size. */
25459 }
25463 /* The zero extensions is often completely free on x86_64, so make
25464 it as cheap as possible. */
25470 else
25481 {
25484 {
25487 }
25490 {
25493 }
25494 }
25495 /* FALLTHRU */
25502 {
25504 {
25507 else
25509 }
25510 else
25511 {
25514 else
25516 }
25517 }
25518 else
25519 {
25522 else
25524 }
25529 {
25530 /* ??? SSE scalar cost should be used here. */
25533 }
25535 {
25538 }
25540 {
25541 /* ??? SSE vector cost should be used here. */
25544 }
25545 else
25546 {
25551 {
25554 nbits++;
25555 }
25556 else
25557 /* This is arbitrary. */
25560 /* Compute costs correctly for widening multiplication. */
25564 {
25571 {
25575 else
25577 }
25581 }
25588 }
25595 /* ??? SSE cost should be used here. */
25600 /* ??? SSE vector cost should be used here. */
25602 else
25609 {
25614 {
25617 {
25624 }
25625 }
25628 {
25631 {
25636 }
25637 }
25639 {
25645 }
25646 }
25647 /* FALLTHRU */
25651 {
25652 /* ??? SSE cost should be used here. */
25655 }
25657 {
25660 }
25662 {
25663 /* ??? SSE vector cost should be used here. */
25666 }
25667 /* FALLTHRU */
25673 {
25680 }
25681 /* FALLTHRU */
25685 {
25686 /* ??? SSE cost should be used here. */
25689 }
25691 {
25694 }
25696 {
25697 /* ??? SSE vector cost should be used here. */
25700 }
25701 /* FALLTHRU */
25706 else
25715 {
25716 /* This kind of construct is implemented using test[bwl].
25717 Treat it as if we had an AND. */
25722 }
25732 /* ??? SSE cost should be used here. */
25737 /* ??? SSE vector cost should be used here. */
25743 /* ??? SSE cost should be used here. */
25748 /* ??? SSE vector cost should be used here. */
25761 /* ??? Assume all of these vector manipulation patterns are
25762 recognizable. In which case they all pretty much have the
25763 same cost. */
25769 }
25770 }
25772 #if TARGET_MACHO
25776 /* Given a symbol name and its associated stub, write out the
25777 definition of the stub. */
25779 void
25781 {
25786 /* For 64-bit we shouldn't get here. */
25789 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25804 else
25811 {
25815 }
25816 else
25822 {
25825 }
25826 else
25835 }
25837 void
25839 {
25842 }
25845 /* Order the registers for register allocator. */
25847 void
25849 {
25853 /* First allocate the local general purpose registers. */
25858 /* Global general purpose registers. */
25863 /* x87 registers come first in case we are doing FP math
25864 using them. */
25869 /* SSE registers. */
25875 /* x87 registers. */
25883 /* Initialize the rest of array as we do not allocate some registers
25884 at all. */
25887 }
25889 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
25890 struct attribute_spec.handler. */
25891 static tree
25893 tree args ATTRIBUTE_UNUSED,
25895 {
25900 {
25902 name);
25905 }
25907 {
25909 name);
25912 }
25914 /* Can combine regparm with all attributes but fastcall. */
25916 {
25918 {
25920 }
25923 }
25925 {
25927 {
25929 }
25932 }
25935 }
25937 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
25938 struct attribute_spec.handler. */
25939 static tree
25941 tree args ATTRIBUTE_UNUSED,
25943 {
25946 {
25949 }
25950 else
25955 {
25957 name);
25959 }
25965 {
25967 name);
25969 }
25972 }
25974 static tree
25976 tree args ATTRIBUTE_UNUSED,
25978 {
25980 {
25982 name);
25985 }
25988 {
25990 name);
25992 }
25994 #ifndef HAVE_AS_IX86_SWAP
25996 #endif
25999 }
26001 static bool
26003 {
26007 }
26009 /* Returns an expression indicating where the this parameter is
26010 located on entry to the FUNCTION. */
26012 static rtx
26014 {
26020 {
26025 else
26028 }
26033 {
26038 else
26039 {
26042 {
26047 }
26048 }
26050 }
26053 }
26055 /* Determine whether x86_output_mi_thunk can succeed. */
26057 static bool
26059 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26061 {
26062 /* 64-bit can handle anything. */
26066 /* For 32-bit, everything's fine if we have one free register. */
26070 /* Need a free register for vcall_offset. */
26074 /* Need a free register for GOT references. */
26078 /* Otherwise ok. */
26080 }
26082 /* Output the assembler code for a thunk function. THUNK_DECL is the
26083 declaration for the thunk function itself, FUNCTION is the decl for
26084 the target function. DELTA is an immediate constant offset to be
26085 added to THIS. If VCALL_OFFSET is nonzero, the word at
26086 *(*this + vcall_offset) should be added to THIS. */
26088 static void
26092 {
26097 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26098 pull it in now and let DELTA benefit. */
26102 {
26103 /* Put the this parameter into %eax. */
26107 }
26108 else
26111 /* Adjust the this parameter by a fixed constant. */
26113 {
26114 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
26115 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
26120 {
26122 {
26128 }
26131 else
26133 }
26136 else
26138 }
26140 /* Adjust the this parameter by a value stored in the vtable. */
26142 {
26145 else
26146 {
26152 }
26158 /* Adjust the this parameter. */
26161 {
26167 }
26170 }
26172 /* If necessary, drop THIS back to its stack slot. */
26174 {
26178 }
26182 {
26185 /* All thunks should be in the same object as their target,
26186 and thus binds_local_p should be true. */
26189 else
26190 {
26196 }
26197 }
26198 else
26199 {
26202 else
26203 #if TARGET_MACHO
26205 {
26207 tmp = (gen_rtx_SYMBOL_REF
26213 }
26214 else
26216 {
26223 }
26224 }
26225 }
26227 static void
26229 {
26231 #if TARGET_MACHO
26233 #endif
26240 }
26242 int
26244 {
26256 }
26258 /* Output assembler code to FILE to increment profiler label # LABELNO
26259 for profiling a function entry. */
26260 void
26262 {
26264 {
26265 #ifndef NO_PROFILE_COUNTERS
26267 #endif
26271 else
26273 }
26275 {
26276 #ifndef NO_PROFILE_COUNTERS
26278 labelno);
26279 #endif
26281 }
26282 else
26283 {
26284 #ifndef NO_PROFILE_COUNTERS
26286 labelno);
26287 #endif
26289 }
26290 }
26292 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26293 /* We don't have exact information about the insn sizes, but we may assume
26294 quite safely that we are informed about all 1 byte insns and memory
26295 address sizes. This is enough to eliminate unnecessary padding in
26296 99% of cases. */
26298 static int
26300 {
26306 /* Discard alignments we've emit and jump instructions. */
26313 /* Important case - calls are always 5 bytes.
26314 It is common to have many calls in the row. */
26323 /* For normal instructions we rely on get_attr_length being exact,
26324 with a few exceptions. */
26326 {
26330 {
26340 /* Otherwise trust get_attr_length. */
26342 }
26347 }
26350 else
26352 }
26354 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26355 window. */
26357 static void
26359 {
26364 /* Look for all minimal intervals of instructions containing 4 jumps.
26365 The intervals are bounded by START and INSN. NBYTES is the total
26366 size of instructions in the interval including INSN and not including
26367 START. When the NBYTES is smaller than 16 bytes, it is possible
26368 that the end of START and INSN ends up in the same 16byte page.
26370 The smallest offset in the page INSN can start is the case where START
26371 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26372 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26373 */
26375 {
26379 {
26385 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26386 already in the current 16 byte page, because otherwise
26387 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26388 bytes to reach 16 byte boundary. */
26396 {
26398 {
26405 else
26408 }
26409 }
26411 }
26422 njumps++;
26423 else
26427 {
26434 else
26437 }
26444 {
26451 }
26452 }
26453 }
26454 #endif
26456 /* AMD Athlon works faster
26457 when RET is not destination of conditional jump or directly preceded
26458 by other jump instruction. We avoid the penalty by inserting NOP just
26459 before the RET instructions in such cases. */
26460 static void
26462 {
26463 edge e;
26464 edge_iterator ei;
26467 {
26470 rtx prev;
26480 {
26481 edge e;
26482 edge_iterator ei;
26488 }
26490 {
26496 /* Empty functions get branch mispredict even when the jump destination
26497 is not visible to us. */
26500 }
26502 {
26505 }
26506 }
26507 }
26509 /* Implement machine specific optimizations. We implement padding of returns
26510 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26511 static void
26513 {
26515 {
26518 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26521 #endif
26522 }
26523 }
26525 /* Return nonzero when QImode register that must be represented via REX prefix
26526 is used. */
26527 bool
26529 {
26537 }
26539 /* Return nonzero when P points to register encoded via REX prefix.
26540 Called via for_each_rtx. */
26541 static int
26543 {
26549 }
26551 /* Return true when INSN mentions register that must be encoded using REX
26552 prefix. */
26553 bool
26555 {
26558 }
26560 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26561 optabs would emit if we didn't have TFmode patterns. */
26563 void
26565 {
26599 }
26600 \f
26601 /* AVX does not support 32-byte integer vector operations,
26602 thus the longest vector we are faced with is V16QImode. */
26603 #define MAX_VECT_LEN 16
26605 struct expand_vec_perm_d
26606 {
26612 };
26617 /* Get a vector mode of the same size as the original but with elements
26618 twice as wide. This is only guaranteed to apply to integral vectors. */
26622 {
26623 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
26628 }
26630 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26631 with all elements equal to VAR. Return true if successful. */
26633 static bool
26636 {
26640 {
26645 /* FALLTHRU */
26655 {
26658 /* First attempt to recognize VAL as-is. */
26662 {
26663 /* If that fails, force VAL into a register. */
26667 }
26668 }
26675 {
26676 rtx x;
26683 }
26693 {
26697 permute:
26704 /* Extend to SImode using a paradoxical SUBREG. */
26708 /* Insert the SImode value as low element of a V4SImode vector. */
26716 }
26724 widen:
26725 /* Replicate the value once into the next wider mode and recurse. */
26726 {
26728 rtx x;
26744 }
26748 {
26757 }
26762 }
26763 }
26765 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26766 whose ONE_VAR element is VAR, and other elements are zero. Return true
26767 if successful. */
26769 static bool
26772 {
26774 rtx new_target;
26779 {
26781 /* For SSE4.1, we normally use vector set. But if the second
26782 element is zero and inter-unit moves are OK, we use movq
26783 instead. */
26784 use_vector_set = (TARGET_64BIT
26785 && TARGET_SSE4_1
26786 && !(TARGET_INTER_UNIT_MOVES
26808 /* Use ix86_expand_vector_set in 64bit mode only. */
26813 }
26816 {
26821 }
26824 {
26829 /* FALLTHRU */
26844 else
26851 {
26852 /* We need to shuffle the value to the correct position, so
26853 create a new pseudo to store the intermediate result. */
26855 /* With SSE2, we can use the integer shuffle insns. */
26857 {
26859 const1_rtx,
26866 }
26868 /* Otherwise convert the intermediate result to V4SFmode and
26869 use the SSE1 shuffle instructions. */
26871 {
26874 }
26875 else
26879 const1_rtx,
26888 }
26903 widen:
26907 /* Zero extend the variable element to SImode and recurse. */
26920 }
26921 }
26923 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26924 consisting of the values in VALS. It is known that all elements
26925 except ONE_VAR are constants. Return true if successful. */
26927 static bool
26930 {
26940 {
26945 /* For the two element vectors, it's just as easy to use
26946 the general case. */
26950 /* Use ix86_expand_vector_set in 64bit mode only. */
26972 widen:
26973 /* There's no way to set one QImode entry easily. Combine
26974 the variable value with its adjacent constant value, and
26975 promote to an HImode set. */
26978 {
26983 }
26984 else
26985 {
26988 }
27002 }
27007 }
27009 /* A subroutine of ix86_expand_vector_init_general. Use vector
27010 concatenate to handle the most general case: all values variable,
27011 and none identical. */
27013 static void
27016 {
27019 rtvec v;
27023 {
27026 {
27059 }
27072 {
27087 }
27092 {
27103 }
27106 half:
27107 /* FIXME: We process inputs backward to help RA. PR 36222. */
27111 {
27116 }
27120 {
27123 {
27127 }
27130 }
27131 else
27137 }
27138 }
27140 /* A subroutine of ix86_expand_vector_init_general. Use vector
27141 interleave to handle the most general case: all values variable,
27142 and none identical. */
27144 static void
27147 {
27156 {
27177 }
27180 {
27181 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27185 /* Insert the SImode value as low element of V4SImode vector. */
27189 op0),
27191 const1_rtx);
27194 /* Cast the V4SImode vector back to a vector in orignal mode. */
27198 /* Load even elements into the second positon. */
27202 const1_rtx));
27204 /* Cast vector to FIRST_IMODE vector. */
27207 }
27209 /* Interleave low FIRST_IMODE vectors. */
27211 {
27215 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27218 }
27220 /* Interleave low SECOND_IMODE vectors. */
27222 {
27225 {
27230 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27231 vector. */
27234 }
27237 /* FALLTHRU */
27244 /* Cast the SECOND_IMODE vector back to a vector on original
27245 mode. */
27252 }
27253 }
27255 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27256 all values variable, and none identical. */
27258 static void
27261 {
27267 {
27272 /* FALLTHRU */
27296 half:
27313 /* FALLTHRU */
27319 /* Don't use ix86_expand_vector_init_interleave if we can't
27320 move from GPR to SSE register directly. */
27336 }
27338 {
27350 {
27354 {
27360 else
27361 {
27366 }
27367 }
27370 }
27375 {
27381 }
27383 {
27389 }
27390 else
27392 }
27393 }
27395 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27396 instructions unless MMX_OK is true. */
27398 void
27400 {
27407 rtx x;
27410 {
27420 }
27422 /* Constants are best loaded from the constant pool. */
27424 {
27427 }
27429 /* If all values are identical, broadcast the value. */
27435 /* Values where only one field is non-constant are best loaded from
27436 the pool and overwritten via move later. */
27438 {
27442 one_var))
27447 }
27450 }
27452 void
27454 {
27459 rtx tmp;
27461 = {
27468 };
27470 = {
27477 };
27481 {
27485 {
27490 else
27494 }
27503 {
27506 /* For the two element vectors, we implement a VEC_CONCAT with
27507 the extraction of the other element. */
27514 else
27519 }
27528 {
27534 /* tmp = target = A B C D */
27536 /* target = A A B B */
27538 /* target = X A B B */
27540 /* target = A X C D */
27547 /* tmp = target = A B C D */
27549 /* tmp = X B C D */
27551 /* target = A B X D */
27558 /* tmp = target = A B C D */
27560 /* tmp = X B C D */
27562 /* target = A B X D */
27570 }
27578 /* Element 0 handled by vec_merge below. */
27580 {
27583 }
27586 {
27587 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27588 store into element 0, then shuffle them back. */
27605 }
27606 else
27607 {
27608 /* For SSE1, we have to reuse the V4SF code. */
27611 }
27664 half:
27665 /* Compute offset. */
27671 /* Extract the half. */
27675 /* Put val in tmp at elt. */
27678 /* Put it back. */
27684 }
27687 {
27691 }
27692 else
27693 {
27702 }
27703 }
27705 void
27707 {
27711 rtx tmp;
27714 {
27719 /* FALLTHRU */
27732 {
27752 }
27764 {
27766 {
27786 }
27790 }
27791 else
27792 {
27793 /* For SSE1, we have to reuse the V4SF code. */
27797 }
27812 /* ??? Could extract the appropriate HImode element and shift. */
27815 }
27818 {
27822 /* Let the rtl optimizers know about the zero extension performed. */
27824 {
27827 }
27830 }
27831 else
27832 {
27839 }
27840 }
27842 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27843 pattern to reduce; DEST is the destination; IN is the input vector. */
27845 void
27847 {
27861 }
27862 \f
27863 /* Target hook for scalar_mode_supported_p. */
27864 static bool
27866 {
27871 else
27873 }
27875 /* Implements target hook vector_mode_supported_p. */
27876 static bool
27878 {
27890 }
27892 /* Target hook for c_mode_for_suffix. */
27893 static enum machine_mode
27895 {
27902 }
27904 /* Worker function for TARGET_MD_ASM_CLOBBERS.
27906 We do this in the new i386 backend to maintain source compatibility
27907 with the old cc0-based compiler. */
27909 static tree
27911 tree inputs ATTRIBUTE_UNUSED,
27912 tree clobbers)
27913 {
27915 clobbers);
27917 clobbers);
27919 }
27921 /* Implements target vector targetm.asm.encode_section_info. This
27922 is not used by netware. */
27924 static void ATTRIBUTE_UNUSED
27926 {
27933 }
27935 /* Worker function for REVERSE_CONDITION. */
27937 enum rtx_code
27939 {
27943 }
27945 /* Output code to perform an x87 FP register move, from OPERANDS[1]
27946 to OPERANDS[0]. */
27950 {
27952 {
27955 {
27959 }
27963 }
27965 {
27969 else
27970 {
27971 /* There is no non-popping store to memory for XFmode.
27972 So if we need one, follow the store with a load. */
27975 else
27977 }
27978 }
27979 else
27981 }
27983 /* Output code to perform a conditional jump to LABEL, if C2 flag in
27984 FP status register is set. */
27986 void
27988 {
27990 rtx temp;
27995 {
28000 }
28001 else
28002 {
28007 }
28011 pc_rtx);
28016 }
28018 /* Output code to perform a log1p XFmode calculation. */
28021 {
28027 rtx test;
28033 XFmode));
28047 }
28049 /* Output code to perform a Newton-Rhapson approximation of a single precision
28050 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28053 {
28068 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28070 /* x0 = rcp(b) estimate */
28073 UNSPEC_RCP)));
28074 /* e0 = x0 * a */
28077 /* e1 = x0 * b */
28080 /* x1 = 2. - e1 */
28083 /* res = e0 * x1 */
28086 }
28088 /* Output code to perform a Newton-Rhapson approximation of a
28089 single precision floating point [reciprocal] square root. */
28093 {
28095 REAL_VALUE_TYPE r;
28110 {
28113 }
28115 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28116 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28118 /* x0 = rsqrt(a) estimate */
28121 UNSPEC_RSQRT)));
28123 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28125 {
28137 }
28139 /* e0 = x0 * a */
28142 /* e1 = e0 * x0 */
28146 /* e2 = e1 - 3. */
28153 /* e3 = -.5 * x0 */
28156 else
28157 /* e3 = -.5 * e0 */
28160 /* ret = e2 * e3 */
28163 }
28165 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28167 static void ATTRIBUTE_UNUSED
28169 tree decl)
28170 {
28171 /* With Binutils 2.15, the "@unwind" marker must be specified on
28172 every occurrence of the ".eh_frame" section, not just the first
28173 one. */
28176 {
28180 }
28182 }
28184 /* Return the mangling of TYPE if it is an extended fundamental type. */
28188 {
28196 {
28198 /* __float128 is "g". */
28201 /* "long double" or __float80 is "e". */
28205 }
28206 }
28208 /* For 32-bit code we can save PIC register setup by using
28209 __stack_chk_fail_local hidden function instead of calling
28210 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28211 register, so it is better to call __stack_chk_fail directly. */
28213 static tree
28215 {
28216 return TARGET_64BIT
28219 }
28221 /* Select a format to encode pointers in exception handling data. CODE
28222 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28223 true if the symbol may be affected by dynamic relocations.
28225 ??? All x86 object file formats are capable of representing this.
28226 After all, the relocation needed is the same as for the call insn.
28227 Whether or not a particular assembler allows us to enter such, I
28228 guess we'll have to see. */
28229 int
28231 {
28233 {
28240 }
28245 }
28246 \f
28247 /* Expand copysign from SIGN to the positive value ABS_VALUE
28248 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28249 the sign-bit. */
28250 static void
28252 {
28256 {
28259 {
28260 /* We need to generate a scalar mode mask in this case. */
28265 }
28266 }
28267 else
28273 }
28275 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28276 mask for masking out the sign-bit is stored in *SMASK, if that is
28277 non-null. */
28278 static rtx
28280 {
28287 {
28288 /* We need to generate a scalar mode mask in this case. */
28293 }
28301 }
28303 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28304 swapping the operands if SWAP_OPERANDS is true. The expanded
28305 code is a forward jump to a newly created label in case the
28306 comparison is true. The generated label rtx is returned. */
28307 static rtx
28310 {
28314 {
28318 }
28331 }
28333 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28334 using comparison code CODE. Operands are swapped for the comparison if
28335 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28336 static rtx
28339 {
28344 {
28348 }
28353 else
28358 }
28360 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28361 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28362 static rtx
28364 {
28365 REAL_VALUE_TYPE TWO52r;
28366 rtx TWO52;
28373 }
28375 /* Expand SSE sequence for computing lround from OP1 storing
28376 into OP0. */
28377 void
28379 {
28380 /* C code for the stuff we're doing below:
28381 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28382 return (long)tmp;
28383 */
28387 rtx adj;
28389 /* load nextafter (0.5, 0.0) */
28394 /* adj = copysign (0.5, op1) */
28398 /* adj = op1 + adj */
28401 /* op0 = (imode)adj */
28403 }
28405 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28406 into OPERAND0. */
28407 void
28409 {
28410 /* C code for the stuff we're doing below (for do_floor):
28411 xi = (long)op1;
28412 xi -= (double)xi > op1 ? 1 : 0;
28413 return xi;
28414 */
28419 /* reg = (long)op1 */
28423 /* freg = (double)reg */
28427 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28438 }
28440 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28441 result in OPERAND0. */
28442 void
28444 {
28445 /* C code for the stuff we're doing below:
28446 xa = fabs (operand1);
28447 if (!isless (xa, 2**52))
28448 return operand1;
28449 xa = xa + 2**52 - 2**52;
28450 return copysign (xa, operand1);
28451 */
28458 /* xa = abs (operand1) */
28461 /* if (!isless (xa, TWO52)) goto label; */
28474 }
28476 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28477 into OPERAND0. */
28478 void
28480 {
28481 /* C code for the stuff we expand below.
28482 double xa = fabs (x), x2;
28483 if (!isless (xa, TWO52))
28484 return x;
28485 xa = xa + TWO52 - TWO52;
28486 x2 = copysign (xa, x);
28487 Compensate. Floor:
28488 if (x2 > x)
28489 x2 -= 1;
28490 Compensate. Ceil:
28491 if (x2 < x)
28492 x2 -= -1;
28493 return x2;
28494 */
28500 /* Temporary for holding the result, initialized to the input
28501 operand to ease control flow. */
28505 /* xa = abs (operand1) */
28508 /* if (!isless (xa, TWO52)) goto label; */
28511 /* xa = xa + TWO52 - TWO52; */
28515 /* xa = copysign (xa, operand1) */
28518 /* generate 1.0 or -1.0 */
28523 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28527 /* We always need to subtract here to preserve signed zero. */
28536 }
28538 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28539 into OPERAND0. */
28540 void
28542 {
28543 /* C code for the stuff we expand below.
28544 double xa = fabs (x), x2;
28545 if (!isless (xa, TWO52))
28546 return x;
28547 x2 = (double)(long)x;
28548 Compensate. Floor:
28549 if (x2 > x)
28550 x2 -= 1;
28551 Compensate. Ceil:
28552 if (x2 < x)
28553 x2 += 1;
28554 if (HONOR_SIGNED_ZEROS (mode))
28555 return copysign (x2, x);
28556 return x2;
28557 */
28563 /* Temporary for holding the result, initialized to the input
28564 operand to ease control flow. */
28568 /* xa = abs (operand1) */
28571 /* if (!isless (xa, TWO52)) goto label; */
28574 /* xa = (double)(long)x */
28579 /* generate 1.0 */
28582 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28597 }
28599 /* Expand SSE sequence for computing round from OPERAND1 storing
28600 into OPERAND0. Sequence that works without relying on DImode truncation
28601 via cvttsd2siq that is only available on 64bit targets. */
28602 void
28604 {
28605 /* C code for the stuff we expand below.
28606 double xa = fabs (x), xa2, x2;
28607 if (!isless (xa, TWO52))
28608 return x;
28609 Using the absolute value and copying back sign makes
28610 -0.0 -> -0.0 correct.
28611 xa2 = xa + TWO52 - TWO52;
28612 Compensate.
28613 dxa = xa2 - xa;
28614 if (dxa <= -0.5)
28615 xa2 += 1;
28616 else if (dxa > 0.5)
28617 xa2 -= 1;
28618 x2 = copysign (xa2, x);
28619 return x2;
28620 */
28626 /* Temporary for holding the result, initialized to the input
28627 operand to ease control flow. */
28631 /* xa = abs (operand1) */
28634 /* if (!isless (xa, TWO52)) goto label; */
28637 /* xa2 = xa + TWO52 - TWO52; */
28641 /* dxa = xa2 - xa; */
28644 /* generate 0.5, 1.0 and -0.5 */
28650 /* Compensate. */
28652 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28657 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28663 /* res = copysign (xa2, operand1) */
28670 }
28672 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28673 into OPERAND0. */
28674 void
28676 {
28677 /* C code for SSE variant we expand below.
28678 double xa = fabs (x), x2;
28679 if (!isless (xa, TWO52))
28680 return x;
28681 x2 = (double)(long)x;
28682 if (HONOR_SIGNED_ZEROS (mode))
28683 return copysign (x2, x);
28684 return x2;
28685 */
28691 /* Temporary for holding the result, initialized to the input
28692 operand to ease control flow. */
28696 /* xa = abs (operand1) */
28699 /* if (!isless (xa, TWO52)) goto label; */
28702 /* x = (double)(long)x */
28714 }
28716 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28717 into OPERAND0. */
28718 void
28720 {
28724 /* C code for SSE variant we expand below.
28725 double xa = fabs (x), x2;
28726 if (!isless (xa, TWO52))
28727 return x;
28728 xa2 = xa + TWO52 - TWO52;
28729 Compensate:
28730 if (xa2 > xa)
28731 xa2 -= 1.0;
28732 x2 = copysign (xa2, x);
28733 return x2;
28734 */
28738 /* Temporary for holding the result, initialized to the input
28739 operand to ease control flow. */
28743 /* xa = abs (operand1) */
28746 /* if (!isless (xa, TWO52)) goto label; */
28749 /* res = xa + TWO52 - TWO52; */
28754 /* generate 1.0 */
28757 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28765 /* res = copysign (res, operand1) */
28772 }
28774 /* Expand SSE sequence for computing round from OPERAND1 storing
28775 into OPERAND0. */
28776 void
28778 {
28779 /* C code for the stuff we're doing below:
28780 double xa = fabs (x);
28781 if (!isless (xa, TWO52))
28782 return x;
28783 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28784 return copysign (xa, x);
28785 */
28791 /* Temporary for holding the result, initialized to the input
28792 operand to ease control flow. */
28800 /* load nextafter (0.5, 0.0) */
28805 /* xa = xa + 0.5 */
28809 /* xa = (double)(int64_t)xa */
28814 /* res = copysign (xa, operand1) */
28821 }
28822 \f
28824 /* Table of valid machine attributes. */
28826 {
28827 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
28828 /* Stdcall attribute says callee is responsible for popping arguments
28829 if they are not variable. */
28831 /* Fastcall attribute says callee is responsible for popping arguments
28832 if they are not variable. */
28834 /* Cdecl attribute says the callee is a normal C declaration */
28836 /* Regparm attribute specifies how many integer arguments are to be
28837 passed in registers. */
28839 /* Sseregparm attribute says we are using x86_64 calling conventions
28840 for FP arguments. */
28842 /* force_align_arg_pointer says this function realigns the stack at entry. */
28845 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28849 #endif
28852 #ifdef SUBTARGET_ATTRIBUTE_TABLE
28853 SUBTARGET_ATTRIBUTE_TABLE,
28854 #endif
28855 /* ms_abi and sysv_abi calling convention function attributes. */
28859 /* End element. */
28861 };
28863 /* Implement targetm.vectorize.builtin_vectorization_cost. */
28864 static int
28866 {
28867 /* If the branch of the runtime test is taken - i.e. - the vectorized
28868 version is skipped - this incurs a misprediction cost (because the
28869 vectorized version is expected to be the fall-through). So we subtract
28870 the latency of a mispredicted branch from the costs that are incured
28871 when the vectorized version is executed.
28873 TODO: The values in individual target tables have to be tuned or new
28874 fields may be needed. For eg. on K8, the default branch path is the
28875 not-taken path. If the taken path is predicted correctly, the minimum
28876 penalty of going down the taken-path is 1 cycle. If the taken-path is
28877 not predicted correctly, then the minimum penalty is 10 cycles. */
28880 {
28882 }
28883 else
28885 }
28887 /* Implement targetm.vectorize.builtin_vec_perm. */
28889 static tree
28891 {
28899 {
28906 get_di:
28917 get_si:
28936 }
28943 }
28945 /* Return a vector mode with twice as many elements as VMODE. */
28946 /* ??? Consider moving this to a table generated by genmodes.c. */
28948 static enum machine_mode
28950 {
28952 {
28975 }
28976 }
28978 /* Construct (set target (vec_select op0 (parallel perm))) and
28979 return true if that's a valid instruction in the active ISA. */
28981 static bool
28983 {
28996 {
28999 }
29001 }
29003 /* Similar, but generate a vec_concat from op0 and op1 as well. */
29005 static bool
29008 {
29010 rtx x;
29015 }
29017 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29018 in terms of blendp[sd] / pblendw / pblendvb. */
29020 static bool
29022 {
29032 /* This is a blend, not a permute. Elements must stay in their
29033 respective lanes. */
29035 {
29039 }
29044 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
29045 decision should be extracted elsewhere, so that we only try that
29046 sequence once all budget==3 options have been tried. */
29048 /* For bytes, see if bytes move in pairs so we can use pblendw with
29049 an immediate argument, rather than pblendvb with a vector argument. */
29051 {
29057 {
29068 }
29069 }
29077 {
29101 do_subreg:
29110 }
29112 /* This matches five different patterns with the different modes. */
29118 }
29120 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29121 in terms of the variable form of vpermilps.
29123 Note that we will have already failed the immediate input vpermilps,
29124 which requires that the high and low part shuffle be identical; the
29125 variable form doesn't require that. */
29127 static bool
29129 {
29136 /* We can only permute within the 128-bit lane. */
29138 {
29142 }
29148 {
29151 /* Within each 128-bit lane, the elements of op0 are numbered
29152 from 0 and the elements of op1 are numbered from 4. */
29159 }
29166 }
29168 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29169 in terms of pshufb or vpperm. */
29171 static bool
29173 {
29189 {
29193 }
29202 else
29203 {
29206 }
29209 }
29211 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
29212 in a single instruction. */
29214 static bool
29216 {
29220 /* Check plain VEC_SELECT first, because AVX has instructions that could
29221 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
29222 input where SEL+CONCAT may not. */
29224 {
29228 /* There are plenty of patterns in sse.md that are written for
29229 SEL+CONCAT and are not replicated for a single op. Perhaps
29230 that should be changed, to avoid the nastiness here. */
29232 /* Recognize interleave style patterns, which means incrementing
29233 every other permutation operand. */
29235 {
29238 }
29242 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
29244 {
29247 {
29250 }
29254 }
29255 }
29257 /* Finally, try the fully general two operand permute. */
29261 /* Recognize interleave style patterns with reversed operands. */
29263 {
29265 {
29269 else
29272 }
29276 }
29278 /* Try the SSE4.1 blend variable merge instructions. */
29282 /* Try one of the AVX vpermil variable permutations. */
29286 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
29291 }
29293 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29294 in terms of a pair of pshuflw + pshufhw instructions. */
29296 static bool
29298 {
29306 /* The two permutations only operate in 64-bit lanes. */
29317 /* Emit the pshuflw. */
29324 /* Emit the pshufhw. */
29332 }
29334 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29335 the permutation using the SSSE3 palignr instruction. This succeeds
29336 when all of the elements in PERM fit within one vector and we merely
29337 need to shift them down so that a single vector permutation has a
29338 chance to succeed. */
29340 static bool
29342 {
29346 rtx shift;
29348 /* Even with AVX, palignr only operates on 128-bit vectors. */
29354 {
29360 }
29364 /* Given that we have SSSE3, we know we'll be able to implement the
29365 single operand permutation after the palignr with pshufb. */
29378 {
29383 }
29385 /* Test for the degenerate case where the alignment by itself
29386 produces the desired permutation. */
29394 }
29396 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29397 a two vector permutation into a single vector permutation by using
29398 an interleave operation to merge the vectors. */
29400 static bool
29402 {
29407 rtx seq;
29413 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
29414 lanes. We can use similar techniques with the vperm2f128 instruction,
29415 but it requires slightly different logic. */
29419 /* Examine from whence the elements come. */
29424 /* Split the two input vectors into 4 halves. */
29433 /* If the elements from the low halves use interleave low, and similarly
29434 for interleave high. If the elements are from mis-matched halves, we
29435 can use shufps for V4SF/V4SI or do a DImode shuffle. */
29437 {
29439 {
29444 }
29445 }
29447 {
29449 {
29454 }
29455 }
29457 {
29459 {
29464 }
29466 {
29471 }
29472 }
29474 {
29476 {
29481 }
29483 {
29488 }
29489 }
29490 else
29493 /* Use the remapping array set up above to move the elements from their
29494 swizzled locations into their final destinations. */
29497 {
29501 }
29506 /* Test if the final remap can be done with a single insn. For V4SFmode or
29507 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
29517 {
29521 }
29528 }
29530 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
29531 permutation with two pshufb insns and an ior. We should have already
29532 failed all two instruction sequences. */
29534 static bool
29536 {
29547 /* Generate two permutation masks. If the required element is within
29548 the given vector it is shuffled into the proper lane. If the required
29549 element is in the other vector, force a zero into the lane by setting
29550 bit 7 in the permutation mask. */
29553 {
29560 {
29563 }
29564 }
29584 }
29586 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
29587 and extract-odd permutations. */
29589 static bool
29591 {
29595 {
29600 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
29604 /* Now an unpck[lh]pd will produce the result required. */
29607 else
29613 {
29623 /* Shuffle within the 128-bit lanes to produce:
29624 { 0 2 1 3 4 6 5 7 } and { 8 a 9 b c e d f }. */
29628 /* Shuffle the lanes around to produce:
29629 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
29633 /* Now a vpermil2p will produce the result required. */
29634 /* ??? The vpermil2p requires a vector constant. Another option
29635 is a unpck[lh]ps to merge the two vectors to produce
29636 { 0 4 2 6 8 c a e } or { 1 5 3 7 9 d b f }. Then use another
29637 vpermilps to get the elements into the final order. */
29642 }
29649 /* These are always directly implementable by expand_vec_perm_1. */
29655 else
29656 {
29657 /* We need 2*log2(N)-1 operations to achieve odd/even
29658 with interleave. */
29667 else
29670 }
29676 else
29677 {
29689 else
29692 }
29697 }
29700 }
29702 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
29703 extract-even and extract-odd permutations. */
29705 static bool
29707 {
29719 }
29721 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
29722 permutations. We assume that expand_vec_perm_1 has already failed. */
29724 static bool
29726 {
29734 {
29737 /* These are special-cased in sse.md so that we can optionally
29738 use the vbroadcast instruction. They expand to two insns
29739 if the input happens to be in a register. */
29746 /* These are always implementable using standard shuffle patterns. */
29751 /* These can be implemented via interleave. We save one insn by
29752 stopping once we have promoted to V4SImode and then use pshufd. */
29753 do
29754 {
29758 {
29761 }
29767 }
29777 }
29778 }
29780 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
29781 broadcast permutations. */
29783 static bool
29785 {
29797 }
29799 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
29800 With all of the interface bits taken care of, perform the expansion
29801 in D and return true on success. */
29803 static bool
29805 {
29806 /* Try a single instruction expansion. */
29810 /* Try sequences of two instructions. */
29824 /* Try sequences of three instructions. */
29829 /* ??? Look for narrow permutations whose element orderings would
29830 allow the promotion to a wider mode. */
29832 /* ??? Look for sequences of interleave or a wider permute that place
29833 the data into the correct lanes for a half-vector shuffle like
29834 pshuf[lh]w or vpermilps. */
29836 /* ??? Look for sequences of interleave that produce the desired results.
29837 The combinatorics of punpck[lh] get pretty ugly... */
29843 }
29845 /* Extract the values from the vector CST into the permutation array in D.
29846 Return 0 on error, 1 if all values from the permutation come from the
29847 first vector, 2 if all values from the second vector, and 3 otherwise. */
29849 static int
29851 {
29857 {
29868 }
29871 /* For all elements from second vector, fold the elements to first. */
29877 }
29879 static rtx
29881 {
29895 {
29899 }
29902 {
29912 {
29918 }
29920 /* The elements of PERM do not suggest that only the first operand
29921 is used, but both operands are identical. Allow easier matching
29922 of the permutation by folding the permutation into the single
29923 input vector. */
29924 {
29929 }
29930 /* FALLTHRU */
29943 }
29949 /* For compiler generated permutations, we should never got here, because
29950 the compiler should also be checking the ok hook. But since this is a
29951 builtin the user has access too, so don't abort. */
29953 {
29976 }
29977 exit_error:
29979 }
29981 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
29983 static bool
29985 {
29994 /* Given sufficient ISA support we can just return true here
29995 for selected vector modes. */
29997 {
29998 /* All implementable with a single vpperm insn. */
30001 /* All implementable with 2 pshufb + 1 ior. */
30004 /* All implementable with shufpd or unpck[lh]pd. */
30007 }
30011 /* This hook is cannot be called in response to something that the
30012 user does (unlike the builtin expander) so we shouldn't ever see
30013 an error generated from the extract. */
30017 /* Implementable with shufps or pshufd. */
30021 /* Otherwise we have to go through the motions and see if we can
30022 figure out how to generate the requested permutation. */
30033 }
30035 void
30037 {
30051 /* We'll either be able to implement the permutation directly... */
30055 /* ... or we use the special-case patterns. */
30057 }
30058 \f
30059 /* This function returns the calling abi specific va_list type node.
30060 It returns the FNDECL specific va_list type. */
30062 tree
30064 {
30071 else
30073 }
30075 /* Returns the canonical va_list type specified by TYPE. If there
30076 is no valid TYPE provided, it return NULL_TREE. */
30078 tree
30080 {
30083 /* Resolve references and pointers to va_list type. */
30090 {
30095 {
30096 /* If va_list is an array type, the argument may have decayed
30097 to a pointer type, e.g. by being passed to another function.
30098 In that case, unwrap both types so that we can compare the
30099 underlying records. */
30102 {
30105 }
30106 }
30113 {
30114 /* If va_list is an array type, the argument may have decayed
30115 to a pointer type, e.g. by being passed to another function.
30116 In that case, unwrap both types so that we can compare the
30117 underlying records. */
30120 {
30123 }
30124 }
30131 {
30132 /* If va_list is an array type, the argument may have decayed
30133 to a pointer type, e.g. by being passed to another function.
30134 In that case, unwrap both types so that we can compare the
30135 underlying records. */
30138 {
30141 }
30142 }
30146 }
30148 }
30150 /* Iterate through the target-specific builtin types for va_list.
30151 IDX denotes the iterator, *PTREE is set to the result type of
30152 the va_list builtin, and *PNAME to its internal type.
30153 Returns zero if there is no element for this index, otherwise
30154 IDX should be increased upon the next call.
30155 Note, do not iterate a base builtin's name like __builtin_va_list.
30156 Used from c_common_nodes_and_builtins. */
30158 int
30160 {
30174 }
30176 }
30178 /* Initialize the GCC target structure. */
30179 #undef TARGET_RETURN_IN_MEMORY
30180 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30182 #undef TARGET_LEGITIMIZE_ADDRESS
30183 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30185 #undef TARGET_ATTRIBUTE_TABLE
30186 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30187 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30188 # undef TARGET_MERGE_DECL_ATTRIBUTES
30189 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30190 #endif
30192 #undef TARGET_COMP_TYPE_ATTRIBUTES
30193 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30195 #undef TARGET_INIT_BUILTINS
30196 #define TARGET_INIT_BUILTINS ix86_init_builtins
30197 #undef TARGET_BUILTIN_DECL
30198 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30199 #undef TARGET_EXPAND_BUILTIN
30200 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30202 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30203 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30204 ix86_builtin_vectorized_function
30206 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30207 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30209 #undef TARGET_BUILTIN_RECIPROCAL
30210 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30212 #undef TARGET_ASM_FUNCTION_EPILOGUE
30213 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30215 #undef TARGET_ENCODE_SECTION_INFO
30216 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30217 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30218 #else
30219 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30220 #endif
30222 #undef TARGET_ASM_OPEN_PAREN
30224 #undef TARGET_ASM_CLOSE_PAREN
30227 #undef TARGET_ASM_BYTE_OP
30228 #define TARGET_ASM_BYTE_OP ASM_BYTE
30230 #undef TARGET_ASM_ALIGNED_HI_OP
30231 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30232 #undef TARGET_ASM_ALIGNED_SI_OP
30233 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30234 #ifdef ASM_QUAD
30235 #undef TARGET_ASM_ALIGNED_DI_OP
30236 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30237 #endif
30239 #undef TARGET_ASM_UNALIGNED_HI_OP
30240 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30241 #undef TARGET_ASM_UNALIGNED_SI_OP
30242 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30243 #undef TARGET_ASM_UNALIGNED_DI_OP
30244 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30246 #undef TARGET_SCHED_ADJUST_COST
30247 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30248 #undef TARGET_SCHED_ISSUE_RATE
30249 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30250 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30251 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30252 ia32_multipass_dfa_lookahead
30254 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30255 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30257 #ifdef HAVE_AS_TLS
30258 #undef TARGET_HAVE_TLS
30259 #define TARGET_HAVE_TLS true
30260 #endif
30261 #undef TARGET_CANNOT_FORCE_CONST_MEM
30262 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30263 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30264 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30266 #undef TARGET_DELEGITIMIZE_ADDRESS
30267 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30269 #undef TARGET_MS_BITFIELD_LAYOUT_P
30270 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30272 #if TARGET_MACHO
30273 #undef TARGET_BINDS_LOCAL_P
30274 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30275 #endif
30276 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30277 #undef TARGET_BINDS_LOCAL_P
30278 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30279 #endif
30281 #undef TARGET_ASM_OUTPUT_MI_THUNK
30282 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30283 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30284 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30286 #undef TARGET_ASM_FILE_START
30287 #define TARGET_ASM_FILE_START x86_file_start
30289 #undef TARGET_DEFAULT_TARGET_FLAGS
30290 #define TARGET_DEFAULT_TARGET_FLAGS \
30291 (TARGET_DEFAULT \
30292 | TARGET_SUBTARGET_DEFAULT \
30293 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT \
30294 | MASK_FUSED_MADD)
30296 #undef TARGET_HANDLE_OPTION
30297 #define TARGET_HANDLE_OPTION ix86_handle_option
30299 #undef TARGET_RTX_COSTS
30300 #define TARGET_RTX_COSTS ix86_rtx_costs
30301 #undef TARGET_ADDRESS_COST
30302 #define TARGET_ADDRESS_COST ix86_address_cost
30304 #undef TARGET_FIXED_CONDITION_CODE_REGS
30305 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30306 #undef TARGET_CC_MODES_COMPATIBLE
30307 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30309 #undef TARGET_MACHINE_DEPENDENT_REORG
30310 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30312 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30313 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30315 #undef TARGET_BUILD_BUILTIN_VA_LIST
30316 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30318 #undef TARGET_FN_ABI_VA_LIST
30319 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30321 #undef TARGET_CANONICAL_VA_LIST_TYPE
30322 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30324 #undef TARGET_EXPAND_BUILTIN_VA_START
30325 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30327 #undef TARGET_MD_ASM_CLOBBERS
30328 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30330 #undef TARGET_PROMOTE_PROTOTYPES
30331 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30332 #undef TARGET_STRUCT_VALUE_RTX
30333 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30334 #undef TARGET_SETUP_INCOMING_VARARGS
30335 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30336 #undef TARGET_MUST_PASS_IN_STACK
30337 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30338 #undef TARGET_PASS_BY_REFERENCE
30339 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30340 #undef TARGET_INTERNAL_ARG_POINTER
30341 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30342 #undef TARGET_UPDATE_STACK_BOUNDARY
30343 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30344 #undef TARGET_GET_DRAP_RTX
30345 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30346 #undef TARGET_STRICT_ARGUMENT_NAMING
30347 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30348 #undef TARGET_STATIC_CHAIN
30349 #define TARGET_STATIC_CHAIN ix86_static_chain
30350 #undef TARGET_TRAMPOLINE_INIT
30351 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30353 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30354 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30356 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30357 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30359 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30360 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30362 #undef TARGET_C_MODE_FOR_SUFFIX
30363 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30365 #ifdef HAVE_AS_TLS
30366 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30367 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30368 #endif
30370 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30371 #undef TARGET_INSERT_ATTRIBUTES
30372 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30373 #endif
30375 #undef TARGET_MANGLE_TYPE
30376 #define TARGET_MANGLE_TYPE ix86_mangle_type
30378 #undef TARGET_STACK_PROTECT_FAIL
30379 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30381 #undef TARGET_FUNCTION_VALUE
30382 #define TARGET_FUNCTION_VALUE ix86_function_value
30384 #undef TARGET_SECONDARY_RELOAD
30385 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30387 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30388 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
30389 ix86_builtin_vectorization_cost
30390 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
30391 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
30392 ix86_vectorize_builtin_vec_perm
30393 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
30394 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
30395 ix86_vectorize_builtin_vec_perm_ok
30397 #undef TARGET_SET_CURRENT_FUNCTION
30398 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30400 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30401 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30403 #undef TARGET_OPTION_SAVE
30404 #define TARGET_OPTION_SAVE ix86_function_specific_save
30406 #undef TARGET_OPTION_RESTORE
30407 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30409 #undef TARGET_OPTION_PRINT
30410 #define TARGET_OPTION_PRINT ix86_function_specific_print
30412 #undef TARGET_CAN_INLINE_P
30413 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30415 #undef TARGET_EXPAND_TO_RTL_HOOK
30416 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30418 #undef TARGET_LEGITIMATE_ADDRESS_P
30419 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30421 #undef TARGET_IRA_COVER_CLASSES
30422 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30424 #undef TARGET_FRAME_POINTER_REQUIRED
30425 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30427 #undef TARGET_CAN_ELIMINATE
30428 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30431 \f