1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Middle-to-low level generation of rtx code and insns.
25 This file contains support functions for creating rtl expressions
26 and manipulating them in the doubly-linked chain of insns.
28 The patterns of the insns are created by machine-dependent
29 routines in insn-emit.c, which is generated automatically from
30 the machine description. These routines make the individual rtx's
31 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
32 which are automatically generated from rtl.def; what is machine
33 dependent is the kind of rtx's they make and what arguments they
38 #include "coretypes.h"
48 #include "hard-reg-set.h"
50 #include "insn-config.h"
53 #include "fixed-value.h"
55 #include "basic-block.h"
58 #include "langhooks.h"
59 #include "tree-pass.h"
62 /* Commonly used modes. */
64 enum machine_mode byte_mode
; /* Mode whose width is BITS_PER_UNIT. */
65 enum machine_mode word_mode
; /* Mode whose width is BITS_PER_WORD. */
66 enum machine_mode double_mode
; /* Mode whose width is DOUBLE_TYPE_SIZE. */
67 enum machine_mode ptr_mode
; /* Mode whose width is POINTER_SIZE. */
70 /* This is *not* reset after each function. It gives each CODE_LABEL
71 in the entire compilation a unique label number. */
73 static GTY(()) int label_num
= 1;
75 /* Nonzero means do not generate NOTEs for source line numbers. */
77 static int no_line_numbers
;
79 /* Commonly used rtx's, so that we only need space for one copy.
80 These are initialized once for the entire compilation.
81 All of these are unique; no other rtx-object will be equal to any
84 rtx global_rtl
[GR_MAX
];
86 /* Commonly used RTL for hard registers. These objects are not necessarily
87 unique, so we allocate them separately from global_rtl. They are
88 initialized once per compilation unit, then copied into regno_reg_rtx
89 at the beginning of each function. */
90 static GTY(()) rtx static_regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
92 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
93 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
94 record a copy of const[012]_rtx. */
96 rtx const_tiny_rtx
[3][(int) MAX_MACHINE_MODE
];
100 REAL_VALUE_TYPE dconst0
;
101 REAL_VALUE_TYPE dconst1
;
102 REAL_VALUE_TYPE dconst2
;
103 REAL_VALUE_TYPE dconst3
;
104 REAL_VALUE_TYPE dconst10
;
105 REAL_VALUE_TYPE dconstm1
;
106 REAL_VALUE_TYPE dconstm2
;
107 REAL_VALUE_TYPE dconsthalf
;
108 REAL_VALUE_TYPE dconstthird
;
109 REAL_VALUE_TYPE dconstsqrt2
;
110 REAL_VALUE_TYPE dconste
;
112 /* Record fixed-point constant 0 and 1. */
113 FIXED_VALUE_TYPE fconst0
[MAX_FCONST0
];
114 FIXED_VALUE_TYPE fconst1
[MAX_FCONST1
];
116 /* All references to the following fixed hard registers go through
117 these unique rtl objects. On machines where the frame-pointer and
118 arg-pointer are the same register, they use the same unique object.
120 After register allocation, other rtl objects which used to be pseudo-regs
121 may be clobbered to refer to the frame-pointer register.
122 But references that were originally to the frame-pointer can be
123 distinguished from the others because they contain frame_pointer_rtx.
125 When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little
126 tricky: until register elimination has taken place hard_frame_pointer_rtx
127 should be used if it is being set, and frame_pointer_rtx otherwise. After
128 register elimination hard_frame_pointer_rtx should always be used.
129 On machines where the two registers are same (most) then these are the
132 In an inline procedure, the stack and frame pointer rtxs may not be
133 used for anything else. */
134 rtx static_chain_rtx
; /* (REG:Pmode STATIC_CHAIN_REGNUM) */
135 rtx static_chain_incoming_rtx
; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */
136 rtx pic_offset_table_rtx
; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */
138 /* This is used to implement __builtin_return_address for some machines.
139 See for instance the MIPS port. */
140 rtx return_address_pointer_rtx
; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */
142 /* We make one copy of (const_int C) where C is in
143 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
144 to save space during the compilation and simplify comparisons of
147 rtx const_int_rtx
[MAX_SAVED_CONST_INT
* 2 + 1];
149 /* A hash table storing CONST_INTs whose absolute value is greater
150 than MAX_SAVED_CONST_INT. */
152 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def
)))
153 htab_t const_int_htab
;
155 /* A hash table storing memory attribute structures. */
156 static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs
)))
157 htab_t mem_attrs_htab
;
159 /* A hash table storing register attribute structures. */
160 static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs
)))
161 htab_t reg_attrs_htab
;
163 /* A hash table storing all CONST_DOUBLEs. */
164 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def
)))
165 htab_t const_double_htab
;
167 #define first_insn (cfun->emit->x_first_insn)
168 #define last_insn (cfun->emit->x_last_insn)
169 #define cur_insn_uid (cfun->emit->x_cur_insn_uid)
170 #define last_location (cfun->emit->x_last_location)
171 #define first_label_num (cfun->emit->x_first_label_num)
173 static rtx
make_call_insn_raw (rtx
);
174 static rtx
change_address_1 (rtx
, enum machine_mode
, rtx
, int);
175 static void set_used_decls (tree
);
176 static void mark_label_nuses (rtx
);
177 static hashval_t
const_int_htab_hash (const void *);
178 static int const_int_htab_eq (const void *, const void *);
179 static hashval_t
const_double_htab_hash (const void *);
180 static int const_double_htab_eq (const void *, const void *);
181 static rtx
lookup_const_double (rtx
);
182 static hashval_t
mem_attrs_htab_hash (const void *);
183 static int mem_attrs_htab_eq (const void *, const void *);
184 static mem_attrs
*get_mem_attrs (alias_set_type
, tree
, rtx
, rtx
, unsigned int,
186 static hashval_t
reg_attrs_htab_hash (const void *);
187 static int reg_attrs_htab_eq (const void *, const void *);
188 static reg_attrs
*get_reg_attrs (tree
, int);
189 static tree
component_ref_for_mem_expr (tree
);
190 static rtx
gen_const_vector (enum machine_mode
, int);
191 static void copy_rtx_if_shared_1 (rtx
*orig
);
193 /* Probability of the conditional branch currently proceeded by try_split.
194 Set to -1 otherwise. */
195 int split_branch_probability
= -1;
197 /* Returns a hash code for X (which is a really a CONST_INT). */
200 const_int_htab_hash (const void *x
)
202 return (hashval_t
) INTVAL ((const_rtx
) x
);
205 /* Returns nonzero if the value represented by X (which is really a
206 CONST_INT) is the same as that given by Y (which is really a
210 const_int_htab_eq (const void *x
, const void *y
)
212 return (INTVAL ((const_rtx
) x
) == *((const HOST_WIDE_INT
*) y
));
215 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
217 const_double_htab_hash (const void *x
)
219 const_rtx
const value
= (const_rtx
) x
;
222 if (GET_MODE (value
) == VOIDmode
)
223 h
= CONST_DOUBLE_LOW (value
) ^ CONST_DOUBLE_HIGH (value
);
226 h
= real_hash (CONST_DOUBLE_REAL_VALUE (value
));
227 /* MODE is used in the comparison, so it should be in the hash. */
228 h
^= GET_MODE (value
);
233 /* Returns nonzero if the value represented by X (really a ...)
234 is the same as that represented by Y (really a ...) */
236 const_double_htab_eq (const void *x
, const void *y
)
238 const_rtx
const a
= (const_rtx
)x
, b
= (const_rtx
)y
;
240 if (GET_MODE (a
) != GET_MODE (b
))
242 if (GET_MODE (a
) == VOIDmode
)
243 return (CONST_DOUBLE_LOW (a
) == CONST_DOUBLE_LOW (b
)
244 && CONST_DOUBLE_HIGH (a
) == CONST_DOUBLE_HIGH (b
));
246 return real_identical (CONST_DOUBLE_REAL_VALUE (a
),
247 CONST_DOUBLE_REAL_VALUE (b
));
250 /* Returns a hash code for X (which is a really a mem_attrs *). */
253 mem_attrs_htab_hash (const void *x
)
255 const mem_attrs
*const p
= (const mem_attrs
*) x
;
257 return (p
->alias
^ (p
->align
* 1000)
258 ^ ((p
->offset
? INTVAL (p
->offset
) : 0) * 50000)
259 ^ ((p
->size
? INTVAL (p
->size
) : 0) * 2500000)
260 ^ (size_t) iterative_hash_expr (p
->expr
, 0));
263 /* Returns nonzero if the value represented by X (which is really a
264 mem_attrs *) is the same as that given by Y (which is also really a
268 mem_attrs_htab_eq (const void *x
, const void *y
)
270 const mem_attrs
*const p
= (const mem_attrs
*) x
;
271 const mem_attrs
*const q
= (const mem_attrs
*) y
;
273 return (p
->alias
== q
->alias
&& p
->offset
== q
->offset
274 && p
->size
== q
->size
&& p
->align
== q
->align
275 && (p
->expr
== q
->expr
276 || (p
->expr
!= NULL_TREE
&& q
->expr
!= NULL_TREE
277 && operand_equal_p (p
->expr
, q
->expr
, 0))));
280 /* Allocate a new mem_attrs structure and insert it into the hash table if
281 one identical to it is not already in the table. We are doing this for
285 get_mem_attrs (alias_set_type alias
, tree expr
, rtx offset
, rtx size
,
286 unsigned int align
, enum machine_mode mode
)
291 /* If everything is the default, we can just return zero.
292 This must match what the corresponding MEM_* macros return when the
293 field is not present. */
294 if (alias
== 0 && expr
== 0 && offset
== 0
296 || (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) == INTVAL (size
)))
297 && (STRICT_ALIGNMENT
&& mode
!= BLKmode
298 ? align
== GET_MODE_ALIGNMENT (mode
) : align
== BITS_PER_UNIT
))
303 attrs
.offset
= offset
;
307 slot
= htab_find_slot (mem_attrs_htab
, &attrs
, INSERT
);
310 *slot
= ggc_alloc (sizeof (mem_attrs
));
311 memcpy (*slot
, &attrs
, sizeof (mem_attrs
));
317 /* Returns a hash code for X (which is a really a reg_attrs *). */
320 reg_attrs_htab_hash (const void *x
)
322 const reg_attrs
*const p
= (const reg_attrs
*) x
;
324 return ((p
->offset
* 1000) ^ (long) p
->decl
);
327 /* Returns nonzero if the value represented by X (which is really a
328 reg_attrs *) is the same as that given by Y (which is also really a
332 reg_attrs_htab_eq (const void *x
, const void *y
)
334 const reg_attrs
*const p
= (const reg_attrs
*) x
;
335 const reg_attrs
*const q
= (const reg_attrs
*) y
;
337 return (p
->decl
== q
->decl
&& p
->offset
== q
->offset
);
339 /* Allocate a new reg_attrs structure and insert it into the hash table if
340 one identical to it is not already in the table. We are doing this for
344 get_reg_attrs (tree decl
, int offset
)
349 /* If everything is the default, we can just return zero. */
350 if (decl
== 0 && offset
== 0)
354 attrs
.offset
= offset
;
356 slot
= htab_find_slot (reg_attrs_htab
, &attrs
, INSERT
);
359 *slot
= ggc_alloc (sizeof (reg_attrs
));
360 memcpy (*slot
, &attrs
, sizeof (reg_attrs
));
368 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule
374 rtx x
= gen_rtx_ASM_INPUT (VOIDmode
, "");
375 MEM_VOLATILE_P (x
) = true;
381 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
382 don't attempt to share with the various global pieces of rtl (such as
383 frame_pointer_rtx). */
386 gen_raw_REG (enum machine_mode mode
, int regno
)
388 rtx x
= gen_rtx_raw_REG (mode
, regno
);
389 ORIGINAL_REGNO (x
) = regno
;
393 /* There are some RTL codes that require special attention; the generation
394 functions do the raw handling. If you add to this list, modify
395 special_rtx in gengenrtl.c as well. */
398 gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED
, HOST_WIDE_INT arg
)
402 if (arg
>= - MAX_SAVED_CONST_INT
&& arg
<= MAX_SAVED_CONST_INT
)
403 return const_int_rtx
[arg
+ MAX_SAVED_CONST_INT
];
405 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
406 if (const_true_rtx
&& arg
== STORE_FLAG_VALUE
)
407 return const_true_rtx
;
410 /* Look up the CONST_INT in the hash table. */
411 slot
= htab_find_slot_with_hash (const_int_htab
, &arg
,
412 (hashval_t
) arg
, INSERT
);
414 *slot
= gen_rtx_raw_CONST_INT (VOIDmode
, arg
);
420 gen_int_mode (HOST_WIDE_INT c
, enum machine_mode mode
)
422 return GEN_INT (trunc_int_for_mode (c
, mode
));
425 /* CONST_DOUBLEs might be created from pairs of integers, or from
426 REAL_VALUE_TYPEs. Also, their length is known only at run time,
427 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
429 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
430 hash table. If so, return its counterpart; otherwise add it
431 to the hash table and return it. */
433 lookup_const_double (rtx real
)
435 void **slot
= htab_find_slot (const_double_htab
, real
, INSERT
);
442 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
443 VALUE in mode MODE. */
445 const_double_from_real_value (REAL_VALUE_TYPE value
, enum machine_mode mode
)
447 rtx real
= rtx_alloc (CONST_DOUBLE
);
448 PUT_MODE (real
, mode
);
452 return lookup_const_double (real
);
455 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
456 of ints: I0 is the low-order word and I1 is the high-order word.
457 Do not use this routine for non-integer modes; convert to
458 REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */
461 immed_double_const (HOST_WIDE_INT i0
, HOST_WIDE_INT i1
, enum machine_mode mode
)
466 /* There are the following cases (note that there are no modes with
467 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT):
469 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
471 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of
472 the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only
473 from copies of the sign bit, and sign of i0 and i1 are the same), then
474 we return a CONST_INT for i0.
475 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
476 if (mode
!= VOIDmode
)
478 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
479 || GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
480 /* We can get a 0 for an error mark. */
481 || GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
482 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
);
484 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
485 return gen_int_mode (i0
, mode
);
487 gcc_assert (GET_MODE_BITSIZE (mode
) == 2 * HOST_BITS_PER_WIDE_INT
);
490 /* If this integer fits in one word, return a CONST_INT. */
491 if ((i1
== 0 && i0
>= 0) || (i1
== ~0 && i0
< 0))
494 /* We use VOIDmode for integers. */
495 value
= rtx_alloc (CONST_DOUBLE
);
496 PUT_MODE (value
, VOIDmode
);
498 CONST_DOUBLE_LOW (value
) = i0
;
499 CONST_DOUBLE_HIGH (value
) = i1
;
501 for (i
= 2; i
< (sizeof CONST_DOUBLE_FORMAT
- 1); i
++)
502 XWINT (value
, i
) = 0;
504 return lookup_const_double (value
);
508 gen_rtx_REG (enum machine_mode mode
, unsigned int regno
)
510 /* In case the MD file explicitly references the frame pointer, have
511 all such references point to the same frame pointer. This is
512 used during frame pointer elimination to distinguish the explicit
513 references to these registers from pseudos that happened to be
516 If we have eliminated the frame pointer or arg pointer, we will
517 be using it as a normal register, for example as a spill
518 register. In such cases, we might be accessing it in a mode that
519 is not Pmode and therefore cannot use the pre-allocated rtx.
521 Also don't do this when we are making new REGs in reload, since
522 we don't want to get confused with the real pointers. */
524 if (mode
== Pmode
&& !reload_in_progress
)
526 if (regno
== FRAME_POINTER_REGNUM
527 && (!reload_completed
|| frame_pointer_needed
))
528 return frame_pointer_rtx
;
529 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
530 if (regno
== HARD_FRAME_POINTER_REGNUM
531 && (!reload_completed
|| frame_pointer_needed
))
532 return hard_frame_pointer_rtx
;
534 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
535 if (regno
== ARG_POINTER_REGNUM
)
536 return arg_pointer_rtx
;
538 #ifdef RETURN_ADDRESS_POINTER_REGNUM
539 if (regno
== RETURN_ADDRESS_POINTER_REGNUM
)
540 return return_address_pointer_rtx
;
542 if (regno
== (unsigned) PIC_OFFSET_TABLE_REGNUM
543 && fixed_regs
[PIC_OFFSET_TABLE_REGNUM
])
544 return pic_offset_table_rtx
;
545 if (regno
== STACK_POINTER_REGNUM
)
546 return stack_pointer_rtx
;
550 /* If the per-function register table has been set up, try to re-use
551 an existing entry in that table to avoid useless generation of RTL.
553 This code is disabled for now until we can fix the various backends
554 which depend on having non-shared hard registers in some cases. Long
555 term we want to re-enable this code as it can significantly cut down
556 on the amount of useless RTL that gets generated.
558 We'll also need to fix some code that runs after reload that wants to
559 set ORIGINAL_REGNO. */
564 && regno
< FIRST_PSEUDO_REGISTER
565 && reg_raw_mode
[regno
] == mode
)
566 return regno_reg_rtx
[regno
];
569 return gen_raw_REG (mode
, regno
);
573 gen_rtx_MEM (enum machine_mode mode
, rtx addr
)
575 rtx rt
= gen_rtx_raw_MEM (mode
, addr
);
577 /* This field is not cleared by the mere allocation of the rtx, so
584 /* Generate a memory referring to non-trapping constant memory. */
587 gen_const_mem (enum machine_mode mode
, rtx addr
)
589 rtx mem
= gen_rtx_MEM (mode
, addr
);
590 MEM_READONLY_P (mem
) = 1;
591 MEM_NOTRAP_P (mem
) = 1;
595 /* Generate a MEM referring to fixed portions of the frame, e.g., register
599 gen_frame_mem (enum machine_mode mode
, rtx addr
)
601 rtx mem
= gen_rtx_MEM (mode
, addr
);
602 MEM_NOTRAP_P (mem
) = 1;
603 set_mem_alias_set (mem
, get_frame_alias_set ());
607 /* Generate a MEM referring to a temporary use of the stack, not part
608 of the fixed stack frame. For example, something which is pushed
609 by a target splitter. */
611 gen_tmp_stack_mem (enum machine_mode mode
, rtx addr
)
613 rtx mem
= gen_rtx_MEM (mode
, addr
);
614 MEM_NOTRAP_P (mem
) = 1;
615 if (!current_function_calls_alloca
)
616 set_mem_alias_set (mem
, get_frame_alias_set ());
620 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
621 this construct would be valid, and false otherwise. */
624 validate_subreg (enum machine_mode omode
, enum machine_mode imode
,
625 rtx reg
, unsigned int offset
)
627 unsigned int isize
= GET_MODE_SIZE (imode
);
628 unsigned int osize
= GET_MODE_SIZE (omode
);
630 /* All subregs must be aligned. */
631 if (offset
% osize
!= 0)
634 /* The subreg offset cannot be outside the inner object. */
638 /* ??? This should not be here. Temporarily continue to allow word_mode
639 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
640 Generally, backends are doing something sketchy but it'll take time to
642 if (omode
== word_mode
)
644 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
645 is the culprit here, and not the backends. */
646 else if (osize
>= UNITS_PER_WORD
&& isize
>= osize
)
648 /* Allow component subregs of complex and vector. Though given the below
649 extraction rules, it's not always clear what that means. */
650 else if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
651 && GET_MODE_INNER (imode
) == omode
)
653 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
654 i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
655 represent this. It's questionable if this ought to be represented at
656 all -- why can't this all be hidden in post-reload splitters that make
657 arbitrarily mode changes to the registers themselves. */
658 else if (VECTOR_MODE_P (omode
) && GET_MODE_INNER (omode
) == imode
)
660 /* Subregs involving floating point modes are not allowed to
661 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
662 (subreg:SI (reg:DF) 0) isn't. */
663 else if (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))
669 /* Paradoxical subregs must have offset zero. */
673 /* This is a normal subreg. Verify that the offset is representable. */
675 /* For hard registers, we already have most of these rules collected in
676 subreg_offset_representable_p. */
677 if (reg
&& REG_P (reg
) && HARD_REGISTER_P (reg
))
679 unsigned int regno
= REGNO (reg
);
681 #ifdef CANNOT_CHANGE_MODE_CLASS
682 if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
683 && GET_MODE_INNER (imode
) == omode
)
685 else if (REG_CANNOT_CHANGE_MODE_P (regno
, imode
, omode
))
689 return subreg_offset_representable_p (regno
, imode
, offset
, omode
);
692 /* For pseudo registers, we want most of the same checks. Namely:
693 If the register no larger than a word, the subreg must be lowpart.
694 If the register is larger than a word, the subreg must be the lowpart
695 of a subword. A subreg does *not* perform arbitrary bit extraction.
696 Given that we've already checked mode/offset alignment, we only have
697 to check subword subregs here. */
698 if (osize
< UNITS_PER_WORD
)
700 enum machine_mode wmode
= isize
> UNITS_PER_WORD
? word_mode
: imode
;
701 unsigned int low_off
= subreg_lowpart_offset (omode
, wmode
);
702 if (offset
% UNITS_PER_WORD
!= low_off
)
709 gen_rtx_SUBREG (enum machine_mode mode
, rtx reg
, int offset
)
711 gcc_assert (validate_subreg (mode
, GET_MODE (reg
), reg
, offset
));
712 return gen_rtx_raw_SUBREG (mode
, reg
, offset
);
715 /* Generate a SUBREG representing the least-significant part of REG if MODE
716 is smaller than mode of REG, otherwise paradoxical SUBREG. */
719 gen_lowpart_SUBREG (enum machine_mode mode
, rtx reg
)
721 enum machine_mode inmode
;
723 inmode
= GET_MODE (reg
);
724 if (inmode
== VOIDmode
)
726 return gen_rtx_SUBREG (mode
, reg
,
727 subreg_lowpart_offset (mode
, inmode
));
730 /* gen_rtvec (n, [rt1, ..., rtn])
732 ** This routine creates an rtvec and stores within it the
733 ** pointers to rtx's which are its arguments.
738 gen_rtvec (int n
, ...)
747 return NULL_RTVEC
; /* Don't allocate an empty rtvec... */
749 vector
= alloca (n
* sizeof (rtx
));
751 for (i
= 0; i
< n
; i
++)
752 vector
[i
] = va_arg (p
, rtx
);
754 /* The definition of VA_* in K&R C causes `n' to go out of scope. */
758 return gen_rtvec_v (save_n
, vector
);
762 gen_rtvec_v (int n
, rtx
*argp
)
768 return NULL_RTVEC
; /* Don't allocate an empty rtvec... */
770 rt_val
= rtvec_alloc (n
); /* Allocate an rtvec... */
772 for (i
= 0; i
< n
; i
++)
773 rt_val
->elem
[i
] = *argp
++;
778 /* Generate a REG rtx for a new pseudo register of mode MODE.
779 This pseudo is assigned the next sequential register number. */
782 gen_reg_rtx (enum machine_mode mode
)
784 struct function
*f
= cfun
;
787 gcc_assert (can_create_pseudo_p ());
789 if (generating_concat_p
790 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
791 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
))
793 /* For complex modes, don't make a single pseudo.
794 Instead, make a CONCAT of two pseudos.
795 This allows noncontiguous allocation of the real and imaginary parts,
796 which makes much better code. Besides, allocating DCmode
797 pseudos overstrains reload on some machines like the 386. */
798 rtx realpart
, imagpart
;
799 enum machine_mode partmode
= GET_MODE_INNER (mode
);
801 realpart
= gen_reg_rtx (partmode
);
802 imagpart
= gen_reg_rtx (partmode
);
803 return gen_rtx_CONCAT (mode
, realpart
, imagpart
);
806 /* Make sure regno_pointer_align, and regno_reg_rtx are large
807 enough to have an element for this pseudo reg number. */
809 if (reg_rtx_no
== f
->emit
->regno_pointer_align_length
)
811 int old_size
= f
->emit
->regno_pointer_align_length
;
815 new = ggc_realloc (f
->emit
->regno_pointer_align
, old_size
* 2);
816 memset (new + old_size
, 0, old_size
);
817 f
->emit
->regno_pointer_align
= (unsigned char *) new;
819 new1
= ggc_realloc (f
->emit
->x_regno_reg_rtx
,
820 old_size
* 2 * sizeof (rtx
));
821 memset (new1
+ old_size
, 0, old_size
* sizeof (rtx
));
822 regno_reg_rtx
= new1
;
824 f
->emit
->regno_pointer_align_length
= old_size
* 2;
827 val
= gen_raw_REG (mode
, reg_rtx_no
);
828 regno_reg_rtx
[reg_rtx_no
++] = val
;
832 /* Update NEW with the same attributes as REG, but offsetted by OFFSET.
833 Do the big endian correction if needed. */
836 update_reg_offset (rtx
new, rtx reg
, int offset
)
839 HOST_WIDE_INT var_size
;
841 /* PR middle-end/14084
842 The problem appears when a variable is stored in a larger register
843 and later it is used in the original mode or some mode in between
844 or some part of variable is accessed.
846 On little endian machines there is no problem because
847 the REG_OFFSET of the start of the variable is the same when
848 accessed in any mode (it is 0).
850 However, this is not true on big endian machines.
851 The offset of the start of the variable is different when accessed
853 When we are taking a part of the REG we have to change the OFFSET
854 from offset WRT size of mode of REG to offset WRT size of variable.
856 If we would not do the big endian correction the resulting REG_OFFSET
857 would be larger than the size of the DECL.
859 Examples of correction, for BYTES_BIG_ENDIAN WORDS_BIG_ENDIAN machine:
861 REG.mode MODE DECL size old offset new offset description
862 DI SI 4 4 0 int32 in SImode
863 DI SI 1 4 0 char in SImode
864 DI QI 1 7 0 char in QImode
865 DI QI 4 5 1 1st element in QImode
867 DI HI 4 6 2 1st element in HImode
870 If the size of DECL is equal or greater than the size of REG
871 we can't do this correction because the register holds the
872 whole variable or a part of the variable and thus the REG_OFFSET
873 is already correct. */
875 decl
= REG_EXPR (reg
);
876 if ((BYTES_BIG_ENDIAN
|| WORDS_BIG_ENDIAN
)
879 && GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (GET_MODE (new))
880 && ((var_size
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
881 && var_size
< GET_MODE_SIZE (GET_MODE (reg
))))
885 /* Convert machine endian to little endian WRT size of mode of REG. */
886 if (WORDS_BIG_ENDIAN
)
887 offset_le
= ((GET_MODE_SIZE (GET_MODE (reg
)) - 1 - offset
)
888 / UNITS_PER_WORD
) * UNITS_PER_WORD
;
890 offset_le
= (offset
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
892 if (BYTES_BIG_ENDIAN
)
893 offset_le
+= ((GET_MODE_SIZE (GET_MODE (reg
)) - 1 - offset
)
896 offset_le
+= offset
% UNITS_PER_WORD
;
898 if (offset_le
>= var_size
)
900 /* MODE is wider than the variable so the new reg will cover
901 the whole variable so the resulting OFFSET should be 0. */
906 /* Convert little endian to machine endian WRT size of variable. */
907 if (WORDS_BIG_ENDIAN
)
908 offset
= ((var_size
- 1 - offset_le
)
909 / UNITS_PER_WORD
) * UNITS_PER_WORD
;
911 offset
= (offset_le
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
913 if (BYTES_BIG_ENDIAN
)
914 offset
+= ((var_size
- 1 - offset_le
)
917 offset
+= offset_le
% UNITS_PER_WORD
;
921 REG_ATTRS (new) = get_reg_attrs (REG_EXPR (reg
),
922 REG_OFFSET (reg
) + offset
);
925 /* Generate a register with same attributes as REG, but offsetted by
929 gen_rtx_REG_offset (rtx reg
, enum machine_mode mode
, unsigned int regno
,
932 rtx
new = gen_rtx_REG (mode
, regno
);
934 update_reg_offset (new, reg
, offset
);
938 /* Generate a new pseudo-register with the same attributes as REG, but
939 offsetted by OFFSET. */
942 gen_reg_rtx_offset (rtx reg
, enum machine_mode mode
, int offset
)
944 rtx
new = gen_reg_rtx (mode
);
946 update_reg_offset (new, reg
, offset
);
950 /* Set the decl for MEM to DECL. */
953 set_reg_attrs_from_mem (rtx reg
, rtx mem
)
955 if (MEM_OFFSET (mem
) && GET_CODE (MEM_OFFSET (mem
)) == CONST_INT
)
957 = get_reg_attrs (MEM_EXPR (mem
), INTVAL (MEM_OFFSET (mem
)));
960 /* Set the register attributes for registers contained in PARM_RTX.
961 Use needed values from memory attributes of MEM. */
964 set_reg_attrs_for_parm (rtx parm_rtx
, rtx mem
)
966 if (REG_P (parm_rtx
))
967 set_reg_attrs_from_mem (parm_rtx
, mem
);
968 else if (GET_CODE (parm_rtx
) == PARALLEL
)
970 /* Check for a NULL entry in the first slot, used to indicate that the
971 parameter goes both on the stack and in registers. */
972 int i
= XEXP (XVECEXP (parm_rtx
, 0, 0), 0) ? 0 : 1;
973 for (; i
< XVECLEN (parm_rtx
, 0); i
++)
975 rtx x
= XVECEXP (parm_rtx
, 0, i
);
976 if (REG_P (XEXP (x
, 0)))
977 REG_ATTRS (XEXP (x
, 0))
978 = get_reg_attrs (MEM_EXPR (mem
),
979 INTVAL (XEXP (x
, 1)));
984 /* Assign the RTX X to declaration T. */
986 set_decl_rtl (tree t
, rtx x
)
988 DECL_WRTL_CHECK (t
)->decl_with_rtl
.rtl
= x
;
992 /* For register, we maintain the reverse information too. */
994 REG_ATTRS (x
) = get_reg_attrs (t
, 0);
995 else if (GET_CODE (x
) == SUBREG
)
996 REG_ATTRS (SUBREG_REG (x
))
997 = get_reg_attrs (t
, -SUBREG_BYTE (x
));
998 if (GET_CODE (x
) == CONCAT
)
1000 if (REG_P (XEXP (x
, 0)))
1001 REG_ATTRS (XEXP (x
, 0)) = get_reg_attrs (t
, 0);
1002 if (REG_P (XEXP (x
, 1)))
1003 REG_ATTRS (XEXP (x
, 1))
1004 = get_reg_attrs (t
, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x
, 0))));
1006 if (GET_CODE (x
) == PARALLEL
)
1009 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1011 rtx y
= XVECEXP (x
, 0, i
);
1012 if (REG_P (XEXP (y
, 0)))
1013 REG_ATTRS (XEXP (y
, 0)) = get_reg_attrs (t
, INTVAL (XEXP (y
, 1)));
1018 /* Assign the RTX X to parameter declaration T. */
1020 set_decl_incoming_rtl (tree t
, rtx x
)
1022 DECL_INCOMING_RTL (t
) = x
;
1026 /* For register, we maintain the reverse information too. */
1028 REG_ATTRS (x
) = get_reg_attrs (t
, 0);
1029 else if (GET_CODE (x
) == SUBREG
)
1030 REG_ATTRS (SUBREG_REG (x
))
1031 = get_reg_attrs (t
, -SUBREG_BYTE (x
));
1032 if (GET_CODE (x
) == CONCAT
)
1034 if (REG_P (XEXP (x
, 0)))
1035 REG_ATTRS (XEXP (x
, 0)) = get_reg_attrs (t
, 0);
1036 if (REG_P (XEXP (x
, 1)))
1037 REG_ATTRS (XEXP (x
, 1))
1038 = get_reg_attrs (t
, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x
, 0))));
1040 if (GET_CODE (x
) == PARALLEL
)
1044 /* Check for a NULL entry, used to indicate that the parameter goes
1045 both on the stack and in registers. */
1046 if (XEXP (XVECEXP (x
, 0, 0), 0))
1051 for (i
= start
; i
< XVECLEN (x
, 0); i
++)
1053 rtx y
= XVECEXP (x
, 0, i
);
1054 if (REG_P (XEXP (y
, 0)))
1055 REG_ATTRS (XEXP (y
, 0)) = get_reg_attrs (t
, INTVAL (XEXP (y
, 1)));
1060 /* Identify REG (which may be a CONCAT) as a user register. */
1063 mark_user_reg (rtx reg
)
1065 if (GET_CODE (reg
) == CONCAT
)
1067 REG_USERVAR_P (XEXP (reg
, 0)) = 1;
1068 REG_USERVAR_P (XEXP (reg
, 1)) = 1;
1072 gcc_assert (REG_P (reg
));
1073 REG_USERVAR_P (reg
) = 1;
1077 /* Identify REG as a probable pointer register and show its alignment
1078 as ALIGN, if nonzero. */
1081 mark_reg_pointer (rtx reg
, int align
)
1083 if (! REG_POINTER (reg
))
1085 REG_POINTER (reg
) = 1;
1088 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1090 else if (align
&& align
< REGNO_POINTER_ALIGN (REGNO (reg
)))
1091 /* We can no-longer be sure just how aligned this pointer is. */
1092 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1095 /* Return 1 plus largest pseudo reg number used in the current function. */
1103 /* Return 1 + the largest label number used so far in the current function. */
1106 max_label_num (void)
1111 /* Return first label number used in this function (if any were used). */
1114 get_first_label_num (void)
1116 return first_label_num
;
1119 /* If the rtx for label was created during the expansion of a nested
1120 function, then first_label_num won't include this label number.
1121 Fix this now so that array indicies work later. */
1124 maybe_set_first_label_num (rtx x
)
1126 if (CODE_LABEL_NUMBER (x
) < first_label_num
)
1127 first_label_num
= CODE_LABEL_NUMBER (x
);
1130 /* Return a value representing some low-order bits of X, where the number
1131 of low-order bits is given by MODE. Note that no conversion is done
1132 between floating-point and fixed-point values, rather, the bit
1133 representation is returned.
1135 This function handles the cases in common between gen_lowpart, below,
1136 and two variants in cse.c and combine.c. These are the cases that can
1137 be safely handled at all points in the compilation.
1139 If this is not a case we can handle, return 0. */
1142 gen_lowpart_common (enum machine_mode mode
, rtx x
)
1144 int msize
= GET_MODE_SIZE (mode
);
1147 enum machine_mode innermode
;
1149 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1150 so we have to make one up. Yuk. */
1151 innermode
= GET_MODE (x
);
1152 if (GET_CODE (x
) == CONST_INT
1153 && msize
* BITS_PER_UNIT
<= HOST_BITS_PER_WIDE_INT
)
1154 innermode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1155 else if (innermode
== VOIDmode
)
1156 innermode
= mode_for_size (HOST_BITS_PER_WIDE_INT
* 2, MODE_INT
, 0);
1158 xsize
= GET_MODE_SIZE (innermode
);
1160 gcc_assert (innermode
!= VOIDmode
&& innermode
!= BLKmode
);
1162 if (innermode
== mode
)
1165 /* MODE must occupy no more words than the mode of X. */
1166 if ((msize
+ (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
1167 > ((xsize
+ (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
1170 /* Don't allow generating paradoxical FLOAT_MODE subregs. */
1171 if (SCALAR_FLOAT_MODE_P (mode
) && msize
> xsize
)
1174 offset
= subreg_lowpart_offset (mode
, innermode
);
1176 if ((GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
1177 && (GET_MODE_CLASS (mode
) == MODE_INT
1178 || GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
))
1180 /* If we are getting the low-order part of something that has been
1181 sign- or zero-extended, we can either just use the object being
1182 extended or make a narrower extension. If we want an even smaller
1183 piece than the size of the object being extended, call ourselves
1186 This case is used mostly by combine and cse. */
1188 if (GET_MODE (XEXP (x
, 0)) == mode
)
1190 else if (msize
< GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))))
1191 return gen_lowpart_common (mode
, XEXP (x
, 0));
1192 else if (msize
< xsize
)
1193 return gen_rtx_fmt_e (GET_CODE (x
), mode
, XEXP (x
, 0));
1195 else if (GET_CODE (x
) == SUBREG
|| REG_P (x
)
1196 || GET_CODE (x
) == CONCAT
|| GET_CODE (x
) == CONST_VECTOR
1197 || GET_CODE (x
) == CONST_DOUBLE
|| GET_CODE (x
) == CONST_INT
)
1198 return simplify_gen_subreg (mode
, x
, innermode
, offset
);
1200 /* Otherwise, we can't do this. */
1205 gen_highpart (enum machine_mode mode
, rtx x
)
1207 unsigned int msize
= GET_MODE_SIZE (mode
);
1210 /* This case loses if X is a subreg. To catch bugs early,
1211 complain if an invalid MODE is used even in other cases. */
1212 gcc_assert (msize
<= UNITS_PER_WORD
1213 || msize
== (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x
)));
1215 result
= simplify_gen_subreg (mode
, x
, GET_MODE (x
),
1216 subreg_highpart_offset (mode
, GET_MODE (x
)));
1217 gcc_assert (result
);
1219 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1220 the target if we have a MEM. gen_highpart must return a valid operand,
1221 emitting code if necessary to do so. */
1224 result
= validize_mem (result
);
1225 gcc_assert (result
);
1231 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1232 be VOIDmode constant. */
1234 gen_highpart_mode (enum machine_mode outermode
, enum machine_mode innermode
, rtx exp
)
1236 if (GET_MODE (exp
) != VOIDmode
)
1238 gcc_assert (GET_MODE (exp
) == innermode
);
1239 return gen_highpart (outermode
, exp
);
1241 return simplify_gen_subreg (outermode
, exp
, innermode
,
1242 subreg_highpart_offset (outermode
, innermode
));
1245 /* Return offset in bytes to get OUTERMODE low part
1246 of the value in mode INNERMODE stored in memory in target format. */
1249 subreg_lowpart_offset (enum machine_mode outermode
, enum machine_mode innermode
)
1251 unsigned int offset
= 0;
1252 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
1256 if (WORDS_BIG_ENDIAN
)
1257 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
1258 if (BYTES_BIG_ENDIAN
)
1259 offset
+= difference
% UNITS_PER_WORD
;
1265 /* Return offset in bytes to get OUTERMODE high part
1266 of the value in mode INNERMODE stored in memory in target format. */
1268 subreg_highpart_offset (enum machine_mode outermode
, enum machine_mode innermode
)
1270 unsigned int offset
= 0;
1271 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
1273 gcc_assert (GET_MODE_SIZE (innermode
) >= GET_MODE_SIZE (outermode
));
1277 if (! WORDS_BIG_ENDIAN
)
1278 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
1279 if (! BYTES_BIG_ENDIAN
)
1280 offset
+= difference
% UNITS_PER_WORD
;
1286 /* Return 1 iff X, assumed to be a SUBREG,
1287 refers to the least significant part of its containing reg.
1288 If X is not a SUBREG, always return 1 (it is its own low part!). */
1291 subreg_lowpart_p (const_rtx x
)
1293 if (GET_CODE (x
) != SUBREG
)
1295 else if (GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
1298 return (subreg_lowpart_offset (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)))
1299 == SUBREG_BYTE (x
));
1302 /* Return subword OFFSET of operand OP.
1303 The word number, OFFSET, is interpreted as the word number starting
1304 at the low-order address. OFFSET 0 is the low-order word if not
1305 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1307 If we cannot extract the required word, we return zero. Otherwise,
1308 an rtx corresponding to the requested word will be returned.
1310 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1311 reload has completed, a valid address will always be returned. After
1312 reload, if a valid address cannot be returned, we return zero.
1314 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1315 it is the responsibility of the caller.
1317 MODE is the mode of OP in case it is a CONST_INT.
1319 ??? This is still rather broken for some cases. The problem for the
1320 moment is that all callers of this thing provide no 'goal mode' to
1321 tell us to work with. This exists because all callers were written
1322 in a word based SUBREG world.
1323 Now use of this function can be deprecated by simplify_subreg in most
1328 operand_subword (rtx op
, unsigned int offset
, int validate_address
, enum machine_mode mode
)
1330 if (mode
== VOIDmode
)
1331 mode
= GET_MODE (op
);
1333 gcc_assert (mode
!= VOIDmode
);
1335 /* If OP is narrower than a word, fail. */
1337 && (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
))
1340 /* If we want a word outside OP, return zero. */
1342 && (offset
+ 1) * UNITS_PER_WORD
> GET_MODE_SIZE (mode
))
1345 /* Form a new MEM at the requested address. */
1348 rtx
new = adjust_address_nv (op
, word_mode
, offset
* UNITS_PER_WORD
);
1350 if (! validate_address
)
1353 else if (reload_completed
)
1355 if (! strict_memory_address_p (word_mode
, XEXP (new, 0)))
1359 return replace_equiv_address (new, XEXP (new, 0));
1362 /* Rest can be handled by simplify_subreg. */
1363 return simplify_gen_subreg (word_mode
, op
, mode
, (offset
* UNITS_PER_WORD
));
1366 /* Similar to `operand_subword', but never return 0. If we can't
1367 extract the required subword, put OP into a register and try again.
1368 The second attempt must succeed. We always validate the address in
1371 MODE is the mode of OP, in case it is CONST_INT. */
1374 operand_subword_force (rtx op
, unsigned int offset
, enum machine_mode mode
)
1376 rtx result
= operand_subword (op
, offset
, 1, mode
);
1381 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
1383 /* If this is a register which can not be accessed by words, copy it
1384 to a pseudo register. */
1386 op
= copy_to_reg (op
);
1388 op
= force_reg (mode
, op
);
1391 result
= operand_subword (op
, offset
, 1, mode
);
1392 gcc_assert (result
);
1397 /* Within a MEM_EXPR, we care about either (1) a component ref of a decl,
1398 or (2) a component ref of something variable. Represent the later with
1399 a NULL expression. */
1402 component_ref_for_mem_expr (tree ref
)
1404 tree inner
= TREE_OPERAND (ref
, 0);
1406 if (TREE_CODE (inner
) == COMPONENT_REF
)
1407 inner
= component_ref_for_mem_expr (inner
);
1410 /* Now remove any conversions: they don't change what the underlying
1411 object is. Likewise for SAVE_EXPR. */
1412 while (TREE_CODE (inner
) == NOP_EXPR
|| TREE_CODE (inner
) == CONVERT_EXPR
1413 || TREE_CODE (inner
) == NON_LVALUE_EXPR
1414 || TREE_CODE (inner
) == VIEW_CONVERT_EXPR
1415 || TREE_CODE (inner
) == SAVE_EXPR
)
1416 inner
= TREE_OPERAND (inner
, 0);
1418 if (! DECL_P (inner
))
1422 if (inner
== TREE_OPERAND (ref
, 0))
1425 return build3 (COMPONENT_REF
, TREE_TYPE (ref
), inner
,
1426 TREE_OPERAND (ref
, 1), NULL_TREE
);
1429 /* Returns 1 if both MEM_EXPR can be considered equal
1433 mem_expr_equal_p (const_tree expr1
, const_tree expr2
)
1438 if (! expr1
|| ! expr2
)
1441 if (TREE_CODE (expr1
) != TREE_CODE (expr2
))
1444 if (TREE_CODE (expr1
) == COMPONENT_REF
)
1446 mem_expr_equal_p (TREE_OPERAND (expr1
, 0),
1447 TREE_OPERAND (expr2
, 0))
1448 && mem_expr_equal_p (TREE_OPERAND (expr1
, 1), /* field decl */
1449 TREE_OPERAND (expr2
, 1));
1451 if (INDIRECT_REF_P (expr1
))
1452 return mem_expr_equal_p (TREE_OPERAND (expr1
, 0),
1453 TREE_OPERAND (expr2
, 0));
1455 /* ARRAY_REFs, ARRAY_RANGE_REFs and BIT_FIELD_REFs should already
1456 have been resolved here. */
1457 gcc_assert (DECL_P (expr1
));
1459 /* Decls with different pointers can't be equal. */
1463 /* Given REF, a MEM, and T, either the type of X or the expression
1464 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1465 if we are making a new object of this type. BITPOS is nonzero if
1466 there is an offset outstanding on T that will be applied later. */
1469 set_mem_attributes_minus_bitpos (rtx ref
, tree t
, int objectp
,
1470 HOST_WIDE_INT bitpos
)
1472 alias_set_type alias
= MEM_ALIAS_SET (ref
);
1473 tree expr
= MEM_EXPR (ref
);
1474 rtx offset
= MEM_OFFSET (ref
);
1475 rtx size
= MEM_SIZE (ref
);
1476 unsigned int align
= MEM_ALIGN (ref
);
1477 HOST_WIDE_INT apply_bitpos
= 0;
1480 /* It can happen that type_for_mode was given a mode for which there
1481 is no language-level type. In which case it returns NULL, which
1486 type
= TYPE_P (t
) ? t
: TREE_TYPE (t
);
1487 if (type
== error_mark_node
)
1490 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1491 wrong answer, as it assumes that DECL_RTL already has the right alias
1492 info. Callers should not set DECL_RTL until after the call to
1493 set_mem_attributes. */
1494 gcc_assert (!DECL_P (t
) || ref
!= DECL_RTL_IF_SET (t
));
1496 /* Get the alias set from the expression or type (perhaps using a
1497 front-end routine) and use it. */
1498 alias
= get_alias_set (t
);
1500 MEM_VOLATILE_P (ref
) |= TYPE_VOLATILE (type
);
1501 MEM_IN_STRUCT_P (ref
)
1502 = AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
;
1503 MEM_POINTER (ref
) = POINTER_TYPE_P (type
);
1505 /* If we are making an object of this type, or if this is a DECL, we know
1506 that it is a scalar if the type is not an aggregate. */
1507 if ((objectp
|| DECL_P (t
))
1508 && ! AGGREGATE_TYPE_P (type
)
1509 && TREE_CODE (type
) != COMPLEX_TYPE
)
1510 MEM_SCALAR_P (ref
) = 1;
1512 /* We can set the alignment from the type if we are making an object,
1513 this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */
1514 if (objectp
|| TREE_CODE (t
) == INDIRECT_REF
1515 || TREE_CODE (t
) == ALIGN_INDIRECT_REF
1516 || TYPE_ALIGN_OK (type
))
1517 align
= MAX (align
, TYPE_ALIGN (type
));
1519 if (TREE_CODE (t
) == MISALIGNED_INDIRECT_REF
)
1521 if (integer_zerop (TREE_OPERAND (t
, 1)))
1522 /* We don't know anything about the alignment. */
1523 align
= BITS_PER_UNIT
;
1525 align
= tree_low_cst (TREE_OPERAND (t
, 1), 1);
1528 /* If the size is known, we can set that. */
1529 if (TYPE_SIZE_UNIT (type
) && host_integerp (TYPE_SIZE_UNIT (type
), 1))
1530 size
= GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type
), 1));
1532 /* If T is not a type, we may be able to deduce some more information about
1538 if (TREE_THIS_VOLATILE (t
))
1539 MEM_VOLATILE_P (ref
) = 1;
1541 /* Now remove any conversions: they don't change what the underlying
1542 object is. Likewise for SAVE_EXPR. */
1543 while (TREE_CODE (t
) == NOP_EXPR
|| TREE_CODE (t
) == CONVERT_EXPR
1544 || TREE_CODE (t
) == NON_LVALUE_EXPR
1545 || TREE_CODE (t
) == VIEW_CONVERT_EXPR
1546 || TREE_CODE (t
) == SAVE_EXPR
)
1547 t
= TREE_OPERAND (t
, 0);
1549 /* We may look through structure-like accesses for the purposes of
1550 examining TREE_THIS_NOTRAP, but not array-like accesses. */
1552 while (TREE_CODE (base
) == COMPONENT_REF
1553 || TREE_CODE (base
) == REALPART_EXPR
1554 || TREE_CODE (base
) == IMAGPART_EXPR
1555 || TREE_CODE (base
) == BIT_FIELD_REF
)
1556 base
= TREE_OPERAND (base
, 0);
1560 if (CODE_CONTAINS_STRUCT (TREE_CODE (base
), TS_DECL_WITH_VIS
))
1561 MEM_NOTRAP_P (ref
) = !DECL_WEAK (base
);
1563 MEM_NOTRAP_P (ref
) = 1;
1566 MEM_NOTRAP_P (ref
) = TREE_THIS_NOTRAP (base
);
1568 base
= get_base_address (base
);
1569 if (base
&& DECL_P (base
)
1570 && TREE_READONLY (base
)
1571 && (TREE_STATIC (base
) || DECL_EXTERNAL (base
)))
1573 tree base_type
= TREE_TYPE (base
);
1574 gcc_assert (!(base_type
&& TYPE_NEEDS_CONSTRUCTING (base_type
))
1575 || DECL_ARTIFICIAL (base
));
1576 MEM_READONLY_P (ref
) = 1;
1579 /* If this expression uses it's parent's alias set, mark it such
1580 that we won't change it. */
1581 if (component_uses_parent_alias_set (t
))
1582 MEM_KEEP_ALIAS_SET_P (ref
) = 1;
1584 /* If this is a decl, set the attributes of the MEM from it. */
1588 offset
= const0_rtx
;
1589 apply_bitpos
= bitpos
;
1590 size
= (DECL_SIZE_UNIT (t
)
1591 && host_integerp (DECL_SIZE_UNIT (t
), 1)
1592 ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t
), 1)) : 0);
1593 align
= DECL_ALIGN (t
);
1596 /* If this is a constant, we know the alignment. */
1597 else if (CONSTANT_CLASS_P (t
))
1599 align
= TYPE_ALIGN (type
);
1600 #ifdef CONSTANT_ALIGNMENT
1601 align
= CONSTANT_ALIGNMENT (t
, align
);
1605 /* If this is a field reference and not a bit-field, record it. */
1606 /* ??? There is some information that can be gleened from bit-fields,
1607 such as the word offset in the structure that might be modified.
1608 But skip it for now. */
1609 else if (TREE_CODE (t
) == COMPONENT_REF
1610 && ! DECL_BIT_FIELD (TREE_OPERAND (t
, 1)))
1612 expr
= component_ref_for_mem_expr (t
);
1613 offset
= const0_rtx
;
1614 apply_bitpos
= bitpos
;
1615 /* ??? Any reason the field size would be different than
1616 the size we got from the type? */
1619 /* If this is an array reference, look for an outer field reference. */
1620 else if (TREE_CODE (t
) == ARRAY_REF
)
1622 tree off_tree
= size_zero_node
;
1623 /* We can't modify t, because we use it at the end of the
1629 tree index
= TREE_OPERAND (t2
, 1);
1630 tree low_bound
= array_ref_low_bound (t2
);
1631 tree unit_size
= array_ref_element_size (t2
);
1633 /* We assume all arrays have sizes that are a multiple of a byte.
1634 First subtract the lower bound, if any, in the type of the
1635 index, then convert to sizetype and multiply by the size of
1636 the array element. */
1637 if (! integer_zerop (low_bound
))
1638 index
= fold_build2 (MINUS_EXPR
, TREE_TYPE (index
),
1641 off_tree
= size_binop (PLUS_EXPR
,
1642 size_binop (MULT_EXPR
,
1643 fold_convert (sizetype
,
1647 t2
= TREE_OPERAND (t2
, 0);
1649 while (TREE_CODE (t2
) == ARRAY_REF
);
1655 if (host_integerp (off_tree
, 1))
1657 HOST_WIDE_INT ioff
= tree_low_cst (off_tree
, 1);
1658 HOST_WIDE_INT aoff
= (ioff
& -ioff
) * BITS_PER_UNIT
;
1659 align
= DECL_ALIGN (t2
);
1660 if (aoff
&& (unsigned HOST_WIDE_INT
) aoff
< align
)
1662 offset
= GEN_INT (ioff
);
1663 apply_bitpos
= bitpos
;
1666 else if (TREE_CODE (t2
) == COMPONENT_REF
)
1668 expr
= component_ref_for_mem_expr (t2
);
1669 if (host_integerp (off_tree
, 1))
1671 offset
= GEN_INT (tree_low_cst (off_tree
, 1));
1672 apply_bitpos
= bitpos
;
1674 /* ??? Any reason the field size would be different than
1675 the size we got from the type? */
1677 else if (flag_argument_noalias
> 1
1678 && (INDIRECT_REF_P (t2
))
1679 && TREE_CODE (TREE_OPERAND (t2
, 0)) == PARM_DECL
)
1686 /* If this is a Fortran indirect argument reference, record the
1688 else if (flag_argument_noalias
> 1
1689 && (INDIRECT_REF_P (t
))
1690 && TREE_CODE (TREE_OPERAND (t
, 0)) == PARM_DECL
)
1697 /* If we modified OFFSET based on T, then subtract the outstanding
1698 bit position offset. Similarly, increase the size of the accessed
1699 object to contain the negative offset. */
1702 offset
= plus_constant (offset
, -(apply_bitpos
/ BITS_PER_UNIT
));
1704 size
= plus_constant (size
, apply_bitpos
/ BITS_PER_UNIT
);
1707 if (TREE_CODE (t
) == ALIGN_INDIRECT_REF
)
1709 /* Force EXPR and OFFSE to NULL, since we don't know exactly what
1710 we're overlapping. */
1715 /* Now set the attributes we computed above. */
1717 = get_mem_attrs (alias
, expr
, offset
, size
, align
, GET_MODE (ref
));
1719 /* If this is already known to be a scalar or aggregate, we are done. */
1720 if (MEM_IN_STRUCT_P (ref
) || MEM_SCALAR_P (ref
))
1723 /* If it is a reference into an aggregate, this is part of an aggregate.
1724 Otherwise we don't know. */
1725 else if (TREE_CODE (t
) == COMPONENT_REF
|| TREE_CODE (t
) == ARRAY_REF
1726 || TREE_CODE (t
) == ARRAY_RANGE_REF
1727 || TREE_CODE (t
) == BIT_FIELD_REF
)
1728 MEM_IN_STRUCT_P (ref
) = 1;
1732 set_mem_attributes (rtx ref
, tree t
, int objectp
)
1734 set_mem_attributes_minus_bitpos (ref
, t
, objectp
, 0);
1737 /* Set the decl for MEM to DECL. */
1740 set_mem_attrs_from_reg (rtx mem
, rtx reg
)
1743 = get_mem_attrs (MEM_ALIAS_SET (mem
), REG_EXPR (reg
),
1744 GEN_INT (REG_OFFSET (reg
)),
1745 MEM_SIZE (mem
), MEM_ALIGN (mem
), GET_MODE (mem
));
1748 /* Set the alias set of MEM to SET. */
1751 set_mem_alias_set (rtx mem
, alias_set_type set
)
1753 #ifdef ENABLE_CHECKING
1754 /* If the new and old alias sets don't conflict, something is wrong. */
1755 gcc_assert (alias_sets_conflict_p (set
, MEM_ALIAS_SET (mem
)));
1758 MEM_ATTRS (mem
) = get_mem_attrs (set
, MEM_EXPR (mem
), MEM_OFFSET (mem
),
1759 MEM_SIZE (mem
), MEM_ALIGN (mem
),
1763 /* Set the alignment of MEM to ALIGN bits. */
1766 set_mem_align (rtx mem
, unsigned int align
)
1768 MEM_ATTRS (mem
) = get_mem_attrs (MEM_ALIAS_SET (mem
), MEM_EXPR (mem
),
1769 MEM_OFFSET (mem
), MEM_SIZE (mem
), align
,
1773 /* Set the expr for MEM to EXPR. */
1776 set_mem_expr (rtx mem
, tree expr
)
1779 = get_mem_attrs (MEM_ALIAS_SET (mem
), expr
, MEM_OFFSET (mem
),
1780 MEM_SIZE (mem
), MEM_ALIGN (mem
), GET_MODE (mem
));
1783 /* Set the offset of MEM to OFFSET. */
1786 set_mem_offset (rtx mem
, rtx offset
)
1788 MEM_ATTRS (mem
) = get_mem_attrs (MEM_ALIAS_SET (mem
), MEM_EXPR (mem
),
1789 offset
, MEM_SIZE (mem
), MEM_ALIGN (mem
),
1793 /* Set the size of MEM to SIZE. */
1796 set_mem_size (rtx mem
, rtx size
)
1798 MEM_ATTRS (mem
) = get_mem_attrs (MEM_ALIAS_SET (mem
), MEM_EXPR (mem
),
1799 MEM_OFFSET (mem
), size
, MEM_ALIGN (mem
),
1803 /* Return a memory reference like MEMREF, but with its mode changed to MODE
1804 and its address changed to ADDR. (VOIDmode means don't change the mode.
1805 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
1806 returned memory location is required to be valid. The memory
1807 attributes are not changed. */
1810 change_address_1 (rtx memref
, enum machine_mode mode
, rtx addr
, int validate
)
1814 gcc_assert (MEM_P (memref
));
1815 if (mode
== VOIDmode
)
1816 mode
= GET_MODE (memref
);
1818 addr
= XEXP (memref
, 0);
1819 if (mode
== GET_MODE (memref
) && addr
== XEXP (memref
, 0)
1820 && (!validate
|| memory_address_p (mode
, addr
)))
1825 if (reload_in_progress
|| reload_completed
)
1826 gcc_assert (memory_address_p (mode
, addr
));
1828 addr
= memory_address (mode
, addr
);
1831 if (rtx_equal_p (addr
, XEXP (memref
, 0)) && mode
== GET_MODE (memref
))
1834 new = gen_rtx_MEM (mode
, addr
);
1835 MEM_COPY_ATTRIBUTES (new, memref
);
1839 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
1840 way we are changing MEMREF, so we only preserve the alias set. */
1843 change_address (rtx memref
, enum machine_mode mode
, rtx addr
)
1845 rtx
new = change_address_1 (memref
, mode
, addr
, 1), size
;
1846 enum machine_mode mmode
= GET_MODE (new);
1849 size
= mmode
== BLKmode
? 0 : GEN_INT (GET_MODE_SIZE (mmode
));
1850 align
= mmode
== BLKmode
? BITS_PER_UNIT
: GET_MODE_ALIGNMENT (mmode
);
1852 /* If there are no changes, just return the original memory reference. */
1855 if (MEM_ATTRS (memref
) == 0
1856 || (MEM_EXPR (memref
) == NULL
1857 && MEM_OFFSET (memref
) == NULL
1858 && MEM_SIZE (memref
) == size
1859 && MEM_ALIGN (memref
) == align
))
1862 new = gen_rtx_MEM (mmode
, XEXP (memref
, 0));
1863 MEM_COPY_ATTRIBUTES (new, memref
);
1867 = get_mem_attrs (MEM_ALIAS_SET (memref
), 0, 0, size
, align
, mmode
);
1872 /* Return a memory reference like MEMREF, but with its mode changed
1873 to MODE and its address offset by OFFSET bytes. If VALIDATE is
1874 nonzero, the memory address is forced to be valid.
1875 If ADJUST is zero, OFFSET is only used to update MEM_ATTRS
1876 and caller is responsible for adjusting MEMREF base register. */
1879 adjust_address_1 (rtx memref
, enum machine_mode mode
, HOST_WIDE_INT offset
,
1880 int validate
, int adjust
)
1882 rtx addr
= XEXP (memref
, 0);
1884 rtx memoffset
= MEM_OFFSET (memref
);
1886 unsigned int memalign
= MEM_ALIGN (memref
);
1888 /* If there are no changes, just return the original memory reference. */
1889 if (mode
== GET_MODE (memref
) && !offset
1890 && (!validate
|| memory_address_p (mode
, addr
)))
1893 /* ??? Prefer to create garbage instead of creating shared rtl.
1894 This may happen even if offset is nonzero -- consider
1895 (plus (plus reg reg) const_int) -- so do this always. */
1896 addr
= copy_rtx (addr
);
1900 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
1901 object, we can merge it into the LO_SUM. */
1902 if (GET_MODE (memref
) != BLKmode
&& GET_CODE (addr
) == LO_SUM
1904 && (unsigned HOST_WIDE_INT
) offset
1905 < GET_MODE_ALIGNMENT (GET_MODE (memref
)) / BITS_PER_UNIT
)
1906 addr
= gen_rtx_LO_SUM (Pmode
, XEXP (addr
, 0),
1907 plus_constant (XEXP (addr
, 1), offset
));
1909 addr
= plus_constant (addr
, offset
);
1912 new = change_address_1 (memref
, mode
, addr
, validate
);
1914 /* Compute the new values of the memory attributes due to this adjustment.
1915 We add the offsets and update the alignment. */
1917 memoffset
= GEN_INT (offset
+ INTVAL (memoffset
));
1919 /* Compute the new alignment by taking the MIN of the alignment and the
1920 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
1925 (unsigned HOST_WIDE_INT
) (offset
& -offset
) * BITS_PER_UNIT
);
1927 /* We can compute the size in a number of ways. */
1928 if (GET_MODE (new) != BLKmode
)
1929 size
= GEN_INT (GET_MODE_SIZE (GET_MODE (new)));
1930 else if (MEM_SIZE (memref
))
1931 size
= plus_constant (MEM_SIZE (memref
), -offset
);
1933 MEM_ATTRS (new) = get_mem_attrs (MEM_ALIAS_SET (memref
), MEM_EXPR (memref
),
1934 memoffset
, size
, memalign
, GET_MODE (new));
1936 /* At some point, we should validate that this offset is within the object,
1937 if all the appropriate values are known. */
1941 /* Return a memory reference like MEMREF, but with its mode changed
1942 to MODE and its address changed to ADDR, which is assumed to be
1943 MEMREF offseted by OFFSET bytes. If VALIDATE is
1944 nonzero, the memory address is forced to be valid. */
1947 adjust_automodify_address_1 (rtx memref
, enum machine_mode mode
, rtx addr
,
1948 HOST_WIDE_INT offset
, int validate
)
1950 memref
= change_address_1 (memref
, VOIDmode
, addr
, validate
);
1951 return adjust_address_1 (memref
, mode
, offset
, validate
, 0);
1954 /* Return a memory reference like MEMREF, but whose address is changed by
1955 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
1956 known to be in OFFSET (possibly 1). */
1959 offset_address (rtx memref
, rtx offset
, unsigned HOST_WIDE_INT pow2
)
1961 rtx
new, addr
= XEXP (memref
, 0);
1963 new = simplify_gen_binary (PLUS
, Pmode
, addr
, offset
);
1965 /* At this point we don't know _why_ the address is invalid. It
1966 could have secondary memory references, multiplies or anything.
1968 However, if we did go and rearrange things, we can wind up not
1969 being able to recognize the magic around pic_offset_table_rtx.
1970 This stuff is fragile, and is yet another example of why it is
1971 bad to expose PIC machinery too early. */
1972 if (! memory_address_p (GET_MODE (memref
), new)
1973 && GET_CODE (addr
) == PLUS
1974 && XEXP (addr
, 0) == pic_offset_table_rtx
)
1976 addr
= force_reg (GET_MODE (addr
), addr
);
1977 new = simplify_gen_binary (PLUS
, Pmode
, addr
, offset
);
1980 update_temp_slot_address (XEXP (memref
, 0), new);
1981 new = change_address_1 (memref
, VOIDmode
, new, 1);
1983 /* If there are no changes, just return the original memory reference. */
1987 /* Update the alignment to reflect the offset. Reset the offset, which
1990 = get_mem_attrs (MEM_ALIAS_SET (memref
), MEM_EXPR (memref
), 0, 0,
1991 MIN (MEM_ALIGN (memref
), pow2
* BITS_PER_UNIT
),
1996 /* Return a memory reference like MEMREF, but with its address changed to
1997 ADDR. The caller is asserting that the actual piece of memory pointed
1998 to is the same, just the form of the address is being changed, such as
1999 by putting something into a register. */
2002 replace_equiv_address (rtx memref
, rtx addr
)
2004 /* change_address_1 copies the memory attribute structure without change
2005 and that's exactly what we want here. */
2006 update_temp_slot_address (XEXP (memref
, 0), addr
);
2007 return change_address_1 (memref
, VOIDmode
, addr
, 1);
2010 /* Likewise, but the reference is not required to be valid. */
2013 replace_equiv_address_nv (rtx memref
, rtx addr
)
2015 return change_address_1 (memref
, VOIDmode
, addr
, 0);
2018 /* Return a memory reference like MEMREF, but with its mode widened to
2019 MODE and offset by OFFSET. This would be used by targets that e.g.
2020 cannot issue QImode memory operations and have to use SImode memory
2021 operations plus masking logic. */
2024 widen_memory_access (rtx memref
, enum machine_mode mode
, HOST_WIDE_INT offset
)
2026 rtx
new = adjust_address_1 (memref
, mode
, offset
, 1, 1);
2027 tree expr
= MEM_EXPR (new);
2028 rtx memoffset
= MEM_OFFSET (new);
2029 unsigned int size
= GET_MODE_SIZE (mode
);
2031 /* If there are no changes, just return the original memory reference. */
2035 /* If we don't know what offset we were at within the expression, then
2036 we can't know if we've overstepped the bounds. */
2042 if (TREE_CODE (expr
) == COMPONENT_REF
)
2044 tree field
= TREE_OPERAND (expr
, 1);
2045 tree offset
= component_ref_field_offset (expr
);
2047 if (! DECL_SIZE_UNIT (field
))
2053 /* Is the field at least as large as the access? If so, ok,
2054 otherwise strip back to the containing structure. */
2055 if (TREE_CODE (DECL_SIZE_UNIT (field
)) == INTEGER_CST
2056 && compare_tree_int (DECL_SIZE_UNIT (field
), size
) >= 0
2057 && INTVAL (memoffset
) >= 0)
2060 if (! host_integerp (offset
, 1))
2066 expr
= TREE_OPERAND (expr
, 0);
2068 = (GEN_INT (INTVAL (memoffset
)
2069 + tree_low_cst (offset
, 1)
2070 + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field
), 1)
2073 /* Similarly for the decl. */
2074 else if (DECL_P (expr
)
2075 && DECL_SIZE_UNIT (expr
)
2076 && TREE_CODE (DECL_SIZE_UNIT (expr
)) == INTEGER_CST
2077 && compare_tree_int (DECL_SIZE_UNIT (expr
), size
) >= 0
2078 && (! memoffset
|| INTVAL (memoffset
) >= 0))
2082 /* The widened memory access overflows the expression, which means
2083 that it could alias another expression. Zap it. */
2090 memoffset
= NULL_RTX
;
2092 /* The widened memory may alias other stuff, so zap the alias set. */
2093 /* ??? Maybe use get_alias_set on any remaining expression. */
2095 MEM_ATTRS (new) = get_mem_attrs (0, expr
, memoffset
, GEN_INT (size
),
2096 MEM_ALIGN (new), mode
);
2101 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2104 gen_label_rtx (void)
2106 return gen_rtx_CODE_LABEL (VOIDmode
, 0, NULL_RTX
, NULL_RTX
,
2107 NULL
, label_num
++, NULL
);
2110 /* For procedure integration. */
2112 /* Install new pointers to the first and last insns in the chain.
2113 Also, set cur_insn_uid to one higher than the last in use.
2114 Used for an inline-procedure after copying the insn chain. */
2117 set_new_first_and_last_insn (rtx first
, rtx last
)
2125 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2126 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2131 /* Go through all the RTL insn bodies and copy any invalid shared
2132 structure. This routine should only be called once. */
2135 unshare_all_rtl_1 (rtx insn
)
2137 /* Unshare just about everything else. */
2138 unshare_all_rtl_in_chain (insn
);
2140 /* Make sure the addresses of stack slots found outside the insn chain
2141 (such as, in DECL_RTL of a variable) are not shared
2142 with the insn chain.
2144 This special care is necessary when the stack slot MEM does not
2145 actually appear in the insn chain. If it does appear, its address
2146 is unshared from all else at that point. */
2147 stack_slot_list
= copy_rtx_if_shared (stack_slot_list
);
2150 /* Go through all the RTL insn bodies and copy any invalid shared
2151 structure, again. This is a fairly expensive thing to do so it
2152 should be done sparingly. */
2155 unshare_all_rtl_again (rtx insn
)
2160 for (p
= insn
; p
; p
= NEXT_INSN (p
))
2163 reset_used_flags (PATTERN (p
));
2164 reset_used_flags (REG_NOTES (p
));
2167 /* Make sure that virtual stack slots are not shared. */
2168 set_used_decls (DECL_INITIAL (cfun
->decl
));
2170 /* Make sure that virtual parameters are not shared. */
2171 for (decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= TREE_CHAIN (decl
))
2172 set_used_flags (DECL_RTL (decl
));
2174 reset_used_flags (stack_slot_list
);
2176 unshare_all_rtl_1 (insn
);
2180 unshare_all_rtl (void)
2182 unshare_all_rtl_1 (get_insns ());
2186 struct tree_opt_pass pass_unshare_all_rtl
=
2188 "unshare", /* name */
2190 unshare_all_rtl
, /* execute */
2193 0, /* static_pass_number */
2195 0, /* properties_required */
2196 0, /* properties_provided */
2197 0, /* properties_destroyed */
2198 0, /* todo_flags_start */
2199 TODO_dump_func
, /* todo_flags_finish */
2204 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2205 Recursively does the same for subexpressions. */
2208 verify_rtx_sharing (rtx orig
, rtx insn
)
2213 const char *format_ptr
;
2218 code
= GET_CODE (x
);
2220 /* These types may be freely shared. */
2235 /* SCRATCH must be shared because they represent distinct values. */
2237 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2242 if (shared_const_p (orig
))
2247 /* A MEM is allowed to be shared if its address is constant. */
2248 if (CONSTANT_ADDRESS_P (XEXP (x
, 0))
2249 || reload_completed
|| reload_in_progress
)
2258 /* This rtx may not be shared. If it has already been seen,
2259 replace it with a copy of itself. */
2260 #ifdef ENABLE_CHECKING
2261 if (RTX_FLAG (x
, used
))
2263 error ("invalid rtl sharing found in the insn");
2265 error ("shared rtx");
2267 internal_error ("internal consistency failure");
2270 gcc_assert (!RTX_FLAG (x
, used
));
2272 RTX_FLAG (x
, used
) = 1;
2274 /* Now scan the subexpressions recursively. */
2276 format_ptr
= GET_RTX_FORMAT (code
);
2278 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
2280 switch (*format_ptr
++)
2283 verify_rtx_sharing (XEXP (x
, i
), insn
);
2287 if (XVEC (x
, i
) != NULL
)
2290 int len
= XVECLEN (x
, i
);
2292 for (j
= 0; j
< len
; j
++)
2294 /* We allow sharing of ASM_OPERANDS inside single
2296 if (j
&& GET_CODE (XVECEXP (x
, i
, j
)) == SET
2297 && (GET_CODE (SET_SRC (XVECEXP (x
, i
, j
)))
2299 verify_rtx_sharing (SET_DEST (XVECEXP (x
, i
, j
)), insn
);
2301 verify_rtx_sharing (XVECEXP (x
, i
, j
), insn
);
2310 /* Go through all the RTL insn bodies and check that there is no unexpected
2311 sharing in between the subexpressions. */
2314 verify_rtl_sharing (void)
2318 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
2321 reset_used_flags (PATTERN (p
));
2322 reset_used_flags (REG_NOTES (p
));
2323 if (GET_CODE (PATTERN (p
)) == SEQUENCE
)
2326 rtx q
, sequence
= PATTERN (p
);
2328 for (i
= 0; i
< XVECLEN (sequence
, 0); i
++)
2330 q
= XVECEXP (sequence
, 0, i
);
2331 gcc_assert (INSN_P (q
));
2332 reset_used_flags (PATTERN (q
));
2333 reset_used_flags (REG_NOTES (q
));
2338 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
2341 verify_rtx_sharing (PATTERN (p
), p
);
2342 verify_rtx_sharing (REG_NOTES (p
), p
);
2346 /* Go through all the RTL insn bodies and copy any invalid shared structure.
2347 Assumes the mark bits are cleared at entry. */
2350 unshare_all_rtl_in_chain (rtx insn
)
2352 for (; insn
; insn
= NEXT_INSN (insn
))
2355 PATTERN (insn
) = copy_rtx_if_shared (PATTERN (insn
));
2356 REG_NOTES (insn
) = copy_rtx_if_shared (REG_NOTES (insn
));
2360 /* Go through all virtual stack slots of a function and mark them as
2361 shared. We never replace the DECL_RTLs themselves with a copy,
2362 but expressions mentioned into a DECL_RTL cannot be shared with
2363 expressions in the instruction stream.
2365 Note that reload may convert pseudo registers into memories in-place.
2366 Pseudo registers are always shared, but MEMs never are. Thus if we
2367 reset the used flags on MEMs in the instruction stream, we must set
2368 them again on MEMs that appear in DECL_RTLs. */
2371 set_used_decls (tree blk
)
2376 for (t
= BLOCK_VARS (blk
); t
; t
= TREE_CHAIN (t
))
2377 if (DECL_RTL_SET_P (t
))
2378 set_used_flags (DECL_RTL (t
));
2380 /* Now process sub-blocks. */
2381 for (t
= BLOCK_SUBBLOCKS (blk
); t
; t
= TREE_CHAIN (t
))
2385 /* Mark ORIG as in use, and return a copy of it if it was already in use.
2386 Recursively does the same for subexpressions. Uses
2387 copy_rtx_if_shared_1 to reduce stack space. */
2390 copy_rtx_if_shared (rtx orig
)
2392 copy_rtx_if_shared_1 (&orig
);
2396 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
2397 use. Recursively does the same for subexpressions. */
2400 copy_rtx_if_shared_1 (rtx
*orig1
)
2406 const char *format_ptr
;
2410 /* Repeat is used to turn tail-recursion into iteration. */
2417 code
= GET_CODE (x
);
2419 /* These types may be freely shared. */
2433 /* SCRATCH must be shared because they represent distinct values. */
2436 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2441 if (shared_const_p (x
))
2450 /* The chain of insns is not being copied. */
2457 /* This rtx may not be shared. If it has already been seen,
2458 replace it with a copy of itself. */
2460 if (RTX_FLAG (x
, used
))
2462 x
= shallow_copy_rtx (x
);
2465 RTX_FLAG (x
, used
) = 1;
2467 /* Now scan the subexpressions recursively.
2468 We can store any replaced subexpressions directly into X
2469 since we know X is not shared! Any vectors in X
2470 must be copied if X was copied. */
2472 format_ptr
= GET_RTX_FORMAT (code
);
2473 length
= GET_RTX_LENGTH (code
);
2476 for (i
= 0; i
< length
; i
++)
2478 switch (*format_ptr
++)
2482 copy_rtx_if_shared_1 (last_ptr
);
2483 last_ptr
= &XEXP (x
, i
);
2487 if (XVEC (x
, i
) != NULL
)
2490 int len
= XVECLEN (x
, i
);
2492 /* Copy the vector iff I copied the rtx and the length
2494 if (copied
&& len
> 0)
2495 XVEC (x
, i
) = gen_rtvec_v (len
, XVEC (x
, i
)->elem
);
2497 /* Call recursively on all inside the vector. */
2498 for (j
= 0; j
< len
; j
++)
2501 copy_rtx_if_shared_1 (last_ptr
);
2502 last_ptr
= &XVECEXP (x
, i
, j
);
2517 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
2518 to look for shared sub-parts. */
2521 reset_used_flags (rtx x
)
2525 const char *format_ptr
;
2528 /* Repeat is used to turn tail-recursion into iteration. */
2533 code
= GET_CODE (x
);
2535 /* These types may be freely shared so we needn't do any resetting
2556 /* The chain of insns is not being copied. */
2563 RTX_FLAG (x
, used
) = 0;
2565 format_ptr
= GET_RTX_FORMAT (code
);
2566 length
= GET_RTX_LENGTH (code
);
2568 for (i
= 0; i
< length
; i
++)
2570 switch (*format_ptr
++)
2578 reset_used_flags (XEXP (x
, i
));
2582 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2583 reset_used_flags (XVECEXP (x
, i
, j
));
2589 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
2590 to look for shared sub-parts. */
2593 set_used_flags (rtx x
)
2597 const char *format_ptr
;
2602 code
= GET_CODE (x
);
2604 /* These types may be freely shared so we needn't do any resetting
2625 /* The chain of insns is not being copied. */
2632 RTX_FLAG (x
, used
) = 1;
2634 format_ptr
= GET_RTX_FORMAT (code
);
2635 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
2637 switch (*format_ptr
++)
2640 set_used_flags (XEXP (x
, i
));
2644 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2645 set_used_flags (XVECEXP (x
, i
, j
));
2651 /* Copy X if necessary so that it won't be altered by changes in OTHER.
2652 Return X or the rtx for the pseudo reg the value of X was copied into.
2653 OTHER must be valid as a SET_DEST. */
2656 make_safe_from (rtx x
, rtx other
)
2659 switch (GET_CODE (other
))
2662 other
= SUBREG_REG (other
);
2664 case STRICT_LOW_PART
:
2667 other
= XEXP (other
, 0);
2676 && GET_CODE (x
) != SUBREG
)
2678 && (REGNO (other
) < FIRST_PSEUDO_REGISTER
2679 || reg_mentioned_p (other
, x
))))
2681 rtx temp
= gen_reg_rtx (GET_MODE (x
));
2682 emit_move_insn (temp
, x
);
2688 /* Emission of insns (adding them to the doubly-linked list). */
2690 /* Return the first insn of the current sequence or current function. */
2698 /* Specify a new insn as the first in the chain. */
2701 set_first_insn (rtx insn
)
2703 gcc_assert (!PREV_INSN (insn
));
2707 /* Return the last insn emitted in current sequence or current function. */
2710 get_last_insn (void)
2715 /* Specify a new insn as the last in the chain. */
2718 set_last_insn (rtx insn
)
2720 gcc_assert (!NEXT_INSN (insn
));
2724 /* Return the last insn emitted, even if it is in a sequence now pushed. */
2727 get_last_insn_anywhere (void)
2729 struct sequence_stack
*stack
;
2732 for (stack
= seq_stack
; stack
; stack
= stack
->next
)
2733 if (stack
->last
!= 0)
2738 /* Return the first nonnote insn emitted in current sequence or current
2739 function. This routine looks inside SEQUENCEs. */
2742 get_first_nonnote_insn (void)
2744 rtx insn
= first_insn
;
2749 for (insn
= next_insn (insn
);
2750 insn
&& NOTE_P (insn
);
2751 insn
= next_insn (insn
))
2755 if (NONJUMP_INSN_P (insn
)
2756 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2757 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2764 /* Return the last nonnote insn emitted in current sequence or current
2765 function. This routine looks inside SEQUENCEs. */
2768 get_last_nonnote_insn (void)
2770 rtx insn
= last_insn
;
2775 for (insn
= previous_insn (insn
);
2776 insn
&& NOTE_P (insn
);
2777 insn
= previous_insn (insn
))
2781 if (NONJUMP_INSN_P (insn
)
2782 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2783 insn
= XVECEXP (PATTERN (insn
), 0,
2784 XVECLEN (PATTERN (insn
), 0) - 1);
2791 /* Return a number larger than any instruction's uid in this function. */
2796 return cur_insn_uid
;
2799 /* Return the next insn. If it is a SEQUENCE, return the first insn
2803 next_insn (rtx insn
)
2807 insn
= NEXT_INSN (insn
);
2808 if (insn
&& NONJUMP_INSN_P (insn
)
2809 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2810 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2816 /* Return the previous insn. If it is a SEQUENCE, return the last insn
2820 previous_insn (rtx insn
)
2824 insn
= PREV_INSN (insn
);
2825 if (insn
&& NONJUMP_INSN_P (insn
)
2826 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2827 insn
= XVECEXP (PATTERN (insn
), 0, XVECLEN (PATTERN (insn
), 0) - 1);
2833 /* Return the next insn after INSN that is not a NOTE. This routine does not
2834 look inside SEQUENCEs. */
2837 next_nonnote_insn (rtx insn
)
2841 insn
= NEXT_INSN (insn
);
2842 if (insn
== 0 || !NOTE_P (insn
))
2849 /* Return the previous insn before INSN that is not a NOTE. This routine does
2850 not look inside SEQUENCEs. */
2853 prev_nonnote_insn (rtx insn
)
2857 insn
= PREV_INSN (insn
);
2858 if (insn
== 0 || !NOTE_P (insn
))
2865 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
2866 or 0, if there is none. This routine does not look inside
2870 next_real_insn (rtx insn
)
2874 insn
= NEXT_INSN (insn
);
2875 if (insn
== 0 || INSN_P (insn
))
2882 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
2883 or 0, if there is none. This routine does not look inside
2887 prev_real_insn (rtx insn
)
2891 insn
= PREV_INSN (insn
);
2892 if (insn
== 0 || INSN_P (insn
))
2899 /* Return the last CALL_INSN in the current list, or 0 if there is none.
2900 This routine does not look inside SEQUENCEs. */
2903 last_call_insn (void)
2907 for (insn
= get_last_insn ();
2908 insn
&& !CALL_P (insn
);
2909 insn
= PREV_INSN (insn
))
2915 /* Find the next insn after INSN that really does something. This routine
2916 does not look inside SEQUENCEs. Until reload has completed, this is the
2917 same as next_real_insn. */
2920 active_insn_p (const_rtx insn
)
2922 return (CALL_P (insn
) || JUMP_P (insn
)
2923 || (NONJUMP_INSN_P (insn
)
2924 && (! reload_completed
2925 || (GET_CODE (PATTERN (insn
)) != USE
2926 && GET_CODE (PATTERN (insn
)) != CLOBBER
))));
2930 next_active_insn (rtx insn
)
2934 insn
= NEXT_INSN (insn
);
2935 if (insn
== 0 || active_insn_p (insn
))
2942 /* Find the last insn before INSN that really does something. This routine
2943 does not look inside SEQUENCEs. Until reload has completed, this is the
2944 same as prev_real_insn. */
2947 prev_active_insn (rtx insn
)
2951 insn
= PREV_INSN (insn
);
2952 if (insn
== 0 || active_insn_p (insn
))
2959 /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */
2962 next_label (rtx insn
)
2966 insn
= NEXT_INSN (insn
);
2967 if (insn
== 0 || LABEL_P (insn
))
2974 /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */
2977 prev_label (rtx insn
)
2981 insn
= PREV_INSN (insn
);
2982 if (insn
== 0 || LABEL_P (insn
))
2989 /* Return the last label to mark the same position as LABEL. Return null
2990 if LABEL itself is null. */
2993 skip_consecutive_labels (rtx label
)
2997 for (insn
= label
; insn
!= 0 && !INSN_P (insn
); insn
= NEXT_INSN (insn
))
3005 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
3006 and REG_CC_USER notes so we can find it. */
3009 link_cc0_insns (rtx insn
)
3011 rtx user
= next_nonnote_insn (insn
);
3013 if (NONJUMP_INSN_P (user
) && GET_CODE (PATTERN (user
)) == SEQUENCE
)
3014 user
= XVECEXP (PATTERN (user
), 0, 0);
3016 REG_NOTES (user
) = gen_rtx_INSN_LIST (REG_CC_SETTER
, insn
,
3018 REG_NOTES (insn
) = gen_rtx_INSN_LIST (REG_CC_USER
, user
, REG_NOTES (insn
));
3021 /* Return the next insn that uses CC0 after INSN, which is assumed to
3022 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3023 applied to the result of this function should yield INSN).
3025 Normally, this is simply the next insn. However, if a REG_CC_USER note
3026 is present, it contains the insn that uses CC0.
3028 Return 0 if we can't find the insn. */
3031 next_cc0_user (rtx insn
)
3033 rtx note
= find_reg_note (insn
, REG_CC_USER
, NULL_RTX
);
3036 return XEXP (note
, 0);
3038 insn
= next_nonnote_insn (insn
);
3039 if (insn
&& NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3040 insn
= XVECEXP (PATTERN (insn
), 0, 0);
3042 if (insn
&& INSN_P (insn
) && reg_mentioned_p (cc0_rtx
, PATTERN (insn
)))
3048 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3049 note, it is the previous insn. */
3052 prev_cc0_setter (rtx insn
)
3054 rtx note
= find_reg_note (insn
, REG_CC_SETTER
, NULL_RTX
);
3057 return XEXP (note
, 0);
3059 insn
= prev_nonnote_insn (insn
);
3060 gcc_assert (sets_cc0_p (PATTERN (insn
)));
3067 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3070 find_auto_inc (rtx
*xp
, void *data
)
3075 if (GET_RTX_CLASS (GET_CODE (x
)) != RTX_AUTOINC
)
3078 switch (GET_CODE (x
))
3086 if (rtx_equal_p (reg
, XEXP (x
, 0)))
3097 /* Increment the label uses for all labels present in rtx. */
3100 mark_label_nuses (rtx x
)
3106 code
= GET_CODE (x
);
3107 if (code
== LABEL_REF
&& LABEL_P (XEXP (x
, 0)))
3108 LABEL_NUSES (XEXP (x
, 0))++;
3110 fmt
= GET_RTX_FORMAT (code
);
3111 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3114 mark_label_nuses (XEXP (x
, i
));
3115 else if (fmt
[i
] == 'E')
3116 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3117 mark_label_nuses (XVECEXP (x
, i
, j
));
3122 /* Try splitting insns that can be split for better scheduling.
3123 PAT is the pattern which might split.
3124 TRIAL is the insn providing PAT.
3125 LAST is nonzero if we should return the last insn of the sequence produced.
3127 If this routine succeeds in splitting, it returns the first or last
3128 replacement insn depending on the value of LAST. Otherwise, it
3129 returns TRIAL. If the insn to be returned can be split, it will be. */
3132 try_split (rtx pat
, rtx trial
, int last
)
3134 rtx before
= PREV_INSN (trial
);
3135 rtx after
= NEXT_INSN (trial
);
3136 int has_barrier
= 0;
3140 rtx insn_last
, insn
;
3143 if (any_condjump_p (trial
)
3144 && (note
= find_reg_note (trial
, REG_BR_PROB
, 0)))
3145 split_branch_probability
= INTVAL (XEXP (note
, 0));
3146 probability
= split_branch_probability
;
3148 seq
= split_insns (pat
, trial
);
3150 split_branch_probability
= -1;
3152 /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER.
3153 We may need to handle this specially. */
3154 if (after
&& BARRIER_P (after
))
3157 after
= NEXT_INSN (after
);
3163 /* Avoid infinite loop if any insn of the result matches
3164 the original pattern. */
3168 if (INSN_P (insn_last
)
3169 && rtx_equal_p (PATTERN (insn_last
), pat
))
3171 if (!NEXT_INSN (insn_last
))
3173 insn_last
= NEXT_INSN (insn_last
);
3176 /* We will be adding the new sequence to the function. The splitters
3177 may have introduced invalid RTL sharing, so unshare the sequence now. */
3178 unshare_all_rtl_in_chain (seq
);
3181 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3185 mark_jump_label (PATTERN (insn
), insn
, 0);
3187 if (probability
!= -1
3188 && any_condjump_p (insn
)
3189 && !find_reg_note (insn
, REG_BR_PROB
, 0))
3191 /* We can preserve the REG_BR_PROB notes only if exactly
3192 one jump is created, otherwise the machine description
3193 is responsible for this step using
3194 split_branch_probability variable. */
3195 gcc_assert (njumps
== 1);
3197 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
3198 GEN_INT (probability
),
3204 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3205 in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */
3208 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3211 rtx
*p
= &CALL_INSN_FUNCTION_USAGE (insn
);
3214 *p
= CALL_INSN_FUNCTION_USAGE (trial
);
3215 SIBLING_CALL_P (insn
) = SIBLING_CALL_P (trial
);
3219 /* Copy notes, particularly those related to the CFG. */
3220 for (note
= REG_NOTES (trial
); note
; note
= XEXP (note
, 1))
3222 switch (REG_NOTE_KIND (note
))
3225 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3228 || (flag_non_call_exceptions
&& INSN_P (insn
)
3229 && may_trap_p (PATTERN (insn
))))
3231 = gen_rtx_EXPR_LIST (REG_EH_REGION
,
3239 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3243 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note
),
3249 case REG_NON_LOCAL_GOTO
:
3250 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3254 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note
),
3262 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3264 rtx reg
= XEXP (note
, 0);
3265 if (!FIND_REG_INC_NOTE (insn
, reg
)
3266 && for_each_rtx (&PATTERN (insn
), find_auto_inc
, reg
) > 0)
3267 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_INC
, reg
,
3278 /* If there are LABELS inside the split insns increment the
3279 usage count so we don't delete the label. */
3280 if (NONJUMP_INSN_P (trial
))
3283 while (insn
!= NULL_RTX
)
3285 if (NONJUMP_INSN_P (insn
))
3286 mark_label_nuses (PATTERN (insn
));
3288 insn
= PREV_INSN (insn
);
3292 tem
= emit_insn_after_setloc (seq
, trial
, INSN_LOCATOR (trial
));
3294 delete_insn (trial
);
3296 emit_barrier_after (tem
);
3298 /* Recursively call try_split for each new insn created; by the
3299 time control returns here that insn will be fully split, so
3300 set LAST and continue from the insn after the one returned.
3301 We can't use next_active_insn here since AFTER may be a note.
3302 Ignore deleted insns, which can be occur if not optimizing. */
3303 for (tem
= NEXT_INSN (before
); tem
!= after
; tem
= NEXT_INSN (tem
))
3304 if (! INSN_DELETED_P (tem
) && INSN_P (tem
))
3305 tem
= try_split (PATTERN (tem
), tem
, 1);
3307 /* Return either the first or the last insn, depending on which was
3310 ? (after
? PREV_INSN (after
) : last_insn
)
3311 : NEXT_INSN (before
);
3314 /* Make and return an INSN rtx, initializing all its slots.
3315 Store PATTERN in the pattern slots. */
3318 make_insn_raw (rtx pattern
)
3322 insn
= rtx_alloc (INSN
);
3324 INSN_UID (insn
) = cur_insn_uid
++;
3325 PATTERN (insn
) = pattern
;
3326 INSN_CODE (insn
) = -1;
3327 REG_NOTES (insn
) = NULL
;
3328 INSN_LOCATOR (insn
) = curr_insn_locator ();
3329 BLOCK_FOR_INSN (insn
) = NULL
;
3331 #ifdef ENABLE_RTL_CHECKING
3334 && (returnjump_p (insn
)
3335 || (GET_CODE (insn
) == SET
3336 && SET_DEST (insn
) == pc_rtx
)))
3338 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
3346 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
3349 make_jump_insn_raw (rtx pattern
)
3353 insn
= rtx_alloc (JUMP_INSN
);
3354 INSN_UID (insn
) = cur_insn_uid
++;
3356 PATTERN (insn
) = pattern
;
3357 INSN_CODE (insn
) = -1;
3358 REG_NOTES (insn
) = NULL
;
3359 JUMP_LABEL (insn
) = NULL
;
3360 INSN_LOCATOR (insn
) = curr_insn_locator ();
3361 BLOCK_FOR_INSN (insn
) = NULL
;
3366 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
3369 make_call_insn_raw (rtx pattern
)
3373 insn
= rtx_alloc (CALL_INSN
);
3374 INSN_UID (insn
) = cur_insn_uid
++;
3376 PATTERN (insn
) = pattern
;
3377 INSN_CODE (insn
) = -1;
3378 REG_NOTES (insn
) = NULL
;
3379 CALL_INSN_FUNCTION_USAGE (insn
) = NULL
;
3380 INSN_LOCATOR (insn
) = curr_insn_locator ();
3381 BLOCK_FOR_INSN (insn
) = NULL
;
3386 /* Add INSN to the end of the doubly-linked list.
3387 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
3392 PREV_INSN (insn
) = last_insn
;
3393 NEXT_INSN (insn
) = 0;
3395 if (NULL
!= last_insn
)
3396 NEXT_INSN (last_insn
) = insn
;
3398 if (NULL
== first_insn
)
3404 /* Add INSN into the doubly-linked list after insn AFTER. This and
3405 the next should be the only functions called to insert an insn once
3406 delay slots have been filled since only they know how to update a
3410 add_insn_after (rtx insn
, rtx after
, basic_block bb
)
3412 rtx next
= NEXT_INSN (after
);
3414 gcc_assert (!optimize
|| !INSN_DELETED_P (after
));
3416 NEXT_INSN (insn
) = next
;
3417 PREV_INSN (insn
) = after
;
3421 PREV_INSN (next
) = insn
;
3422 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3423 PREV_INSN (XVECEXP (PATTERN (next
), 0, 0)) = insn
;
3425 else if (last_insn
== after
)
3429 struct sequence_stack
*stack
= seq_stack
;
3430 /* Scan all pending sequences too. */
3431 for (; stack
; stack
= stack
->next
)
3432 if (after
== stack
->last
)
3441 if (!BARRIER_P (after
)
3442 && !BARRIER_P (insn
)
3443 && (bb
= BLOCK_FOR_INSN (after
)))
3445 set_block_for_insn (insn
, bb
);
3447 df_insn_rescan (insn
);
3448 /* Should not happen as first in the BB is always
3449 either NOTE or LABEL. */
3450 if (BB_END (bb
) == after
3451 /* Avoid clobbering of structure when creating new BB. */
3452 && !BARRIER_P (insn
)
3453 && !NOTE_INSN_BASIC_BLOCK_P (insn
))
3457 NEXT_INSN (after
) = insn
;
3458 if (NONJUMP_INSN_P (after
) && GET_CODE (PATTERN (after
)) == SEQUENCE
)
3460 rtx sequence
= PATTERN (after
);
3461 NEXT_INSN (XVECEXP (sequence
, 0, XVECLEN (sequence
, 0) - 1)) = insn
;
3465 /* Add INSN into the doubly-linked list before insn BEFORE. This and
3466 the previous should be the only functions called to insert an insn
3467 once delay slots have been filled since only they know how to
3468 update a SEQUENCE. If BB is NULL, an attempt is made to infer the
3472 add_insn_before (rtx insn
, rtx before
, basic_block bb
)
3474 rtx prev
= PREV_INSN (before
);
3476 gcc_assert (!optimize
|| !INSN_DELETED_P (before
));
3478 PREV_INSN (insn
) = prev
;
3479 NEXT_INSN (insn
) = before
;
3483 NEXT_INSN (prev
) = insn
;
3484 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3486 rtx sequence
= PATTERN (prev
);
3487 NEXT_INSN (XVECEXP (sequence
, 0, XVECLEN (sequence
, 0) - 1)) = insn
;
3490 else if (first_insn
== before
)
3494 struct sequence_stack
*stack
= seq_stack
;
3495 /* Scan all pending sequences too. */
3496 for (; stack
; stack
= stack
->next
)
3497 if (before
== stack
->first
)
3499 stack
->first
= insn
;
3507 && !BARRIER_P (before
)
3508 && !BARRIER_P (insn
))
3509 bb
= BLOCK_FOR_INSN (before
);
3513 set_block_for_insn (insn
, bb
);
3515 df_insn_rescan (insn
);
3516 /* Should not happen as first in the BB is always either NOTE or
3518 gcc_assert (BB_HEAD (bb
) != insn
3519 /* Avoid clobbering of structure when creating new BB. */
3521 || NOTE_INSN_BASIC_BLOCK_P (insn
));
3524 PREV_INSN (before
) = insn
;
3525 if (NONJUMP_INSN_P (before
) && GET_CODE (PATTERN (before
)) == SEQUENCE
)
3526 PREV_INSN (XVECEXP (PATTERN (before
), 0, 0)) = insn
;
3530 /* Replace insn with an deleted instruction note. */
3532 void set_insn_deleted (rtx insn
)
3534 df_insn_delete (BLOCK_FOR_INSN (insn
), INSN_UID (insn
));
3535 PUT_CODE (insn
, NOTE
);
3536 NOTE_KIND (insn
) = NOTE_INSN_DELETED
;
3540 /* Remove an insn from its doubly-linked list. This function knows how
3541 to handle sequences. */
3543 remove_insn (rtx insn
)
3545 rtx next
= NEXT_INSN (insn
);
3546 rtx prev
= PREV_INSN (insn
);
3549 /* Later in the code, the block will be marked dirty. */
3550 df_insn_delete (NULL
, INSN_UID (insn
));
3554 NEXT_INSN (prev
) = next
;
3555 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3557 rtx sequence
= PATTERN (prev
);
3558 NEXT_INSN (XVECEXP (sequence
, 0, XVECLEN (sequence
, 0) - 1)) = next
;
3561 else if (first_insn
== insn
)
3565 struct sequence_stack
*stack
= seq_stack
;
3566 /* Scan all pending sequences too. */
3567 for (; stack
; stack
= stack
->next
)
3568 if (insn
== stack
->first
)
3570 stack
->first
= next
;
3579 PREV_INSN (next
) = prev
;
3580 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3581 PREV_INSN (XVECEXP (PATTERN (next
), 0, 0)) = prev
;
3583 else if (last_insn
== insn
)
3587 struct sequence_stack
*stack
= seq_stack
;
3588 /* Scan all pending sequences too. */
3589 for (; stack
; stack
= stack
->next
)
3590 if (insn
== stack
->last
)
3598 if (!BARRIER_P (insn
)
3599 && (bb
= BLOCK_FOR_INSN (insn
)))
3602 df_set_bb_dirty (bb
);
3603 if (BB_HEAD (bb
) == insn
)
3605 /* Never ever delete the basic block note without deleting whole
3607 gcc_assert (!NOTE_P (insn
));
3608 BB_HEAD (bb
) = next
;
3610 if (BB_END (bb
) == insn
)
3615 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
3618 add_function_usage_to (rtx call_insn
, rtx call_fusage
)
3620 gcc_assert (call_insn
&& CALL_P (call_insn
));
3622 /* Put the register usage information on the CALL. If there is already
3623 some usage information, put ours at the end. */
3624 if (CALL_INSN_FUNCTION_USAGE (call_insn
))
3628 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); XEXP (link
, 1) != 0;
3629 link
= XEXP (link
, 1))
3632 XEXP (link
, 1) = call_fusage
;
3635 CALL_INSN_FUNCTION_USAGE (call_insn
) = call_fusage
;
3638 /* Delete all insns made since FROM.
3639 FROM becomes the new last instruction. */
3642 delete_insns_since (rtx from
)
3647 NEXT_INSN (from
) = 0;
3651 /* This function is deprecated, please use sequences instead.
3653 Move a consecutive bunch of insns to a different place in the chain.
3654 The insns to be moved are those between FROM and TO.
3655 They are moved to a new position after the insn AFTER.
3656 AFTER must not be FROM or TO or any insn in between.
3658 This function does not know about SEQUENCEs and hence should not be
3659 called after delay-slot filling has been done. */
3662 reorder_insns_nobb (rtx from
, rtx to
, rtx after
)
3664 /* Splice this bunch out of where it is now. */
3665 if (PREV_INSN (from
))
3666 NEXT_INSN (PREV_INSN (from
)) = NEXT_INSN (to
);
3668 PREV_INSN (NEXT_INSN (to
)) = PREV_INSN (from
);
3669 if (last_insn
== to
)
3670 last_insn
= PREV_INSN (from
);
3671 if (first_insn
== from
)
3672 first_insn
= NEXT_INSN (to
);
3674 /* Make the new neighbors point to it and it to them. */
3675 if (NEXT_INSN (after
))
3676 PREV_INSN (NEXT_INSN (after
)) = to
;
3678 NEXT_INSN (to
) = NEXT_INSN (after
);
3679 PREV_INSN (from
) = after
;
3680 NEXT_INSN (after
) = from
;
3681 if (after
== last_insn
)
3685 /* Same as function above, but take care to update BB boundaries. */
3687 reorder_insns (rtx from
, rtx to
, rtx after
)
3689 rtx prev
= PREV_INSN (from
);
3690 basic_block bb
, bb2
;
3692 reorder_insns_nobb (from
, to
, after
);
3694 if (!BARRIER_P (after
)
3695 && (bb
= BLOCK_FOR_INSN (after
)))
3698 df_set_bb_dirty (bb
);
3700 if (!BARRIER_P (from
)
3701 && (bb2
= BLOCK_FOR_INSN (from
)))
3703 if (BB_END (bb2
) == to
)
3704 BB_END (bb2
) = prev
;
3705 df_set_bb_dirty (bb2
);
3708 if (BB_END (bb
) == after
)
3711 for (x
= from
; x
!= NEXT_INSN (to
); x
= NEXT_INSN (x
))
3714 set_block_for_insn (x
, bb
);
3715 df_insn_change_bb (x
);
3721 /* Emit insn(s) of given code and pattern
3722 at a specified place within the doubly-linked list.
3724 All of the emit_foo global entry points accept an object
3725 X which is either an insn list or a PATTERN of a single
3728 There are thus a few canonical ways to generate code and
3729 emit it at a specific place in the instruction stream. For
3730 example, consider the instruction named SPOT and the fact that
3731 we would like to emit some instructions before SPOT. We might
3735 ... emit the new instructions ...
3736 insns_head = get_insns ();
3739 emit_insn_before (insns_head, SPOT);
3741 It used to be common to generate SEQUENCE rtl instead, but that
3742 is a relic of the past which no longer occurs. The reason is that
3743 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
3744 generated would almost certainly die right after it was created. */
3746 /* Make X be output before the instruction BEFORE. */
3749 emit_insn_before_noloc (rtx x
, rtx before
, basic_block bb
)
3754 gcc_assert (before
);
3759 switch (GET_CODE (x
))
3770 rtx next
= NEXT_INSN (insn
);
3771 add_insn_before (insn
, before
, bb
);
3777 #ifdef ENABLE_RTL_CHECKING
3784 last
= make_insn_raw (x
);
3785 add_insn_before (last
, before
, bb
);
3792 /* Make an instruction with body X and code JUMP_INSN
3793 and output it before the instruction BEFORE. */
3796 emit_jump_insn_before_noloc (rtx x
, rtx before
)
3798 rtx insn
, last
= NULL_RTX
;
3800 gcc_assert (before
);
3802 switch (GET_CODE (x
))
3813 rtx next
= NEXT_INSN (insn
);
3814 add_insn_before (insn
, before
, NULL
);
3820 #ifdef ENABLE_RTL_CHECKING
3827 last
= make_jump_insn_raw (x
);
3828 add_insn_before (last
, before
, NULL
);
3835 /* Make an instruction with body X and code CALL_INSN
3836 and output it before the instruction BEFORE. */
3839 emit_call_insn_before_noloc (rtx x
, rtx before
)
3841 rtx last
= NULL_RTX
, insn
;
3843 gcc_assert (before
);
3845 switch (GET_CODE (x
))
3856 rtx next
= NEXT_INSN (insn
);
3857 add_insn_before (insn
, before
, NULL
);
3863 #ifdef ENABLE_RTL_CHECKING
3870 last
= make_call_insn_raw (x
);
3871 add_insn_before (last
, before
, NULL
);
3878 /* Make an insn of code BARRIER
3879 and output it before the insn BEFORE. */
3882 emit_barrier_before (rtx before
)
3884 rtx insn
= rtx_alloc (BARRIER
);
3886 INSN_UID (insn
) = cur_insn_uid
++;
3888 add_insn_before (insn
, before
, NULL
);
3892 /* Emit the label LABEL before the insn BEFORE. */
3895 emit_label_before (rtx label
, rtx before
)
3897 /* This can be called twice for the same label as a result of the
3898 confusion that follows a syntax error! So make it harmless. */
3899 if (INSN_UID (label
) == 0)
3901 INSN_UID (label
) = cur_insn_uid
++;
3902 add_insn_before (label
, before
, NULL
);
3908 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
3911 emit_note_before (enum insn_note subtype
, rtx before
)
3913 rtx note
= rtx_alloc (NOTE
);
3914 INSN_UID (note
) = cur_insn_uid
++;
3915 NOTE_KIND (note
) = subtype
;
3916 BLOCK_FOR_INSN (note
) = NULL
;
3917 memset (&NOTE_DATA (note
), 0, sizeof (NOTE_DATA (note
)));
3919 add_insn_before (note
, before
, NULL
);
3923 /* Helper for emit_insn_after, handles lists of instructions
3927 emit_insn_after_1 (rtx first
, rtx after
, basic_block bb
)
3931 if (!bb
&& !BARRIER_P (after
))
3932 bb
= BLOCK_FOR_INSN (after
);
3936 df_set_bb_dirty (bb
);
3937 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
3938 if (!BARRIER_P (last
))
3940 set_block_for_insn (last
, bb
);
3941 df_insn_rescan (last
);
3943 if (!BARRIER_P (last
))
3945 set_block_for_insn (last
, bb
);
3946 df_insn_rescan (last
);
3948 if (BB_END (bb
) == after
)
3952 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
3955 after_after
= NEXT_INSN (after
);
3957 NEXT_INSN (after
) = first
;
3958 PREV_INSN (first
) = after
;
3959 NEXT_INSN (last
) = after_after
;
3961 PREV_INSN (after_after
) = last
;
3963 if (after
== last_insn
)
3968 /* Make X be output after the insn AFTER and set the BB of insn. If
3969 BB is NULL, an attempt is made to infer the BB from AFTER. */
3972 emit_insn_after_noloc (rtx x
, rtx after
, basic_block bb
)
3981 switch (GET_CODE (x
))
3989 last
= emit_insn_after_1 (x
, after
, bb
);
3992 #ifdef ENABLE_RTL_CHECKING
3999 last
= make_insn_raw (x
);
4000 add_insn_after (last
, after
, bb
);
4008 /* Make an insn of code JUMP_INSN with body X
4009 and output it after the insn AFTER. */
4012 emit_jump_insn_after_noloc (rtx x
, rtx after
)
4018 switch (GET_CODE (x
))
4026 last
= emit_insn_after_1 (x
, after
, NULL
);
4029 #ifdef ENABLE_RTL_CHECKING
4036 last
= make_jump_insn_raw (x
);
4037 add_insn_after (last
, after
, NULL
);
4044 /* Make an instruction with body X and code CALL_INSN
4045 and output it after the instruction AFTER. */
4048 emit_call_insn_after_noloc (rtx x
, rtx after
)
4054 switch (GET_CODE (x
))
4062 last
= emit_insn_after_1 (x
, after
, NULL
);
4065 #ifdef ENABLE_RTL_CHECKING
4072 last
= make_call_insn_raw (x
);
4073 add_insn_after (last
, after
, NULL
);
4080 /* Make an insn of code BARRIER
4081 and output it after the insn AFTER. */
4084 emit_barrier_after (rtx after
)
4086 rtx insn
= rtx_alloc (BARRIER
);
4088 INSN_UID (insn
) = cur_insn_uid
++;
4090 add_insn_after (insn
, after
, NULL
);
4094 /* Emit the label LABEL after the insn AFTER. */
4097 emit_label_after (rtx label
, rtx after
)
4099 /* This can be called twice for the same label
4100 as a result of the confusion that follows a syntax error!
4101 So make it harmless. */
4102 if (INSN_UID (label
) == 0)
4104 INSN_UID (label
) = cur_insn_uid
++;
4105 add_insn_after (label
, after
, NULL
);
4111 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4114 emit_note_after (enum insn_note subtype
, rtx after
)
4116 rtx note
= rtx_alloc (NOTE
);
4117 INSN_UID (note
) = cur_insn_uid
++;
4118 NOTE_KIND (note
) = subtype
;
4119 BLOCK_FOR_INSN (note
) = NULL
;
4120 memset (&NOTE_DATA (note
), 0, sizeof (NOTE_DATA (note
)));
4121 add_insn_after (note
, after
, NULL
);
4125 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4127 emit_insn_after_setloc (rtx pattern
, rtx after
, int loc
)
4129 rtx last
= emit_insn_after_noloc (pattern
, after
, NULL
);
4131 if (pattern
== NULL_RTX
|| !loc
)
4134 after
= NEXT_INSN (after
);
4137 if (active_insn_p (after
) && !INSN_LOCATOR (after
))
4138 INSN_LOCATOR (after
) = loc
;
4141 after
= NEXT_INSN (after
);
4146 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4148 emit_insn_after (rtx pattern
, rtx after
)
4151 return emit_insn_after_setloc (pattern
, after
, INSN_LOCATOR (after
));
4153 return emit_insn_after_noloc (pattern
, after
, NULL
);
4156 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4158 emit_jump_insn_after_setloc (rtx pattern
, rtx after
, int loc
)
4160 rtx last
= emit_jump_insn_after_noloc (pattern
, after
);
4162 if (pattern
== NULL_RTX
|| !loc
)
4165 after
= NEXT_INSN (after
);
4168 if (active_insn_p (after
) && !INSN_LOCATOR (after
))
4169 INSN_LOCATOR (after
) = loc
;
4172 after
= NEXT_INSN (after
);
4177 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4179 emit_jump_insn_after (rtx pattern
, rtx after
)
4182 return emit_jump_insn_after_setloc (pattern
, after
, INSN_LOCATOR (after
));
4184 return emit_jump_insn_after_noloc (pattern
, after
);
4187 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4189 emit_call_insn_after_setloc (rtx pattern
, rtx after
, int loc
)
4191 rtx last
= emit_call_insn_after_noloc (pattern
, after
);
4193 if (pattern
== NULL_RTX
|| !loc
)
4196 after
= NEXT_INSN (after
);
4199 if (active_insn_p (after
) && !INSN_LOCATOR (after
))
4200 INSN_LOCATOR (after
) = loc
;
4203 after
= NEXT_INSN (after
);
4208 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4210 emit_call_insn_after (rtx pattern
, rtx after
)
4213 return emit_call_insn_after_setloc (pattern
, after
, INSN_LOCATOR (after
));
4215 return emit_call_insn_after_noloc (pattern
, after
);
4218 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */
4220 emit_insn_before_setloc (rtx pattern
, rtx before
, int loc
)
4222 rtx first
= PREV_INSN (before
);
4223 rtx last
= emit_insn_before_noloc (pattern
, before
, NULL
);
4225 if (pattern
== NULL_RTX
|| !loc
)
4229 first
= get_insns ();
4231 first
= NEXT_INSN (first
);
4234 if (active_insn_p (first
) && !INSN_LOCATOR (first
))
4235 INSN_LOCATOR (first
) = loc
;
4238 first
= NEXT_INSN (first
);
4243 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4245 emit_insn_before (rtx pattern
, rtx before
)
4247 if (INSN_P (before
))
4248 return emit_insn_before_setloc (pattern
, before
, INSN_LOCATOR (before
));
4250 return emit_insn_before_noloc (pattern
, before
, NULL
);
4253 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4255 emit_jump_insn_before_setloc (rtx pattern
, rtx before
, int loc
)
4257 rtx first
= PREV_INSN (before
);
4258 rtx last
= emit_jump_insn_before_noloc (pattern
, before
);
4260 if (pattern
== NULL_RTX
)
4263 first
= NEXT_INSN (first
);
4266 if (active_insn_p (first
) && !INSN_LOCATOR (first
))
4267 INSN_LOCATOR (first
) = loc
;
4270 first
= NEXT_INSN (first
);
4275 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4277 emit_jump_insn_before (rtx pattern
, rtx before
)
4279 if (INSN_P (before
))
4280 return emit_jump_insn_before_setloc (pattern
, before
, INSN_LOCATOR (before
));
4282 return emit_jump_insn_before_noloc (pattern
, before
);
4285 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4287 emit_call_insn_before_setloc (rtx pattern
, rtx before
, int loc
)
4289 rtx first
= PREV_INSN (before
);
4290 rtx last
= emit_call_insn_before_noloc (pattern
, before
);
4292 if (pattern
== NULL_RTX
)
4295 first
= NEXT_INSN (first
);
4298 if (active_insn_p (first
) && !INSN_LOCATOR (first
))
4299 INSN_LOCATOR (first
) = loc
;
4302 first
= NEXT_INSN (first
);
4307 /* like emit_call_insn_before_noloc,
4308 but set insn_locator according to before. */
4310 emit_call_insn_before (rtx pattern
, rtx before
)
4312 if (INSN_P (before
))
4313 return emit_call_insn_before_setloc (pattern
, before
, INSN_LOCATOR (before
));
4315 return emit_call_insn_before_noloc (pattern
, before
);
4318 /* Take X and emit it at the end of the doubly-linked
4321 Returns the last insn emitted. */
4326 rtx last
= last_insn
;
4332 switch (GET_CODE (x
))
4343 rtx next
= NEXT_INSN (insn
);
4350 #ifdef ENABLE_RTL_CHECKING
4357 last
= make_insn_raw (x
);
4365 /* Make an insn of code JUMP_INSN with pattern X
4366 and add it to the end of the doubly-linked list. */
4369 emit_jump_insn (rtx x
)
4371 rtx last
= NULL_RTX
, insn
;
4373 switch (GET_CODE (x
))
4384 rtx next
= NEXT_INSN (insn
);
4391 #ifdef ENABLE_RTL_CHECKING
4398 last
= make_jump_insn_raw (x
);
4406 /* Make an insn of code CALL_INSN with pattern X
4407 and add it to the end of the doubly-linked list. */
4410 emit_call_insn (rtx x
)
4414 switch (GET_CODE (x
))
4422 insn
= emit_insn (x
);
4425 #ifdef ENABLE_RTL_CHECKING
4432 insn
= make_call_insn_raw (x
);
4440 /* Add the label LABEL to the end of the doubly-linked list. */
4443 emit_label (rtx label
)
4445 /* This can be called twice for the same label
4446 as a result of the confusion that follows a syntax error!
4447 So make it harmless. */
4448 if (INSN_UID (label
) == 0)
4450 INSN_UID (label
) = cur_insn_uid
++;
4456 /* Make an insn of code BARRIER
4457 and add it to the end of the doubly-linked list. */
4462 rtx barrier
= rtx_alloc (BARRIER
);
4463 INSN_UID (barrier
) = cur_insn_uid
++;
4468 /* Emit a copy of note ORIG. */
4471 emit_note_copy (rtx orig
)
4475 note
= rtx_alloc (NOTE
);
4477 INSN_UID (note
) = cur_insn_uid
++;
4478 NOTE_DATA (note
) = NOTE_DATA (orig
);
4479 NOTE_KIND (note
) = NOTE_KIND (orig
);
4480 BLOCK_FOR_INSN (note
) = NULL
;
4486 /* Make an insn of code NOTE or type NOTE_NO
4487 and add it to the end of the doubly-linked list. */
4490 emit_note (enum insn_note kind
)
4494 note
= rtx_alloc (NOTE
);
4495 INSN_UID (note
) = cur_insn_uid
++;
4496 NOTE_KIND (note
) = kind
;
4497 memset (&NOTE_DATA (note
), 0, sizeof (NOTE_DATA (note
)));
4498 BLOCK_FOR_INSN (note
) = NULL
;
4503 /* Cause next statement to emit a line note even if the line number
4507 force_next_line_note (void)
4509 #ifdef USE_MAPPED_LOCATION
4512 last_location
.line
= -1;
4516 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
4517 note of this type already exists, remove it first. */
4520 set_unique_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
4522 rtx note
= find_reg_note (insn
, kind
, NULL_RTX
);
4523 rtx new_note
= NULL
;
4529 /* Don't add REG_EQUAL/REG_EQUIV notes if the insn
4530 has multiple sets (some callers assume single_set
4531 means the insn only has one set, when in fact it
4532 means the insn only has one * useful * set). */
4533 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
4539 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
4540 It serves no useful purpose and breaks eliminate_regs. */
4541 if (GET_CODE (datum
) == ASM_OPERANDS
)
4546 XEXP (note
, 0) = datum
;
4547 df_notes_rescan (insn
);
4555 XEXP (note
, 0) = datum
;
4561 new_note
= gen_rtx_EXPR_LIST (kind
, datum
, REG_NOTES (insn
));
4562 REG_NOTES (insn
) = new_note
;
4568 df_notes_rescan (insn
);
4574 return REG_NOTES (insn
);
4577 /* Return an indication of which type of insn should have X as a body.
4578 The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */
4580 static enum rtx_code
4581 classify_insn (rtx x
)
4585 if (GET_CODE (x
) == CALL
)
4587 if (GET_CODE (x
) == RETURN
)
4589 if (GET_CODE (x
) == SET
)
4591 if (SET_DEST (x
) == pc_rtx
)
4593 else if (GET_CODE (SET_SRC (x
)) == CALL
)
4598 if (GET_CODE (x
) == PARALLEL
)
4601 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
4602 if (GET_CODE (XVECEXP (x
, 0, j
)) == CALL
)
4604 else if (GET_CODE (XVECEXP (x
, 0, j
)) == SET
4605 && SET_DEST (XVECEXP (x
, 0, j
)) == pc_rtx
)
4607 else if (GET_CODE (XVECEXP (x
, 0, j
)) == SET
4608 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == CALL
)
4614 /* Emit the rtl pattern X as an appropriate kind of insn.
4615 If X is a label, it is simply added into the insn chain. */
4620 enum rtx_code code
= classify_insn (x
);
4625 return emit_label (x
);
4627 return emit_insn (x
);
4630 rtx insn
= emit_jump_insn (x
);
4631 if (any_uncondjump_p (insn
) || GET_CODE (x
) == RETURN
)
4632 return emit_barrier ();
4636 return emit_call_insn (x
);
4642 /* Space for free sequence stack entries. */
4643 static GTY ((deletable
)) struct sequence_stack
*free_sequence_stack
;
4645 /* Begin emitting insns to a sequence. If this sequence will contain
4646 something that might cause the compiler to pop arguments to function
4647 calls (because those pops have previously been deferred; see
4648 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
4649 before calling this function. That will ensure that the deferred
4650 pops are not accidentally emitted in the middle of this sequence. */
4653 start_sequence (void)
4655 struct sequence_stack
*tem
;
4657 if (free_sequence_stack
!= NULL
)
4659 tem
= free_sequence_stack
;
4660 free_sequence_stack
= tem
->next
;
4663 tem
= ggc_alloc (sizeof (struct sequence_stack
));
4665 tem
->next
= seq_stack
;
4666 tem
->first
= first_insn
;
4667 tem
->last
= last_insn
;
4675 /* Set up the insn chain starting with FIRST as the current sequence,
4676 saving the previously current one. See the documentation for
4677 start_sequence for more information about how to use this function. */
4680 push_to_sequence (rtx first
)
4686 for (last
= first
; last
&& NEXT_INSN (last
); last
= NEXT_INSN (last
));
4692 /* Like push_to_sequence, but take the last insn as an argument to avoid
4693 looping through the list. */
4696 push_to_sequence2 (rtx first
, rtx last
)
4704 /* Set up the outer-level insn chain
4705 as the current sequence, saving the previously current one. */
4708 push_topmost_sequence (void)
4710 struct sequence_stack
*stack
, *top
= NULL
;
4714 for (stack
= seq_stack
; stack
; stack
= stack
->next
)
4717 first_insn
= top
->first
;
4718 last_insn
= top
->last
;
4721 /* After emitting to the outer-level insn chain, update the outer-level
4722 insn chain, and restore the previous saved state. */
4725 pop_topmost_sequence (void)
4727 struct sequence_stack
*stack
, *top
= NULL
;
4729 for (stack
= seq_stack
; stack
; stack
= stack
->next
)
4732 top
->first
= first_insn
;
4733 top
->last
= last_insn
;
4738 /* After emitting to a sequence, restore previous saved state.
4740 To get the contents of the sequence just made, you must call
4741 `get_insns' *before* calling here.
4743 If the compiler might have deferred popping arguments while
4744 generating this sequence, and this sequence will not be immediately
4745 inserted into the instruction stream, use do_pending_stack_adjust
4746 before calling get_insns. That will ensure that the deferred
4747 pops are inserted into this sequence, and not into some random
4748 location in the instruction stream. See INHIBIT_DEFER_POP for more
4749 information about deferred popping of arguments. */
4754 struct sequence_stack
*tem
= seq_stack
;
4756 first_insn
= tem
->first
;
4757 last_insn
= tem
->last
;
4758 seq_stack
= tem
->next
;
4760 memset (tem
, 0, sizeof (*tem
));
4761 tem
->next
= free_sequence_stack
;
4762 free_sequence_stack
= tem
;
4765 /* Return 1 if currently emitting into a sequence. */
4768 in_sequence_p (void)
4770 return seq_stack
!= 0;
4773 /* Put the various virtual registers into REGNO_REG_RTX. */
4776 init_virtual_regs (struct emit_status
*es
)
4778 rtx
*ptr
= es
->x_regno_reg_rtx
;
4779 ptr
[VIRTUAL_INCOMING_ARGS_REGNUM
] = virtual_incoming_args_rtx
;
4780 ptr
[VIRTUAL_STACK_VARS_REGNUM
] = virtual_stack_vars_rtx
;
4781 ptr
[VIRTUAL_STACK_DYNAMIC_REGNUM
] = virtual_stack_dynamic_rtx
;
4782 ptr
[VIRTUAL_OUTGOING_ARGS_REGNUM
] = virtual_outgoing_args_rtx
;
4783 ptr
[VIRTUAL_CFA_REGNUM
] = virtual_cfa_rtx
;
4787 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
4788 static rtx copy_insn_scratch_in
[MAX_RECOG_OPERANDS
];
4789 static rtx copy_insn_scratch_out
[MAX_RECOG_OPERANDS
];
4790 static int copy_insn_n_scratches
;
4792 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
4793 copied an ASM_OPERANDS.
4794 In that case, it is the original input-operand vector. */
4795 static rtvec orig_asm_operands_vector
;
4797 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
4798 copied an ASM_OPERANDS.
4799 In that case, it is the copied input-operand vector. */
4800 static rtvec copy_asm_operands_vector
;
4802 /* Likewise for the constraints vector. */
4803 static rtvec orig_asm_constraints_vector
;
4804 static rtvec copy_asm_constraints_vector
;
4806 /* Recursively create a new copy of an rtx for copy_insn.
4807 This function differs from copy_rtx in that it handles SCRATCHes and
4808 ASM_OPERANDs properly.
4809 Normally, this function is not used directly; use copy_insn as front end.
4810 However, you could first copy an insn pattern with copy_insn and then use
4811 this function afterwards to properly copy any REG_NOTEs containing
4815 copy_insn_1 (rtx orig
)
4820 const char *format_ptr
;
4822 code
= GET_CODE (orig
);
4836 if (REG_P (XEXP (orig
, 0)) && REGNO (XEXP (orig
, 0)) < FIRST_PSEUDO_REGISTER
)
4841 for (i
= 0; i
< copy_insn_n_scratches
; i
++)
4842 if (copy_insn_scratch_in
[i
] == orig
)
4843 return copy_insn_scratch_out
[i
];
4847 if (shared_const_p (orig
))
4851 /* A MEM with a constant address is not sharable. The problem is that
4852 the constant address may need to be reloaded. If the mem is shared,
4853 then reloading one copy of this mem will cause all copies to appear
4854 to have been reloaded. */
4860 /* Copy the various flags, fields, and other information. We assume
4861 that all fields need copying, and then clear the fields that should
4862 not be copied. That is the sensible default behavior, and forces
4863 us to explicitly document why we are *not* copying a flag. */
4864 copy
= shallow_copy_rtx (orig
);
4866 /* We do not copy the USED flag, which is used as a mark bit during
4867 walks over the RTL. */
4868 RTX_FLAG (copy
, used
) = 0;
4870 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
4873 RTX_FLAG (copy
, jump
) = 0;
4874 RTX_FLAG (copy
, call
) = 0;
4875 RTX_FLAG (copy
, frame_related
) = 0;
4878 format_ptr
= GET_RTX_FORMAT (GET_CODE (copy
));
4880 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (copy
)); i
++)
4881 switch (*format_ptr
++)
4884 if (XEXP (orig
, i
) != NULL
)
4885 XEXP (copy
, i
) = copy_insn_1 (XEXP (orig
, i
));
4890 if (XVEC (orig
, i
) == orig_asm_constraints_vector
)
4891 XVEC (copy
, i
) = copy_asm_constraints_vector
;
4892 else if (XVEC (orig
, i
) == orig_asm_operands_vector
)
4893 XVEC (copy
, i
) = copy_asm_operands_vector
;
4894 else if (XVEC (orig
, i
) != NULL
)
4896 XVEC (copy
, i
) = rtvec_alloc (XVECLEN (orig
, i
));
4897 for (j
= 0; j
< XVECLEN (copy
, i
); j
++)
4898 XVECEXP (copy
, i
, j
) = copy_insn_1 (XVECEXP (orig
, i
, j
));
4909 /* These are left unchanged. */
4916 if (code
== SCRATCH
)
4918 i
= copy_insn_n_scratches
++;
4919 gcc_assert (i
< MAX_RECOG_OPERANDS
);
4920 copy_insn_scratch_in
[i
] = orig
;
4921 copy_insn_scratch_out
[i
] = copy
;
4923 else if (code
== ASM_OPERANDS
)
4925 orig_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (orig
);
4926 copy_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (copy
);
4927 orig_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig
);
4928 copy_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy
);
4934 /* Create a new copy of an rtx.
4935 This function differs from copy_rtx in that it handles SCRATCHes and
4936 ASM_OPERANDs properly.
4937 INSN doesn't really have to be a full INSN; it could be just the
4940 copy_insn (rtx insn
)
4942 copy_insn_n_scratches
= 0;
4943 orig_asm_operands_vector
= 0;
4944 orig_asm_constraints_vector
= 0;
4945 copy_asm_operands_vector
= 0;
4946 copy_asm_constraints_vector
= 0;
4947 return copy_insn_1 (insn
);
4950 /* Initialize data structures and variables in this file
4951 before generating rtl for each function. */
4956 struct function
*f
= cfun
;
4958 f
->emit
= ggc_alloc (sizeof (struct emit_status
));
4962 reg_rtx_no
= LAST_VIRTUAL_REGISTER
+ 1;
4963 last_location
= UNKNOWN_LOCATION
;
4964 first_label_num
= label_num
;
4967 /* Init the tables that describe all the pseudo regs. */
4969 f
->emit
->regno_pointer_align_length
= LAST_VIRTUAL_REGISTER
+ 101;
4971 f
->emit
->regno_pointer_align
4972 = ggc_alloc_cleared (f
->emit
->regno_pointer_align_length
4973 * sizeof (unsigned char));
4976 = ggc_alloc (f
->emit
->regno_pointer_align_length
* sizeof (rtx
));
4978 /* Put copies of all the hard registers into regno_reg_rtx. */
4979 memcpy (regno_reg_rtx
,
4980 static_regno_reg_rtx
,
4981 FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
4983 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
4984 init_virtual_regs (f
->emit
);
4986 /* Indicate that the virtual registers and stack locations are
4988 REG_POINTER (stack_pointer_rtx
) = 1;
4989 REG_POINTER (frame_pointer_rtx
) = 1;
4990 REG_POINTER (hard_frame_pointer_rtx
) = 1;
4991 REG_POINTER (arg_pointer_rtx
) = 1;
4993 REG_POINTER (virtual_incoming_args_rtx
) = 1;
4994 REG_POINTER (virtual_stack_vars_rtx
) = 1;
4995 REG_POINTER (virtual_stack_dynamic_rtx
) = 1;
4996 REG_POINTER (virtual_outgoing_args_rtx
) = 1;
4997 REG_POINTER (virtual_cfa_rtx
) = 1;
4999 #ifdef STACK_BOUNDARY
5000 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM
) = STACK_BOUNDARY
;
5001 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5002 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5003 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) = STACK_BOUNDARY
;
5005 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5006 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM
) = STACK_BOUNDARY
;
5007 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM
) = STACK_BOUNDARY
;
5008 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5009 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM
) = BITS_PER_WORD
;
5012 #ifdef INIT_EXPANDERS
5017 /* Generate a vector constant for mode MODE and constant value CONSTANT. */
5020 gen_const_vector (enum machine_mode mode
, int constant
)
5025 enum machine_mode inner
;
5027 units
= GET_MODE_NUNITS (mode
);
5028 inner
= GET_MODE_INNER (mode
);
5030 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner
));
5032 v
= rtvec_alloc (units
);
5034 /* We need to call this function after we set the scalar const_tiny_rtx
5036 gcc_assert (const_tiny_rtx
[constant
][(int) inner
]);
5038 for (i
= 0; i
< units
; ++i
)
5039 RTVEC_ELT (v
, i
) = const_tiny_rtx
[constant
][(int) inner
];
5041 tem
= gen_rtx_raw_CONST_VECTOR (mode
, v
);
5045 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
5046 all elements are zero, and the one vector when all elements are one. */
5048 gen_rtx_CONST_VECTOR (enum machine_mode mode
, rtvec v
)
5050 enum machine_mode inner
= GET_MODE_INNER (mode
);
5051 int nunits
= GET_MODE_NUNITS (mode
);
5055 /* Check to see if all of the elements have the same value. */
5056 x
= RTVEC_ELT (v
, nunits
- 1);
5057 for (i
= nunits
- 2; i
>= 0; i
--)
5058 if (RTVEC_ELT (v
, i
) != x
)
5061 /* If the values are all the same, check to see if we can use one of the
5062 standard constant vectors. */
5065 if (x
== CONST0_RTX (inner
))
5066 return CONST0_RTX (mode
);
5067 else if (x
== CONST1_RTX (inner
))
5068 return CONST1_RTX (mode
);
5071 return gen_rtx_raw_CONST_VECTOR (mode
, v
);
5074 /* Create some permanent unique rtl objects shared between all functions.
5075 LINE_NUMBERS is nonzero if line numbers are to be generated. */
5078 init_emit_once (int line_numbers
)
5081 enum machine_mode mode
;
5082 enum machine_mode double_mode
;
5084 /* We need reg_raw_mode, so initialize the modes now. */
5085 init_reg_modes_once ();
5087 /* Initialize the CONST_INT, CONST_DOUBLE, and memory attribute hash
5089 const_int_htab
= htab_create_ggc (37, const_int_htab_hash
,
5090 const_int_htab_eq
, NULL
);
5092 const_double_htab
= htab_create_ggc (37, const_double_htab_hash
,
5093 const_double_htab_eq
, NULL
);
5095 mem_attrs_htab
= htab_create_ggc (37, mem_attrs_htab_hash
,
5096 mem_attrs_htab_eq
, NULL
);
5097 reg_attrs_htab
= htab_create_ggc (37, reg_attrs_htab_hash
,
5098 reg_attrs_htab_eq
, NULL
);
5100 no_line_numbers
= ! line_numbers
;
5102 /* Compute the word and byte modes. */
5104 byte_mode
= VOIDmode
;
5105 word_mode
= VOIDmode
;
5106 double_mode
= VOIDmode
;
5108 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
5110 mode
= GET_MODE_WIDER_MODE (mode
))
5112 if (GET_MODE_BITSIZE (mode
) == BITS_PER_UNIT
5113 && byte_mode
== VOIDmode
)
5116 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
5117 && word_mode
== VOIDmode
)
5121 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
5123 mode
= GET_MODE_WIDER_MODE (mode
))
5125 if (GET_MODE_BITSIZE (mode
) == DOUBLE_TYPE_SIZE
5126 && double_mode
== VOIDmode
)
5130 ptr_mode
= mode_for_size (POINTER_SIZE
, GET_MODE_CLASS (Pmode
), 0);
5132 /* Assign register numbers to the globally defined register rtx.
5133 This must be done at runtime because the register number field
5134 is in a union and some compilers can't initialize unions. */
5136 pc_rtx
= gen_rtx_PC (VOIDmode
);
5137 cc0_rtx
= gen_rtx_CC0 (VOIDmode
);
5138 stack_pointer_rtx
= gen_raw_REG (Pmode
, STACK_POINTER_REGNUM
);
5139 frame_pointer_rtx
= gen_raw_REG (Pmode
, FRAME_POINTER_REGNUM
);
5140 if (hard_frame_pointer_rtx
== 0)
5141 hard_frame_pointer_rtx
= gen_raw_REG (Pmode
,
5142 HARD_FRAME_POINTER_REGNUM
);
5143 if (arg_pointer_rtx
== 0)
5144 arg_pointer_rtx
= gen_raw_REG (Pmode
, ARG_POINTER_REGNUM
);
5145 virtual_incoming_args_rtx
=
5146 gen_raw_REG (Pmode
, VIRTUAL_INCOMING_ARGS_REGNUM
);
5147 virtual_stack_vars_rtx
=
5148 gen_raw_REG (Pmode
, VIRTUAL_STACK_VARS_REGNUM
);
5149 virtual_stack_dynamic_rtx
=
5150 gen_raw_REG (Pmode
, VIRTUAL_STACK_DYNAMIC_REGNUM
);
5151 virtual_outgoing_args_rtx
=
5152 gen_raw_REG (Pmode
, VIRTUAL_OUTGOING_ARGS_REGNUM
);
5153 virtual_cfa_rtx
= gen_raw_REG (Pmode
, VIRTUAL_CFA_REGNUM
);
5155 /* Initialize RTL for commonly used hard registers. These are
5156 copied into regno_reg_rtx as we begin to compile each function. */
5157 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5158 static_regno_reg_rtx
[i
] = gen_raw_REG (reg_raw_mode
[i
], i
);
5160 #ifdef INIT_EXPANDERS
5161 /* This is to initialize {init|mark|free}_machine_status before the first
5162 call to push_function_context_to. This is needed by the Chill front
5163 end which calls push_function_context_to before the first call to
5164 init_function_start. */
5168 /* Create the unique rtx's for certain rtx codes and operand values. */
5170 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
5171 tries to use these variables. */
5172 for (i
= - MAX_SAVED_CONST_INT
; i
<= MAX_SAVED_CONST_INT
; i
++)
5173 const_int_rtx
[i
+ MAX_SAVED_CONST_INT
] =
5174 gen_rtx_raw_CONST_INT (VOIDmode
, (HOST_WIDE_INT
) i
);
5176 if (STORE_FLAG_VALUE
>= - MAX_SAVED_CONST_INT
5177 && STORE_FLAG_VALUE
<= MAX_SAVED_CONST_INT
)
5178 const_true_rtx
= const_int_rtx
[STORE_FLAG_VALUE
+ MAX_SAVED_CONST_INT
];
5180 const_true_rtx
= gen_rtx_CONST_INT (VOIDmode
, STORE_FLAG_VALUE
);
5182 REAL_VALUE_FROM_INT (dconst0
, 0, 0, double_mode
);
5183 REAL_VALUE_FROM_INT (dconst1
, 1, 0, double_mode
);
5184 REAL_VALUE_FROM_INT (dconst2
, 2, 0, double_mode
);
5185 REAL_VALUE_FROM_INT (dconst3
, 3, 0, double_mode
);
5186 REAL_VALUE_FROM_INT (dconst10
, 10, 0, double_mode
);
5187 REAL_VALUE_FROM_INT (dconstm1
, -1, -1, double_mode
);
5188 REAL_VALUE_FROM_INT (dconstm2
, -2, -1, double_mode
);
5190 dconsthalf
= dconst1
;
5191 SET_REAL_EXP (&dconsthalf
, REAL_EXP (&dconsthalf
) - 1);
5193 real_arithmetic (&dconstthird
, RDIV_EXPR
, &dconst1
, &dconst3
);
5195 /* Initialize mathematical constants for constant folding builtins.
5196 These constants need to be given to at least 160 bits precision. */
5197 real_from_string (&dconstsqrt2
,
5198 "1.4142135623730950488016887242096980785696718753769480731766797379907");
5199 real_from_string (&dconste
,
5200 "2.7182818284590452353602874713526624977572470936999595749669676277241");
5202 for (i
= 0; i
< (int) ARRAY_SIZE (const_tiny_rtx
); i
++)
5204 REAL_VALUE_TYPE
*r
=
5205 (i
== 0 ? &dconst0
: i
== 1 ? &dconst1
: &dconst2
);
5207 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
5209 mode
= GET_MODE_WIDER_MODE (mode
))
5210 const_tiny_rtx
[i
][(int) mode
] =
5211 CONST_DOUBLE_FROM_REAL_VALUE (*r
, mode
);
5213 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT
);
5215 mode
= GET_MODE_WIDER_MODE (mode
))
5216 const_tiny_rtx
[i
][(int) mode
] =
5217 CONST_DOUBLE_FROM_REAL_VALUE (*r
, mode
);
5219 const_tiny_rtx
[i
][(int) VOIDmode
] = GEN_INT (i
);
5221 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
5223 mode
= GET_MODE_WIDER_MODE (mode
))
5224 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
5226 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT
);
5228 mode
= GET_MODE_WIDER_MODE (mode
))
5229 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
5232 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT
);
5234 mode
= GET_MODE_WIDER_MODE (mode
))
5236 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
5237 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
5240 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT
);
5242 mode
= GET_MODE_WIDER_MODE (mode
))
5244 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
5245 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
5248 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
5250 mode
= GET_MODE_WIDER_MODE (mode
))
5252 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
5253 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
5256 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
5258 mode
= GET_MODE_WIDER_MODE (mode
))
5260 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
5261 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
5264 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FRACT
);
5266 mode
= GET_MODE_WIDER_MODE (mode
))
5268 FCONST0(mode
).data
.high
= 0;
5269 FCONST0(mode
).data
.low
= 0;
5270 FCONST0(mode
).mode
= mode
;
5273 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_UFRACT
);
5275 mode
= GET_MODE_WIDER_MODE (mode
))
5277 FCONST0(mode
).data
.high
= 0;
5278 FCONST0(mode
).data
.low
= 0;
5279 FCONST0(mode
).mode
= mode
;
5282 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_ACCUM
);
5284 mode
= GET_MODE_WIDER_MODE (mode
))
5286 FCONST0(mode
).data
.high
= 0;
5287 FCONST0(mode
).data
.low
= 0;
5288 FCONST0(mode
).mode
= mode
;
5290 /* We store the value 1. */
5291 FCONST1(mode
).data
.high
= 0;
5292 FCONST1(mode
).data
.low
= 0;
5293 FCONST1(mode
).mode
= mode
;
5294 lshift_double (1, 0, GET_MODE_FBIT (mode
),
5295 2 * HOST_BITS_PER_WIDE_INT
,
5296 &FCONST1(mode
).data
.low
,
5297 &FCONST1(mode
).data
.high
,
5298 SIGNED_FIXED_POINT_MODE_P (mode
));
5301 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_UACCUM
);
5303 mode
= GET_MODE_WIDER_MODE (mode
))
5305 FCONST0(mode
).data
.high
= 0;
5306 FCONST0(mode
).data
.low
= 0;
5307 FCONST0(mode
).mode
= mode
;
5309 /* We store the value 1. */
5310 FCONST1(mode
).data
.high
= 0;
5311 FCONST1(mode
).data
.low
= 0;
5312 FCONST1(mode
).mode
= mode
;
5313 lshift_double (1, 0, GET_MODE_FBIT (mode
),
5314 2 * HOST_BITS_PER_WIDE_INT
,
5315 &FCONST1(mode
).data
.low
,
5316 &FCONST1(mode
).data
.high
,
5317 SIGNED_FIXED_POINT_MODE_P (mode
));
5320 for (i
= (int) CCmode
; i
< (int) MAX_MACHINE_MODE
; ++i
)
5321 if (GET_MODE_CLASS ((enum machine_mode
) i
) == MODE_CC
)
5322 const_tiny_rtx
[0][i
] = const0_rtx
;
5324 const_tiny_rtx
[0][(int) BImode
] = const0_rtx
;
5325 if (STORE_FLAG_VALUE
== 1)
5326 const_tiny_rtx
[1][(int) BImode
] = const1_rtx
;
5328 #ifdef RETURN_ADDRESS_POINTER_REGNUM
5329 return_address_pointer_rtx
5330 = gen_raw_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
);
5333 #ifdef STATIC_CHAIN_REGNUM
5334 static_chain_rtx
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5336 #ifdef STATIC_CHAIN_INCOMING_REGNUM
5337 if (STATIC_CHAIN_INCOMING_REGNUM
!= STATIC_CHAIN_REGNUM
)
5338 static_chain_incoming_rtx
5339 = gen_rtx_REG (Pmode
, STATIC_CHAIN_INCOMING_REGNUM
);
5342 static_chain_incoming_rtx
= static_chain_rtx
;
5346 static_chain_rtx
= STATIC_CHAIN
;
5348 #ifdef STATIC_CHAIN_INCOMING
5349 static_chain_incoming_rtx
= STATIC_CHAIN_INCOMING
;
5351 static_chain_incoming_rtx
= static_chain_rtx
;
5355 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
5356 pic_offset_table_rtx
= gen_raw_REG (Pmode
, PIC_OFFSET_TABLE_REGNUM
);
5359 /* Produce exact duplicate of insn INSN after AFTER.
5360 Care updating of libcall regions if present. */
5363 emit_copy_of_insn_after (rtx insn
, rtx after
)
5366 rtx note1
, note2
, link
;
5368 switch (GET_CODE (insn
))
5371 new = emit_insn_after (copy_insn (PATTERN (insn
)), after
);
5375 new = emit_jump_insn_after (copy_insn (PATTERN (insn
)), after
);
5379 new = emit_call_insn_after (copy_insn (PATTERN (insn
)), after
);
5380 if (CALL_INSN_FUNCTION_USAGE (insn
))
5381 CALL_INSN_FUNCTION_USAGE (new)
5382 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn
));
5383 SIBLING_CALL_P (new) = SIBLING_CALL_P (insn
);
5384 CONST_OR_PURE_CALL_P (new) = CONST_OR_PURE_CALL_P (insn
);
5391 /* Update LABEL_NUSES. */
5392 mark_jump_label (PATTERN (new), new, 0);
5394 INSN_LOCATOR (new) = INSN_LOCATOR (insn
);
5396 /* If the old insn is frame related, then so is the new one. This is
5397 primarily needed for IA-64 unwind info which marks epilogue insns,
5398 which may be duplicated by the basic block reordering code. */
5399 RTX_FRAME_RELATED_P (new) = RTX_FRAME_RELATED_P (insn
);
5401 /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will
5403 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
5404 if (REG_NOTE_KIND (link
) != REG_LABEL
)
5406 if (GET_CODE (link
) == EXPR_LIST
)
5408 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link
),
5409 copy_insn_1 (XEXP (link
, 0)), REG_NOTES (new));
5412 = gen_rtx_INSN_LIST (REG_NOTE_KIND (link
),
5413 XEXP (link
, 0), REG_NOTES (new));
5416 /* Fix the libcall sequences. */
5417 if ((note1
= find_reg_note (new, REG_RETVAL
, NULL_RTX
)) != NULL
)
5420 while ((note2
= find_reg_note (p
, REG_LIBCALL
, NULL_RTX
)) == NULL
)
5422 XEXP (note1
, 0) = p
;
5423 XEXP (note2
, 0) = new;
5425 INSN_CODE (new) = INSN_CODE (insn
);
5429 static GTY((deletable
)) rtx hard_reg_clobbers
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
5431 gen_hard_reg_clobber (enum machine_mode mode
, unsigned int regno
)
5433 if (hard_reg_clobbers
[mode
][regno
])
5434 return hard_reg_clobbers
[mode
][regno
];
5436 return (hard_reg_clobbers
[mode
][regno
] =
5437 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (mode
, regno
)));
5440 #include "gt-emit-rtl.h"