| blob | 6786902fac5d5d53f1d7bf1716d90e4452f3dd6d |
1 ;;- Machine description for Blackfin for GNU compiler
2 ;; Copyright 2005, 2006 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ; operand punctuation marks:
23 ;
24 ; X -- integer value printed as log2
25 ; Y -- integer value printed as log2(~value) - for bitclear
26 ; h -- print half word register, low part
27 ; d -- print half word register, high part
28 ; D -- print operand as dregs pairs
29 ; w -- print operand as accumulator register word (a0w, a1w)
30 ; H -- high part of double mode operand
31 ; T -- byte register representation Oct. 02 2001
33 ; constant operand classes
34 ;
35 ; J 2**N 5bit imm scaled
36 ; Ks7 -64 .. 63 signed 7bit imm
37 ; Ku5 0..31 unsigned 5bit imm
38 ; Ks4 -8 .. 7 signed 4bit imm
39 ; Ks3 -4 .. 3 signed 3bit imm
40 ; Ku3 0 .. 7 unsigned 3bit imm
41 ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
42 ;
43 ; register operands
44 ; d (r0..r7)
45 ; a (p0..p5,fp,sp)
46 ; e (a0, a1)
47 ; b (i0..i3)
48 ; f (m0..m3)
49 ; v (b0..b3)
50 ; c (i0..i3,m0..m3) CIRCREGS
51 ; C (CC) CCREGS
52 ; t (lt0,lt1)
53 ; k (lc0,lc1)
54 ; u (lb0,lb1)
55 ;
57 ;; Define constants for hard registers.
59 (define_constants
60 [(REG_R0 0)
61 (REG_R1 1)
62 (REG_R2 2)
63 (REG_R3 3)
64 (REG_R4 4)
65 (REG_R5 5)
66 (REG_R6 6)
67 (REG_R7 7)
69 (REG_P0 8)
70 (REG_P1 9)
71 (REG_P2 10)
72 (REG_P3 11)
73 (REG_P4 12)
74 (REG_P5 13)
75 (REG_P6 14)
76 (REG_P7 15)
78 (REG_SP 14)
79 (REG_FP 15)
81 (REG_I0 16)
82 (REG_I1 17)
83 (REG_I2 18)
84 (REG_I3 19)
86 (REG_B0 20)
87 (REG_B1 21)
88 (REG_B2 22)
89 (REG_B3 23)
91 (REG_L0 24)
92 (REG_L1 25)
93 (REG_L2 26)
94 (REG_L3 27)
96 (REG_M0 28)
97 (REG_M1 29)
98 (REG_M2 30)
99 (REG_M3 31)
101 (REG_A0 32)
102 (REG_A1 33)
104 (REG_CC 34)
105 (REG_RETS 35)
106 (REG_RETI 36)
107 (REG_RETX 37)
108 (REG_RETN 38)
109 (REG_RETE 39)
111 (REG_ASTAT 40)
112 (REG_SEQSTAT 41)
113 (REG_USP 42)
115 (REG_ARGP 43)
117 (REG_LT0 44)
118 (REG_LT1 45)
119 (REG_LC0 46)
120 (REG_LC1 47)
121 (REG_LB0 48)
122 (REG_LB1 49)])
124 ;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
126 (define_constants
127 [(UNSPEC_CBRANCH_TAKEN 0)
128 (UNSPEC_CBRANCH_NOPS 1)
129 (UNSPEC_RETURN 2)
130 (UNSPEC_MOVE_PIC 3)
131 (UNSPEC_LIBRARY_OFFSET 4)
132 (UNSPEC_PUSH_MULTIPLE 5)
133 ;; Multiply or MAC with extra CONST_INT operand specifying the macflag
134 (UNSPEC_MUL_WITH_FLAG 6)
135 (UNSPEC_MAC_WITH_FLAG 7)
136 (UNSPEC_MOVE_FDPIC 8)
137 (UNSPEC_FUNCDESC_GOT17M4 9)
138 (UNSPEC_LSETUP_END 10)
139 ;; Distinguish a 32-bit version of an insn from a 16-bit version.
140 (UNSPEC_32BIT 11)])
142 (define_constants
143 [(UNSPEC_VOLATILE_EH_RETURN 0)
144 (UNSPEC_VOLATILE_CSYNC 1)
145 (UNSPEC_VOLATILE_SSYNC 2)
146 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)])
148 (define_constants
149 [(MACFLAG_NONE 0)
150 (MACFLAG_T 1)
151 (MACFLAG_FU 2)
152 (MACFLAG_TFU 3)
153 (MACFLAG_IS 4)
154 (MACFLAG_IU 5)
155 (MACFLAG_W32 6)
156 (MACFLAG_M 7)
157 (MACFLAG_S2RND 8)
158 (MACFLAG_ISS2 9)
159 (MACFLAG_IH 10)])
161 (define_attr "type"
162 "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
163 (const_string "misc"))
165 (define_attr "addrtype" "32bit,preg,ireg"
166 (cond [(and (eq_attr "type" "mcld")
167 (and (match_operand 0 "d_register_operand" "")
168 (match_operand 1 "mem_p_address_operand" "")))
169 (const_string "preg")
170 (and (eq_attr "type" "mcld")
171 (and (match_operand 0 "d_register_operand" "")
172 (match_operand 1 "mem_i_address_operand" "")))
173 (const_string "ireg")
174 (and (eq_attr "type" "mcst")
175 (and (match_operand 1 "d_register_operand" "")
176 (match_operand 0 "mem_p_address_operand" "")))
177 (const_string "preg")
178 (and (eq_attr "type" "mcst")
179 (and (match_operand 1 "d_register_operand" "")
180 (match_operand 0 "mem_i_address_operand" "")))
181 (const_string "ireg")]
182 (const_string "32bit")))
184 ;; Scheduling definitions
186 (define_automaton "bfin")
188 (define_cpu_unit "slot0" "bfin")
189 (define_cpu_unit "slot1" "bfin")
190 (define_cpu_unit "slot2" "bfin")
192 ;; Three units used to enforce parallel issue restrictions:
193 ;; only one of the 16-bit slots can use a P register in an address,
194 ;; and only one them can be a store.
195 (define_cpu_unit "store" "bfin")
196 (define_cpu_unit "pregs" "bfin")
198 (define_reservation "core" "slot0+slot1+slot2")
200 (define_insn_reservation "alu" 1
201 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
202 "core")
204 (define_insn_reservation "imul" 3
205 (eq_attr "type" "mult")
206 "core*3")
208 (define_insn_reservation "dsp32" 1
209 (eq_attr "type" "dsp32")
210 "slot0")
212 (define_insn_reservation "load32" 1
213 (and (not (eq_attr "seq_insns" "multi"))
214 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
215 "core")
217 (define_insn_reservation "loadp" 1
218 (and (not (eq_attr "seq_insns" "multi"))
219 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
220 "(slot1|slot2)+pregs")
222 (define_insn_reservation "loadi" 1
223 (and (not (eq_attr "seq_insns" "multi"))
224 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
225 "(slot1|slot2)")
227 (define_insn_reservation "store32" 1
228 (and (not (eq_attr "seq_insns" "multi"))
229 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
230 "core")
232 (define_insn_reservation "storep" 1
233 (and (not (eq_attr "seq_insns" "multi"))
234 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg")))
235 "(slot1|slot2)+pregs+store")
237 (define_insn_reservation "storei" 1
238 (and (not (eq_attr "seq_insns" "multi"))
239 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
240 "(slot1|slot2)+store")
242 (define_insn_reservation "multi" 2
243 (eq_attr "seq_insns" "multi")
244 "core")
246 (absence_set "slot0" "slot1,slot2")
247 (absence_set "slot1" "slot2")
249 ;; Make sure genautomata knows about the maximum latency that can be produced
250 ;; by the adjust_cost function.
251 (define_insn_reservation "dummy" 5
252 (eq_attr "type" "dummy")
253 "core")
254 \f
255 ;; Operand and operator predicates
257 (include "predicates.md")
259 \f
260 ;;; FRIO branches have been optimized for code density
261 ;;; this comes at a slight cost of complexity when
262 ;;; a compiler needs to generate branches in the general
263 ;;; case. In order to generate the correct branching
264 ;;; mechanisms the compiler needs keep track of instruction
265 ;;; lengths. The follow table describes how to count instructions
266 ;;; for the FRIO architecture.
267 ;;;
268 ;;; unconditional br are 12-bit imm pcrelative branches *2
269 ;;; conditional br are 10-bit imm pcrelative branches *2
270 ;;; brcc 10-bit:
271 ;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
272 ;;; br 12-bit :
273 ;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
274 ;;; NOTE : For brcc we generate instructions such as
275 ;;; if cc jmp; jump.[sl] offset
276 ;;; offset of jump.[sl] is from the jump instruction but
277 ;;; gcc calculates length from the if cc jmp instruction
278 ;;; furthermore gcc takes the end address of the branch instruction
279 ;;; as (pc) for a forward branch
280 ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
281 ;;;
282 ;;; The way the (pc) rtx works in these calculations is somewhat odd;
283 ;;; for backward branches it's the address of the current instruction,
284 ;;; for forward branches it's the previously known address of the following
285 ;;; instruction - we have to take this into account by reducing the range
286 ;;; for a forward branch.
288 ;; Lengths for type "mvi" insns are always defined by the instructions
289 ;; themselves.
290 (define_attr "length" ""
291 (cond [(eq_attr "type" "mcld")
292 (if_then_else (match_operand 1 "effective_address_32bit_p" "")
293 (const_int 4) (const_int 2))
295 (eq_attr "type" "mcst")
296 (if_then_else (match_operand 0 "effective_address_32bit_p" "")
297 (const_int 4) (const_int 2))
299 (eq_attr "type" "move") (const_int 2)
301 (eq_attr "type" "dsp32") (const_int 4)
302 (eq_attr "type" "call") (const_int 4)
304 (eq_attr "type" "br")
305 (if_then_else (and
306 (le (minus (match_dup 0) (pc)) (const_int 4092))
307 (ge (minus (match_dup 0) (pc)) (const_int -4096)))
308 (const_int 2)
309 (const_int 4))
311 (eq_attr "type" "brcc")
312 (cond [(and
313 (le (minus (match_dup 3) (pc)) (const_int 1020))
314 (ge (minus (match_dup 3) (pc)) (const_int -1024)))
315 (const_int 2)
316 (and
317 (le (minus (match_dup 3) (pc)) (const_int 4092))
318 (ge (minus (match_dup 3) (pc)) (const_int -4094)))
319 (const_int 4)]
320 (const_int 6))
321 ]
323 (const_int 2)))
325 ;; Classify the insns into those that are one instruction and those that
326 ;; are more than one in sequence.
327 (define_attr "seq_insns" "single,multi"
328 (const_string "single"))
330 ;; Conditional moves
332 (define_expand "movsicc"
333 [(set (match_operand:SI 0 "register_operand" "")
334 (if_then_else:SI (match_operand 1 "comparison_operator" "")
335 (match_operand:SI 2 "register_operand" "")
336 (match_operand:SI 3 "register_operand" "")))]
337 ""
338 {
339 operands[1] = bfin_gen_compare (operands[1], SImode);
340 })
342 (define_insn "*movsicc_insn1"
343 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
344 (if_then_else:SI
345 (eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
346 (const_int 0))
347 (match_operand:SI 1 "register_operand" "da,0,da")
348 (match_operand:SI 2 "register_operand" "0,da,da")))]
349 ""
350 "@
351 if !cc %0 =%1; /* movsicc-1a */
352 if cc %0 =%2; /* movsicc-1b */
353 if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */"
354 [(set_attr "length" "2,2,4")
355 (set_attr "type" "movcc")
356 (set_attr "seq_insns" "*,*,multi")])
358 (define_insn "*movsicc_insn2"
359 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
360 (if_then_else:SI
361 (ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
362 (const_int 0))
363 (match_operand:SI 1 "register_operand" "0,da,da")
364 (match_operand:SI 2 "register_operand" "da,0,da")))]
365 ""
366 "@
367 if !cc %0 =%2; /* movsicc-2b */
368 if cc %0 =%1; /* movsicc-2a */
369 if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */"
370 [(set_attr "length" "2,2,4")
371 (set_attr "type" "movcc")
372 (set_attr "seq_insns" "*,*,multi")])
374 ;; Insns to load HIGH and LO_SUM
376 (define_insn "movsi_high"
377 [(set (match_operand:SI 0 "register_operand" "=x")
378 (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
379 "reload_completed"
380 "%d0 = %d1;"
381 [(set_attr "type" "mvi")
382 (set_attr "length" "4")])
384 (define_insn "movstricthi_high"
385 [(set (match_operand:SI 0 "register_operand" "+x")
386 (ior:SI (and:SI (match_dup 0) (const_int 65535))
387 (match_operand:SI 1 "immediate_operand" "i")))]
388 "reload_completed"
389 "%d0 = %d1;"
390 [(set_attr "type" "mvi")
391 (set_attr "length" "4")])
393 (define_insn "movsi_low"
394 [(set (match_operand:SI 0 "register_operand" "=x")
395 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
396 (match_operand:SI 2 "immediate_operand" "i")))]
397 "reload_completed"
398 "%h0 = %h2;"
399 [(set_attr "type" "mvi")
400 (set_attr "length" "4")])
402 (define_insn "movsi_high_pic"
403 [(set (match_operand:SI 0 "register_operand" "=x")
404 (high:SI (unspec:SI [(match_operand:SI 1 "" "")]
405 UNSPEC_MOVE_PIC)))]
406 ""
407 "%d0 = %1@GOT_LOW;"
408 [(set_attr "type" "mvi")
409 (set_attr "length" "4")])
411 (define_insn "movsi_low_pic"
412 [(set (match_operand:SI 0 "register_operand" "=x")
413 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
414 (unspec:SI [(match_operand:SI 2 "" "")]
415 UNSPEC_MOVE_PIC)))]
416 ""
417 "%h0 = %h2@GOT_HIGH;"
418 [(set_attr "type" "mvi")
419 (set_attr "length" "4")])
421 ;;; Move instructions
423 (define_insn_and_split "movdi_insn"
424 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
425 (match_operand:DI 1 "general_operand" "iFx,r,mx"))]
426 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
427 "#"
428 "reload_completed"
429 [(set (match_dup 2) (match_dup 3))
430 (set (match_dup 4) (match_dup 5))]
431 {
432 rtx lo_half[2], hi_half[2];
433 split_di (operands, 2, lo_half, hi_half);
435 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
436 {
437 operands[2] = hi_half[0];
438 operands[3] = hi_half[1];
439 operands[4] = lo_half[0];
440 operands[5] = lo_half[1];
441 }
442 else
443 {
444 operands[2] = lo_half[0];
445 operands[3] = lo_half[1];
446 operands[4] = hi_half[0];
447 operands[5] = hi_half[1];
448 }
449 })
451 (define_insn "movbi"
452 [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
453 (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
455 ""
456 "@
457 %0 = %1;
458 %0 = %1 (X);
459 %0 = B %1 (Z)%!
460 B %0 = %1;
461 CC = %1;
462 %0 = CC;
463 R0 = R0 | R0; CC = AC0;"
464 [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
465 (set_attr "length" "2,2,*,*,2,2,4")
466 (set_attr "seq_insns" "*,*,*,*,*,*,multi")])
468 (define_insn "movpdi"
469 [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
470 (match_operand:PDI 1 "general_operand" " e,e,>"))]
471 ""
472 "@
473 %0 = %1;
474 %0 = %x1; %0 = %w1;
475 %w0 = %1; %x0 = %1;"
476 [(set_attr "type" "move,mcst,mcld")
477 (set_attr "seq_insns" "*,multi,multi")])
479 (define_insn "load_accumulator"
480 [(set (match_operand:PDI 0 "register_operand" "=e")
481 (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
482 ""
483 "%0 = %1;"
484 [(set_attr "type" "move")])
486 (define_insn_and_split "load_accumulator_pair"
487 [(set (match_operand:V2PDI 0 "register_operand" "=e")
488 (sign_extend:V2PDI (vec_concat:V2SI
489 (match_operand:SI 1 "register_operand" "d")
490 (match_operand:SI 2 "register_operand" "d"))))]
491 ""
492 "#"
493 "reload_completed"
494 [(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
495 (set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
496 {
497 operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
498 operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
499 })
501 (define_insn "*pushsi_insn"
502 [(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
503 (match_operand:SI 0 "register_operand" "xy"))]
504 ""
505 "[--SP] = %0;"
506 [(set_attr "type" "mcst")
507 (set_attr "addrtype" "32bit")
508 (set_attr "length" "2")])
510 (define_insn "*popsi_insn"
511 [(set (match_operand:SI 0 "register_operand" "=d,xy")
512 (mem:SI (post_inc:SI (reg:SI REG_SP))))]
513 ""
514 "%0 = [SP++]%!"
515 [(set_attr "type" "mcld")
516 (set_attr "addrtype" "preg,32bit")
517 (set_attr "length" "2")])
519 ;; The first alternative is used to make reload choose a limited register
520 ;; class when faced with a movsi_insn that had its input operand replaced
521 ;; with a PLUS. We generally require fewer secondary reloads this way.
523 (define_insn "*movsi_insn"
524 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr")
525 (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))]
526 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
527 "@
528 %0 = %1;
529 %0 = %1;
530 %0 = %1;
531 %0 = %1;
532 %0 = %1 (X);
533 %0 = %1 (X);
534 %0 = %1 (Z);
535 #
536 %0 = %1%!
537 %0 = %1%!"
538 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
539 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
541 (define_insn "*movsi_insn32"
542 [(set (match_operand:SI 0 "register_operand" "=d,d")
543 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
544 ""
545 "@
546 %0 = ROT %1 BY 0%!
547 %0 = %0 -|- %0%!"
548 [(set_attr "type" "dsp32")])
550 (define_split
551 [(set (match_operand:SI 0 "d_register_operand" "")
552 (const_int 0))]
553 "splitting_for_sched && !optimize_size"
554 [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))])
556 (define_split
557 [(set (match_operand:SI 0 "d_register_operand" "")
558 (match_operand:SI 1 "d_register_operand" ""))]
559 "splitting_for_sched && !optimize_size"
560 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))])
562 (define_insn_and_split "*movv2hi_insn"
563 [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
564 (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
566 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
567 "@
568 #
569 %0 = %1;
570 %0 = %1%!
571 %0 = %1%!"
572 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
573 [(set (match_dup 0) (high:SI (match_dup 2)))
574 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
575 {
576 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
577 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
579 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
580 operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
581 }
582 [(set_attr "type" "move,move,mcld,mcst")
583 (set_attr "length" "2,2,*,*")])
585 (define_insn "*movhi_insn"
586 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
587 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
588 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
589 {
590 static const char *templates[] = {
591 "%0 = %1;",
592 "%0 = %1 (X);",
593 "%0 = %1 (X);",
594 "%0 = W %1 (X)%!",
595 "W %0 = %1%!",
596 "%h0 = W %1%!",
597 "W %0 = %h1%!"
598 };
599 int alt = which_alternative;
600 rtx mem = (MEM_P (operands[0]) ? operands[0]
601 : MEM_P (operands[1]) ? operands[1] : NULL_RTX);
602 if (mem && bfin_dsp_memref_p (mem))
603 alt += 2;
604 return templates[alt];
605 }
606 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
607 (set_attr "length" "2,2,4,*,*")])
609 (define_insn "*movqi_insn"
610 [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
611 (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
612 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
613 "@
614 %0 = %1;
615 %0 = %1 (X);
616 %0 = %1 (X);
617 %0 = B %1 (X)%!
618 B %0 = %1%!"
619 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
620 (set_attr "length" "2,2,4,*,*")])
622 (define_insn "*movsf_insn"
623 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
624 (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
625 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
626 "@
627 %0 = %1;
628 #
629 %0 = %1%!
630 %0 = %1%!"
631 [(set_attr "type" "move,*,mcld,mcst")])
633 (define_insn_and_split "movdf_insn"
634 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
635 (match_operand:DF 1 "general_operand" "iFx,r,mx"))]
636 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
637 "#"
638 "reload_completed"
639 [(set (match_dup 2) (match_dup 3))
640 (set (match_dup 4) (match_dup 5))]
641 {
642 rtx lo_half[2], hi_half[2];
643 split_di (operands, 2, lo_half, hi_half);
645 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
646 {
647 operands[2] = hi_half[0];
648 operands[3] = hi_half[1];
649 operands[4] = lo_half[0];
650 operands[5] = lo_half[1];
651 }
652 else
653 {
654 operands[2] = lo_half[0];
655 operands[3] = lo_half[1];
656 operands[4] = hi_half[0];
657 operands[5] = hi_half[1];
658 }
659 })
661 ;; Storing halfwords.
662 (define_insn "*movsi_insv"
663 [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
664 (const_int 16)
665 (const_int 16))
666 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
667 ""
668 "@
669 %d0 = %h1 << 0%!
670 %d0 = %1;"
671 [(set_attr "type" "dsp32,mvi")])
673 (define_expand "insv"
674 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
675 (match_operand:SI 1 "immediate_operand" "")
676 (match_operand:SI 2 "immediate_operand" ""))
677 (match_operand:SI 3 "nonmemory_operand" ""))]
678 ""
679 {
680 if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
681 FAIL;
683 /* From mips.md: insert_bit_field doesn't verify that our source
684 matches the predicate, so check it again here. */
685 if (! register_operand (operands[0], VOIDmode))
686 FAIL;
687 })
689 ;; This is the main "hook" for PIC code. When generating
690 ;; PIC, movsi is responsible for determining when the source address
691 ;; needs PIC relocation and appropriately calling legitimize_pic_address
692 ;; to perform the actual relocation.
694 (define_expand "movsi"
695 [(set (match_operand:SI 0 "nonimmediate_operand" "")
696 (match_operand:SI 1 "general_operand" ""))]
697 ""
698 {
699 if (expand_move (operands, SImode))
700 DONE;
701 })
703 (define_expand "movv2hi"
704 [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
705 (match_operand:V2HI 1 "general_operand" ""))]
706 ""
707 "expand_move (operands, V2HImode);")
709 (define_expand "movdi"
710 [(set (match_operand:DI 0 "nonimmediate_operand" "")
711 (match_operand:DI 1 "general_operand" ""))]
712 ""
713 "expand_move (operands, DImode);")
715 (define_expand "movsf"
716 [(set (match_operand:SF 0 "nonimmediate_operand" "")
717 (match_operand:SF 1 "general_operand" ""))]
718 ""
719 "expand_move (operands, SFmode);")
721 (define_expand "movdf"
722 [(set (match_operand:DF 0 "nonimmediate_operand" "")
723 (match_operand:DF 1 "general_operand" ""))]
724 ""
725 "expand_move (operands, DFmode);")
727 (define_expand "movhi"
728 [(set (match_operand:HI 0 "nonimmediate_operand" "")
729 (match_operand:HI 1 "general_operand" ""))]
730 ""
731 "expand_move (operands, HImode);")
733 (define_expand "movqi"
734 [(set (match_operand:QI 0 "nonimmediate_operand" "")
735 (match_operand:QI 1 "general_operand" ""))]
736 ""
737 " expand_move (operands, QImode); ")
739 ;; Some define_splits to break up SI/SFmode loads of immediate constants.
741 (define_split
742 [(set (match_operand:SI 0 "register_operand" "")
743 (match_operand:SI 1 "symbolic_or_const_operand" ""))]
744 "reload_completed
745 /* Always split symbolic operands; split integer constants that are
746 too large for a single instruction. */
747 && (GET_CODE (operands[1]) != CONST_INT
748 || (INTVAL (operands[1]) < -32768
749 || INTVAL (operands[1]) >= 65536
750 || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
751 [(set (match_dup 0) (high:SI (match_dup 1)))
752 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
753 {
754 if (GET_CODE (operands[1]) == CONST_INT
755 && split_load_immediate (operands))
756 DONE;
757 /* ??? Do something about TARGET_LOW_64K. */
758 })
760 (define_split
761 [(set (match_operand:SF 0 "register_operand" "")
762 (match_operand:SF 1 "immediate_operand" ""))]
763 "reload_completed"
764 [(set (match_dup 2) (high:SI (match_dup 3)))
765 (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
766 {
767 long values;
768 REAL_VALUE_TYPE value;
770 gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
772 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
773 REAL_VALUE_TO_TARGET_SINGLE (value, values);
775 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
776 operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
777 if (values >= -32768 && values < 65536)
778 {
779 emit_move_insn (operands[2], operands[3]);
780 DONE;
781 }
782 if (split_load_immediate (operands + 2))
783 DONE;
784 })
786 ;; Sadly, this can't be a proper named movstrict pattern, since the compiler
787 ;; expects to be able to use registers for operand 1.
788 ;; Note that the asm instruction is defined by the manual to take an unsigned
789 ;; constant, but it doesn't matter to the assembler, and the compiler only
790 ;; deals with sign-extended constants. Hence "Ksh".
791 (define_insn "movstricthi_1"
792 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
793 (match_operand:HI 1 "immediate_operand" "Ksh"))]
794 ""
795 "%h0 = %1;"
796 [(set_attr "type" "mvi")
797 (set_attr "length" "4")])
799 ;; Sign and zero extensions
801 (define_insn_and_split "extendhisi2"
802 [(set (match_operand:SI 0 "register_operand" "=d, d")
803 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
804 ""
805 "@
806 %0 = %h1 (X);
807 %0 = W %h1 (X)%!"
808 "reload_completed && bfin_dsp_memref_p (operands[1])"
809 [(set (match_dup 2) (match_dup 1))
810 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
811 {
812 operands[2] = gen_lowpart (HImode, operands[0]);
813 }
814 [(set_attr "type" "alu0,mcld")])
816 (define_insn_and_split "zero_extendhisi2"
817 [(set (match_operand:SI 0 "register_operand" "=d, d")
818 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
819 ""
820 "@
821 %0 = %h1 (Z);
822 %0 = W %h1 (Z)%!"
823 "reload_completed && bfin_dsp_memref_p (operands[1])"
824 [(set (match_dup 2) (match_dup 1))
825 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
826 {
827 operands[2] = gen_lowpart (HImode, operands[0]);
828 }
829 [(set_attr "type" "alu0,mcld")])
831 (define_insn "zero_extendbisi2"
832 [(set (match_operand:SI 0 "register_operand" "=d")
833 (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
834 ""
835 "%0 = %1;"
836 [(set_attr "type" "compare")])
838 (define_insn "extendqihi2"
839 [(set (match_operand:HI 0 "register_operand" "=d, d")
840 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
841 ""
842 "@
843 %0 = B %1 (X)%!
844 %0 = %T1 (X);"
845 [(set_attr "type" "mcld,alu0")])
847 (define_insn "extendqisi2"
848 [(set (match_operand:SI 0 "register_operand" "=d, d")
849 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
850 ""
851 "@
852 %0 = B %1 (X)%!
853 %0 = %T1 (X);"
854 [(set_attr "type" "mcld,alu0")])
857 (define_insn "zero_extendqihi2"
858 [(set (match_operand:HI 0 "register_operand" "=d, d")
859 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
860 ""
861 "@
862 %0 = B %1 (Z)%!
863 %0 = %T1 (Z);"
864 [(set_attr "type" "mcld,alu0")])
867 (define_insn "zero_extendqisi2"
868 [(set (match_operand:SI 0 "register_operand" "=d, d")
869 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
870 ""
871 "@
872 %0 = B %1 (Z)%!
873 %0 = %T1 (Z);"
874 [(set_attr "type" "mcld,alu0")])
876 ;; DImode logical operations
878 (define_code_macro any_logical [and ior xor])
879 (define_code_attr optab [(and "and")
880 (ior "ior")
881 (xor "xor")])
882 (define_code_attr op [(and "&")
883 (ior "|")
884 (xor "^")])
885 (define_code_attr high_result [(and "0")
886 (ior "%H1")
887 (xor "%H1")])
889 (define_insn "<optab>di3"
890 [(set (match_operand:DI 0 "register_operand" "=d")
891 (any_logical:DI (match_operand:DI 1 "register_operand" "0")
892 (match_operand:DI 2 "register_operand" "d")))]
893 ""
894 "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;"
895 [(set_attr "length" "4")
896 (set_attr "seq_insns" "multi")])
898 (define_insn "*<optab>di_zesidi_di"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (any_logical:DI (zero_extend:DI
901 (match_operand:SI 2 "register_operand" "d"))
902 (match_operand:DI 1 "register_operand" "d")))]
903 ""
904 "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;"
905 [(set_attr "length" "4")
906 (set_attr "seq_insns" "multi")])
908 (define_insn "*<optab>di_sesdi_di"
909 [(set (match_operand:DI 0 "register_operand" "=d")
910 (any_logical:DI (sign_extend:DI
911 (match_operand:SI 2 "register_operand" "d"))
912 (match_operand:DI 1 "register_operand" "0")))
913 (clobber (match_scratch:SI 3 "=&d"))]
914 ""
915 "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;"
916 [(set_attr "length" "8")
917 (set_attr "seq_insns" "multi")])
919 (define_insn "negdi2"
920 [(set (match_operand:DI 0 "register_operand" "=d")
921 (neg:DI (match_operand:DI 1 "register_operand" "d")))
922 (clobber (match_scratch:SI 2 "=&d"))
923 (clobber (reg:CC REG_CC))]
924 ""
925 "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;"
926 [(set_attr "length" "16")
927 (set_attr "seq_insns" "multi")])
929 (define_insn "one_cmpldi2"
930 [(set (match_operand:DI 0 "register_operand" "=d")
931 (not:DI (match_operand:DI 1 "register_operand" "d")))]
932 ""
933 "%0 = ~%1;\\n\\t%H0 = ~%H1;"
934 [(set_attr "length" "4")
935 (set_attr "seq_insns" "multi")])
937 ;; DImode zero and sign extend patterns
939 (define_insn_and_split "zero_extendsidi2"
940 [(set (match_operand:DI 0 "register_operand" "=d")
941 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
942 ""
943 "#"
944 "reload_completed"
945 [(set (match_dup 3) (const_int 0))]
946 {
947 split_di (operands, 1, operands + 2, operands + 3);
948 if (REGNO (operands[0]) != REGNO (operands[1]))
949 emit_move_insn (operands[2], operands[1]);
950 })
952 (define_insn "zero_extendqidi2"
953 [(set (match_operand:DI 0 "register_operand" "=d")
954 (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
955 ""
956 "%0 = %T1 (Z);\\n\\t%H0 = 0;"
957 [(set_attr "length" "4")
958 (set_attr "seq_insns" "multi")])
960 (define_insn "zero_extendhidi2"
961 [(set (match_operand:DI 0 "register_operand" "=d")
962 (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
963 ""
964 "%0 = %h1 (Z);\\n\\t%H0 = 0;"
965 [(set_attr "length" "4")
966 (set_attr "seq_insns" "multi")])
968 (define_insn_and_split "extendsidi2"
969 [(set (match_operand:DI 0 "register_operand" "=d")
970 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
971 ""
972 "#"
973 "reload_completed"
974 [(set (match_dup 3) (match_dup 1))
975 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
976 {
977 split_di (operands, 1, operands + 2, operands + 3);
978 if (REGNO (operands[0]) != REGNO (operands[1]))
979 emit_move_insn (operands[2], operands[1]);
980 })
982 (define_insn_and_split "extendqidi2"
983 [(set (match_operand:DI 0 "register_operand" "=d")
984 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
985 ""
986 "#"
987 "reload_completed"
988 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
989 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
990 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
991 {
992 split_di (operands, 1, operands + 2, operands + 3);
993 })
995 (define_insn_and_split "extendhidi2"
996 [(set (match_operand:DI 0 "register_operand" "=d")
997 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
998 ""
999 "#"
1000 "reload_completed"
1001 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
1002 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
1003 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1004 {
1005 split_di (operands, 1, operands + 2, operands + 3);
1006 })
1008 ;; DImode arithmetic operations
1010 (define_insn "add_with_carry"
1011 [(set (match_operand:SI 0 "register_operand" "=d,d")
1012 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1013 (match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
1014 (set (match_operand:SI 3 "register_operand" "=d,d")
1015 (truncate:SI
1016 (lshiftrt:DI (plus:DI (zero_extend:DI (match_dup 1))
1017 (zero_extend:DI (match_dup 2)))
1018 (const_int 32))))
1019 (clobber (reg:CC 34))]
1020 ""
1021 "@
1022 %0 += %2; cc = ac0; %3 = cc;
1023 %0 = %0 + %2; cc = ac0; %3 = cc;"
1024 [(set_attr "type" "alu0")
1025 (set_attr "length" "6")
1026 (set_attr "seq_insns" "multi")])
1028 (define_insn "adddi3"
1029 [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
1030 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
1031 (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d")))
1032 (clobber (match_scratch:SI 3 "=&d,&d,&d"))
1033 (clobber (reg:CC 34))]
1034 ""
1035 "@
1036 %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3;
1037 %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3;
1038 %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;"
1039 [(set_attr "type" "alu0")
1040 (set_attr "length" "10,8,10")
1041 (set_attr "seq_insns" "multi,multi,multi")])
1043 (define_insn "subdi3"
1044 [(set (match_operand:DI 0 "register_operand" "=&d")
1045 (minus:DI (match_operand:DI 1 "register_operand" "0")
1046 (match_operand:DI 2 "register_operand" "d")))
1047 (clobber (reg:CC 34))]
1048 ""
1049 "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1050 [(set_attr "length" "10")
1051 (set_attr "seq_insns" "multi")])
1053 (define_insn "*subdi_di_zesidi"
1054 [(set (match_operand:DI 0 "register_operand" "=d")
1055 (minus:DI (match_operand:DI 1 "register_operand" "0")
1056 (zero_extend:DI
1057 (match_operand:SI 2 "register_operand" "d"))))
1058 (clobber (match_scratch:SI 3 "=&d"))
1059 (clobber (reg:CC 34))]
1060 ""
1061 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;"
1062 [(set_attr "length" "10")
1063 (set_attr "seq_insns" "multi")])
1065 (define_insn "*subdi_zesidi_di"
1066 [(set (match_operand:DI 0 "register_operand" "=d")
1067 (minus:DI (zero_extend:DI
1068 (match_operand:SI 2 "register_operand" "d"))
1069 (match_operand:DI 1 "register_operand" "0")))
1070 (clobber (match_scratch:SI 3 "=&d"))
1071 (clobber (reg:CC 34))]
1072 ""
1073 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1"
1074 [(set_attr "length" "12")
1075 (set_attr "seq_insns" "multi")])
1077 (define_insn "*subdi_di_sesidi"
1078 [(set (match_operand:DI 0 "register_operand" "=d")
1079 (minus:DI (match_operand:DI 1 "register_operand" "0")
1080 (sign_extend:DI
1081 (match_operand:SI 2 "register_operand" "d"))))
1082 (clobber (match_scratch:SI 3 "=&d"))
1083 (clobber (reg:CC 34))]
1084 ""
1085 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1086 [(set_attr "length" "14")
1087 (set_attr "seq_insns" "multi")])
1089 (define_insn "*subdi_sesidi_di"
1090 [(set (match_operand:DI 0 "register_operand" "=d")
1091 (minus:DI (sign_extend:DI
1092 (match_operand:SI 2 "register_operand" "d"))
1093 (match_operand:DI 1 "register_operand" "0")))
1094 (clobber (match_scratch:SI 3 "=&d"))
1095 (clobber (reg:CC 34))]
1096 ""
1097 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1098 [(set_attr "length" "14")
1099 (set_attr "seq_insns" "multi")])
1101 ;; Combined shift/add instructions
1103 (define_insn ""
1104 [(set (match_operand:SI 0 "register_operand" "=a,d")
1105 (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1106 (match_operand:SI 2 "register_operand" "a,d"))
1107 (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
1108 ""
1109 "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
1110 [(set_attr "type" "alu0")])
1112 (define_insn ""
1113 [(set (match_operand:SI 0 "register_operand" "=a")
1114 (plus:SI (match_operand:SI 1 "register_operand" "a")
1115 (mult:SI (match_operand:SI 2 "register_operand" "a")
1116 (match_operand:SI 3 "scale_by_operand" "i"))))]
1117 ""
1118 "%0 = %1 + (%2 << %X3);"
1119 [(set_attr "type" "alu0")])
1121 (define_insn ""
1122 [(set (match_operand:SI 0 "register_operand" "=a")
1123 (plus:SI (match_operand:SI 1 "register_operand" "a")
1124 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1125 (match_operand:SI 3 "pos_scale_operand" "i"))))]
1126 ""
1127 "%0 = %1 + (%2 << %3);"
1128 [(set_attr "type" "alu0")])
1130 (define_insn ""
1131 [(set (match_operand:SI 0 "register_operand" "=a")
1132 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
1133 (match_operand:SI 2 "scale_by_operand" "i"))
1134 (match_operand:SI 3 "register_operand" "a")))]
1135 ""
1136 "%0 = %3 + (%1 << %X2);"
1137 [(set_attr "type" "alu0")])
1139 (define_insn ""
1140 [(set (match_operand:SI 0 "register_operand" "=a")
1141 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
1142 (match_operand:SI 2 "pos_scale_operand" "i"))
1143 (match_operand:SI 3 "register_operand" "a")))]
1144 ""
1145 "%0 = %3 + (%1 << %2);"
1146 [(set_attr "type" "alu0")])
1148 (define_insn "mulhisi3"
1149 [(set (match_operand:SI 0 "register_operand" "=d")
1150 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1151 (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1152 ""
1153 "%0 = %h1 * %h2 (IS)%!"
1154 [(set_attr "type" "dsp32")])
1156 (define_insn "umulhisi3"
1157 [(set (match_operand:SI 0 "register_operand" "=d")
1158 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1159 (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1160 ""
1161 "%0 = %h1 * %h2 (FU)%!"
1162 [(set_attr "type" "dsp32")])
1164 (define_insn "usmulhisi3"
1165 [(set (match_operand:SI 0 "register_operand" "=W")
1166 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
1167 (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
1168 ""
1169 "%0 = %h2 * %h1 (IS,M)%!"
1170 [(set_attr "type" "dsp32")])
1172 ;; The processor also supports ireg += mreg or ireg -= mreg, but these
1173 ;; are unusable if we don't ensure that the corresponding lreg is zero.
1174 ;; The same applies to the add/subtract constant versions involving
1175 ;; iregs
1177 (define_insn "addsi3"
1178 [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
1179 (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
1180 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
1181 ""
1182 "@
1183 %0 += %2;
1184 %0 = %1 + %2;
1185 %0 = %1 + %2;"
1186 [(set_attr "type" "alu0")
1187 (set_attr "length" "2,2,2")])
1189 (define_insn "ssaddsi3"
1190 [(set (match_operand:SI 0 "register_operand" "=d")
1191 (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1192 (match_operand:SI 2 "register_operand" "d")))]
1193 ""
1194 "%0 = %1 + %2 (S)%!"
1195 [(set_attr "type" "dsp32")])
1197 (define_insn "subsi3"
1198 [(set (match_operand:SI 0 "register_operand" "=da,d,a")
1199 (minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
1200 (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))]
1201 ""
1202 {
1203 static const char *const strings_subsi3[] = {
1204 "%0 += -%2;",
1205 "%0 = %1 - %2;",
1206 "%0 -= %2;",
1207 };
1209 if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
1210 rtx tmp_op = operands[2];
1211 operands[2] = GEN_INT (-INTVAL (operands[2]));
1212 output_asm_insn ("%0 += %2;", operands);
1213 operands[2] = tmp_op;
1214 return "";
1215 }
1217 return strings_subsi3[which_alternative];
1218 }
1219 [(set_attr "type" "alu0")])
1221 (define_insn "sssubsi3"
1222 [(set (match_operand:SI 0 "register_operand" "=d")
1223 (ss_minus:SI (match_operand:SI 1 "register_operand" "d")
1224 (match_operand:SI 2 "register_operand" "d")))]
1225 ""
1226 "%0 = %1 - %2 (S)%!"
1227 [(set_attr "type" "dsp32")])
1229 ;; Bit test instructions
1231 (define_insn "*not_bittst"
1232 [(set (match_operand:BI 0 "register_operand" "=C")
1233 (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1234 (const_int 1)
1235 (match_operand:SI 2 "immediate_operand" "Ku5"))
1236 (const_int 0)))]
1237 ""
1238 "cc = !BITTST (%1,%2);"
1239 [(set_attr "type" "alu0")])
1241 (define_insn "*bittst"
1242 [(set (match_operand:BI 0 "register_operand" "=C")
1243 (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1244 (const_int 1)
1245 (match_operand:SI 2 "immediate_operand" "Ku5"))
1246 (const_int 0)))]
1247 ""
1248 "cc = BITTST (%1,%2);"
1249 [(set_attr "type" "alu0")])
1251 (define_insn_and_split "*bit_extract"
1252 [(set (match_operand:SI 0 "register_operand" "=d")
1253 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1254 (const_int 1)
1255 (match_operand:SI 2 "immediate_operand" "Ku5")))
1256 (clobber (reg:BI REG_CC))]
1257 ""
1258 "#"
1259 ""
1260 [(set (reg:BI REG_CC)
1261 (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1262 (const_int 0)))
1263 (set (match_dup 0)
1264 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1266 (define_insn_and_split "*not_bit_extract"
1267 [(set (match_operand:SI 0 "register_operand" "=d")
1268 (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1269 (const_int 1)
1270 (match_operand:SI 2 "immediate_operand" "Ku5")))
1271 (clobber (reg:BI REG_CC))]
1272 ""
1273 "#"
1274 ""
1275 [(set (reg:BI REG_CC)
1276 (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1277 (const_int 0)))
1278 (set (match_dup 0)
1279 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1281 (define_insn "*andsi_insn"
1282 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1283 (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
1284 (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
1285 ""
1286 "@
1287 BITCLR (%0,%Y2);
1288 %0 = %T1 (Z);
1289 %0 = %h1 (Z);
1290 %0 = %1 & %2;"
1291 [(set_attr "type" "alu0")])
1293 (define_expand "andsi3"
1294 [(set (match_operand:SI 0 "register_operand" "")
1295 (and:SI (match_operand:SI 1 "register_operand" "")
1296 (match_operand:SI 2 "general_operand" "")))]
1297 ""
1298 {
1299 if (highbits_operand (operands[2], SImode))
1300 {
1301 operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
1302 emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
1303 emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
1304 DONE;
1305 }
1306 if (! rhs_andsi3_operand (operands[2], SImode))
1307 operands[2] = force_reg (SImode, operands[2]);
1308 })
1310 (define_insn "iorsi3"
1311 [(set (match_operand:SI 0 "register_operand" "=d,d")
1312 (ior:SI (match_operand:SI 1 "register_operand" "%0,d")
1313 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1314 ""
1315 "@
1316 BITSET (%0, %X2);
1317 %0 = %1 | %2;"
1318 [(set_attr "type" "alu0")])
1320 (define_insn "xorsi3"
1321 [(set (match_operand:SI 0 "register_operand" "=d,d")
1322 (xor:SI (match_operand:SI 1 "register_operand" "%0,d")
1323 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1324 ""
1325 "@
1326 BITTGL (%0, %X2);
1327 %0 = %1 ^ %2;"
1328 [(set_attr "type" "alu0")])
1330 (define_insn "smaxsi3"
1331 [(set (match_operand:SI 0 "register_operand" "=d")
1332 (smax:SI (match_operand:SI 1 "register_operand" "d")
1333 (match_operand:SI 2 "register_operand" "d")))]
1334 ""
1335 "%0 = max(%1,%2)%!"
1336 [(set_attr "type" "dsp32")])
1338 (define_insn "sminsi3"
1339 [(set (match_operand:SI 0 "register_operand" "=d")
1340 (smin:SI (match_operand:SI 1 "register_operand" "d")
1341 (match_operand:SI 2 "register_operand" "d")))]
1342 ""
1343 "%0 = min(%1,%2)%!"
1344 [(set_attr "type" "dsp32")])
1346 (define_insn "abssi2"
1347 [(set (match_operand:SI 0 "register_operand" "=d")
1348 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1349 ""
1350 "%0 = abs %1%!"
1351 [(set_attr "type" "dsp32")])
1353 (define_insn "negsi2"
1354 [(set (match_operand:SI 0 "register_operand" "=d")
1355 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1356 ""
1357 "%0 = -%1;"
1358 [(set_attr "type" "alu0")])
1360 (define_insn "ssnegsi2"
1361 [(set (match_operand:SI 0 "register_operand" "=d")
1362 (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
1363 ""
1364 "%0 = -%1 (S)%!"
1365 [(set_attr "type" "dsp32")])
1367 (define_insn "one_cmplsi2"
1368 [(set (match_operand:SI 0 "register_operand" "=d")
1369 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1370 ""
1371 "%0 = ~%1;"
1372 [(set_attr "type" "alu0")])
1374 (define_insn "signbitssi2"
1375 [(set (match_operand:HI 0 "register_operand" "=d")
1376 (if_then_else:HI
1377 (lt (match_operand:SI 1 "register_operand" "d") (const_int 0))
1378 (clz:HI (not:SI (match_dup 1)))
1379 (clz:HI (match_dup 1))))]
1380 ""
1381 "%h0 = signbits %1%!"
1382 [(set_attr "type" "dsp32")])
1384 (define_insn "smaxhi3"
1385 [(set (match_operand:HI 0 "register_operand" "=d")
1386 (smax:HI (match_operand:HI 1 "register_operand" "d")
1387 (match_operand:HI 2 "register_operand" "d")))]
1388 ""
1389 "%0 = max(%1,%2) (V)%!"
1390 [(set_attr "type" "dsp32")])
1392 (define_insn "sminhi3"
1393 [(set (match_operand:HI 0 "register_operand" "=d")
1394 (smin:HI (match_operand:HI 1 "register_operand" "d")
1395 (match_operand:HI 2 "register_operand" "d")))]
1396 ""
1397 "%0 = min(%1,%2) (V)%!"
1398 [(set_attr "type" "dsp32")])
1400 (define_insn "abshi2"
1401 [(set (match_operand:HI 0 "register_operand" "=d")
1402 (abs:HI (match_operand:HI 1 "register_operand" "d")))]
1403 ""
1404 "%0 = abs %1 (V)%!"
1405 [(set_attr "type" "dsp32")])
1407 (define_insn "neghi2"
1408 [(set (match_operand:HI 0 "register_operand" "=d")
1409 (neg:HI (match_operand:HI 1 "register_operand" "d")))]
1410 ""
1411 "%0 = -%1;"
1412 [(set_attr "type" "alu0")])
1414 (define_insn "ssneghi2"
1415 [(set (match_operand:HI 0 "register_operand" "=d")
1416 (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
1417 ""
1418 "%0 = -%1 (V)%!"
1419 [(set_attr "type" "dsp32")])
1421 (define_insn "signbitshi2"
1422 [(set (match_operand:HI 0 "register_operand" "=d")
1423 (if_then_else:HI
1424 (lt (match_operand:HI 1 "register_operand" "d") (const_int 0))
1425 (clz:HI (not:HI (match_dup 1)))
1426 (clz:HI (match_dup 1))))]
1427 ""
1428 "%h0 = signbits %h1%!"
1429 [(set_attr "type" "dsp32")])
1431 (define_insn "mulsi3"
1432 [(set (match_operand:SI 0 "register_operand" "=d")
1433 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1434 (match_operand:SI 2 "register_operand" "d")))]
1435 ""
1436 "%0 *= %2;"
1437 [(set_attr "type" "mult")])
1439 (define_expand "ashlsi3"
1440 [(set (match_operand:SI 0 "register_operand" "")
1441 (ashift:SI (match_operand:SI 1 "register_operand" "")
1442 (match_operand:SI 2 "nonmemory_operand" "")))]
1443 ""
1444 {
1445 if (GET_CODE (operands[2]) == CONST_INT
1446 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
1447 {
1448 emit_insn (gen_movsi (operands[0], const0_rtx));
1449 DONE;
1450 }
1451 })
1453 (define_insn_and_split "*ashlsi3_insn"
1454 [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a")
1455 (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a")
1456 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))]
1457 ""
1458 "@
1459 %0 <<= %2;
1460 %0 = %1 << %2%!
1461 %0 = %1 + %1;
1462 %0 = %1 << %2;
1463 #"
1464 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1465 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1466 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1467 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1468 [(set_attr "type" "shft,dsp32,shft,shft,*")])
1470 (define_insn "ashrsi3"
1471 [(set (match_operand:SI 0 "register_operand" "=d,d")
1472 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1473 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
1474 ""
1475 "@
1476 %0 >>>= %2;
1477 %0 = %1 >>> %2%!"
1478 [(set_attr "type" "shft,dsp32")])
1480 (define_insn "ror_one"
1481 [(set (match_operand:SI 0 "register_operand" "=d")
1482 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1483 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1484 (set (reg:BI REG_CC)
1485 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1486 ""
1487 "%0 = ROT %1 BY -1%!"
1488 [(set_attr "type" "dsp32")])
1490 (define_insn "rol_one"
1491 [(set (match_operand:SI 0 "register_operand" "+d")
1492 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1493 (zero_extend:SI (reg:BI REG_CC))))
1494 (set (reg:BI REG_CC)
1495 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1496 ""
1497 "%0 = ROT %1 BY 1%!"
1498 [(set_attr "type" "dsp32")])
1500 (define_expand "lshrdi3"
1501 [(set (match_operand:DI 0 "register_operand" "")
1502 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1503 (match_operand:DI 2 "general_operand" "")))]
1504 ""
1505 {
1506 rtx lo_half[2], hi_half[2];
1508 if (operands[2] != const1_rtx)
1509 FAIL;
1510 if (! rtx_equal_p (operands[0], operands[1]))
1511 emit_move_insn (operands[0], operands[1]);
1513 split_di (operands, 2, lo_half, hi_half);
1515 emit_move_insn (bfin_cc_rtx, const0_rtx);
1516 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1517 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1518 DONE;
1519 })
1521 (define_expand "ashrdi3"
1522 [(set (match_operand:DI 0 "register_operand" "")
1523 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
1524 (match_operand:DI 2 "general_operand" "")))]
1525 ""
1526 {
1527 rtx lo_half[2], hi_half[2];
1529 if (operands[2] != const1_rtx)
1530 FAIL;
1531 if (! rtx_equal_p (operands[0], operands[1]))
1532 emit_move_insn (operands[0], operands[1]);
1534 split_di (operands, 2, lo_half, hi_half);
1536 emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
1537 hi_half[1], const0_rtx));
1538 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1539 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1540 DONE;
1541 })
1543 (define_expand "ashldi3"
1544 [(set (match_operand:DI 0 "register_operand" "")
1545 (ashift:DI (match_operand:DI 1 "register_operand" "")
1546 (match_operand:DI 2 "general_operand" "")))]
1547 ""
1548 {
1549 rtx lo_half[2], hi_half[2];
1551 if (operands[2] != const1_rtx)
1552 FAIL;
1553 if (! rtx_equal_p (operands[0], operands[1]))
1554 emit_move_insn (operands[0], operands[1]);
1556 split_di (operands, 2, lo_half, hi_half);
1558 emit_move_insn (bfin_cc_rtx, const0_rtx);
1559 emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
1560 emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
1561 DONE;
1562 })
1564 (define_insn "lshrsi3"
1565 [(set (match_operand:SI 0 "register_operand" "=d,d,a")
1566 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a")
1567 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))]
1568 ""
1569 "@
1570 %0 >>= %2;
1571 %0 = %1 >> %2%!
1572 %0 = %1 >> %2;"
1573 [(set_attr "type" "shft,dsp32,shft")])
1575 ;; A pattern to reload the equivalent of
1576 ;; (set (Dreg) (plus (FP) (large_constant)))
1577 ;; or
1578 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1579 ;; using a scratch register
1580 (define_expand "reload_insi"
1581 [(parallel [(set (match_operand:SI 0 "register_operand" "=w")
1582 (match_operand:SI 1 "fp_plus_const_operand" ""))
1583 (clobber (match_operand:SI 2 "register_operand" "=&a"))])]
1584 ""
1585 {
1586 rtx fp_op = XEXP (operands[1], 0);
1587 rtx const_op = XEXP (operands[1], 1);
1588 rtx primary = operands[0];
1589 rtx scratch = operands[2];
1591 emit_move_insn (scratch, const_op);
1592 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1593 emit_move_insn (primary, scratch);
1594 DONE;
1595 })
1597 ;; Jump instructions
1599 (define_insn "jump"
1600 [(set (pc)
1601 (label_ref (match_operand 0 "" "")))]
1602 ""
1603 {
1604 if (get_attr_length (insn) == 2)
1605 return "jump.s %0;";
1606 else
1607 return "jump.l %0;";
1608 }
1609 [(set_attr "type" "br")])
1611 (define_insn "indirect_jump"
1612 [(set (pc)
1613 (match_operand:SI 0 "register_operand" "a"))]
1614 ""
1615 "jump (%0);"
1616 [(set_attr "type" "misc")])
1618 (define_expand "tablejump"
1619 [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1620 (use (label_ref (match_operand 1 "" "")))])]
1621 ""
1622 {
1623 /* In PIC mode, the table entries are stored PC relative.
1624 Convert the relative address to an absolute address. */
1625 if (flag_pic)
1626 {
1627 rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
1629 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
1630 op1, NULL_RTX, 0, OPTAB_DIRECT);
1631 }
1632 })
1634 (define_insn "*tablejump_internal"
1635 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1636 (use (label_ref (match_operand 1 "" "")))]
1637 ""
1638 "jump (%0);"
1639 [(set_attr "type" "misc")])
1641 ;; Hardware loop
1643 ; operand 0 is the loop count pseudo register
1644 ; operand 1 is the number of loop iterations or 0 if it is unknown
1645 ; operand 2 is the maximum number of loop iterations
1646 ; operand 3 is the number of levels of enclosed loops
1647 ; operand 4 is the label to jump to at the top of the loop
1648 (define_expand "doloop_end"
1649 [(parallel [(set (pc) (if_then_else
1650 (ne (match_operand:SI 0 "" "")
1651 (const_int 1))
1652 (label_ref (match_operand 4 "" ""))
1653 (pc)))
1654 (set (match_dup 0)
1655 (plus:SI (match_dup 0)
1656 (const_int -1)))
1657 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1658 (clobber (match_scratch:SI 5 ""))])]
1659 ""
1660 {
1661 /* The loop optimizer doesn't check the predicates... */
1662 if (GET_MODE (operands[0]) != SImode)
1663 FAIL;
1664 /* Due to limitations in the hardware (an initial loop count of 0
1665 does not loop 2^32 times) we must avoid to generate a hardware
1666 loops when we cannot rule out this case. */
1667 if (!flag_unsafe_loop_optimizations
1668 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF)
1669 FAIL;
1670 bfin_hardware_loop ();
1671 })
1673 (define_insn "loop_end"
1674 [(set (pc)
1675 (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m")
1676 (const_int 1))
1677 (label_ref (match_operand 1 "" ""))
1678 (pc)))
1679 (set (match_dup 0)
1680 (plus (match_dup 0)
1681 (const_int -1)))
1682 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1683 (clobber (match_scratch:SI 2 "=X,&r,&r"))]
1684 ""
1685 "@
1686 /* loop end %0 %l1 */
1687 #
1688 #"
1689 [(set_attr "length" "6,10,14")])
1691 (define_split
1692 [(set (pc)
1693 (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "")
1694 (const_int 1))
1695 (label_ref (match_operand 1 "" ""))
1696 (pc)))
1697 (set (match_dup 0)
1698 (plus (match_dup 0)
1699 (const_int -1)))
1700 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1701 (clobber (match_scratch:SI 2 "=&r"))]
1702 "reload_completed"
1703 [(set (match_dup 2) (match_dup 0))
1704 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1705 (set (match_dup 0) (match_dup 2))
1706 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1707 (set (pc)
1708 (if_then_else (eq (reg:BI REG_CC)
1709 (const_int 0))
1710 (label_ref (match_dup 1))
1711 (pc)))]
1712 "")
1714 (define_insn "lsetup_with_autoinit"
1715 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1716 (label_ref (match_operand 1 "" "")))
1717 (set (match_operand:SI 2 "lb_register_operand" "=u")
1718 (label_ref (match_operand 3 "" "")))
1719 (set (match_operand:SI 4 "lc_register_operand" "=k")
1720 (match_operand:SI 5 "register_operand" "a"))]
1721 ""
1722 "LSETUP (%1, %3) %4 = %5;"
1723 [(set_attr "length" "4")])
1725 (define_insn "lsetup_without_autoinit"
1726 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1727 (label_ref (match_operand 1 "" "")))
1728 (set (match_operand:SI 2 "lb_register_operand" "=u")
1729 (label_ref (match_operand 3 "" "")))
1730 (use (match_operand:SI 4 "lc_register_operand" "k"))]
1731 ""
1732 "LSETUP (%1, %3) %4;"
1733 [(set_attr "length" "4")])
1735 ;; Call instructions..
1737 ;; The explicit MEM inside the UNSPEC prevents the compiler from moving
1738 ;; the load before a branch after a NULL test, or before a store that
1739 ;; initializes a function descriptor.
1741 (define_insn_and_split "load_funcdescsi"
1742 [(set (match_operand:SI 0 "register_operand" "=a")
1743 (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
1744 UNSPEC_VOLATILE_LOAD_FUNCDESC))]
1745 ""
1746 "#"
1747 "reload_completed"
1748 [(set (match_dup 0) (mem:SI (match_dup 1)))])
1750 (define_expand "call"
1751 [(parallel [(call (match_operand:SI 0 "" "")
1752 (match_operand 1 "" ""))
1753 (use (match_operand 2 "" ""))])]
1754 ""
1755 {
1756 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
1757 DONE;
1758 })
1760 (define_expand "sibcall"
1761 [(parallel [(call (match_operand:SI 0 "" "")
1762 (match_operand 1 "" ""))
1763 (use (match_operand 2 "" ""))
1764 (return)])]
1765 ""
1766 {
1767 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
1768 DONE;
1769 })
1771 (define_expand "call_value"
1772 [(parallel [(set (match_operand 0 "register_operand" "")
1773 (call (match_operand:SI 1 "" "")
1774 (match_operand 2 "" "")))
1775 (use (match_operand 3 "" ""))])]
1776 ""
1777 {
1778 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
1779 DONE;
1780 })
1782 (define_expand "sibcall_value"
1783 [(parallel [(set (match_operand 0 "register_operand" "")
1784 (call (match_operand:SI 1 "" "")
1785 (match_operand 2 "" "")))
1786 (use (match_operand 3 "" ""))
1787 (return)])]
1788 ""
1789 {
1790 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
1791 DONE;
1792 })
1794 (define_insn "*call_symbol_fdpic"
1795 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1796 (match_operand 1 "general_operand" "g"))
1797 (use (match_operand:SI 2 "register_operand" "Z"))
1798 (use (match_operand 3 "" ""))]
1799 "! SIBLING_CALL_P (insn)
1800 && GET_CODE (operands[0]) == SYMBOL_REF
1801 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1802 "call %0;"
1803 [(set_attr "type" "call")
1804 (set_attr "length" "4")])
1806 (define_insn "*sibcall_symbol_fdpic"
1807 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1808 (match_operand 1 "general_operand" "g"))
1809 (use (match_operand:SI 2 "register_operand" "Z"))
1810 (use (match_operand 3 "" ""))
1811 (return)]
1812 "SIBLING_CALL_P (insn)
1813 && GET_CODE (operands[0]) == SYMBOL_REF
1814 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1815 "jump.l %0;"
1816 [(set_attr "type" "br")
1817 (set_attr "length" "4")])
1819 (define_insn "*call_value_symbol_fdpic"
1820 [(set (match_operand 0 "register_operand" "=d")
1821 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1822 (match_operand 2 "general_operand" "g")))
1823 (use (match_operand:SI 3 "register_operand" "Z"))
1824 (use (match_operand 4 "" ""))]
1825 "! SIBLING_CALL_P (insn)
1826 && GET_CODE (operands[1]) == SYMBOL_REF
1827 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1828 "call %1;"
1829 [(set_attr "type" "call")
1830 (set_attr "length" "4")])
1832 (define_insn "*sibcall_value_symbol_fdpic"
1833 [(set (match_operand 0 "register_operand" "=d")
1834 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1835 (match_operand 2 "general_operand" "g")))
1836 (use (match_operand:SI 3 "register_operand" "Z"))
1837 (use (match_operand 4 "" ""))
1838 (return)]
1839 "SIBLING_CALL_P (insn)
1840 && GET_CODE (operands[1]) == SYMBOL_REF
1841 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1842 "jump.l %1;"
1843 [(set_attr "type" "br")
1844 (set_attr "length" "4")])
1846 (define_insn "*call_insn_fdpic"
1847 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1848 (match_operand 1 "general_operand" "g"))
1849 (use (match_operand:SI 2 "register_operand" "Z"))
1850 (use (match_operand 3 "" ""))]
1851 "! SIBLING_CALL_P (insn)"
1852 "call (%0);"
1853 [(set_attr "type" "call")
1854 (set_attr "length" "2")])
1856 (define_insn "*sibcall_insn_fdpic"
1857 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1858 (match_operand 1 "general_operand" "g"))
1859 (use (match_operand:SI 2 "register_operand" "Z"))
1860 (use (match_operand 3 "" ""))
1861 (return)]
1862 "SIBLING_CALL_P (insn)"
1863 "jump (%0);"
1864 [(set_attr "type" "br")
1865 (set_attr "length" "2")])
1867 (define_insn "*call_value_insn_fdpic"
1868 [(set (match_operand 0 "register_operand" "=d")
1869 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1870 (match_operand 2 "general_operand" "g")))
1871 (use (match_operand:SI 3 "register_operand" "Z"))
1872 (use (match_operand 4 "" ""))]
1873 "! SIBLING_CALL_P (insn)"
1874 "call (%1);"
1875 [(set_attr "type" "call")
1876 (set_attr "length" "2")])
1878 (define_insn "*sibcall_value_insn_fdpic"
1879 [(set (match_operand 0 "register_operand" "=d")
1880 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1881 (match_operand 2 "general_operand" "g")))
1882 (use (match_operand:SI 3 "register_operand" "Z"))
1883 (use (match_operand 4 "" ""))
1884 (return)]
1885 "SIBLING_CALL_P (insn)"
1886 "jump (%1);"
1887 [(set_attr "type" "br")
1888 (set_attr "length" "2")])
1890 (define_insn "*call_symbol"
1891 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1892 (match_operand 1 "general_operand" "g"))
1893 (use (match_operand 2 "" ""))]
1894 "! SIBLING_CALL_P (insn)
1895 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1896 && GET_CODE (operands[0]) == SYMBOL_REF
1897 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1898 "call %0;"
1899 [(set_attr "type" "call")
1900 (set_attr "length" "4")])
1902 (define_insn "*sibcall_symbol"
1903 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1904 (match_operand 1 "general_operand" "g"))
1905 (use (match_operand 2 "" ""))
1906 (return)]
1907 "SIBLING_CALL_P (insn)
1908 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1909 && GET_CODE (operands[0]) == SYMBOL_REF
1910 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1911 "jump.l %0;"
1912 [(set_attr "type" "br")
1913 (set_attr "length" "4")])
1915 (define_insn "*call_value_symbol"
1916 [(set (match_operand 0 "register_operand" "=d")
1917 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1918 (match_operand 2 "general_operand" "g")))
1919 (use (match_operand 3 "" ""))]
1920 "! SIBLING_CALL_P (insn)
1921 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1922 && GET_CODE (operands[1]) == SYMBOL_REF
1923 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
1924 "call %1;"
1925 [(set_attr "type" "call")
1926 (set_attr "length" "4")])
1928 (define_insn "*sibcall_value_symbol"
1929 [(set (match_operand 0 "register_operand" "=d")
1930 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1931 (match_operand 2 "general_operand" "g")))
1932 (use (match_operand 3 "" ""))
1933 (return)]
1934 "SIBLING_CALL_P (insn)
1935 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1936 && GET_CODE (operands[1]) == SYMBOL_REF
1937 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
1938 "jump.l %1;"
1939 [(set_attr "type" "br")
1940 (set_attr "length" "4")])
1942 (define_insn "*call_insn"
1943 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
1944 (match_operand 1 "general_operand" "g"))
1945 (use (match_operand 2 "" ""))]
1946 "! SIBLING_CALL_P (insn)"
1947 "call (%0);"
1948 [(set_attr "type" "call")
1949 (set_attr "length" "2")])
1951 (define_insn "*sibcall_insn"
1952 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
1953 (match_operand 1 "general_operand" "g"))
1954 (use (match_operand 2 "" ""))
1955 (return)]
1956 "SIBLING_CALL_P (insn)"
1957 "jump (%0);"
1958 [(set_attr "type" "br")
1959 (set_attr "length" "2")])
1961 (define_insn "*call_value_insn"
1962 [(set (match_operand 0 "register_operand" "=d")
1963 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
1964 (match_operand 2 "general_operand" "g")))
1965 (use (match_operand 3 "" ""))]
1966 "! SIBLING_CALL_P (insn)"
1967 "call (%1);"
1968 [(set_attr "type" "call")
1969 (set_attr "length" "2")])
1971 (define_insn "*sibcall_value_insn"
1972 [(set (match_operand 0 "register_operand" "=d")
1973 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
1974 (match_operand 2 "general_operand" "g")))
1975 (use (match_operand 3 "" ""))
1976 (return)]
1977 "SIBLING_CALL_P (insn)"
1978 "jump (%1);"
1979 [(set_attr "type" "br")
1980 (set_attr "length" "2")])
1982 ;; Block move patterns
1984 ;; We cheat. This copies one more word than operand 2 indicates.
1986 (define_insn "rep_movsi"
1987 [(set (match_operand:SI 0 "register_operand" "=&a")
1988 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
1989 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1990 (const_int 2)))
1991 (const_int 4)))
1992 (set (match_operand:SI 1 "register_operand" "=&b")
1993 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
1994 (ashift:SI (match_dup 2) (const_int 2)))
1995 (const_int 4)))
1996 (set (mem:BLK (match_dup 3))
1997 (mem:BLK (match_dup 4)))
1998 (use (match_dup 2))
1999 (clobber (match_scratch:HI 5 "=&d"))
2000 (clobber (reg:SI REG_LT1))
2001 (clobber (reg:SI REG_LC1))
2002 (clobber (reg:SI REG_LB1))]
2003 ""
2004 "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
2005 [(set_attr "type" "misc")
2006 (set_attr "length" "16")
2007 (set_attr "seq_insns" "multi")])
2009 (define_insn "rep_movhi"
2010 [(set (match_operand:SI 0 "register_operand" "=&a")
2011 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2012 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2013 (const_int 1)))
2014 (const_int 2)))
2015 (set (match_operand:SI 1 "register_operand" "=&b")
2016 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2017 (ashift:SI (match_dup 2) (const_int 1)))
2018 (const_int 2)))
2019 (set (mem:BLK (match_dup 3))
2020 (mem:BLK (match_dup 4)))
2021 (use (match_dup 2))
2022 (clobber (match_scratch:HI 5 "=&d"))
2023 (clobber (reg:SI REG_LT1))
2024 (clobber (reg:SI REG_LC1))
2025 (clobber (reg:SI REG_LB1))]
2026 ""
2027 "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
2028 [(set_attr "type" "misc")
2029 (set_attr "length" "16")
2030 (set_attr "seq_insns" "multi")])
2032 (define_expand "movmemsi"
2033 [(match_operand:BLK 0 "general_operand" "")
2034 (match_operand:BLK 1 "general_operand" "")
2035 (match_operand:SI 2 "const_int_operand" "")
2036 (match_operand:SI 3 "const_int_operand" "")]
2037 ""
2038 {
2039 if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
2040 DONE;
2041 FAIL;
2042 })
2044 ;; Conditional branch patterns
2045 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
2047 ;; The only outcome of this pattern is that global variables
2048 ;; bfin_compare_op[01] are set for use in bcond patterns.
2050 (define_expand "cmpbi"
2051 [(set (cc0) (compare (match_operand:BI 0 "register_operand" "")
2052 (match_operand:BI 1 "immediate_operand" "")))]
2053 ""
2054 {
2055 bfin_compare_op0 = operands[0];
2056 bfin_compare_op1 = operands[1];
2057 DONE;
2058 })
2060 (define_expand "cmpsi"
2061 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2062 (match_operand:SI 1 "reg_or_const_int_operand" "")))]
2063 ""
2064 {
2065 bfin_compare_op0 = operands[0];
2066 bfin_compare_op1 = operands[1];
2067 DONE;
2068 })
2070 (define_insn "compare_eq"
2071 [(set (match_operand:BI 0 "register_operand" "=C,C")
2072 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
2073 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2074 ""
2075 "cc =%1==%2;"
2076 [(set_attr "type" "compare")])
2078 (define_insn "compare_ne"
2079 [(set (match_operand:BI 0 "register_operand" "=C,C")
2080 (ne:BI (match_operand:SI 1 "register_operand" "d,a")
2081 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2082 "0"
2083 "cc =%1!=%2;"
2084 [(set_attr "type" "compare")])
2086 (define_insn "compare_lt"
2087 [(set (match_operand:BI 0 "register_operand" "=C,C")
2088 (lt:BI (match_operand:SI 1 "register_operand" "d,a")
2089 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2090 ""
2091 "cc =%1<%2;"
2092 [(set_attr "type" "compare")])
2094 (define_insn "compare_le"
2095 [(set (match_operand:BI 0 "register_operand" "=C,C")
2096 (le:BI (match_operand:SI 1 "register_operand" "d,a")
2097 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2098 ""
2099 "cc =%1<=%2;"
2100 [(set_attr "type" "compare")])
2102 (define_insn "compare_leu"
2103 [(set (match_operand:BI 0 "register_operand" "=C,C")
2104 (leu:BI (match_operand:SI 1 "register_operand" "d,a")
2105 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2106 ""
2107 "cc =%1<=%2 (iu);"
2108 [(set_attr "type" "compare")])
2110 (define_insn "compare_ltu"
2111 [(set (match_operand:BI 0 "register_operand" "=C,C")
2112 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
2113 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2114 ""
2115 "cc =%1<%2 (iu);"
2116 [(set_attr "type" "compare")])
2118 (define_expand "beq"
2119 [(set (match_dup 1) (match_dup 2))
2120 (set (pc)
2121 (if_then_else (match_dup 3)
2122 (label_ref (match_operand 0 "" ""))
2123 (pc)))]
2124 ""
2125 {
2126 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2127 operands[1] = bfin_cc_rtx; /* hard register: CC */
2128 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2129 /* If we have a BImode input, then we already have a compare result, and
2130 do not need to emit another comparison. */
2131 if (GET_MODE (bfin_compare_op0) == BImode)
2132 {
2133 gcc_assert (bfin_compare_op1 == const0_rtx);
2134 emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0]));
2135 DONE;
2136 }
2138 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2139 })
2141 (define_expand "bne"
2142 [(set (match_dup 1) (match_dup 2))
2143 (set (pc)
2144 (if_then_else (match_dup 3)
2145 (label_ref (match_operand 0 "" ""))
2146 (pc)))]
2147 ""
2148 {
2149 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2150 /* If we have a BImode input, then we already have a compare result, and
2151 do not need to emit another comparison. */
2152 if (GET_MODE (bfin_compare_op0) == BImode)
2153 {
2154 rtx cmp = gen_rtx_NE (BImode, op0, op1);
2156 gcc_assert (bfin_compare_op1 == const0_rtx);
2157 emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
2158 DONE;
2159 }
2161 operands[1] = bfin_cc_rtx; /* hard register: CC */
2162 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2163 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2164 })
2166 (define_expand "bgt"
2167 [(set (match_dup 1) (match_dup 2))
2168 (set (pc)
2169 (if_then_else (match_dup 3)
2170 (label_ref (match_operand 0 "" ""))
2171 (pc)))]
2172 ""
2173 {
2174 operands[1] = bfin_cc_rtx;
2175 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2176 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2177 })
2179 (define_expand "bgtu"
2180 [(set (match_dup 1) (match_dup 2))
2181 (set (pc)
2182 (if_then_else (match_dup 3)
2183 (label_ref (match_operand 0 "" ""))
2184 (pc)))]
2185 ""
2186 {
2187 operands[1] = bfin_cc_rtx;
2188 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2189 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2190 })
2192 (define_expand "blt"
2193 [(set (match_dup 1) (match_dup 2))
2194 (set (pc)
2195 (if_then_else (match_dup 3)
2196 (label_ref (match_operand 0 "" ""))
2197 (pc)))]
2198 ""
2199 {
2200 operands[1] = bfin_cc_rtx;
2201 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2202 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2203 })
2205 (define_expand "bltu"
2206 [(set (match_dup 1) (match_dup 2))
2207 (set (pc)
2208 (if_then_else (match_dup 3)
2209 (label_ref (match_operand 0 "" ""))
2210 (pc)))]
2211 ""
2212 {
2213 operands[1] = bfin_cc_rtx;
2214 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2215 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2216 })
2219 (define_expand "bge"
2220 [(set (match_dup 1) (match_dup 2))
2221 (set (pc)
2222 (if_then_else (match_dup 3)
2223 (label_ref (match_operand 0 "" ""))
2224 (pc)))]
2225 ""
2226 {
2227 operands[1] = bfin_cc_rtx;
2228 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2229 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2230 })
2232 (define_expand "bgeu"
2233 [(set (match_dup 1) (match_dup 2))
2234 (set (pc)
2235 (if_then_else (match_dup 3)
2236 (label_ref (match_operand 0 "" ""))
2237 (pc)))]
2238 ""
2239 {
2240 operands[1] = bfin_cc_rtx;
2241 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2242 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2243 })
2245 (define_expand "ble"
2246 [(set (match_dup 1) (match_dup 2))
2247 (set (pc)
2248 (if_then_else (match_dup 3)
2249 (label_ref (match_operand 0 "" ""))
2250 (pc)))]
2251 ""
2252 {
2253 operands[1] = bfin_cc_rtx;
2254 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2255 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2256 })
2258 (define_expand "bleu"
2259 [(set (match_dup 1) (match_dup 2))
2260 (set (pc)
2261 (if_then_else (match_dup 3)
2262 (label_ref (match_operand 0 "" ""))
2263 (pc)))
2264 ]
2265 ""
2266 {
2267 operands[1] = bfin_cc_rtx;
2268 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2269 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2270 })
2272 (define_insn "cbranchbi4"
2273 [(set (pc)
2274 (if_then_else
2275 (match_operator 0 "bfin_cbranch_operator"
2276 [(match_operand:BI 1 "register_operand" "C")
2277 (match_operand:BI 2 "immediate_operand" "P0")])
2278 (label_ref (match_operand 3 "" ""))
2279 (pc)))]
2280 ""
2281 {
2282 asm_conditional_branch (insn, operands, 0, 0);
2283 return "";
2284 }
2285 [(set_attr "type" "brcc")])
2287 ;; Special cbranch patterns to deal with the speculative load problem - see
2288 ;; bfin_reorg for details.
2290 (define_insn "cbranch_predicted_taken"
2291 [(set (pc)
2292 (if_then_else
2293 (match_operator 0 "bfin_cbranch_operator"
2294 [(match_operand:BI 1 "register_operand" "C")
2295 (match_operand:BI 2 "immediate_operand" "P0")])
2296 (label_ref (match_operand 3 "" ""))
2297 (pc)))
2298 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2299 ""
2300 {
2301 asm_conditional_branch (insn, operands, 0, 1);
2302 return "";
2303 }
2304 [(set_attr "type" "brcc")])
2306 (define_insn "cbranch_with_nops"
2307 [(set (pc)
2308 (if_then_else
2309 (match_operator 0 "bfin_cbranch_operator"
2310 [(match_operand:BI 1 "register_operand" "C")
2311 (match_operand:BI 2 "immediate_operand" "P0")])
2312 (label_ref (match_operand 3 "" ""))
2313 (pc)))
2314 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2315 "reload_completed"
2316 {
2317 asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
2318 return "";
2319 }
2320 [(set_attr "type" "brcc")
2321 (set_attr "length" "6")])
2323 ;; setcc insns. */
2324 (define_expand "seq"
2325 [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3)))
2326 (set (match_operand:SI 0 "register_operand" "")
2327 (ne:SI (match_dup 1) (const_int 0)))]
2328 ""
2329 {
2330 operands[2] = bfin_compare_op0;
2331 operands[3] = bfin_compare_op1;
2332 operands[1] = bfin_cc_rtx;
2333 })
2335 (define_expand "slt"
2336 [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3)))
2337 (set (match_operand:SI 0 "register_operand" "")
2338 (ne:SI (match_dup 1) (const_int 0)))]
2339 ""
2340 {
2341 operands[2] = bfin_compare_op0;
2342 operands[3] = bfin_compare_op1;
2343 operands[1] = bfin_cc_rtx;
2344 })
2346 (define_expand "sle"
2347 [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3)))
2348 (set (match_operand:SI 0 "register_operand" "")
2349 (ne:SI (match_dup 1) (const_int 0)))]
2350 ""
2351 {
2352 operands[2] = bfin_compare_op0;
2353 operands[3] = bfin_compare_op1;
2354 operands[1] = bfin_cc_rtx;
2355 })
2357 (define_expand "sltu"
2358 [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3)))
2359 (set (match_operand:SI 0 "register_operand" "")
2360 (ne:SI (match_dup 1) (const_int 0)))]
2361 ""
2362 {
2363 operands[2] = bfin_compare_op0;
2364 operands[3] = bfin_compare_op1;
2365 operands[1] = bfin_cc_rtx;
2366 })
2368 (define_expand "sleu"
2369 [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
2370 (set (match_operand:SI 0 "register_operand" "")
2371 (ne:SI (match_dup 1) (const_int 0)))]
2372 ""
2373 {
2374 operands[2] = bfin_compare_op0;
2375 operands[3] = bfin_compare_op1;
2376 operands[1] = bfin_cc_rtx;
2377 })
2379 (define_insn "nop"
2380 [(const_int 0)]
2381 ""
2382 "nop;")
2384 (define_insn "mnop"
2385 [(unspec [(const_int 0)] UNSPEC_32BIT)]
2386 ""
2387 "mnop%!"
2388 [(set_attr "type" "dsp32")])
2390 ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
2391 (define_insn "movsibi"
2392 [(set (match_operand:BI 0 "register_operand" "=C")
2393 (ne:BI (match_operand:SI 1 "register_operand" "d")
2394 (const_int 0)))]
2395 ""
2396 "CC = %1;"
2397 [(set_attr "length" "2")])
2399 (define_insn "movbisi"
2400 [(set (match_operand:SI 0 "register_operand" "=d")
2401 (ne:SI (match_operand:BI 1 "register_operand" "C")
2402 (const_int 0)))]
2403 ""
2404 "%0 = CC;"
2405 [(set_attr "length" "2")])
2407 (define_insn ""
2408 [(set (match_operand:BI 0 "register_operand" "=C")
2409 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2410 (const_int 0)))]
2411 ""
2412 "%0 = ! %0;" /* NOT CC;" */
2413 [(set_attr "type" "compare")])
2415 ;; Vector and DSP insns
2417 (define_insn ""
2418 [(set (match_operand:SI 0 "register_operand" "=d")
2419 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2420 (const_int 24))
2421 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2422 (const_int 8))))]
2423 ""
2424 "%0 = ALIGN8(%1, %2)%!"
2425 [(set_attr "type" "dsp32")])
2427 (define_insn ""
2428 [(set (match_operand:SI 0 "register_operand" "=d")
2429 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2430 (const_int 16))
2431 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2432 (const_int 16))))]
2433 ""
2434 "%0 = ALIGN16(%1, %2)%!"
2435 [(set_attr "type" "dsp32")])
2437 (define_insn ""
2438 [(set (match_operand:SI 0 "register_operand" "=d")
2439 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2440 (const_int 8))
2441 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2442 (const_int 24))))]
2443 ""
2444 "%0 = ALIGN24(%1, %2)%!"
2445 [(set_attr "type" "dsp32")])
2447 ;; Prologue and epilogue.
2449 (define_expand "prologue"
2450 [(const_int 1)]
2451 ""
2452 "bfin_expand_prologue (); DONE;")
2454 (define_expand "epilogue"
2455 [(const_int 1)]
2456 ""
2457 "bfin_expand_epilogue (1, 0); DONE;")
2459 (define_expand "sibcall_epilogue"
2460 [(const_int 1)]
2461 ""
2462 "bfin_expand_epilogue (0, 0); DONE;")
2464 (define_expand "eh_return"
2465 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")]
2466 UNSPEC_VOLATILE_EH_RETURN)]
2467 ""
2468 {
2469 emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]);
2470 emit_jump_insn (gen_eh_return_internal ());
2471 emit_barrier ();
2472 DONE;
2473 })
2475 (define_insn_and_split "eh_return_internal"
2476 [(set (pc)
2477 (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))]
2478 ""
2479 "#"
2480 "reload_completed"
2481 [(const_int 1)]
2482 "bfin_expand_epilogue (1, 1); DONE;")
2484 (define_insn "link"
2485 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2486 (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
2487 (set (reg:SI REG_FP)
2488 (plus:SI (reg:SI REG_SP) (const_int -8)))
2489 (set (reg:SI REG_SP)
2490 (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
2491 ""
2492 "LINK %Z0;"
2493 [(set_attr "length" "4")])
2495 (define_insn "unlink"
2496 [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
2497 (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
2498 (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
2499 ""
2500 "UNLINK;"
2501 [(set_attr "length" "4")])
2503 ;; This pattern is slightly clumsy. The stack adjust must be the final SET in
2504 ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
2505 ;; where on the stack, since it goes through all elements of the parallel in
2506 ;; sequence.
2507 (define_insn "push_multiple"
2508 [(match_parallel 0 "push_multiple_operation"
2509 [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
2510 ""
2511 {
2512 output_push_multiple (insn, operands);
2513 return "";
2514 })
2516 (define_insn "pop_multiple"
2517 [(match_parallel 0 "pop_multiple_operation"
2518 [(set (reg:SI REG_SP)
2519 (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
2520 ""
2521 {
2522 output_pop_multiple (insn, operands);
2523 return "";
2524 })
2526 (define_insn "return_internal"
2527 [(return)
2528 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)]
2529 "reload_completed"
2530 {
2531 switch (INTVAL (operands[0]))
2532 {
2533 case EXCPT_HANDLER:
2534 return "rtx;";
2535 case NMI_HANDLER:
2536 return "rtn;";
2537 case INTERRUPT_HANDLER:
2538 return "rti;";
2539 case SUBROUTINE:
2540 return "rts;";
2541 }
2542 gcc_unreachable ();
2543 })
2545 (define_insn "csync"
2546 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2547 ""
2548 "csync;"
2549 [(set_attr "type" "sync")])
2551 (define_insn "ssync"
2552 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
2553 ""
2554 "ssync;"
2555 [(set_attr "type" "sync")])
2557 (define_insn "trap"
2558 [(trap_if (const_int 1) (const_int 3))]
2559 ""
2560 "excpt 3;"
2561 [(set_attr "type" "misc")
2562 (set_attr "length" "2")])
2564 (define_insn "trapifcc"
2565 [(trap_if (reg:BI REG_CC) (const_int 3))]
2566 ""
2567 "if !cc jump 4 (bp); excpt 3;"
2568 [(set_attr "type" "misc")
2569 (set_attr "length" "4")
2570 (set_attr "seq_insns" "multi")])
2572 ;;; Vector instructions
2574 ;; First, all sorts of move variants
2576 (define_insn "movhi_low2high"
2577 [(set (match_operand:V2HI 0 "register_operand" "=d")
2578 (vec_concat:V2HI
2579 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2580 (parallel [(const_int 0)]))
2581 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2582 (parallel [(const_int 0)]))))]
2583 ""
2584 "%d0 = %h2 << 0%!"
2585 [(set_attr "type" "dsp32")])
2587 (define_insn "movhi_high2high"
2588 [(set (match_operand:V2HI 0 "register_operand" "=d")
2589 (vec_concat:V2HI
2590 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2591 (parallel [(const_int 0)]))
2592 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2593 (parallel [(const_int 1)]))))]
2594 ""
2595 "%d0 = %d2 << 0%!"
2596 [(set_attr "type" "dsp32")])
2598 (define_insn "movhi_low2low"
2599 [(set (match_operand:V2HI 0 "register_operand" "=d")
2600 (vec_concat:V2HI
2601 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2602 (parallel [(const_int 0)]))
2603 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2604 (parallel [(const_int 1)]))))]
2605 ""
2606 "%h0 = %h2 << 0%!"
2607 [(set_attr "type" "dsp32")])
2609 (define_insn "movhi_high2low"
2610 [(set (match_operand:V2HI 0 "register_operand" "=d")
2611 (vec_concat:V2HI
2612 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2613 (parallel [(const_int 1)]))
2614 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2615 (parallel [(const_int 1)]))))]
2616 ""
2617 "%h0 = %d2 << 0%!"
2618 [(set_attr "type" "dsp32")])
2620 (define_insn "movhiv2hi_low"
2621 [(set (match_operand:V2HI 0 "register_operand" "=d")
2622 (vec_concat:V2HI
2623 (match_operand:HI 2 "register_operand" "d")
2624 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2625 (parallel [(const_int 1)]))))]
2626 ""
2627 "%h0 = %h2 << 0%!"
2628 [(set_attr "type" "dsp32")])
2630 (define_insn "movhiv2hi_high"
2631 [(set (match_operand:V2HI 0 "register_operand" "=d")
2632 (vec_concat:V2HI
2633 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2634 (parallel [(const_int 0)]))
2635 (match_operand:HI 2 "register_operand" "d")))]
2636 ""
2637 "%d0 = %h2 << 0%!"
2638 [(set_attr "type" "dsp32")])
2640 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2641 ;; The order of operands is intentional to match the VDSP builtin (high word
2642 ;; is passed first).
2643 (define_insn_and_split "composev2hi"
2644 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
2645 (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
2646 (match_operand:HI 1 "register_operand" "d,d")))]
2647 ""
2648 "@
2649 %d0 = %h2 << 0%!
2650 #"
2651 "reload_completed"
2652 [(set (match_dup 0)
2653 (vec_concat:V2HI
2654 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
2655 (match_dup 2)))
2656 (set (match_dup 0)
2657 (vec_concat:V2HI
2658 (match_dup 1)
2659 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2660 ""
2661 [(set_attr "type" "dsp32")])
2663 ; Like composev2hi, but operating on elements of V2HI vectors.
2664 ; Useful on its own, and as a combiner bridge for the multiply and
2665 ; mac patterns.
2666 (define_insn "packv2hi"
2667 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d")
2668 (vec_concat:V2HI (vec_select:HI
2669 (match_operand:V2HI 1 "register_operand" "d,d,d,d")
2670 (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")]))
2671 (vec_select:HI
2672 (match_operand:V2HI 2 "register_operand" "d,d,d,d")
2673 (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))]
2674 ""
2675 "@
2676 %0 = PACK (%h2,%h1)%!
2677 %0 = PACK (%h2,%d1)%!
2678 %0 = PACK (%d2,%h1)%!
2679 %0 = PACK (%d2,%d1)%!"
2680 [(set_attr "type" "dsp32")])
2682 (define_insn "movv2hi_hi"
2683 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2684 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2685 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2686 ""
2687 "@
2688 /* optimized out */
2689 %h0 = %h1 << 0%!
2690 %h0 = %d1 << 0%!"
2691 [(set_attr "type" "dsp32")])
2693 (define_expand "movv2hi_hi_low"
2694 [(set (match_operand:HI 0 "register_operand" "")
2695 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2696 (parallel [(const_int 0)])))]
2697 ""
2698 "")
2700 (define_expand "movv2hi_hi_high"
2701 [(set (match_operand:HI 0 "register_operand" "")
2702 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2703 (parallel [(const_int 1)])))]
2704 ""
2705 "")
2707 ;; Unusual arithmetic operations on 16-bit registers.
2709 (define_insn "ssaddhi3"
2710 [(set (match_operand:HI 0 "register_operand" "=d")
2711 (ss_plus:HI (match_operand:HI 1 "register_operand" "d")
2712 (match_operand:HI 2 "register_operand" "d")))]
2713 ""
2714 "%h0 = %h1 + %h2 (S)%!"
2715 [(set_attr "type" "dsp32")])
2717 (define_insn "sssubhi3"
2718 [(set (match_operand:HI 0 "register_operand" "=d")
2719 (ss_minus:HI (match_operand:HI 1 "register_operand" "d")
2720 (match_operand:HI 2 "register_operand" "d")))]
2721 ""
2722 "%h0 = %h1 - %h2 (S)%!"
2723 [(set_attr "type" "dsp32")])
2725 ;; V2HI vector insns
2727 (define_insn "addv2hi3"
2728 [(set (match_operand:V2HI 0 "register_operand" "=d")
2729 (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2730 (match_operand:V2HI 2 "register_operand" "d")))]
2731 ""
2732 "%0 = %1 +|+ %2%!"
2733 [(set_attr "type" "dsp32")])
2735 (define_insn "ssaddv2hi3"
2736 [(set (match_operand:V2HI 0 "register_operand" "=d")
2737 (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2738 (match_operand:V2HI 2 "register_operand" "d")))]
2739 ""
2740 "%0 = %1 +|+ %2 (S)%!"
2741 [(set_attr "type" "dsp32")])
2743 (define_insn "subv2hi3"
2744 [(set (match_operand:V2HI 0 "register_operand" "=d")
2745 (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2746 (match_operand:V2HI 2 "register_operand" "d")))]
2747 ""
2748 "%0 = %1 -|- %2%!"
2749 [(set_attr "type" "dsp32")])
2751 (define_insn "sssubv2hi3"
2752 [(set (match_operand:V2HI 0 "register_operand" "=d")
2753 (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2754 (match_operand:V2HI 2 "register_operand" "d")))]
2755 ""
2756 "%0 = %1 -|- %2 (S)%!"
2757 [(set_attr "type" "dsp32")])
2759 (define_insn "addsubv2hi3"
2760 [(set (match_operand:V2HI 0 "register_operand" "=d")
2761 (vec_concat:V2HI
2762 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2763 (parallel [(const_int 0)]))
2764 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2765 (parallel [(const_int 0)])))
2766 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2767 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2768 ""
2769 "%0 = %1 +|- %2%!"
2770 [(set_attr "type" "dsp32")])
2772 (define_insn "subaddv2hi3"
2773 [(set (match_operand:V2HI 0 "register_operand" "=d")
2774 (vec_concat:V2HI
2775 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2776 (parallel [(const_int 0)]))
2777 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2778 (parallel [(const_int 0)])))
2779 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2780 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2781 ""
2782 "%0 = %1 -|+ %2%!"
2783 [(set_attr "type" "dsp32")])
2785 (define_insn "ssaddsubv2hi3"
2786 [(set (match_operand:V2HI 0 "register_operand" "=d")
2787 (vec_concat:V2HI
2788 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2789 (parallel [(const_int 0)]))
2790 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2791 (parallel [(const_int 0)])))
2792 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2793 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2794 ""
2795 "%0 = %1 +|- %2 (S)%!"
2796 [(set_attr "type" "dsp32")])
2798 (define_insn "sssubaddv2hi3"
2799 [(set (match_operand:V2HI 0 "register_operand" "=d")
2800 (vec_concat:V2HI
2801 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2802 (parallel [(const_int 0)]))
2803 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2804 (parallel [(const_int 0)])))
2805 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2806 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2807 ""
2808 "%0 = %1 -|+ %2 (S)%!"
2809 [(set_attr "type" "dsp32")])
2811 (define_insn "sublohiv2hi3"
2812 [(set (match_operand:HI 0 "register_operand" "=d")
2813 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2814 (parallel [(const_int 1)]))
2815 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2816 (parallel [(const_int 0)]))))]
2817 ""
2818 "%h0 = %d1 - %h2%!"
2819 [(set_attr "type" "dsp32")])
2821 (define_insn "subhilov2hi3"
2822 [(set (match_operand:HI 0 "register_operand" "=d")
2823 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2824 (parallel [(const_int 0)]))
2825 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2826 (parallel [(const_int 1)]))))]
2827 ""
2828 "%h0 = %h1 - %d2%!"
2829 [(set_attr "type" "dsp32")])
2831 (define_insn "sssublohiv2hi3"
2832 [(set (match_operand:HI 0 "register_operand" "=d")
2833 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2834 (parallel [(const_int 1)]))
2835 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2836 (parallel [(const_int 0)]))))]
2837 ""
2838 "%h0 = %d1 - %h2 (S)%!"
2839 [(set_attr "type" "dsp32")])
2841 (define_insn "sssubhilov2hi3"
2842 [(set (match_operand:HI 0 "register_operand" "=d")
2843 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2844 (parallel [(const_int 0)]))
2845 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2846 (parallel [(const_int 1)]))))]
2847 ""
2848 "%h0 = %h1 - %d2 (S)%!"
2849 [(set_attr "type" "dsp32")])
2851 (define_insn "addlohiv2hi3"
2852 [(set (match_operand:HI 0 "register_operand" "=d")
2853 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2854 (parallel [(const_int 1)]))
2855 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2856 (parallel [(const_int 0)]))))]
2857 ""
2858 "%h0 = %d1 + %h2%!"
2859 [(set_attr "type" "dsp32")])
2861 (define_insn "addhilov2hi3"
2862 [(set (match_operand:HI 0 "register_operand" "=d")
2863 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2864 (parallel [(const_int 0)]))
2865 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2866 (parallel [(const_int 1)]))))]
2867 ""
2868 "%h0 = %h1 + %d2%!"
2869 [(set_attr "type" "dsp32")])
2871 (define_insn "ssaddlohiv2hi3"
2872 [(set (match_operand:HI 0 "register_operand" "=d")
2873 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2874 (parallel [(const_int 1)]))
2875 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2876 (parallel [(const_int 0)]))))]
2877 ""
2878 "%h0 = %d1 + %h2 (S)%!"
2879 [(set_attr "type" "dsp32")])
2881 (define_insn "ssaddhilov2hi3"
2882 [(set (match_operand:HI 0 "register_operand" "=d")
2883 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2884 (parallel [(const_int 0)]))
2885 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2886 (parallel [(const_int 1)]))))]
2887 ""
2888 "%h0 = %h1 + %d2 (S)%!"
2889 [(set_attr "type" "dsp32")])
2891 (define_insn "sminv2hi3"
2892 [(set (match_operand:V2HI 0 "register_operand" "=d")
2893 (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
2894 (match_operand:V2HI 2 "register_operand" "d")))]
2895 ""
2896 "%0 = MIN (%1, %2) (V)%!"
2897 [(set_attr "type" "dsp32")])
2899 (define_insn "smaxv2hi3"
2900 [(set (match_operand:V2HI 0 "register_operand" "=d")
2901 (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
2902 (match_operand:V2HI 2 "register_operand" "d")))]
2903 ""
2904 "%0 = MAX (%1, %2) (V)%!"
2905 [(set_attr "type" "dsp32")])
2907 ;; Multiplications.
2909 ;; The Blackfin allows a lot of different options, and we need many patterns to
2910 ;; cover most of the hardware's abilities.
2911 ;; There are a few simple patterns using MULT rtx codes, but most of them use
2912 ;; an unspec with a const_int operand that determines which flag to use in the
2913 ;; instruction.
2914 ;; There are variants for single and parallel multiplications.
2915 ;; There are variants which just use 16-bit lowparts as inputs, and variants
2916 ;; which allow the user to choose just which halves to use as input values.
2917 ;; There are variants which set D registers, variants which set accumulators,
2918 ;; variants which set both, some of them optionally using the accumulators as
2919 ;; inputs for multiply-accumulate operations.
2921 (define_insn "flag_mulhi"
2922 [(set (match_operand:HI 0 "register_operand" "=d")
2923 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2924 (match_operand:HI 2 "register_operand" "d")
2925 (match_operand 3 "const_int_operand" "n")]
2926 UNSPEC_MUL_WITH_FLAG))]
2927 ""
2928 "%h0 = %h1 * %h2 %M3%!"
2929 [(set_attr "type" "dsp32")])
2931 (define_insn "flag_mulhisi"
2932 [(set (match_operand:SI 0 "register_operand" "=d")
2933 (unspec:SI [(match_operand:HI 1 "register_operand" "d")
2934 (match_operand:HI 2 "register_operand" "d")
2935 (match_operand 3 "const_int_operand" "n")]
2936 UNSPEC_MUL_WITH_FLAG))]
2937 ""
2938 "%0 = %h1 * %h2 %M3%!"
2939 [(set_attr "type" "dsp32")])
2941 (define_insn "flag_mulhisi_parts"
2942 [(set (match_operand:SI 0 "register_operand" "=d")
2943 (unspec:SI [(vec_select:HI
2944 (match_operand:V2HI 1 "register_operand" "d")
2945 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2946 (vec_select:HI
2947 (match_operand:V2HI 2 "register_operand" "d")
2948 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
2949 (match_operand 5 "const_int_operand" "n")]
2950 UNSPEC_MUL_WITH_FLAG))]
2951 ""
2952 {
2953 const char *templates[] = {
2954 "%0 = %h1 * %h2 %M5%!",
2955 "%0 = %d1 * %h2 %M5%!",
2956 "%0 = %h1 * %d2 %M5%!",
2957 "%0 = %d1 * %d2 %M5%!" };
2958 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
2959 return templates[alt];
2960 }
2961 [(set_attr "type" "dsp32")])
2963 (define_insn "flag_machi"
2964 [(set (match_operand:HI 0 "register_operand" "=d")
2965 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2966 (match_operand:HI 2 "register_operand" "d")
2967 (match_operand 3 "register_operand" "A")
2968 (match_operand 4 "const01_operand" "P0P1")
2969 (match_operand 5 "const_int_operand" "n")]
2970 UNSPEC_MAC_WITH_FLAG))
2971 (set (match_operand:PDI 6 "register_operand" "=A")
2972 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
2973 (match_dup 4) (match_dup 5)]
2974 UNSPEC_MAC_WITH_FLAG))]
2975 ""
2976 "%h0 = (A0 %b4 %h1 * %h2) %M6%!"
2977 [(set_attr "type" "dsp32")])
2979 (define_insn "flag_machi_acconly"
2980 [(set (match_operand:PDI 0 "register_operand" "=e")
2981 (unspec:PDI [(match_operand:HI 1 "register_operand" "d")
2982 (match_operand:HI 2 "register_operand" "d")
2983 (match_operand 3 "register_operand" "A")
2984 (match_operand 4 "const01_operand" "P0P1")
2985 (match_operand 5 "const_int_operand" "n")]
2986 UNSPEC_MAC_WITH_FLAG))]
2987 ""
2988 "%0 %b4 %h1 * %h2 %M6%!"
2989 [(set_attr "type" "dsp32")])
2991 (define_insn "flag_macinithi"
2992 [(set (match_operand:HI 0 "register_operand" "=d")
2993 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2994 (match_operand:HI 2 "register_operand" "d")
2995 (match_operand 3 "const_int_operand" "n")]
2996 UNSPEC_MAC_WITH_FLAG))
2997 (set (match_operand:PDI 4 "register_operand" "=A")
2998 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
2999 UNSPEC_MAC_WITH_FLAG))]
3000 ""
3001 "%h0 = (A0 = %h1 * %h2) %M3%!"
3002 [(set_attr "type" "dsp32")])
3004 (define_insn "flag_macinit1hi"
3005 [(set (match_operand:PDI 0 "register_operand" "=e")
3006 (unspec:PDI [(match_operand:HI 1 "register_operand" "d")
3007 (match_operand:HI 2 "register_operand" "d")
3008 (match_operand 3 "const_int_operand" "n")]
3009 UNSPEC_MAC_WITH_FLAG))]
3010 ""
3011 "%0 = %h1 * %h2 %M3%!"
3012 [(set_attr "type" "dsp32")])
3014 (define_insn "mulv2hi3"
3015 [(set (match_operand:V2HI 0 "register_operand" "=d")
3016 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
3017 (match_operand:V2HI 2 "register_operand" "d")))]
3018 ""
3019 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!"
3020 [(set_attr "type" "dsp32")])
3022 (define_insn "flag_mulv2hi"
3023 [(set (match_operand:V2HI 0 "register_operand" "=d")
3024 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
3025 (match_operand:V2HI 2 "register_operand" "d")
3026 (match_operand 3 "const_int_operand" "n")]
3027 UNSPEC_MUL_WITH_FLAG))]
3028 ""
3029 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!"
3030 [(set_attr "type" "dsp32")])
3032 (define_insn "flag_mulv2hi_parts"
3033 [(set (match_operand:V2HI 0 "register_operand" "=d")
3034 (unspec:V2HI [(vec_concat:V2HI
3035 (vec_select:HI
3036 (match_operand:V2HI 1 "register_operand" "d")
3037 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3038 (vec_select:HI
3039 (match_dup 1)
3040 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3041 (vec_concat:V2HI
3042 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3043 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3044 (vec_select:HI (match_dup 2)
3045 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3046 (match_operand 7 "const_int_operand" "n")]
3047 UNSPEC_MUL_WITH_FLAG))]
3048 ""
3049 {
3050 const char *templates[] = {
3051 "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!",
3052 "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!",
3053 "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!",
3054 "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!",
3055 "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!",
3056 "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!",
3057 "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!",
3058 "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!",
3059 "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!",
3060 "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!",
3061 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!",
3062 "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!",
3063 "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!",
3064 "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!",
3065 "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!",
3066 "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" };
3067 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3068 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3069 return templates[alt];
3070 }
3071 [(set_attr "type" "dsp32")])
3073 ;; A slightly complicated pattern.
3074 ;; Operand 0 is the halfword output; operand 11 is the accumulator output
3075 ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
3076 ;; parts of these 2x16 bit registers to use.
3077 ;; Operand 7 is the accumulator input.
3078 ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
3079 ;; Operand 10 is the macflag to be used.
3080 (define_insn "flag_macv2hi_parts"
3081 [(set (match_operand:V2HI 0 "register_operand" "=d")
3082 (unspec:V2HI [(vec_concat:V2HI
3083 (vec_select:HI
3084 (match_operand:V2HI 1 "register_operand" "d")
3085 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3086 (vec_select:HI
3087 (match_dup 1)
3088 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3089 (vec_concat:V2HI
3090 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3091 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3092 (vec_select:HI (match_dup 2)
3093 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3094 (match_operand:V2PDI 7 "register_operand" "e")
3095 (match_operand 8 "const01_operand" "P0P1")
3096 (match_operand 9 "const01_operand" "P0P1")
3097 (match_operand 10 "const_int_operand" "n")]
3098 UNSPEC_MAC_WITH_FLAG))
3099 (set (match_operand:V2PDI 11 "register_operand" "=e")
3100 (unspec:V2PDI [(vec_concat:V2HI
3101 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3102 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3103 (vec_concat:V2HI
3104 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3105 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3106 (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
3107 UNSPEC_MAC_WITH_FLAG))]
3108 ""
3109 {
3110 const char *templates[] = {
3111 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3112 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3113 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3114 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3115 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3116 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3117 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3118 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3119 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3120 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3121 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3122 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3123 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3124 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3125 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3126 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" };
3127 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3128 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3129 return templates[alt];
3130 }
3131 [(set_attr "type" "dsp32")])
3133 (define_insn "flag_macv2hi_parts_acconly"
3134 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3135 (unspec:V2PDI [(vec_concat:V2HI
3136 (vec_select:HI
3137 (match_operand:V2HI 1 "register_operand" "d")
3138 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3139 (vec_select:HI
3140 (match_dup 1)
3141 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3142 (vec_concat:V2HI
3143 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3144 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3145 (vec_select:HI (match_dup 2)
3146 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3147 (match_operand:V2PDI 7 "register_operand" "e")
3148 (match_operand 8 "const01_operand" "P0P1")
3149 (match_operand 9 "const01_operand" "P0P1")
3150 (match_operand 10 "const_int_operand" "n")]
3151 UNSPEC_MAC_WITH_FLAG))]
3152 ""
3153 {
3154 const char *templates[] = {
3155 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3156 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3157 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3158 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3159 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3160 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3161 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3162 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3163 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3164 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3165 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3166 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3167 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3168 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3169 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!",
3170 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" };
3171 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3172 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3173 return templates[alt];
3174 }
3175 [(set_attr "type" "dsp32")])
3177 ;; Same as above, but initializing the accumulators and therefore a couple fewer
3178 ;; necessary operands.
3179 (define_insn "flag_macinitv2hi_parts"
3180 [(set (match_operand:V2HI 0 "register_operand" "=d")
3181 (unspec:V2HI [(vec_concat:V2HI
3182 (vec_select:HI
3183 (match_operand:V2HI 1 "register_operand" "d")
3184 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3185 (vec_select:HI
3186 (match_dup 1)
3187 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3188 (vec_concat:V2HI
3189 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3190 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3191 (vec_select:HI (match_dup 2)
3192 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3193 (match_operand 7 "const_int_operand" "n")]
3194 UNSPEC_MAC_WITH_FLAG))
3195 (set (match_operand:V2PDI 8 "register_operand" "=e")
3196 (unspec:V2PDI [(vec_concat:V2HI
3197 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3198 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3199 (vec_concat:V2HI
3200 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3201 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3202 (match_dup 7)]
3203 UNSPEC_MAC_WITH_FLAG))]
3204 ""
3205 {
3206 const char *templates[] = {
3207 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3208 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3209 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3210 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3211 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3212 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3213 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3214 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3215 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3216 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3217 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3218 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3219 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3220 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3221 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!",
3222 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" };
3223 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3224 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3225 return templates[alt];
3226 }
3227 [(set_attr "type" "dsp32")])
3229 (define_insn "flag_macinit1v2hi_parts"
3230 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3231 (unspec:V2PDI [(vec_concat:V2HI
3232 (vec_select:HI
3233 (match_operand:V2HI 1 "register_operand" "d")
3234 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3235 (vec_select:HI
3236 (match_dup 1)
3237 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3238 (vec_concat:V2HI
3239 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3240 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3241 (vec_select:HI (match_dup 2)
3242 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3243 (match_operand 7 "const_int_operand" "n")]
3244 UNSPEC_MAC_WITH_FLAG))]
3245 ""
3246 {
3247 const char *templates[] = {
3248 "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!",
3249 "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!",
3250 "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!",
3251 "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!",
3252 "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!",
3253 "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!",
3254 "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!",
3255 "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!",
3256 "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!",
3257 "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!",
3258 "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!",
3259 "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!",
3260 "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!",
3261 "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!",
3262 "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!",
3263 "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" };
3264 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3265 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3266 return templates[alt];
3267 }
3268 [(set_attr "type" "dsp32")])
3270 (define_code_macro s_or_u [sign_extend zero_extend])
3271 (define_code_attr su_optab [(sign_extend "mul")
3272 (zero_extend "umul")])
3273 (define_code_attr su_modifier [(sign_extend "IS")
3274 (zero_extend "FU")])
3276 (define_insn "<su_optab>hisi_ll"
3277 [(set (match_operand:SI 0 "register_operand" "=d")
3278 (mult:SI (s_or_u:SI
3279 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3280 (parallel [(const_int 0)])))
3281 (s_or_u:SI
3282 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3283 (parallel [(const_int 0)])))))]
3284 ""
3285 "%0 = %h1 * %h2 (<su_modifier>)%!"
3286 [(set_attr "type" "dsp32")])
3288 (define_insn "<su_optab>hisi_lh"
3289 [(set (match_operand:SI 0 "register_operand" "=d")
3290 (mult:SI (s_or_u:SI
3291 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3292 (parallel [(const_int 0)])))
3293 (s_or_u:SI
3294 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3295 (parallel [(const_int 1)])))))]
3296 ""
3297 "%0 = %h1 * %d2 (<su_modifier>)%!"
3298 [(set_attr "type" "dsp32")])
3300 (define_insn "<su_optab>hisi_hl"
3301 [(set (match_operand:SI 0 "register_operand" "=d")
3302 (mult:SI (s_or_u:SI
3303 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3304 (parallel [(const_int 1)])))
3305 (s_or_u:SI
3306 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3307 (parallel [(const_int 0)])))))]
3308 ""
3309 "%0 = %d1 * %h2 (<su_modifier>)%!"
3310 [(set_attr "type" "dsp32")])
3312 (define_insn "<su_optab>hisi_hh"
3313 [(set (match_operand:SI 0 "register_operand" "=d")
3314 (mult:SI (s_or_u:SI
3315 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3316 (parallel [(const_int 1)])))
3317 (s_or_u:SI
3318 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3319 (parallel [(const_int 1)])))))]
3320 ""
3321 "%0 = %d1 * %d2 (<su_modifier>)%!"
3322 [(set_attr "type" "dsp32")])
3324 ;; Additional variants for signed * unsigned multiply.
3326 (define_insn "usmulhisi_ull"
3327 [(set (match_operand:SI 0 "register_operand" "=W")
3328 (mult:SI (zero_extend:SI
3329 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3330 (parallel [(const_int 0)])))
3331 (sign_extend:SI
3332 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3333 (parallel [(const_int 0)])))))]
3334 ""
3335 "%0 = %h2 * %h1 (IS,M)%!"
3336 [(set_attr "type" "dsp32")])
3338 (define_insn "usmulhisi_ulh"
3339 [(set (match_operand:SI 0 "register_operand" "=W")
3340 (mult:SI (zero_extend:SI
3341 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3342 (parallel [(const_int 0)])))
3343 (sign_extend:SI
3344 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3345 (parallel [(const_int 1)])))))]
3346 ""
3347 "%0 = %d2 * %h1 (IS,M)%!"
3348 [(set_attr "type" "dsp32")])
3350 (define_insn "usmulhisi_uhl"
3351 [(set (match_operand:SI 0 "register_operand" "=W")
3352 (mult:SI (zero_extend:SI
3353 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3354 (parallel [(const_int 1)])))
3355 (sign_extend:SI
3356 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3357 (parallel [(const_int 0)])))))]
3358 ""
3359 "%0 = %h2 * %d1 (IS,M)%!"
3360 [(set_attr "type" "dsp32")])
3362 (define_insn "usmulhisi_uhh"
3363 [(set (match_operand:SI 0 "register_operand" "=W")
3364 (mult:SI (zero_extend:SI
3365 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3366 (parallel [(const_int 1)])))
3367 (sign_extend:SI
3368 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3369 (parallel [(const_int 1)])))))]
3370 ""
3371 "%0 = %d2 * %d1 (IS,M)%!"
3372 [(set_attr "type" "dsp32")])
3374 ;; Parallel versions of these operations. First, normal signed or unsigned
3375 ;; multiplies.
3377 (define_insn "<su_optab>hisi_ll_lh"
3378 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3379 (mult:SI (s_or_u:SI
3380 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3381 (parallel [(const_int 0)])))
3382 (s_or_u:SI
3383 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3384 (parallel [(const_int 0)])))))
3385 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3386 (mult:SI (s_or_u:SI
3387 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3388 (s_or_u:SI
3389 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3390 ""
3391 "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
3392 [(set_attr "type" "dsp32")])
3394 (define_insn "<su_optab>hisi_ll_hl"
3395 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3396 (mult:SI (s_or_u:SI
3397 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3398 (parallel [(const_int 0)])))
3399 (s_or_u:SI
3400 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3401 (parallel [(const_int 0)])))))
3402 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3403 (mult:SI (s_or_u:SI
3404 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3405 (s_or_u:SI
3406 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3407 ""
3408 "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
3409 [(set_attr "type" "dsp32")])
3411 (define_insn "<su_optab>hisi_ll_hh"
3412 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3413 (mult:SI (s_or_u:SI
3414 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3415 (parallel [(const_int 0)])))
3416 (s_or_u:SI
3417 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3418 (parallel [(const_int 0)])))))
3419 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3420 (mult:SI (s_or_u:SI
3421 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3422 (s_or_u:SI
3423 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3424 ""
3425 "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3426 [(set_attr "type" "dsp32")])
3428 (define_insn "<su_optab>hisi_lh_hl"
3429 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3430 (mult:SI (s_or_u:SI
3431 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3432 (parallel [(const_int 0)])))
3433 (s_or_u:SI
3434 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3435 (parallel [(const_int 1)])))))
3436 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3437 (mult:SI (s_or_u:SI
3438 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3439 (s_or_u:SI
3440 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3441 ""
3442 "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
3443 [(set_attr "type" "dsp32")])
3445 (define_insn "<su_optab>hisi_lh_hh"
3446 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3447 (mult:SI (s_or_u:SI
3448 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3449 (parallel [(const_int 0)])))
3450 (s_or_u:SI
3451 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3452 (parallel [(const_int 1)])))))
3453 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3454 (mult:SI (s_or_u:SI
3455 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3456 (s_or_u:SI
3457 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3458 ""
3459 "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
3460 [(set_attr "type" "dsp32")])
3462 (define_insn "<su_optab>hisi_hl_hh"
3463 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3464 (mult:SI (s_or_u:SI
3465 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3466 (parallel [(const_int 1)])))
3467 (s_or_u:SI
3468 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3469 (parallel [(const_int 0)])))))
3470 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3471 (mult:SI (s_or_u:SI
3472 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3473 (s_or_u:SI
3474 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3475 ""
3476 "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3477 [(set_attr "type" "dsp32")])
3479 ;; Special signed * unsigned variants.
3481 (define_insn "usmulhisi_ll_lul"
3482 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3483 (mult:SI (sign_extend:SI
3484 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3485 (parallel [(const_int 0)])))
3486 (sign_extend:SI
3487 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3488 (parallel [(const_int 0)])))))
3489 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3490 (mult:SI (sign_extend:SI
3491 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3492 (zero_extend:SI
3493 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3494 ""
3495 "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3496 [(set_attr "type" "dsp32")])
3498 (define_insn "usmulhisi_ll_luh"
3499 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3500 (mult:SI (sign_extend:SI
3501 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3502 (parallel [(const_int 0)])))
3503 (sign_extend:SI
3504 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3505 (parallel [(const_int 0)])))))
3506 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3507 (mult:SI (sign_extend:SI
3508 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3509 (zero_extend:SI
3510 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3511 ""
3512 "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3513 [(set_attr "type" "dsp32")])
3515 (define_insn "usmulhisi_ll_hul"
3516 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3517 (mult:SI (sign_extend:SI
3518 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3519 (parallel [(const_int 0)])))
3520 (sign_extend:SI
3521 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3522 (parallel [(const_int 0)])))))
3523 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3524 (mult:SI (sign_extend:SI
3525 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3526 (zero_extend:SI
3527 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3528 ""
3529 "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3530 [(set_attr "type" "dsp32")])
3532 (define_insn "usmulhisi_ll_huh"
3533 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3534 (mult:SI (sign_extend:SI
3535 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3536 (parallel [(const_int 0)])))
3537 (sign_extend:SI
3538 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3539 (parallel [(const_int 0)])))))
3540 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3541 (mult:SI (sign_extend:SI
3542 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3543 (zero_extend:SI
3544 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3545 ""
3546 "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3547 [(set_attr "type" "dsp32")])
3549 (define_insn "usmulhisi_lh_lul"
3550 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3551 (mult:SI (sign_extend:SI
3552 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3553 (parallel [(const_int 0)])))
3554 (sign_extend:SI
3555 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3556 (parallel [(const_int 1)])))))
3557 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3558 (mult:SI (sign_extend:SI
3559 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3560 (zero_extend:SI
3561 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3562 ""
3563 "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3564 [(set_attr "type" "dsp32")])
3566 (define_insn "usmulhisi_lh_luh"
3567 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3568 (mult:SI (sign_extend:SI
3569 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3570 (parallel [(const_int 0)])))
3571 (sign_extend:SI
3572 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3573 (parallel [(const_int 1)])))))
3574 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3575 (mult:SI (sign_extend:SI
3576 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3577 (zero_extend:SI
3578 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3579 ""
3580 "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3581 [(set_attr "type" "dsp32")])
3583 (define_insn "usmulhisi_lh_hul"
3584 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3585 (mult:SI (sign_extend:SI
3586 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3587 (parallel [(const_int 0)])))
3588 (sign_extend:SI
3589 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3590 (parallel [(const_int 1)])))))
3591 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3592 (mult:SI (sign_extend:SI
3593 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3594 (zero_extend:SI
3595 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3596 ""
3597 "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3598 [(set_attr "type" "dsp32")])
3600 (define_insn "usmulhisi_lh_huh"
3601 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3602 (mult:SI (sign_extend:SI
3603 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3604 (parallel [(const_int 0)])))
3605 (sign_extend:SI
3606 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3607 (parallel [(const_int 1)])))))
3608 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3609 (mult:SI (sign_extend:SI
3610 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3611 (zero_extend:SI
3612 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3613 ""
3614 "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
3615 [(set_attr "type" "dsp32")])
3617 (define_insn "usmulhisi_hl_lul"
3618 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3619 (mult:SI (sign_extend:SI
3620 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3621 (parallel [(const_int 1)])))
3622 (sign_extend:SI
3623 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3624 (parallel [(const_int 0)])))))
3625 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3626 (mult:SI (sign_extend:SI
3627 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3628 (zero_extend:SI
3629 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3630 ""
3631 "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3632 [(set_attr "type" "dsp32")])
3634 (define_insn "usmulhisi_hl_luh"
3635 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3636 (mult:SI (sign_extend:SI
3637 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3638 (parallel [(const_int 1)])))
3639 (sign_extend:SI
3640 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3641 (parallel [(const_int 0)])))))
3642 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3643 (mult:SI (sign_extend:SI
3644 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3645 (zero_extend:SI
3646 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3647 ""
3648 "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3649 [(set_attr "type" "dsp32")])
3651 (define_insn "usmulhisi_hl_hul"
3652 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3653 (mult:SI (sign_extend:SI
3654 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3655 (parallel [(const_int 1)])))
3656 (sign_extend:SI
3657 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3658 (parallel [(const_int 0)])))))
3659 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3660 (mult:SI (sign_extend:SI
3661 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3662 (zero_extend:SI
3663 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3664 ""
3665 "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3666 [(set_attr "type" "dsp32")])
3668 (define_insn "usmulhisi_hl_huh"
3669 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3670 (mult:SI (sign_extend:SI
3671 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3672 (parallel [(const_int 1)])))
3673 (sign_extend:SI
3674 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3675 (parallel [(const_int 0)])))))
3676 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3677 (mult:SI (sign_extend:SI
3678 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3679 (zero_extend:SI
3680 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3681 ""
3682 "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3683 [(set_attr "type" "dsp32")])
3685 (define_insn "usmulhisi_hh_lul"
3686 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3687 (mult:SI (sign_extend:SI
3688 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3689 (parallel [(const_int 1)])))
3690 (sign_extend:SI
3691 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3692 (parallel [(const_int 1)])))))
3693 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3694 (mult:SI (sign_extend:SI
3695 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3696 (zero_extend:SI
3697 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3698 ""
3699 "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3700 [(set_attr "type" "dsp32")])
3702 (define_insn "usmulhisi_hh_luh"
3703 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3704 (mult:SI (sign_extend:SI
3705 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3706 (parallel [(const_int 1)])))
3707 (sign_extend:SI
3708 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3709 (parallel [(const_int 1)])))))
3710 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3711 (mult:SI (sign_extend:SI
3712 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3713 (zero_extend:SI
3714 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3715 ""
3716 "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3717 [(set_attr "type" "dsp32")])
3719 (define_insn "usmulhisi_hh_hul"
3720 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3721 (mult:SI (sign_extend:SI
3722 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3723 (parallel [(const_int 1)])))
3724 (sign_extend:SI
3725 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3726 (parallel [(const_int 1)])))))
3727 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3728 (mult:SI (sign_extend:SI
3729 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3730 (zero_extend:SI
3731 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3732 ""
3733 "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3734 [(set_attr "type" "dsp32")])
3736 (define_insn "usmulhisi_hh_huh"
3737 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3738 (mult:SI (sign_extend:SI
3739 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3740 (parallel [(const_int 1)])))
3741 (sign_extend:SI
3742 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3743 (parallel [(const_int 1)])))))
3744 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3745 (mult:SI (sign_extend:SI
3746 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3747 (zero_extend:SI
3748 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3749 ""
3750 "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
3751 [(set_attr "type" "dsp32")])
3753 ;; Vector neg/abs.
3755 (define_insn "ssnegv2hi2"
3756 [(set (match_operand:V2HI 0 "register_operand" "=d")
3757 (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3758 ""
3759 "%0 = - %1 (V)%!"
3760 [(set_attr "type" "dsp32")])
3762 (define_insn "absv2hi2"
3763 [(set (match_operand:V2HI 0 "register_operand" "=d")
3764 (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3765 ""
3766 "%0 = ABS %1 (V)%!"
3767 [(set_attr "type" "dsp32")])
3769 ;; Shifts.
3771 (define_insn "ssashiftv2hi3"
3772 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3773 (if_then_else:V2HI
3774 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3775 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3776 (match_dup 2))
3777 (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
3778 ""
3779 "@
3780 %0 = ASHIFT %1 BY %h2 (V, S)%!
3781 %0 = %1 << %2 (V,S)%!
3782 %0 = %1 >>> %N2 (V,S)%!"
3783 [(set_attr "type" "dsp32")])
3785 (define_insn "ssashifthi3"
3786 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3787 (if_then_else:HI
3788 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3789 (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3790 (match_dup 2))
3791 (ss_ashift:HI (match_dup 1) (match_dup 2))))]
3792 ""
3793 "@
3794 %0 = ASHIFT %1 BY %h2 (V, S)%!
3795 %0 = %1 << %2 (V,S)%!
3796 %0 = %1 >>> %N2 (V,S)%!"
3797 [(set_attr "type" "dsp32")])
3799 (define_insn "lshiftv2hi3"
3800 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3801 (if_then_else:V2HI
3802 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3803 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3804 (match_dup 2))
3805 (ashift:V2HI (match_dup 1) (match_dup 2))))]
3806 ""
3807 "@
3808 %0 = LSHIFT %1 BY %h2 (V)%!
3809 %0 = %1 << %2 (V)%!
3810 %0 = %1 >> %N2 (V)%!"
3811 [(set_attr "type" "dsp32")])
3813 (define_insn "lshifthi3"
3814 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3815 (if_then_else:HI
3816 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3817 (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3818 (match_dup 2))
3819 (ashift:HI (match_dup 1) (match_dup 2))))]
3820 ""
3821 "@
3822 %0 = LSHIFT %1 BY %h2 (V)%!
3823 %0 = %1 << %2 (V)%!
3824 %0 = %1 >> %N2 (V)%!"
3825 [(set_attr "type" "dsp32")])