1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (and (match_operand 0 "register_operand")
37 (match_test "GET_CODE (op) != REG
38 || ALTIVEC_REGNO_P (REGNO (op))
39 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
41 ;; Return 1 if op is a VSX register.
42 (define_predicate "vsx_register_operand"
43 (and (match_operand 0 "register_operand")
44 (match_test "GET_CODE (op) != REG
45 || VSX_REGNO_P (REGNO (op))
46 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
48 ;; Return 1 if op is a vector register that operates on floating point vectors
49 ;; (either altivec or VSX).
50 (define_predicate "vfloat_operand"
51 (and (match_operand 0 "register_operand")
52 (match_test "GET_CODE (op) != REG
53 || VFLOAT_REGNO_P (REGNO (op))
54 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
56 ;; Return 1 if op is a vector register that operates on integer vectors
57 ;; (only altivec, VSX doesn't support integer vectors)
58 (define_predicate "vint_operand"
59 (and (match_operand 0 "register_operand")
60 (match_test "GET_CODE (op) != REG
61 || VINT_REGNO_P (REGNO (op))
62 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
64 ;; Return 1 if op is a vector register to do logical operations on (and, or,
66 (define_predicate "vlogical_operand"
67 (and (match_operand 0 "register_operand")
68 (match_test "GET_CODE (op) != REG
69 || VLOGICAL_REGNO_P (REGNO (op))
70 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
72 ;; Return 1 if op is the carry register.
73 (define_predicate "ca_operand"
74 (and (match_code "reg")
75 (match_test "CA_REGNO_P (REGNO (op))")))
77 ;; Return 1 if op is a signed 5-bit constant integer.
78 (define_predicate "s5bit_cint_operand"
79 (and (match_code "const_int")
80 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
82 ;; Return 1 if op is a unsigned 5-bit constant integer.
83 (define_predicate "u5bit_cint_operand"
84 (and (match_code "const_int")
85 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
87 ;; Return 1 if op is a signed 8-bit constant integer.
88 ;; Integer multiplication complete more quickly
89 (define_predicate "s8bit_cint_operand"
90 (and (match_code "const_int")
91 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
93 ;; Return 1 if op is a constant integer that can fit in a D field.
94 (define_predicate "short_cint_operand"
95 (and (match_code "const_int")
96 (match_test "satisfies_constraint_I (op)")))
98 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
99 (define_predicate "u_short_cint_operand"
100 (and (match_code "const_int")
101 (match_test "satisfies_constraint_K (op)")))
103 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
104 (define_predicate "non_short_cint_operand"
105 (and (match_code "const_int")
106 (match_test "(unsigned HOST_WIDE_INT)
107 (INTVAL (op) + 0x8000) >= 0x10000")))
109 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
110 (define_predicate "exact_log2_cint_operand"
111 (and (match_code "const_int")
112 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
114 ;; Return 1 if op is a register that is not special.
115 (define_predicate "gpc_reg_operand"
116 (and (match_operand 0 "register_operand")
117 (match_test "(GET_CODE (op) != REG
118 || (REGNO (op) >= ARG_POINTER_REGNUM
119 && !CA_REGNO_P (REGNO (op)))
120 || REGNO (op) < MQ_REGNO)
121 && !((TARGET_E500_DOUBLE || TARGET_SPE)
122 && invalid_e500_subreg (op, mode))")))
124 ;; Return 1 if op is a register that is a condition register field.
125 (define_predicate "cc_reg_operand"
126 (and (match_operand 0 "register_operand")
127 (match_test "GET_CODE (op) != REG
128 || REGNO (op) > LAST_VIRTUAL_REGISTER
129 || CR_REGNO_P (REGNO (op))")))
131 ;; Return 1 if op is a register that is a condition register field not cr0.
132 (define_predicate "cc_reg_not_cr0_operand"
133 (and (match_operand 0 "register_operand")
134 (match_test "GET_CODE (op) != REG
135 || REGNO (op) > LAST_VIRTUAL_REGISTER
136 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
138 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
139 (define_predicate "cc_reg_not_micro_cr0_operand"
140 (and (match_operand 0 "register_operand")
141 (match_test "GET_CODE (op) != REG
142 || REGNO (op) > LAST_VIRTUAL_REGISTER
143 || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
144 || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
146 ;; Return 1 if op is a constant integer valid for D field
147 ;; or non-special register register.
148 (define_predicate "reg_or_short_operand"
149 (if_then_else (match_code "const_int")
150 (match_operand 0 "short_cint_operand")
151 (match_operand 0 "gpc_reg_operand")))
153 ;; Return 1 if op is a constant integer valid whose negation is valid for
154 ;; D field or non-special register register.
155 ;; Do not allow a constant zero because all patterns that call this
156 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
157 ;; or equal to const, which does not work for zero.
158 (define_predicate "reg_or_neg_short_operand"
159 (if_then_else (match_code "const_int")
160 (match_test "satisfies_constraint_P (op)
161 && INTVAL (op) != 0")
162 (match_operand 0 "gpc_reg_operand")))
164 ;; Return 1 if op is a constant integer valid for DS field
165 ;; or non-special register.
166 (define_predicate "reg_or_aligned_short_operand"
167 (if_then_else (match_code "const_int")
168 (and (match_operand 0 "short_cint_operand")
169 (match_test "!(INTVAL (op) & 3)"))
170 (match_operand 0 "gpc_reg_operand")))
172 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
173 ;; or non-special register.
174 (define_predicate "reg_or_u_short_operand"
175 (if_then_else (match_code "const_int")
176 (match_operand 0 "u_short_cint_operand")
177 (match_operand 0 "gpc_reg_operand")))
179 ;; Return 1 if op is any constant integer
180 ;; or non-special register.
181 (define_predicate "reg_or_cint_operand"
182 (ior (match_code "const_int")
183 (match_operand 0 "gpc_reg_operand")))
185 ;; Return 1 if op is a constant integer valid for addition
186 ;; or non-special register.
187 (define_predicate "reg_or_add_cint_operand"
188 (if_then_else (match_code "const_int")
189 (match_test "(HOST_BITS_PER_WIDE_INT == 32
190 && (mode == SImode || INTVAL (op) < 0x7fff8000))
191 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
192 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
193 (match_operand 0 "gpc_reg_operand")))
195 ;; Return 1 if op is a constant integer valid for subtraction
196 ;; or non-special register.
197 (define_predicate "reg_or_sub_cint_operand"
198 (if_then_else (match_code "const_int")
199 (match_test "(HOST_BITS_PER_WIDE_INT == 32
200 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
201 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
203 ? 0x80000000 : 0x80008000))
204 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
205 (match_operand 0 "gpc_reg_operand")))
207 ;; Return 1 if op is any 32-bit unsigned constant integer
208 ;; or non-special register.
209 (define_predicate "reg_or_logical_cint_operand"
210 (if_then_else (match_code "const_int")
211 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
213 || ((INTVAL (op) & GET_MODE_MASK (mode)
214 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
215 (if_then_else (match_code "const_double")
216 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
218 && CONST_DOUBLE_HIGH (op) == 0")
219 (match_operand 0 "gpc_reg_operand"))))
221 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
222 ;; with no more than one instruction per word.
223 (define_predicate "easy_fp_constant"
224 (match_code "const_double")
229 if (GET_MODE (op) != mode
230 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
233 /* Consider all constants with -msoft-float to be easy. */
234 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
235 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
239 if (DECIMAL_FLOAT_MODE_P (mode))
242 /* If we are using V.4 style PIC, consider all constants to be hard. */
243 if (flag_pic && DEFAULT_ABI == ABI_V4)
246 #ifdef TARGET_RELOCATABLE
247 /* Similarly if we are using -mrelocatable, consider all constants
249 if (TARGET_RELOCATABLE)
256 if (TARGET_E500_DOUBLE)
259 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
260 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
262 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
263 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
264 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
265 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
268 /* The constant 0.f is easy under VSX. */
269 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
272 /* Force constants to memory before reload to utilize
273 compress_float_constant.
274 Avoid this when flag_unsafe_math_optimizations is enabled
275 because RDIV division to reciprocal optimization is not able
276 to regenerate the division. */
277 if (TARGET_E500_DOUBLE
278 || (!reload_in_progress && !reload_completed
279 && !flag_unsafe_math_optimizations))
282 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
283 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
285 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
286 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
289 /* The constant 0.f is easy. */
290 if (op == CONST0_RTX (SFmode))
293 /* Force constants to memory before reload to utilize
294 compress_float_constant.
295 Avoid this when flag_unsafe_math_optimizations is enabled
296 because RDIV division to reciprocal optimization is not able
297 to regenerate the division. */
298 if (!reload_in_progress && !reload_completed
299 && !flag_unsafe_math_optimizations)
302 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
303 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
305 return num_insns_constant_wide (k[0]) == 1;
308 return ((TARGET_POWERPC64
309 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
310 || (num_insns_constant (op, DImode) <= 2));
320 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
321 ;; vector register without using memory.
322 (define_predicate "easy_vector_constant"
323 (match_code "const_vector")
325 /* As the paired vectors are actually FPRs it seems that there is
326 no easy way to load a CONST_VECTOR without using memory. */
327 if (TARGET_PAIRED_FLOAT)
330 if ((VSX_VECTOR_MODE (mode) || mode == TImode) && zero_constant (op, mode))
333 if (ALTIVEC_VECTOR_MODE (mode))
335 if (zero_constant (op, mode))
337 return easy_altivec_constant (op, mode);
340 if (SPE_VECTOR_MODE (mode))
343 if (zero_constant (op, mode))
345 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
348 /* Limit SPE vectors to 15 bits signed. These we can generate with:
353 I don't know how efficient it would be to allow bigger constants,
354 considering we'll have an extra 'ori' for every 'li'. I doubt 5
355 instructions is better than a 64-bit memory load, but I don't
356 have the e500 timing specs. */
357 if (mode == V2SImode)
359 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
360 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
361 return cst >= -0x7fff && cst <= 0x7fff
362 && cst2 >= -0x7fff && cst2 <= 0x7fff;
369 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
370 (define_predicate "easy_vector_constant_add_self"
371 (and (match_code "const_vector")
372 (and (match_test "TARGET_ALTIVEC")
373 (match_test "easy_altivec_constant (op, mode)")))
375 HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
376 val = ((val & 0xff) ^ 0x80) - 0x80;
377 return EASY_VECTOR_15_ADD_SELF (val);
380 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
381 (define_predicate "easy_vector_constant_msb"
382 (and (match_code "const_vector")
383 (and (match_test "TARGET_ALTIVEC")
384 (match_test "easy_altivec_constant (op, mode)")))
386 HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
387 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
390 ;; Return 1 if operand is constant zero (scalars and vectors).
391 (define_predicate "zero_constant"
392 (and (match_code "const_int,const_double,const_vector")
393 (match_test "op == CONST0_RTX (mode)")))
395 ;; Return 1 if operand is 0.0.
396 ;; or non-special register register field no cr0
397 (define_predicate "zero_fp_constant"
398 (and (match_code "const_double")
399 (match_test "SCALAR_FLOAT_MODE_P (mode)
400 && op == CONST0_RTX (mode)")))
402 ;; Return 1 if the operand is in volatile memory. Note that during the
403 ;; RTL generation phase, memory_operand does not return TRUE for volatile
404 ;; memory references. So this function allows us to recognize volatile
405 ;; references where it's safe.
406 (define_predicate "volatile_mem_operand"
407 (and (and (match_code "mem")
408 (match_test "MEM_VOLATILE_P (op)"))
409 (if_then_else (match_test "reload_completed")
410 (match_operand 0 "memory_operand")
411 (if_then_else (match_test "reload_in_progress")
412 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
413 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
415 ;; Return 1 if the operand is an offsettable memory operand.
416 (define_predicate "offsettable_mem_operand"
417 (and (match_operand 0 "memory_operand")
418 (match_test "offsettable_nonstrict_memref_p (op)")))
420 ;; Return 1 if the operand is a memory operand with an address divisible by 4
421 (define_predicate "word_offset_memref_operand"
422 (match_operand 0 "memory_operand")
424 /* Address inside MEM. */
427 /* Extract address from auto-inc/dec. */
428 if (GET_CODE (op) == PRE_INC
429 || GET_CODE (op) == PRE_DEC)
431 else if (GET_CODE (op) == PRE_MODIFY)
434 return (GET_CODE (op) != PLUS
435 || ! REG_P (XEXP (op, 0))
436 || GET_CODE (XEXP (op, 1)) != CONST_INT
437 || INTVAL (XEXP (op, 1)) % 4 == 0);
440 ;; Return 1 if the operand is an indexed or indirect memory operand.
441 (define_predicate "indexed_or_indirect_operand"
445 if (VECTOR_MEM_ALTIVEC_P (mode)
446 && GET_CODE (op) == AND
447 && GET_CODE (XEXP (op, 1)) == CONST_INT
448 && INTVAL (XEXP (op, 1)) == -16)
451 return indexed_or_indirect_address (op, mode);
454 ;; Return 1 if the operand is an indexed or indirect memory operand with an
455 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
456 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
457 ;; while VSX uses the full address and traps)
458 (define_predicate "altivec_indexed_or_indirect_operand"
462 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
463 && GET_CODE (op) == AND
464 && GET_CODE (XEXP (op, 1)) == CONST_INT
465 && INTVAL (XEXP (op, 1)) == -16)
466 return indexed_or_indirect_address (XEXP (op, 0), mode);
471 ;; Return 1 if the operand is an indexed or indirect address.
472 (define_special_predicate "indexed_or_indirect_address"
473 (and (match_test "REG_P (op)
474 || (GET_CODE (op) == PLUS
475 /* Omit testing REG_P (XEXP (op, 0)). */
476 && REG_P (XEXP (op, 1)))")
477 (match_operand 0 "address_operand")))
479 ;; Used for the destination of the fix_truncdfsi2 expander.
480 ;; If stfiwx will be used, the result goes to memory; otherwise,
481 ;; we're going to emit a store and a load of a subreg, so the dest is a
483 (define_predicate "fix_trunc_dest_operand"
484 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
485 (match_operand 0 "memory_operand")
486 (match_operand 0 "gpc_reg_operand")))
488 ;; Return 1 if the operand is either a non-special register or can be used
489 ;; as the operand of a `mode' add insn.
490 (define_predicate "add_operand"
491 (if_then_else (match_code "const_int")
492 (match_test "satisfies_constraint_I (op)
493 || satisfies_constraint_L (op)")
494 (match_operand 0 "gpc_reg_operand")))
496 ;; Return 1 if OP is a constant but not a valid add_operand.
497 (define_predicate "non_add_cint_operand"
498 (and (match_code "const_int")
499 (match_test "!satisfies_constraint_I (op)
500 && !satisfies_constraint_L (op)")))
502 ;; Return 1 if the operand is a constant that can be used as the operand
504 (define_predicate "logical_const_operand"
505 (match_code "const_int,const_double")
507 HOST_WIDE_INT opl, oph;
509 if (GET_CODE (op) == CONST_INT)
511 opl = INTVAL (op) & GET_MODE_MASK (mode);
513 if (HOST_BITS_PER_WIDE_INT <= 32
514 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
517 else if (GET_CODE (op) == CONST_DOUBLE)
519 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
521 opl = CONST_DOUBLE_LOW (op);
522 oph = CONST_DOUBLE_HIGH (op);
529 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
530 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
533 ;; Return 1 if the operand is a non-special register or a constant that
534 ;; can be used as the operand of an OR or XOR.
535 (define_predicate "logical_operand"
536 (ior (match_operand 0 "gpc_reg_operand")
537 (match_operand 0 "logical_const_operand")))
539 ;; Return 1 if op is a constant that is not a logical operand, but could
540 ;; be split into one.
541 (define_predicate "non_logical_cint_operand"
542 (and (match_code "const_int,const_double")
543 (and (not (match_operand 0 "logical_operand"))
544 (match_operand 0 "reg_or_logical_cint_operand"))))
546 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
547 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
548 ;; transitions). Reject all ones and all zeros, since these should have
549 ;; been optimized away and confuse the making of MB and ME.
550 (define_predicate "mask_operand"
551 (match_code "const_int")
553 HOST_WIDE_INT c, lsb;
557 if (TARGET_POWERPC64)
559 /* Fail if the mask is not 32-bit. */
560 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
563 /* Fail if the mask wraps around because the upper 32-bits of the
564 mask will all be 1s, contrary to GCC's internal view. */
565 if ((c & 0x80000001) == 0x80000001)
569 /* We don't change the number of transitions by inverting,
570 so make sure we start with the LS bit zero. */
574 /* Reject all zeros or all ones. */
578 /* Find the first transition. */
581 /* Invert to look for a second transition. */
584 /* Erase first transition. */
587 /* Find the second transition (if any). */
590 /* Match if all the bits above are 1's (or c is zero). */
594 ;; Return 1 for the PowerPC64 rlwinm corner case.
595 (define_predicate "mask_operand_wrap"
596 (match_code "const_int")
598 HOST_WIDE_INT c, lsb;
602 if ((c & 0x80000001) != 0x80000001)
616 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
617 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
618 ;; transition). Reject all zeros, since zero should have been
619 ;; optimized away and confuses the making of MB and ME.
620 (define_predicate "mask64_operand"
621 (match_code "const_int")
623 HOST_WIDE_INT c, lsb;
627 /* Reject all zeros. */
631 /* We don't change the number of transitions by inverting,
632 so make sure we start with the LS bit zero. */
636 /* Find the first transition. */
639 /* Match if all the bits above are 1's (or c is zero). */
643 ;; Like mask64_operand, but allow up to three transitions. This
644 ;; predicate is used by insn patterns that generate two rldicl or
645 ;; rldicr machine insns.
646 (define_predicate "mask64_2_operand"
647 (match_code "const_int")
649 HOST_WIDE_INT c, lsb;
653 /* Disallow all zeros. */
657 /* We don't change the number of transitions by inverting,
658 so make sure we start with the LS bit zero. */
662 /* Find the first transition. */
665 /* Invert to look for a second transition. */
668 /* Erase first transition. */
671 /* Find the second transition. */
674 /* Invert to look for a third transition. */
677 /* Erase second transition. */
680 /* Find the third transition (if any). */
683 /* Match if all the bits above are 1's (or c is zero). */
687 ;; Like and_operand, but also match constants that can be implemented
688 ;; with two rldicl or rldicr insns.
689 (define_predicate "and64_2_operand"
690 (ior (match_operand 0 "mask64_2_operand")
691 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
692 (match_operand 0 "gpc_reg_operand")
693 (match_operand 0 "logical_operand"))))
695 ;; Return 1 if the operand is either a non-special register or a
696 ;; constant that can be used as the operand of a logical AND.
697 (define_predicate "and_operand"
698 (ior (match_operand 0 "mask_operand")
699 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
700 (match_operand 0 "mask64_operand"))
701 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
702 (match_operand 0 "gpc_reg_operand")
703 (match_operand 0 "logical_operand")))))
705 ;; Return 1 if the operand is either a logical operand or a short cint operand.
706 (define_predicate "scc_eq_operand"
707 (ior (match_operand 0 "logical_operand")
708 (match_operand 0 "short_cint_operand")))
710 ;; Return 1 if the operand is a general non-special register or memory operand.
711 (define_predicate "reg_or_mem_operand"
712 (ior (match_operand 0 "memory_operand")
713 (ior (and (match_code "mem")
714 (match_test "macho_lo_sum_memory_operand (op, mode)"))
715 (ior (match_operand 0 "volatile_mem_operand")
716 (match_operand 0 "gpc_reg_operand")))))
718 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
719 (define_predicate "reg_or_none500mem_operand"
720 (if_then_else (match_code "mem")
721 (and (match_test "!TARGET_E500_DOUBLE")
722 (ior (match_operand 0 "memory_operand")
723 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
724 (match_operand 0 "volatile_mem_operand"))))
725 (match_operand 0 "gpc_reg_operand")))
727 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
728 (define_predicate "zero_reg_mem_operand"
729 (ior (match_operand 0 "zero_fp_constant")
730 (match_operand 0 "reg_or_mem_operand")))
732 ;; Return 1 if the operand is a general register or memory operand without
733 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
735 (define_predicate "lwa_operand"
736 (match_code "reg,subreg,mem")
740 if (reload_completed && GET_CODE (inner) == SUBREG)
741 inner = SUBREG_REG (inner);
743 return gpc_reg_operand (inner, mode)
744 || (memory_operand (inner, mode)
745 && GET_CODE (XEXP (inner, 0)) != PRE_INC
746 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
747 && (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY
748 || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0))
749 && (GET_CODE (XEXP (inner, 0)) != PLUS
750 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
751 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
754 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
755 (define_predicate "symbol_ref_operand"
756 (and (match_code "symbol_ref")
757 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
758 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
760 ;; Return 1 if op is an operand that can be loaded via the GOT.
761 ;; or non-special register register field no cr0
762 (define_predicate "got_operand"
763 (match_code "symbol_ref,const,label_ref"))
765 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
766 ;; excluding labels involving addition.
767 (define_predicate "got_no_const_operand"
768 (match_code "symbol_ref,label_ref"))
770 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
771 (define_predicate "rs6000_tls_symbol_ref"
772 (and (match_code "symbol_ref")
773 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
775 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
776 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
777 (define_predicate "call_operand"
778 (if_then_else (match_code "reg")
779 (match_test "REGNO (op) == LR_REGNO
780 || REGNO (op) == CTR_REGNO
781 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
782 (match_code "symbol_ref")))
784 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
786 (define_predicate "current_file_function_operand"
787 (and (match_code "symbol_ref")
788 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
789 && ((SYMBOL_REF_LOCAL_P (op)
790 && (DEFAULT_ABI != ABI_AIX
791 || !SYMBOL_REF_EXTERNAL_P (op)))
792 || (op == XEXP (DECL_RTL (current_function_decl),
795 ;; Return 1 if this operand is a valid input for a move insn.
796 (define_predicate "input_operand"
797 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
798 const_double,const_vector,const_int,plus")
800 /* Memory is always valid. */
801 if (memory_operand (op, mode))
804 /* For floating-point, easy constants are valid. */
805 if (SCALAR_FLOAT_MODE_P (mode)
807 && easy_fp_constant (op, mode))
810 /* Allow any integer constant. */
811 if (GET_MODE_CLASS (mode) == MODE_INT
812 && (GET_CODE (op) == CONST_INT
813 || GET_CODE (op) == CONST_DOUBLE))
816 /* Allow easy vector constants. */
817 if (GET_CODE (op) == CONST_VECTOR
818 && easy_vector_constant (op, mode))
821 /* Do not allow invalid E500 subregs. */
822 if ((TARGET_E500_DOUBLE || TARGET_SPE)
823 && GET_CODE (op) == SUBREG
824 && invalid_e500_subreg (op, mode))
827 /* For floating-point or multi-word mode, the only remaining valid type
829 if (SCALAR_FLOAT_MODE_P (mode)
830 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
831 return register_operand (op, mode);
833 /* The only cases left are integral modes one word or smaller (we
834 do not get called for MODE_CC values). These can be in any
836 if (register_operand (op, mode))
839 /* A SYMBOL_REF referring to the TOC is valid. */
840 if (legitimate_constant_pool_address_p (op, false))
843 /* A constant pool expression (relative to the TOC) is valid */
844 if (toc_relative_expr_p (op))
847 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
849 if (DEFAULT_ABI == ABI_V4
850 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
851 && small_data_operand (op, Pmode))
857 ;; Return true if OP is an invalid SUBREG operation on the e500.
858 (define_predicate "rs6000_nonimmediate_operand"
859 (match_code "reg,subreg,mem")
861 if ((TARGET_E500_DOUBLE || TARGET_SPE)
862 && GET_CODE (op) == SUBREG
863 && invalid_e500_subreg (op, mode))
866 return nonimmediate_operand (op, mode);
869 ;; Return true if operand is boolean operator.
870 (define_predicate "boolean_operator"
871 (match_code "and,ior,xor"))
873 ;; Return true if operand is OR-form of boolean operator.
874 (define_predicate "boolean_or_operator"
875 (match_code "ior,xor"))
877 ;; Return true if operand is an equality operator.
878 (define_special_predicate "equality_operator"
879 (match_code "eq,ne"))
881 ;; Return true if operand is MIN or MAX operator.
882 (define_predicate "min_max_operator"
883 (match_code "smin,smax,umin,umax"))
885 ;; Return 1 if OP is a comparison operation that is valid for a branch
886 ;; instruction. We check the opcode against the mode of the CC value.
887 ;; validate_condition_mode is an assertion.
888 (define_predicate "branch_comparison_operator"
889 (and (match_operand 0 "comparison_operator")
890 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
891 (match_test "validate_condition_mode (GET_CODE (op),
892 GET_MODE (XEXP (op, 0))),
895 (define_predicate "rs6000_cbranch_operator"
896 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
897 (match_operand 0 "ordered_comparison_operator")
898 (match_operand 0 "comparison_operator")))
900 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
901 ;; it must be a positive comparison.
902 (define_predicate "scc_comparison_operator"
903 (and (match_operand 0 "branch_comparison_operator")
904 (match_code "eq,lt,gt,ltu,gtu,unordered")))
906 ;; Return 1 if OP is a comparison operation that is valid for a branch
907 ;; insn, which is true if the corresponding bit in the CC register is set.
908 (define_predicate "branch_positive_comparison_operator"
909 (and (match_operand 0 "branch_comparison_operator")
910 (match_code "eq,lt,gt,ltu,gtu,unordered")))
912 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
913 (define_predicate "load_multiple_operation"
914 (match_code "parallel")
916 int count = XVECLEN (op, 0);
917 unsigned int dest_regno;
921 /* Perform a quick check so we don't blow up below. */
923 || GET_CODE (XVECEXP (op, 0, 0)) != SET
924 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
925 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
928 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
929 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
931 for (i = 1; i < count; i++)
933 rtx elt = XVECEXP (op, 0, i);
935 if (GET_CODE (elt) != SET
936 || GET_CODE (SET_DEST (elt)) != REG
937 || GET_MODE (SET_DEST (elt)) != SImode
938 || REGNO (SET_DEST (elt)) != dest_regno + i
939 || GET_CODE (SET_SRC (elt)) != MEM
940 || GET_MODE (SET_SRC (elt)) != SImode
941 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
942 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
943 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
944 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
951 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
952 ;; The second vector element is a CLOBBER.
953 (define_predicate "store_multiple_operation"
954 (match_code "parallel")
956 int count = XVECLEN (op, 0) - 1;
957 unsigned int src_regno;
961 /* Perform a quick check so we don't blow up below. */
963 || GET_CODE (XVECEXP (op, 0, 0)) != SET
964 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
965 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
968 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
969 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
971 for (i = 1; i < count; i++)
973 rtx elt = XVECEXP (op, 0, i + 1);
975 if (GET_CODE (elt) != SET
976 || GET_CODE (SET_SRC (elt)) != REG
977 || GET_MODE (SET_SRC (elt)) != SImode
978 || REGNO (SET_SRC (elt)) != src_regno + i
979 || GET_CODE (SET_DEST (elt)) != MEM
980 || GET_MODE (SET_DEST (elt)) != SImode
981 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
982 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
983 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
984 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
991 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
993 (define_predicate "save_world_operation"
994 (match_code "parallel")
999 int count = XVECLEN (op, 0);
1005 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1006 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1009 for (i=1; i <= 18; i++)
1011 elt = XVECEXP (op, 0, index++);
1012 if (GET_CODE (elt) != SET
1013 || GET_CODE (SET_DEST (elt)) != MEM
1014 || ! memory_operand (SET_DEST (elt), DFmode)
1015 || GET_CODE (SET_SRC (elt)) != REG
1016 || GET_MODE (SET_SRC (elt)) != DFmode)
1020 for (i=1; i <= 12; i++)
1022 elt = XVECEXP (op, 0, index++);
1023 if (GET_CODE (elt) != SET
1024 || GET_CODE (SET_DEST (elt)) != MEM
1025 || GET_CODE (SET_SRC (elt)) != REG
1026 || GET_MODE (SET_SRC (elt)) != V4SImode)
1030 for (i=1; i <= 19; i++)
1032 elt = XVECEXP (op, 0, index++);
1033 if (GET_CODE (elt) != SET
1034 || GET_CODE (SET_DEST (elt)) != MEM
1035 || ! memory_operand (SET_DEST (elt), Pmode)
1036 || GET_CODE (SET_SRC (elt)) != REG
1037 || GET_MODE (SET_SRC (elt)) != Pmode)
1041 elt = XVECEXP (op, 0, index++);
1042 if (GET_CODE (elt) != SET
1043 || GET_CODE (SET_DEST (elt)) != MEM
1044 || ! memory_operand (SET_DEST (elt), Pmode)
1045 || GET_CODE (SET_SRC (elt)) != REG
1046 || REGNO (SET_SRC (elt)) != CR2_REGNO
1047 || GET_MODE (SET_SRC (elt)) != Pmode)
1050 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1051 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1056 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1058 (define_predicate "restore_world_operation"
1059 (match_code "parallel")
1064 int count = XVECLEN (op, 0);
1070 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1071 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1072 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1073 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1076 elt = XVECEXP (op, 0, index++);
1077 if (GET_CODE (elt) != SET
1078 || GET_CODE (SET_SRC (elt)) != MEM
1079 || ! memory_operand (SET_SRC (elt), Pmode)
1080 || GET_CODE (SET_DEST (elt)) != REG
1081 || REGNO (SET_DEST (elt)) != CR2_REGNO
1082 || GET_MODE (SET_DEST (elt)) != Pmode)
1085 for (i=1; i <= 19; i++)
1087 elt = XVECEXP (op, 0, index++);
1088 if (GET_CODE (elt) != SET
1089 || GET_CODE (SET_SRC (elt)) != MEM
1090 || ! memory_operand (SET_SRC (elt), Pmode)
1091 || GET_CODE (SET_DEST (elt)) != REG
1092 || GET_MODE (SET_DEST (elt)) != Pmode)
1096 for (i=1; i <= 12; i++)
1098 elt = XVECEXP (op, 0, index++);
1099 if (GET_CODE (elt) != SET
1100 || GET_CODE (SET_SRC (elt)) != MEM
1101 || GET_CODE (SET_DEST (elt)) != REG
1102 || GET_MODE (SET_DEST (elt)) != V4SImode)
1106 for (i=1; i <= 18; i++)
1108 elt = XVECEXP (op, 0, index++);
1109 if (GET_CODE (elt) != SET
1110 || GET_CODE (SET_SRC (elt)) != MEM
1111 || ! memory_operand (SET_SRC (elt), DFmode)
1112 || GET_CODE (SET_DEST (elt)) != REG
1113 || GET_MODE (SET_DEST (elt)) != DFmode)
1117 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1118 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1119 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1120 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1121 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1126 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1127 (define_predicate "vrsave_operation"
1128 (match_code "parallel")
1130 int count = XVECLEN (op, 0);
1131 unsigned int dest_regno, src_regno;
1135 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1136 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1137 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1138 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1141 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1142 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1144 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1147 for (i = 1; i < count; i++)
1149 rtx elt = XVECEXP (op, 0, i);
1151 if (GET_CODE (elt) != CLOBBER
1152 && GET_CODE (elt) != SET)
1159 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1160 (define_predicate "mfcr_operation"
1161 (match_code "parallel")
1163 int count = XVECLEN (op, 0);
1166 /* Perform a quick check so we don't blow up below. */
1168 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1169 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1170 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1173 for (i = 0; i < count; i++)
1175 rtx exp = XVECEXP (op, 0, i);
1180 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1182 if (GET_CODE (src_reg) != REG
1183 || GET_MODE (src_reg) != CCmode
1184 || ! CR_REGNO_P (REGNO (src_reg)))
1187 if (GET_CODE (exp) != SET
1188 || GET_CODE (SET_DEST (exp)) != REG
1189 || GET_MODE (SET_DEST (exp)) != SImode
1190 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1192 unspec = SET_SRC (exp);
1193 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1195 if (GET_CODE (unspec) != UNSPEC
1196 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1197 || XVECLEN (unspec, 0) != 2
1198 || XVECEXP (unspec, 0, 0) != src_reg
1199 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1200 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1206 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1207 (define_predicate "mtcrf_operation"
1208 (match_code "parallel")
1210 int count = XVECLEN (op, 0);
1214 /* Perform a quick check so we don't blow up below. */
1216 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1217 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1218 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1220 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1222 if (GET_CODE (src_reg) != REG
1223 || GET_MODE (src_reg) != SImode
1224 || ! INT_REGNO_P (REGNO (src_reg)))
1227 for (i = 0; i < count; i++)
1229 rtx exp = XVECEXP (op, 0, i);
1233 if (GET_CODE (exp) != SET
1234 || GET_CODE (SET_DEST (exp)) != REG
1235 || GET_MODE (SET_DEST (exp)) != CCmode
1236 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1238 unspec = SET_SRC (exp);
1239 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1241 if (GET_CODE (unspec) != UNSPEC
1242 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1243 || XVECLEN (unspec, 0) != 2
1244 || XVECEXP (unspec, 0, 0) != src_reg
1245 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1246 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1252 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1253 (define_predicate "lmw_operation"
1254 (match_code "parallel")
1256 int count = XVECLEN (op, 0);
1257 unsigned int dest_regno;
1259 unsigned int base_regno;
1260 HOST_WIDE_INT offset;
1263 /* Perform a quick check so we don't blow up below. */
1265 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1266 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1267 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1270 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1271 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1274 || count != 32 - (int) dest_regno)
1277 if (legitimate_indirect_address_p (src_addr, 0))
1280 base_regno = REGNO (src_addr);
1281 if (base_regno == 0)
1284 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1286 offset = INTVAL (XEXP (src_addr, 1));
1287 base_regno = REGNO (XEXP (src_addr, 0));
1292 for (i = 0; i < count; i++)
1294 rtx elt = XVECEXP (op, 0, i);
1297 HOST_WIDE_INT newoffset;
1299 if (GET_CODE (elt) != SET
1300 || GET_CODE (SET_DEST (elt)) != REG
1301 || GET_MODE (SET_DEST (elt)) != SImode
1302 || REGNO (SET_DEST (elt)) != dest_regno + i
1303 || GET_CODE (SET_SRC (elt)) != MEM
1304 || GET_MODE (SET_SRC (elt)) != SImode)
1306 newaddr = XEXP (SET_SRC (elt), 0);
1307 if (legitimate_indirect_address_p (newaddr, 0))
1312 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1314 addr_reg = XEXP (newaddr, 0);
1315 newoffset = INTVAL (XEXP (newaddr, 1));
1319 if (REGNO (addr_reg) != base_regno
1320 || newoffset != offset + 4 * i)
1327 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1328 (define_predicate "stmw_operation"
1329 (match_code "parallel")
1331 int count = XVECLEN (op, 0);
1332 unsigned int src_regno;
1334 unsigned int base_regno;
1335 HOST_WIDE_INT offset;
1338 /* Perform a quick check so we don't blow up below. */
1340 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1341 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1342 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1345 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1346 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1349 || count != 32 - (int) src_regno)
1352 if (legitimate_indirect_address_p (dest_addr, 0))
1355 base_regno = REGNO (dest_addr);
1356 if (base_regno == 0)
1359 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1361 offset = INTVAL (XEXP (dest_addr, 1));
1362 base_regno = REGNO (XEXP (dest_addr, 0));
1367 for (i = 0; i < count; i++)
1369 rtx elt = XVECEXP (op, 0, i);
1372 HOST_WIDE_INT newoffset;
1374 if (GET_CODE (elt) != SET
1375 || GET_CODE (SET_SRC (elt)) != REG
1376 || GET_MODE (SET_SRC (elt)) != SImode
1377 || REGNO (SET_SRC (elt)) != src_regno + i
1378 || GET_CODE (SET_DEST (elt)) != MEM
1379 || GET_MODE (SET_DEST (elt)) != SImode)
1381 newaddr = XEXP (SET_DEST (elt), 0);
1382 if (legitimate_indirect_address_p (newaddr, 0))
1387 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1389 addr_reg = XEXP (newaddr, 0);
1390 newoffset = INTVAL (XEXP (newaddr, 1));
1394 if (REGNO (addr_reg) != base_regno
1395 || newoffset != offset + 4 * i)