| blob | e1eeaa6b96fc8b55500263140a21418167fe66f7 |
1 ;;- Machine description for Blackfin for GNU compiler
2 ;; Copyright 2005, 2006 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ; operand punctuation marks:
23 ;
24 ; X -- integer value printed as log2
25 ; Y -- integer value printed as log2(~value) - for bitclear
26 ; h -- print half word register, low part
27 ; d -- print half word register, high part
28 ; D -- print operand as dregs pairs
29 ; w -- print operand as accumulator register word (a0w, a1w)
30 ; H -- high part of double mode operand
31 ; T -- byte register representation Oct. 02 2001
33 ; constant operand classes
34 ;
35 ; J 2**N 5bit imm scaled
36 ; Ks7 -64 .. 63 signed 7bit imm
37 ; Ku5 0..31 unsigned 5bit imm
38 ; Ks4 -8 .. 7 signed 4bit imm
39 ; Ks3 -4 .. 3 signed 3bit imm
40 ; Ku3 0 .. 7 unsigned 3bit imm
41 ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
42 ;
43 ; register operands
44 ; d (r0..r7)
45 ; a (p0..p5,fp,sp)
46 ; e (a0, a1)
47 ; b (i0..i3)
48 ; f (m0..m3)
49 ; v (b0..b3)
50 ; c (i0..i3,m0..m3) CIRCREGS
51 ; C (CC) CCREGS
52 ; t (lt0,lt1)
53 ; k (lc0,lc1)
54 ; u (lb0,lb1)
55 ;
57 ;; Define constants for hard registers.
59 (define_constants
60 [(REG_R0 0)
61 (REG_R1 1)
62 (REG_R2 2)
63 (REG_R3 3)
64 (REG_R4 4)
65 (REG_R5 5)
66 (REG_R6 6)
67 (REG_R7 7)
69 (REG_P0 8)
70 (REG_P1 9)
71 (REG_P2 10)
72 (REG_P3 11)
73 (REG_P4 12)
74 (REG_P5 13)
75 (REG_P6 14)
76 (REG_P7 15)
78 (REG_SP 14)
79 (REG_FP 15)
81 (REG_I0 16)
82 (REG_I1 17)
83 (REG_I2 18)
84 (REG_I3 19)
86 (REG_B0 20)
87 (REG_B1 21)
88 (REG_B2 22)
89 (REG_B3 23)
91 (REG_L0 24)
92 (REG_L1 25)
93 (REG_L2 26)
94 (REG_L3 27)
96 (REG_M0 28)
97 (REG_M1 29)
98 (REG_M2 30)
99 (REG_M3 31)
101 (REG_A0 32)
102 (REG_A1 33)
104 (REG_CC 34)
105 (REG_RETS 35)
106 (REG_RETI 36)
107 (REG_RETX 37)
108 (REG_RETN 38)
109 (REG_RETE 39)
111 (REG_ASTAT 40)
112 (REG_SEQSTAT 41)
113 (REG_USP 42)
115 (REG_ARGP 43)
117 (REG_LT0 44)
118 (REG_LT1 45)
119 (REG_LC0 46)
120 (REG_LC1 47)
121 (REG_LB0 48)
122 (REG_LB1 49)])
124 ;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
126 (define_constants
127 [(UNSPEC_CBRANCH_TAKEN 0)
128 (UNSPEC_CBRANCH_NOPS 1)
129 (UNSPEC_RETURN 2)
130 (UNSPEC_MOVE_PIC 3)
131 (UNSPEC_LIBRARY_OFFSET 4)
132 (UNSPEC_PUSH_MULTIPLE 5)
133 ;; Multiply or MAC with extra CONST_INT operand specifying the macflag
134 (UNSPEC_MUL_WITH_FLAG 6)
135 (UNSPEC_MAC_WITH_FLAG 7)
136 (UNSPEC_MOVE_FDPIC 8)
137 (UNSPEC_FUNCDESC_GOT17M4 9)
138 (UNSPEC_LSETUP_END 10)
139 ;; Distinguish a 32-bit version of an insn from a 16-bit version.
140 (UNSPEC_32BIT 11)])
142 (define_constants
143 [(UNSPEC_VOLATILE_EH_RETURN 0)
144 (UNSPEC_VOLATILE_CSYNC 1)
145 (UNSPEC_VOLATILE_SSYNC 2)
146 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)])
148 (define_constants
149 [(MACFLAG_NONE 0)
150 (MACFLAG_T 1)
151 (MACFLAG_FU 2)
152 (MACFLAG_TFU 3)
153 (MACFLAG_IS 4)
154 (MACFLAG_IU 5)
155 (MACFLAG_W32 6)
156 (MACFLAG_M 7)
157 (MACFLAG_IS_M 8)
158 (MACFLAG_S2RND 9)
159 (MACFLAG_ISS2 10)
160 (MACFLAG_IH 11)])
162 (define_attr "type"
163 "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
164 (const_string "misc"))
166 (define_attr "addrtype" "32bit,preg,ireg"
167 (cond [(and (eq_attr "type" "mcld")
168 (and (match_operand 0 "d_register_operand" "")
169 (match_operand 1 "mem_p_address_operand" "")))
170 (const_string "preg")
171 (and (eq_attr "type" "mcld")
172 (and (match_operand 0 "d_register_operand" "")
173 (match_operand 1 "mem_i_address_operand" "")))
174 (const_string "ireg")
175 (and (eq_attr "type" "mcst")
176 (and (match_operand 1 "d_register_operand" "")
177 (match_operand 0 "mem_p_address_operand" "")))
178 (const_string "preg")
179 (and (eq_attr "type" "mcst")
180 (and (match_operand 1 "d_register_operand" "")
181 (match_operand 0 "mem_i_address_operand" "")))
182 (const_string "ireg")]
183 (const_string "32bit")))
185 ;; Scheduling definitions
187 (define_automaton "bfin")
189 (define_cpu_unit "slot0" "bfin")
190 (define_cpu_unit "slot1" "bfin")
191 (define_cpu_unit "slot2" "bfin")
193 ;; Three units used to enforce parallel issue restrictions:
194 ;; only one of the 16-bit slots can use a P register in an address,
195 ;; and only one them can be a store.
196 (define_cpu_unit "store" "bfin")
197 (define_cpu_unit "pregs" "bfin")
199 (define_reservation "core" "slot0+slot1+slot2")
201 (define_insn_reservation "alu" 1
202 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
203 "core")
205 (define_insn_reservation "imul" 3
206 (eq_attr "type" "mult")
207 "core*3")
209 (define_insn_reservation "dsp32" 1
210 (eq_attr "type" "dsp32")
211 "slot0")
213 (define_insn_reservation "load32" 1
214 (and (not (eq_attr "seq_insns" "multi"))
215 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
216 "core")
218 (define_insn_reservation "loadp" 1
219 (and (not (eq_attr "seq_insns" "multi"))
220 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
221 "(slot1|slot2)+pregs")
223 (define_insn_reservation "loadi" 1
224 (and (not (eq_attr "seq_insns" "multi"))
225 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
226 "(slot1|slot2)")
228 (define_insn_reservation "store32" 1
229 (and (not (eq_attr "seq_insns" "multi"))
230 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
231 "core")
233 (define_insn_reservation "storep" 1
234 (and (not (eq_attr "seq_insns" "multi"))
235 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg")))
236 "(slot1|slot2)+pregs+store")
238 (define_insn_reservation "storei" 1
239 (and (not (eq_attr "seq_insns" "multi"))
240 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
241 "(slot1|slot2)+store")
243 (define_insn_reservation "multi" 2
244 (eq_attr "seq_insns" "multi")
245 "core")
247 (absence_set "slot0" "slot1,slot2")
248 (absence_set "slot1" "slot2")
250 ;; Make sure genautomata knows about the maximum latency that can be produced
251 ;; by the adjust_cost function.
252 (define_insn_reservation "dummy" 5
253 (eq_attr "type" "dummy")
254 "core")
255 \f
256 ;; Operand and operator predicates
258 (include "predicates.md")
260 \f
261 ;;; FRIO branches have been optimized for code density
262 ;;; this comes at a slight cost of complexity when
263 ;;; a compiler needs to generate branches in the general
264 ;;; case. In order to generate the correct branching
265 ;;; mechanisms the compiler needs keep track of instruction
266 ;;; lengths. The follow table describes how to count instructions
267 ;;; for the FRIO architecture.
268 ;;;
269 ;;; unconditional br are 12-bit imm pcrelative branches *2
270 ;;; conditional br are 10-bit imm pcrelative branches *2
271 ;;; brcc 10-bit:
272 ;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
273 ;;; br 12-bit :
274 ;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
275 ;;; NOTE : For brcc we generate instructions such as
276 ;;; if cc jmp; jump.[sl] offset
277 ;;; offset of jump.[sl] is from the jump instruction but
278 ;;; gcc calculates length from the if cc jmp instruction
279 ;;; furthermore gcc takes the end address of the branch instruction
280 ;;; as (pc) for a forward branch
281 ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
282 ;;;
283 ;;; The way the (pc) rtx works in these calculations is somewhat odd;
284 ;;; for backward branches it's the address of the current instruction,
285 ;;; for forward branches it's the previously known address of the following
286 ;;; instruction - we have to take this into account by reducing the range
287 ;;; for a forward branch.
289 ;; Lengths for type "mvi" insns are always defined by the instructions
290 ;; themselves.
291 (define_attr "length" ""
292 (cond [(eq_attr "type" "mcld")
293 (if_then_else (match_operand 1 "effective_address_32bit_p" "")
294 (const_int 4) (const_int 2))
296 (eq_attr "type" "mcst")
297 (if_then_else (match_operand 0 "effective_address_32bit_p" "")
298 (const_int 4) (const_int 2))
300 (eq_attr "type" "move") (const_int 2)
302 (eq_attr "type" "dsp32") (const_int 4)
303 (eq_attr "type" "call") (const_int 4)
305 (eq_attr "type" "br")
306 (if_then_else (and
307 (le (minus (match_dup 0) (pc)) (const_int 4092))
308 (ge (minus (match_dup 0) (pc)) (const_int -4096)))
309 (const_int 2)
310 (const_int 4))
312 (eq_attr "type" "brcc")
313 (cond [(and
314 (le (minus (match_dup 3) (pc)) (const_int 1020))
315 (ge (minus (match_dup 3) (pc)) (const_int -1024)))
316 (const_int 2)
317 (and
318 (le (minus (match_dup 3) (pc)) (const_int 4092))
319 (ge (minus (match_dup 3) (pc)) (const_int -4094)))
320 (const_int 4)]
321 (const_int 6))
322 ]
324 (const_int 2)))
326 ;; Classify the insns into those that are one instruction and those that
327 ;; are more than one in sequence.
328 (define_attr "seq_insns" "single,multi"
329 (const_string "single"))
331 ;; Conditional moves
333 (define_expand "movsicc"
334 [(set (match_operand:SI 0 "register_operand" "")
335 (if_then_else:SI (match_operand 1 "comparison_operator" "")
336 (match_operand:SI 2 "register_operand" "")
337 (match_operand:SI 3 "register_operand" "")))]
338 ""
339 {
340 operands[1] = bfin_gen_compare (operands[1], SImode);
341 })
343 (define_insn "*movsicc_insn1"
344 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
345 (if_then_else:SI
346 (eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
347 (const_int 0))
348 (match_operand:SI 1 "register_operand" "da,0,da")
349 (match_operand:SI 2 "register_operand" "0,da,da")))]
350 ""
351 "@
352 if !cc %0 =%1; /* movsicc-1a */
353 if cc %0 =%2; /* movsicc-1b */
354 if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */"
355 [(set_attr "length" "2,2,4")
356 (set_attr "type" "movcc")
357 (set_attr "seq_insns" "*,*,multi")])
359 (define_insn "*movsicc_insn2"
360 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
361 (if_then_else:SI
362 (ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
363 (const_int 0))
364 (match_operand:SI 1 "register_operand" "0,da,da")
365 (match_operand:SI 2 "register_operand" "da,0,da")))]
366 ""
367 "@
368 if !cc %0 =%2; /* movsicc-2b */
369 if cc %0 =%1; /* movsicc-2a */
370 if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */"
371 [(set_attr "length" "2,2,4")
372 (set_attr "type" "movcc")
373 (set_attr "seq_insns" "*,*,multi")])
375 ;; Insns to load HIGH and LO_SUM
377 (define_insn "movsi_high"
378 [(set (match_operand:SI 0 "register_operand" "=x")
379 (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
380 "reload_completed"
381 "%d0 = %d1;"
382 [(set_attr "type" "mvi")
383 (set_attr "length" "4")])
385 (define_insn "movstricthi_high"
386 [(set (match_operand:SI 0 "register_operand" "+x")
387 (ior:SI (and:SI (match_dup 0) (const_int 65535))
388 (match_operand:SI 1 "immediate_operand" "i")))]
389 "reload_completed"
390 "%d0 = %d1;"
391 [(set_attr "type" "mvi")
392 (set_attr "length" "4")])
394 (define_insn "movsi_low"
395 [(set (match_operand:SI 0 "register_operand" "=x")
396 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
397 (match_operand:SI 2 "immediate_operand" "i")))]
398 "reload_completed"
399 "%h0 = %h2;"
400 [(set_attr "type" "mvi")
401 (set_attr "length" "4")])
403 (define_insn "movsi_high_pic"
404 [(set (match_operand:SI 0 "register_operand" "=x")
405 (high:SI (unspec:SI [(match_operand:SI 1 "" "")]
406 UNSPEC_MOVE_PIC)))]
407 ""
408 "%d0 = %1@GOT_LOW;"
409 [(set_attr "type" "mvi")
410 (set_attr "length" "4")])
412 (define_insn "movsi_low_pic"
413 [(set (match_operand:SI 0 "register_operand" "=x")
414 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
415 (unspec:SI [(match_operand:SI 2 "" "")]
416 UNSPEC_MOVE_PIC)))]
417 ""
418 "%h0 = %h2@GOT_HIGH;"
419 [(set_attr "type" "mvi")
420 (set_attr "length" "4")])
422 ;;; Move instructions
424 (define_insn_and_split "movdi_insn"
425 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
426 (match_operand:DI 1 "general_operand" "iFx,r,mx"))]
427 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
428 "#"
429 "reload_completed"
430 [(set (match_dup 2) (match_dup 3))
431 (set (match_dup 4) (match_dup 5))]
432 {
433 rtx lo_half[2], hi_half[2];
434 split_di (operands, 2, lo_half, hi_half);
436 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
437 {
438 operands[2] = hi_half[0];
439 operands[3] = hi_half[1];
440 operands[4] = lo_half[0];
441 operands[5] = lo_half[1];
442 }
443 else
444 {
445 operands[2] = lo_half[0];
446 operands[3] = lo_half[1];
447 operands[4] = hi_half[0];
448 operands[5] = hi_half[1];
449 }
450 })
452 (define_insn "movbi"
453 [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
454 (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
456 ""
457 "@
458 %0 = %1;
459 %0 = %1 (X);
460 %0 = B %1 (Z)%!
461 B %0 = %1;
462 CC = %1;
463 %0 = CC;
464 R0 = R0 | R0; CC = AC0;"
465 [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
466 (set_attr "length" "2,2,*,*,2,2,4")
467 (set_attr "seq_insns" "*,*,*,*,*,*,multi")])
469 (define_insn "movpdi"
470 [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
471 (match_operand:PDI 1 "general_operand" " e,e,>"))]
472 ""
473 "@
474 %0 = %1;
475 %0 = %x1; %0 = %w1;
476 %w0 = %1; %x0 = %1;"
477 [(set_attr "type" "move,mcst,mcld")
478 (set_attr "seq_insns" "*,multi,multi")])
480 (define_insn "load_accumulator"
481 [(set (match_operand:PDI 0 "register_operand" "=e")
482 (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
483 ""
484 "%0 = %1;"
485 [(set_attr "type" "move")])
487 (define_insn_and_split "load_accumulator_pair"
488 [(set (match_operand:V2PDI 0 "register_operand" "=e")
489 (sign_extend:V2PDI (vec_concat:V2SI
490 (match_operand:SI 1 "register_operand" "d")
491 (match_operand:SI 2 "register_operand" "d"))))]
492 ""
493 "#"
494 "reload_completed"
495 [(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
496 (set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
497 {
498 operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
499 operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
500 })
502 (define_insn "*pushsi_insn"
503 [(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
504 (match_operand:SI 0 "register_operand" "xy"))]
505 ""
506 "[--SP] = %0;"
507 [(set_attr "type" "mcst")
508 (set_attr "addrtype" "32bit")
509 (set_attr "length" "2")])
511 (define_insn "*popsi_insn"
512 [(set (match_operand:SI 0 "register_operand" "=d,xy")
513 (mem:SI (post_inc:SI (reg:SI REG_SP))))]
514 ""
515 "%0 = [SP++]%!"
516 [(set_attr "type" "mcld")
517 (set_attr "addrtype" "preg,32bit")
518 (set_attr "length" "2")])
520 ;; The first alternative is used to make reload choose a limited register
521 ;; class when faced with a movsi_insn that had its input operand replaced
522 ;; with a PLUS. We generally require fewer secondary reloads this way.
524 (define_insn "*movsi_insn"
525 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr")
526 (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))]
527 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
528 "@
529 %0 = %1;
530 %0 = %1;
531 %0 = %1;
532 %0 = %1;
533 %0 = %1 (X);
534 %0 = %1 (X);
535 %0 = %1 (Z);
536 #
537 %0 = %1%!
538 %0 = %1%!"
539 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
540 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
542 (define_insn "*movsi_insn32"
543 [(set (match_operand:SI 0 "register_operand" "=d,d")
544 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
545 ""
546 "@
547 %0 = ROT %1 BY 0%!
548 %0 = %0 -|- %0%!"
549 [(set_attr "type" "dsp32")])
551 (define_split
552 [(set (match_operand:SI 0 "d_register_operand" "")
553 (const_int 0))]
554 "splitting_for_sched && !optimize_size"
555 [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))])
557 (define_split
558 [(set (match_operand:SI 0 "d_register_operand" "")
559 (match_operand:SI 1 "d_register_operand" ""))]
560 "splitting_for_sched && !optimize_size"
561 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))])
563 (define_insn_and_split "*movv2hi_insn"
564 [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
565 (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
567 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
568 "@
569 #
570 %0 = %1;
571 %0 = %1%!
572 %0 = %1%!"
573 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
574 [(set (match_dup 0) (high:SI (match_dup 2)))
575 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
576 {
577 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
578 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
580 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
581 operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
582 }
583 [(set_attr "type" "move,move,mcld,mcst")
584 (set_attr "length" "2,2,*,*")])
586 (define_insn "*movhi_insn"
587 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
588 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
589 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
590 {
591 static const char *templates[] = {
592 "%0 = %1;",
593 "%0 = %1 (X);",
594 "%0 = %1 (X);",
595 "%0 = W %1 (X)%!",
596 "W %0 = %1%!",
597 "%h0 = W %1%!",
598 "W %0 = %h1%!"
599 };
600 int alt = which_alternative;
601 rtx mem = (MEM_P (operands[0]) ? operands[0]
602 : MEM_P (operands[1]) ? operands[1] : NULL_RTX);
603 if (mem && bfin_dsp_memref_p (mem))
604 alt += 2;
605 return templates[alt];
606 }
607 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
608 (set_attr "length" "2,2,4,*,*")])
610 (define_insn "*movqi_insn"
611 [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
612 (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
613 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
614 "@
615 %0 = %1;
616 %0 = %1 (X);
617 %0 = %1 (X);
618 %0 = B %1 (X)%!
619 B %0 = %1%!"
620 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
621 (set_attr "length" "2,2,4,*,*")])
623 (define_insn "*movsf_insn"
624 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
625 (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
626 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
627 "@
628 %0 = %1;
629 #
630 %0 = %1%!
631 %0 = %1%!"
632 [(set_attr "type" "move,*,mcld,mcst")])
634 (define_insn_and_split "movdf_insn"
635 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
636 (match_operand:DF 1 "general_operand" "iFx,r,mx"))]
637 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
638 "#"
639 "reload_completed"
640 [(set (match_dup 2) (match_dup 3))
641 (set (match_dup 4) (match_dup 5))]
642 {
643 rtx lo_half[2], hi_half[2];
644 split_di (operands, 2, lo_half, hi_half);
646 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
647 {
648 operands[2] = hi_half[0];
649 operands[3] = hi_half[1];
650 operands[4] = lo_half[0];
651 operands[5] = lo_half[1];
652 }
653 else
654 {
655 operands[2] = lo_half[0];
656 operands[3] = lo_half[1];
657 operands[4] = hi_half[0];
658 operands[5] = hi_half[1];
659 }
660 })
662 ;; Storing halfwords.
663 (define_insn "*movsi_insv"
664 [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
665 (const_int 16)
666 (const_int 16))
667 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
668 ""
669 "@
670 %d0 = %h1 << 0%!
671 %d0 = %1;"
672 [(set_attr "type" "dsp32,mvi")])
674 (define_expand "insv"
675 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
676 (match_operand:SI 1 "immediate_operand" "")
677 (match_operand:SI 2 "immediate_operand" ""))
678 (match_operand:SI 3 "nonmemory_operand" ""))]
679 ""
680 {
681 if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
682 FAIL;
684 /* From mips.md: insert_bit_field doesn't verify that our source
685 matches the predicate, so check it again here. */
686 if (! register_operand (operands[0], VOIDmode))
687 FAIL;
688 })
690 ;; This is the main "hook" for PIC code. When generating
691 ;; PIC, movsi is responsible for determining when the source address
692 ;; needs PIC relocation and appropriately calling legitimize_pic_address
693 ;; to perform the actual relocation.
695 (define_expand "movsi"
696 [(set (match_operand:SI 0 "nonimmediate_operand" "")
697 (match_operand:SI 1 "general_operand" ""))]
698 ""
699 {
700 if (expand_move (operands, SImode))
701 DONE;
702 })
704 (define_expand "movv2hi"
705 [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
706 (match_operand:V2HI 1 "general_operand" ""))]
707 ""
708 "expand_move (operands, V2HImode);")
710 (define_expand "movdi"
711 [(set (match_operand:DI 0 "nonimmediate_operand" "")
712 (match_operand:DI 1 "general_operand" ""))]
713 ""
714 "expand_move (operands, DImode);")
716 (define_expand "movsf"
717 [(set (match_operand:SF 0 "nonimmediate_operand" "")
718 (match_operand:SF 1 "general_operand" ""))]
719 ""
720 "expand_move (operands, SFmode);")
722 (define_expand "movdf"
723 [(set (match_operand:DF 0 "nonimmediate_operand" "")
724 (match_operand:DF 1 "general_operand" ""))]
725 ""
726 "expand_move (operands, DFmode);")
728 (define_expand "movhi"
729 [(set (match_operand:HI 0 "nonimmediate_operand" "")
730 (match_operand:HI 1 "general_operand" ""))]
731 ""
732 "expand_move (operands, HImode);")
734 (define_expand "movqi"
735 [(set (match_operand:QI 0 "nonimmediate_operand" "")
736 (match_operand:QI 1 "general_operand" ""))]
737 ""
738 " expand_move (operands, QImode); ")
740 ;; Some define_splits to break up SI/SFmode loads of immediate constants.
742 (define_split
743 [(set (match_operand:SI 0 "register_operand" "")
744 (match_operand:SI 1 "symbolic_or_const_operand" ""))]
745 "reload_completed
746 /* Always split symbolic operands; split integer constants that are
747 too large for a single instruction. */
748 && (GET_CODE (operands[1]) != CONST_INT
749 || (INTVAL (operands[1]) < -32768
750 || INTVAL (operands[1]) >= 65536
751 || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
752 [(set (match_dup 0) (high:SI (match_dup 1)))
753 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
754 {
755 if (GET_CODE (operands[1]) == CONST_INT
756 && split_load_immediate (operands))
757 DONE;
758 /* ??? Do something about TARGET_LOW_64K. */
759 })
761 (define_split
762 [(set (match_operand:SF 0 "register_operand" "")
763 (match_operand:SF 1 "immediate_operand" ""))]
764 "reload_completed"
765 [(set (match_dup 2) (high:SI (match_dup 3)))
766 (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
767 {
768 long values;
769 REAL_VALUE_TYPE value;
771 gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
773 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
774 REAL_VALUE_TO_TARGET_SINGLE (value, values);
776 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
777 operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
778 if (values >= -32768 && values < 65536)
779 {
780 emit_move_insn (operands[2], operands[3]);
781 DONE;
782 }
783 if (split_load_immediate (operands + 2))
784 DONE;
785 })
787 ;; Sadly, this can't be a proper named movstrict pattern, since the compiler
788 ;; expects to be able to use registers for operand 1.
789 ;; Note that the asm instruction is defined by the manual to take an unsigned
790 ;; constant, but it doesn't matter to the assembler, and the compiler only
791 ;; deals with sign-extended constants. Hence "Ksh".
792 (define_insn "movstricthi_1"
793 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
794 (match_operand:HI 1 "immediate_operand" "Ksh"))]
795 ""
796 "%h0 = %1;"
797 [(set_attr "type" "mvi")
798 (set_attr "length" "4")])
800 ;; Sign and zero extensions
802 (define_insn_and_split "extendhisi2"
803 [(set (match_operand:SI 0 "register_operand" "=d, d")
804 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
805 ""
806 "@
807 %0 = %h1 (X);
808 %0 = W %h1 (X)%!"
809 "reload_completed && bfin_dsp_memref_p (operands[1])"
810 [(set (match_dup 2) (match_dup 1))
811 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
812 {
813 operands[2] = gen_lowpart (HImode, operands[0]);
814 }
815 [(set_attr "type" "alu0,mcld")])
817 (define_insn_and_split "zero_extendhisi2"
818 [(set (match_operand:SI 0 "register_operand" "=d, d")
819 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
820 ""
821 "@
822 %0 = %h1 (Z);
823 %0 = W %h1 (Z)%!"
824 "reload_completed && bfin_dsp_memref_p (operands[1])"
825 [(set (match_dup 2) (match_dup 1))
826 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
827 {
828 operands[2] = gen_lowpart (HImode, operands[0]);
829 }
830 [(set_attr "type" "alu0,mcld")])
832 (define_insn "zero_extendbisi2"
833 [(set (match_operand:SI 0 "register_operand" "=d")
834 (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
835 ""
836 "%0 = %1;"
837 [(set_attr "type" "compare")])
839 (define_insn "extendqihi2"
840 [(set (match_operand:HI 0 "register_operand" "=d, d")
841 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
842 ""
843 "@
844 %0 = B %1 (X)%!
845 %0 = %T1 (X);"
846 [(set_attr "type" "mcld,alu0")])
848 (define_insn "extendqisi2"
849 [(set (match_operand:SI 0 "register_operand" "=d, d")
850 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
851 ""
852 "@
853 %0 = B %1 (X)%!
854 %0 = %T1 (X);"
855 [(set_attr "type" "mcld,alu0")])
858 (define_insn "zero_extendqihi2"
859 [(set (match_operand:HI 0 "register_operand" "=d, d")
860 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
861 ""
862 "@
863 %0 = B %1 (Z)%!
864 %0 = %T1 (Z);"
865 [(set_attr "type" "mcld,alu0")])
868 (define_insn "zero_extendqisi2"
869 [(set (match_operand:SI 0 "register_operand" "=d, d")
870 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
871 ""
872 "@
873 %0 = B %1 (Z)%!
874 %0 = %T1 (Z);"
875 [(set_attr "type" "mcld,alu0")])
877 ;; DImode logical operations
879 (define_code_macro any_logical [and ior xor])
880 (define_code_attr optab [(and "and")
881 (ior "ior")
882 (xor "xor")])
883 (define_code_attr op [(and "&")
884 (ior "|")
885 (xor "^")])
886 (define_code_attr high_result [(and "0")
887 (ior "%H1")
888 (xor "%H1")])
890 (define_insn "<optab>di3"
891 [(set (match_operand:DI 0 "register_operand" "=d")
892 (any_logical:DI (match_operand:DI 1 "register_operand" "0")
893 (match_operand:DI 2 "register_operand" "d")))]
894 ""
895 "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;"
896 [(set_attr "length" "4")
897 (set_attr "seq_insns" "multi")])
899 (define_insn "*<optab>di_zesidi_di"
900 [(set (match_operand:DI 0 "register_operand" "=d")
901 (any_logical:DI (zero_extend:DI
902 (match_operand:SI 2 "register_operand" "d"))
903 (match_operand:DI 1 "register_operand" "d")))]
904 ""
905 "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;"
906 [(set_attr "length" "4")
907 (set_attr "seq_insns" "multi")])
909 (define_insn "*<optab>di_sesdi_di"
910 [(set (match_operand:DI 0 "register_operand" "=d")
911 (any_logical:DI (sign_extend:DI
912 (match_operand:SI 2 "register_operand" "d"))
913 (match_operand:DI 1 "register_operand" "0")))
914 (clobber (match_scratch:SI 3 "=&d"))]
915 ""
916 "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;"
917 [(set_attr "length" "8")
918 (set_attr "seq_insns" "multi")])
920 (define_insn "negdi2"
921 [(set (match_operand:DI 0 "register_operand" "=d")
922 (neg:DI (match_operand:DI 1 "register_operand" "d")))
923 (clobber (match_scratch:SI 2 "=&d"))
924 (clobber (reg:CC REG_CC))]
925 ""
926 "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;"
927 [(set_attr "length" "16")
928 (set_attr "seq_insns" "multi")])
930 (define_insn "one_cmpldi2"
931 [(set (match_operand:DI 0 "register_operand" "=d")
932 (not:DI (match_operand:DI 1 "register_operand" "d")))]
933 ""
934 "%0 = ~%1;\\n\\t%H0 = ~%H1;"
935 [(set_attr "length" "4")
936 (set_attr "seq_insns" "multi")])
938 ;; DImode zero and sign extend patterns
940 (define_insn_and_split "zero_extendsidi2"
941 [(set (match_operand:DI 0 "register_operand" "=d")
942 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
943 ""
944 "#"
945 "reload_completed"
946 [(set (match_dup 3) (const_int 0))]
947 {
948 split_di (operands, 1, operands + 2, operands + 3);
949 if (REGNO (operands[0]) != REGNO (operands[1]))
950 emit_move_insn (operands[2], operands[1]);
951 })
953 (define_insn "zero_extendqidi2"
954 [(set (match_operand:DI 0 "register_operand" "=d")
955 (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
956 ""
957 "%0 = %T1 (Z);\\n\\t%H0 = 0;"
958 [(set_attr "length" "4")
959 (set_attr "seq_insns" "multi")])
961 (define_insn "zero_extendhidi2"
962 [(set (match_operand:DI 0 "register_operand" "=d")
963 (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
964 ""
965 "%0 = %h1 (Z);\\n\\t%H0 = 0;"
966 [(set_attr "length" "4")
967 (set_attr "seq_insns" "multi")])
969 (define_insn_and_split "extendsidi2"
970 [(set (match_operand:DI 0 "register_operand" "=d")
971 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
972 ""
973 "#"
974 "reload_completed"
975 [(set (match_dup 3) (match_dup 1))
976 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
977 {
978 split_di (operands, 1, operands + 2, operands + 3);
979 if (REGNO (operands[0]) != REGNO (operands[1]))
980 emit_move_insn (operands[2], operands[1]);
981 })
983 (define_insn_and_split "extendqidi2"
984 [(set (match_operand:DI 0 "register_operand" "=d")
985 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
986 ""
987 "#"
988 "reload_completed"
989 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
990 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
991 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
992 {
993 split_di (operands, 1, operands + 2, operands + 3);
994 })
996 (define_insn_and_split "extendhidi2"
997 [(set (match_operand:DI 0 "register_operand" "=d")
998 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
999 ""
1000 "#"
1001 "reload_completed"
1002 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
1003 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
1004 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1005 {
1006 split_di (operands, 1, operands + 2, operands + 3);
1007 })
1009 ;; DImode arithmetic operations
1011 (define_insn "add_with_carry"
1012 [(set (match_operand:SI 0 "register_operand" "=d,d")
1013 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1014 (match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
1015 (set (match_operand:SI 3 "register_operand" "=d,d")
1016 (truncate:SI
1017 (lshiftrt:DI (plus:DI (zero_extend:DI (match_dup 1))
1018 (zero_extend:DI (match_dup 2)))
1019 (const_int 32))))
1020 (clobber (reg:CC 34))]
1021 ""
1022 "@
1023 %0 += %2; cc = ac0; %3 = cc;
1024 %0 = %0 + %2; cc = ac0; %3 = cc;"
1025 [(set_attr "type" "alu0")
1026 (set_attr "length" "6")
1027 (set_attr "seq_insns" "multi")])
1029 (define_insn "adddi3"
1030 [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
1031 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
1032 (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d")))
1033 (clobber (match_scratch:SI 3 "=&d,&d,&d"))
1034 (clobber (reg:CC 34))]
1035 ""
1036 "@
1037 %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3;
1038 %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3;
1039 %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;"
1040 [(set_attr "type" "alu0")
1041 (set_attr "length" "10,8,10")
1042 (set_attr "seq_insns" "multi,multi,multi")])
1044 (define_insn "subdi3"
1045 [(set (match_operand:DI 0 "register_operand" "=&d")
1046 (minus:DI (match_operand:DI 1 "register_operand" "0")
1047 (match_operand:DI 2 "register_operand" "d")))
1048 (clobber (reg:CC 34))]
1049 ""
1050 "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1051 [(set_attr "length" "10")
1052 (set_attr "seq_insns" "multi")])
1054 (define_insn "*subdi_di_zesidi"
1055 [(set (match_operand:DI 0 "register_operand" "=d")
1056 (minus:DI (match_operand:DI 1 "register_operand" "0")
1057 (zero_extend:DI
1058 (match_operand:SI 2 "register_operand" "d"))))
1059 (clobber (match_scratch:SI 3 "=&d"))
1060 (clobber (reg:CC 34))]
1061 ""
1062 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;"
1063 [(set_attr "length" "10")
1064 (set_attr "seq_insns" "multi")])
1066 (define_insn "*subdi_zesidi_di"
1067 [(set (match_operand:DI 0 "register_operand" "=d")
1068 (minus:DI (zero_extend:DI
1069 (match_operand:SI 2 "register_operand" "d"))
1070 (match_operand:DI 1 "register_operand" "0")))
1071 (clobber (match_scratch:SI 3 "=&d"))
1072 (clobber (reg:CC 34))]
1073 ""
1074 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1"
1075 [(set_attr "length" "12")
1076 (set_attr "seq_insns" "multi")])
1078 (define_insn "*subdi_di_sesidi"
1079 [(set (match_operand:DI 0 "register_operand" "=d")
1080 (minus:DI (match_operand:DI 1 "register_operand" "0")
1081 (sign_extend:DI
1082 (match_operand:SI 2 "register_operand" "d"))))
1083 (clobber (match_scratch:SI 3 "=&d"))
1084 (clobber (reg:CC 34))]
1085 ""
1086 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1087 [(set_attr "length" "14")
1088 (set_attr "seq_insns" "multi")])
1090 (define_insn "*subdi_sesidi_di"
1091 [(set (match_operand:DI 0 "register_operand" "=d")
1092 (minus:DI (sign_extend:DI
1093 (match_operand:SI 2 "register_operand" "d"))
1094 (match_operand:DI 1 "register_operand" "0")))
1095 (clobber (match_scratch:SI 3 "=&d"))
1096 (clobber (reg:CC 34))]
1097 ""
1098 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1099 [(set_attr "length" "14")
1100 (set_attr "seq_insns" "multi")])
1102 ;; Combined shift/add instructions
1104 (define_insn ""
1105 [(set (match_operand:SI 0 "register_operand" "=a,d")
1106 (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1107 (match_operand:SI 2 "register_operand" "a,d"))
1108 (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
1109 ""
1110 "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
1111 [(set_attr "type" "alu0")])
1113 (define_insn ""
1114 [(set (match_operand:SI 0 "register_operand" "=a")
1115 (plus:SI (match_operand:SI 1 "register_operand" "a")
1116 (mult:SI (match_operand:SI 2 "register_operand" "a")
1117 (match_operand:SI 3 "scale_by_operand" "i"))))]
1118 ""
1119 "%0 = %1 + (%2 << %X3);"
1120 [(set_attr "type" "alu0")])
1122 (define_insn ""
1123 [(set (match_operand:SI 0 "register_operand" "=a")
1124 (plus:SI (match_operand:SI 1 "register_operand" "a")
1125 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1126 (match_operand:SI 3 "pos_scale_operand" "i"))))]
1127 ""
1128 "%0 = %1 + (%2 << %3);"
1129 [(set_attr "type" "alu0")])
1131 (define_insn ""
1132 [(set (match_operand:SI 0 "register_operand" "=a")
1133 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
1134 (match_operand:SI 2 "scale_by_operand" "i"))
1135 (match_operand:SI 3 "register_operand" "a")))]
1136 ""
1137 "%0 = %3 + (%1 << %X2);"
1138 [(set_attr "type" "alu0")])
1140 (define_insn ""
1141 [(set (match_operand:SI 0 "register_operand" "=a")
1142 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
1143 (match_operand:SI 2 "pos_scale_operand" "i"))
1144 (match_operand:SI 3 "register_operand" "a")))]
1145 ""
1146 "%0 = %3 + (%1 << %2);"
1147 [(set_attr "type" "alu0")])
1149 (define_insn "mulhisi3"
1150 [(set (match_operand:SI 0 "register_operand" "=d")
1151 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1152 (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1153 ""
1154 "%0 = %h1 * %h2 (IS)%!"
1155 [(set_attr "type" "dsp32")])
1157 (define_insn "umulhisi3"
1158 [(set (match_operand:SI 0 "register_operand" "=d")
1159 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1160 (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1161 ""
1162 "%0 = %h1 * %h2 (FU)%!"
1163 [(set_attr "type" "dsp32")])
1165 (define_insn "usmulhisi3"
1166 [(set (match_operand:SI 0 "register_operand" "=W")
1167 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
1168 (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
1169 ""
1170 "%0 = %h2 * %h1 (IS,M)%!"
1171 [(set_attr "type" "dsp32")])
1173 ;; The processor also supports ireg += mreg or ireg -= mreg, but these
1174 ;; are unusable if we don't ensure that the corresponding lreg is zero.
1175 ;; The same applies to the add/subtract constant versions involving
1176 ;; iregs
1178 (define_insn "addsi3"
1179 [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
1180 (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
1181 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
1182 ""
1183 "@
1184 %0 += %2;
1185 %0 = %1 + %2;
1186 %0 = %1 + %2;"
1187 [(set_attr "type" "alu0")
1188 (set_attr "length" "2,2,2")])
1190 (define_insn "ssaddsi3"
1191 [(set (match_operand:SI 0 "register_operand" "=d")
1192 (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1193 (match_operand:SI 2 "register_operand" "d")))]
1194 ""
1195 "%0 = %1 + %2 (S)%!"
1196 [(set_attr "type" "dsp32")])
1198 (define_insn "subsi3"
1199 [(set (match_operand:SI 0 "register_operand" "=da,d,a")
1200 (minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
1201 (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))]
1202 ""
1203 {
1204 static const char *const strings_subsi3[] = {
1205 "%0 += -%2;",
1206 "%0 = %1 - %2;",
1207 "%0 -= %2;",
1208 };
1210 if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
1211 rtx tmp_op = operands[2];
1212 operands[2] = GEN_INT (-INTVAL (operands[2]));
1213 output_asm_insn ("%0 += %2;", operands);
1214 operands[2] = tmp_op;
1215 return "";
1216 }
1218 return strings_subsi3[which_alternative];
1219 }
1220 [(set_attr "type" "alu0")])
1222 (define_insn "sssubsi3"
1223 [(set (match_operand:SI 0 "register_operand" "=d")
1224 (ss_minus:SI (match_operand:SI 1 "register_operand" "d")
1225 (match_operand:SI 2 "register_operand" "d")))]
1226 ""
1227 "%0 = %1 - %2 (S)%!"
1228 [(set_attr "type" "dsp32")])
1230 ;; Accumulator addition
1232 (define_insn "sum_of_accumulators"
1233 [(set (match_operand:SI 0 "register_operand" "=d")
1234 (ss_truncate:SI
1235 (ss_plus:PDI (match_operand:PDI 2 "register_operand" "1")
1236 (match_operand:PDI 3 "register_operand" "B"))))
1237 (set (match_operand:PDI 1 "register_operand" "=A")
1238 (ss_plus:PDI (match_dup 2) (match_dup 3)))]
1239 ""
1240 "%0 = (A0 += A1)%!"
1241 [(set_attr "type" "dsp32")])
1243 ;; Bit test instructions
1245 (define_insn "*not_bittst"
1246 [(set (match_operand:BI 0 "register_operand" "=C")
1247 (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1248 (const_int 1)
1249 (match_operand:SI 2 "immediate_operand" "Ku5"))
1250 (const_int 0)))]
1251 ""
1252 "cc = !BITTST (%1,%2);"
1253 [(set_attr "type" "alu0")])
1255 (define_insn "*bittst"
1256 [(set (match_operand:BI 0 "register_operand" "=C")
1257 (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1258 (const_int 1)
1259 (match_operand:SI 2 "immediate_operand" "Ku5"))
1260 (const_int 0)))]
1261 ""
1262 "cc = BITTST (%1,%2);"
1263 [(set_attr "type" "alu0")])
1265 (define_insn_and_split "*bit_extract"
1266 [(set (match_operand:SI 0 "register_operand" "=d")
1267 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1268 (const_int 1)
1269 (match_operand:SI 2 "immediate_operand" "Ku5")))
1270 (clobber (reg:BI REG_CC))]
1271 ""
1272 "#"
1273 ""
1274 [(set (reg:BI REG_CC)
1275 (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1276 (const_int 0)))
1277 (set (match_dup 0)
1278 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1280 (define_insn_and_split "*not_bit_extract"
1281 [(set (match_operand:SI 0 "register_operand" "=d")
1282 (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1283 (const_int 1)
1284 (match_operand:SI 2 "immediate_operand" "Ku5")))
1285 (clobber (reg:BI REG_CC))]
1286 ""
1287 "#"
1288 ""
1289 [(set (reg:BI REG_CC)
1290 (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1291 (const_int 0)))
1292 (set (match_dup 0)
1293 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1295 (define_insn "*andsi_insn"
1296 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1297 (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
1298 (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
1299 ""
1300 "@
1301 BITCLR (%0,%Y2);
1302 %0 = %T1 (Z);
1303 %0 = %h1 (Z);
1304 %0 = %1 & %2;"
1305 [(set_attr "type" "alu0")])
1307 (define_expand "andsi3"
1308 [(set (match_operand:SI 0 "register_operand" "")
1309 (and:SI (match_operand:SI 1 "register_operand" "")
1310 (match_operand:SI 2 "general_operand" "")))]
1311 ""
1312 {
1313 if (highbits_operand (operands[2], SImode))
1314 {
1315 operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
1316 emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
1317 emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
1318 DONE;
1319 }
1320 if (! rhs_andsi3_operand (operands[2], SImode))
1321 operands[2] = force_reg (SImode, operands[2]);
1322 })
1324 (define_insn "iorsi3"
1325 [(set (match_operand:SI 0 "register_operand" "=d,d")
1326 (ior:SI (match_operand:SI 1 "register_operand" "%0,d")
1327 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1328 ""
1329 "@
1330 BITSET (%0, %X2);
1331 %0 = %1 | %2;"
1332 [(set_attr "type" "alu0")])
1334 (define_insn "xorsi3"
1335 [(set (match_operand:SI 0 "register_operand" "=d,d")
1336 (xor:SI (match_operand:SI 1 "register_operand" "%0,d")
1337 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1338 ""
1339 "@
1340 BITTGL (%0, %X2);
1341 %0 = %1 ^ %2;"
1342 [(set_attr "type" "alu0")])
1344 (define_insn "smaxsi3"
1345 [(set (match_operand:SI 0 "register_operand" "=d")
1346 (smax:SI (match_operand:SI 1 "register_operand" "d")
1347 (match_operand:SI 2 "register_operand" "d")))]
1348 ""
1349 "%0 = max(%1,%2)%!"
1350 [(set_attr "type" "dsp32")])
1352 (define_insn "sminsi3"
1353 [(set (match_operand:SI 0 "register_operand" "=d")
1354 (smin:SI (match_operand:SI 1 "register_operand" "d")
1355 (match_operand:SI 2 "register_operand" "d")))]
1356 ""
1357 "%0 = min(%1,%2)%!"
1358 [(set_attr "type" "dsp32")])
1360 (define_insn "abssi2"
1361 [(set (match_operand:SI 0 "register_operand" "=d")
1362 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1363 ""
1364 "%0 = abs %1%!"
1365 [(set_attr "type" "dsp32")])
1367 (define_insn "negsi2"
1368 [(set (match_operand:SI 0 "register_operand" "=d")
1369 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1370 ""
1371 "%0 = -%1;"
1372 [(set_attr "type" "alu0")])
1374 (define_insn "ssnegsi2"
1375 [(set (match_operand:SI 0 "register_operand" "=d")
1376 (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
1377 ""
1378 "%0 = -%1 (S)%!"
1379 [(set_attr "type" "dsp32")])
1381 (define_insn "one_cmplsi2"
1382 [(set (match_operand:SI 0 "register_operand" "=d")
1383 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1384 ""
1385 "%0 = ~%1;"
1386 [(set_attr "type" "alu0")])
1388 (define_insn "signbitssi2"
1389 [(set (match_operand:HI 0 "register_operand" "=d")
1390 (if_then_else:HI
1391 (lt (match_operand:SI 1 "register_operand" "d") (const_int 0))
1392 (clz:HI (not:SI (match_dup 1)))
1393 (clz:HI (match_dup 1))))]
1394 ""
1395 "%h0 = signbits %1%!"
1396 [(set_attr "type" "dsp32")])
1398 (define_insn "smaxhi3"
1399 [(set (match_operand:HI 0 "register_operand" "=d")
1400 (smax:HI (match_operand:HI 1 "register_operand" "d")
1401 (match_operand:HI 2 "register_operand" "d")))]
1402 ""
1403 "%0 = max(%1,%2) (V)%!"
1404 [(set_attr "type" "dsp32")])
1406 (define_insn "sminhi3"
1407 [(set (match_operand:HI 0 "register_operand" "=d")
1408 (smin:HI (match_operand:HI 1 "register_operand" "d")
1409 (match_operand:HI 2 "register_operand" "d")))]
1410 ""
1411 "%0 = min(%1,%2) (V)%!"
1412 [(set_attr "type" "dsp32")])
1414 (define_insn "abshi2"
1415 [(set (match_operand:HI 0 "register_operand" "=d")
1416 (abs:HI (match_operand:HI 1 "register_operand" "d")))]
1417 ""
1418 "%0 = abs %1 (V)%!"
1419 [(set_attr "type" "dsp32")])
1421 (define_insn "neghi2"
1422 [(set (match_operand:HI 0 "register_operand" "=d")
1423 (neg:HI (match_operand:HI 1 "register_operand" "d")))]
1424 ""
1425 "%0 = -%1;"
1426 [(set_attr "type" "alu0")])
1428 (define_insn "ssneghi2"
1429 [(set (match_operand:HI 0 "register_operand" "=d")
1430 (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
1431 ""
1432 "%0 = -%1 (V)%!"
1433 [(set_attr "type" "dsp32")])
1435 (define_insn "signbitshi2"
1436 [(set (match_operand:HI 0 "register_operand" "=d")
1437 (if_then_else:HI
1438 (lt (match_operand:HI 1 "register_operand" "d") (const_int 0))
1439 (clz:HI (not:HI (match_dup 1)))
1440 (clz:HI (match_dup 1))))]
1441 ""
1442 "%h0 = signbits %h1%!"
1443 [(set_attr "type" "dsp32")])
1445 (define_insn "mulsi3"
1446 [(set (match_operand:SI 0 "register_operand" "=d")
1447 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1448 (match_operand:SI 2 "register_operand" "d")))]
1449 ""
1450 "%0 *= %2;"
1451 [(set_attr "type" "mult")])
1453 (define_expand "umulsi3_highpart"
1454 [(set (match_operand:SI 0 "register_operand" "")
1455 (truncate:SI
1456 (lshiftrt:DI
1457 (mult:DI (zero_extend:DI
1458 (match_operand:SI 1 "nonimmediate_operand" ""))
1459 (zero_extend:DI
1460 (match_operand:SI 2 "register_operand" "")))
1461 (const_int 32))))]
1462 ""
1463 {
1464 rtx umulsi3_highpart_libfunc
1465 = init_one_libfunc ("__umulsi3_highpart");
1467 emit_library_call_value (umulsi3_highpart_libfunc,
1468 operands[0], LCT_NORMAL, SImode,
1469 2, operands[1], SImode, operands[2], SImode);
1470 DONE;
1471 })
1473 (define_expand "smulsi3_highpart"
1474 [(set (match_operand:SI 0 "register_operand" "")
1475 (truncate:SI
1476 (lshiftrt:DI
1477 (mult:DI (sign_extend:DI
1478 (match_operand:SI 1 "nonimmediate_operand" ""))
1479 (sign_extend:DI
1480 (match_operand:SI 2 "register_operand" "")))
1481 (const_int 32))))]
1482 ""
1483 {
1484 rtx smulsi3_highpart_libfunc
1485 = init_one_libfunc ("__smulsi3_highpart");
1487 emit_library_call_value (smulsi3_highpart_libfunc,
1488 operands[0], LCT_NORMAL, SImode,
1489 2, operands[1], SImode, operands[2], SImode);
1490 DONE;
1491 })
1493 (define_expand "ashlsi3"
1494 [(set (match_operand:SI 0 "register_operand" "")
1495 (ashift:SI (match_operand:SI 1 "register_operand" "")
1496 (match_operand:SI 2 "nonmemory_operand" "")))]
1497 ""
1498 {
1499 if (GET_CODE (operands[2]) == CONST_INT
1500 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
1501 {
1502 emit_insn (gen_movsi (operands[0], const0_rtx));
1503 DONE;
1504 }
1505 })
1507 (define_insn_and_split "*ashlsi3_insn"
1508 [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a")
1509 (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a")
1510 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))]
1511 ""
1512 "@
1513 %0 <<= %2;
1514 %0 = %1 << %2%!
1515 %0 = %1 + %1;
1516 %0 = %1 << %2;
1517 #"
1518 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1519 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1520 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1521 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1522 [(set_attr "type" "shft,dsp32,shft,shft,*")])
1524 (define_insn "ashrsi3"
1525 [(set (match_operand:SI 0 "register_operand" "=d,d")
1526 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1527 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
1528 ""
1529 "@
1530 %0 >>>= %2;
1531 %0 = %1 >>> %2%!"
1532 [(set_attr "type" "shft,dsp32")])
1534 (define_insn "rotl16"
1535 [(set (match_operand:SI 0 "register_operand" "=d")
1536 (rotate:SI (match_operand:SI 1 "register_operand" "d")
1537 (const_int 16)))]
1538 ""
1539 "%0 = PACK (%h1, %d1)%!"
1540 [(set_attr "type" "dsp32")])
1542 (define_expand "rotlsi3"
1543 [(set (match_operand:SI 0 "register_operand" "")
1544 (rotate:SI (match_operand:SI 1 "register_operand" "")
1545 (match_operand:SI 2 "immediate_operand" "")))]
1546 ""
1547 {
1548 if (INTVAL (operands[2]) != 16)
1549 FAIL;
1550 })
1552 (define_expand "rotrsi3"
1553 [(set (match_operand:SI 0 "register_operand" "")
1554 (rotatert:SI (match_operand:SI 1 "register_operand" "")
1555 (match_operand:SI 2 "immediate_operand" "")))]
1556 ""
1557 {
1558 if (INTVAL (operands[2]) != 16)
1559 FAIL;
1560 emit_insn (gen_rotl16 (operands[0], operands[1]));
1561 DONE;
1562 })
1565 (define_insn "ror_one"
1566 [(set (match_operand:SI 0 "register_operand" "=d")
1567 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1568 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1569 (set (reg:BI REG_CC)
1570 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1571 ""
1572 "%0 = ROT %1 BY -1%!"
1573 [(set_attr "type" "dsp32")])
1575 (define_insn "rol_one"
1576 [(set (match_operand:SI 0 "register_operand" "+d")
1577 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1578 (zero_extend:SI (reg:BI REG_CC))))
1579 (set (reg:BI REG_CC)
1580 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1581 ""
1582 "%0 = ROT %1 BY 1%!"
1583 [(set_attr "type" "dsp32")])
1585 (define_expand "lshrdi3"
1586 [(set (match_operand:DI 0 "register_operand" "")
1587 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1588 (match_operand:DI 2 "general_operand" "")))]
1589 ""
1590 {
1591 rtx lo_half[2], hi_half[2];
1593 if (operands[2] != const1_rtx)
1594 FAIL;
1595 if (! rtx_equal_p (operands[0], operands[1]))
1596 emit_move_insn (operands[0], operands[1]);
1598 split_di (operands, 2, lo_half, hi_half);
1600 emit_move_insn (bfin_cc_rtx, const0_rtx);
1601 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1602 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1603 DONE;
1604 })
1606 (define_expand "ashrdi3"
1607 [(set (match_operand:DI 0 "register_operand" "")
1608 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
1609 (match_operand:DI 2 "general_operand" "")))]
1610 ""
1611 {
1612 rtx lo_half[2], hi_half[2];
1614 if (operands[2] != const1_rtx)
1615 FAIL;
1616 if (! rtx_equal_p (operands[0], operands[1]))
1617 emit_move_insn (operands[0], operands[1]);
1619 split_di (operands, 2, lo_half, hi_half);
1621 emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
1622 hi_half[1], const0_rtx));
1623 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1624 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1625 DONE;
1626 })
1628 (define_expand "ashldi3"
1629 [(set (match_operand:DI 0 "register_operand" "")
1630 (ashift:DI (match_operand:DI 1 "register_operand" "")
1631 (match_operand:DI 2 "general_operand" "")))]
1632 ""
1633 {
1634 rtx lo_half[2], hi_half[2];
1636 if (operands[2] != const1_rtx)
1637 FAIL;
1638 if (! rtx_equal_p (operands[0], operands[1]))
1639 emit_move_insn (operands[0], operands[1]);
1641 split_di (operands, 2, lo_half, hi_half);
1643 emit_move_insn (bfin_cc_rtx, const0_rtx);
1644 emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
1645 emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
1646 DONE;
1647 })
1649 (define_insn "lshrsi3"
1650 [(set (match_operand:SI 0 "register_operand" "=d,d,a")
1651 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a")
1652 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))]
1653 ""
1654 "@
1655 %0 >>= %2;
1656 %0 = %1 >> %2%!
1657 %0 = %1 >> %2;"
1658 [(set_attr "type" "shft,dsp32,shft")])
1660 (define_insn "lshrpdi3"
1661 [(set (match_operand:PDI 0 "register_operand" "=e")
1662 (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1663 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1664 ""
1665 "%0 = %1 >> %2%!"
1666 [(set_attr "type" "dsp32")])
1668 (define_insn "ashrpdi3"
1669 [(set (match_operand:PDI 0 "register_operand" "=e")
1670 (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1671 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1672 ""
1673 "%0 = %1 >>> %2%!"
1674 [(set_attr "type" "dsp32")])
1676 ;; A pattern to reload the equivalent of
1677 ;; (set (Dreg) (plus (FP) (large_constant)))
1678 ;; or
1679 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1680 ;; using a scratch register
1681 (define_expand "reload_insi"
1682 [(parallel [(set (match_operand:SI 0 "register_operand" "=w")
1683 (match_operand:SI 1 "fp_plus_const_operand" ""))
1684 (clobber (match_operand:SI 2 "register_operand" "=&a"))])]
1685 ""
1686 {
1687 rtx fp_op = XEXP (operands[1], 0);
1688 rtx const_op = XEXP (operands[1], 1);
1689 rtx primary = operands[0];
1690 rtx scratch = operands[2];
1692 emit_move_insn (scratch, const_op);
1693 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1694 emit_move_insn (primary, scratch);
1695 DONE;
1696 })
1698 ;; Jump instructions
1700 (define_insn "jump"
1701 [(set (pc)
1702 (label_ref (match_operand 0 "" "")))]
1703 ""
1704 {
1705 if (get_attr_length (insn) == 2)
1706 return "jump.s %0;";
1707 else
1708 return "jump.l %0;";
1709 }
1710 [(set_attr "type" "br")])
1712 (define_insn "indirect_jump"
1713 [(set (pc)
1714 (match_operand:SI 0 "register_operand" "a"))]
1715 ""
1716 "jump (%0);"
1717 [(set_attr "type" "misc")])
1719 (define_expand "tablejump"
1720 [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1721 (use (label_ref (match_operand 1 "" "")))])]
1722 ""
1723 {
1724 /* In PIC mode, the table entries are stored PC relative.
1725 Convert the relative address to an absolute address. */
1726 if (flag_pic)
1727 {
1728 rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
1730 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
1731 op1, NULL_RTX, 0, OPTAB_DIRECT);
1732 }
1733 })
1735 (define_insn "*tablejump_internal"
1736 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1737 (use (label_ref (match_operand 1 "" "")))]
1738 ""
1739 "jump (%0);"
1740 [(set_attr "type" "misc")])
1742 ;; Hardware loop
1744 ; operand 0 is the loop count pseudo register
1745 ; operand 1 is the number of loop iterations or 0 if it is unknown
1746 ; operand 2 is the maximum number of loop iterations
1747 ; operand 3 is the number of levels of enclosed loops
1748 ; operand 4 is the label to jump to at the top of the loop
1749 (define_expand "doloop_end"
1750 [(parallel [(set (pc) (if_then_else
1751 (ne (match_operand:SI 0 "" "")
1752 (const_int 1))
1753 (label_ref (match_operand 4 "" ""))
1754 (pc)))
1755 (set (match_dup 0)
1756 (plus:SI (match_dup 0)
1757 (const_int -1)))
1758 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1759 (clobber (match_scratch:SI 5 ""))])]
1760 ""
1761 {
1762 /* The loop optimizer doesn't check the predicates... */
1763 if (GET_MODE (operands[0]) != SImode)
1764 FAIL;
1765 /* Due to limitations in the hardware (an initial loop count of 0
1766 does not loop 2^32 times) we must avoid to generate a hardware
1767 loops when we cannot rule out this case. */
1768 if (!flag_unsafe_loop_optimizations
1769 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF)
1770 FAIL;
1771 bfin_hardware_loop ();
1772 })
1774 (define_insn "loop_end"
1775 [(set (pc)
1776 (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m")
1777 (const_int 1))
1778 (label_ref (match_operand 1 "" ""))
1779 (pc)))
1780 (set (match_dup 0)
1781 (plus (match_dup 0)
1782 (const_int -1)))
1783 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1784 (clobber (match_scratch:SI 2 "=X,&r,&r"))]
1785 ""
1786 "@
1787 /* loop end %0 %l1 */
1788 #
1789 #"
1790 [(set_attr "length" "6,10,14")])
1792 (define_split
1793 [(set (pc)
1794 (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "")
1795 (const_int 1))
1796 (label_ref (match_operand 1 "" ""))
1797 (pc)))
1798 (set (match_dup 0)
1799 (plus (match_dup 0)
1800 (const_int -1)))
1801 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1802 (clobber (match_scratch:SI 2 "=&r"))]
1803 "reload_completed"
1804 [(set (match_dup 2) (match_dup 0))
1805 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1806 (set (match_dup 0) (match_dup 2))
1807 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1808 (set (pc)
1809 (if_then_else (eq (reg:BI REG_CC)
1810 (const_int 0))
1811 (label_ref (match_dup 1))
1812 (pc)))]
1813 "")
1815 (define_insn "lsetup_with_autoinit"
1816 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1817 (label_ref (match_operand 1 "" "")))
1818 (set (match_operand:SI 2 "lb_register_operand" "=u")
1819 (label_ref (match_operand 3 "" "")))
1820 (set (match_operand:SI 4 "lc_register_operand" "=k")
1821 (match_operand:SI 5 "register_operand" "a"))]
1822 ""
1823 "LSETUP (%1, %3) %4 = %5;"
1824 [(set_attr "length" "4")])
1826 (define_insn "lsetup_without_autoinit"
1827 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1828 (label_ref (match_operand 1 "" "")))
1829 (set (match_operand:SI 2 "lb_register_operand" "=u")
1830 (label_ref (match_operand 3 "" "")))
1831 (use (match_operand:SI 4 "lc_register_operand" "k"))]
1832 ""
1833 "LSETUP (%1, %3) %4;"
1834 [(set_attr "length" "4")])
1836 ;; Call instructions..
1838 ;; The explicit MEM inside the UNSPEC prevents the compiler from moving
1839 ;; the load before a branch after a NULL test, or before a store that
1840 ;; initializes a function descriptor.
1842 (define_insn_and_split "load_funcdescsi"
1843 [(set (match_operand:SI 0 "register_operand" "=a")
1844 (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
1845 UNSPEC_VOLATILE_LOAD_FUNCDESC))]
1846 ""
1847 "#"
1848 "reload_completed"
1849 [(set (match_dup 0) (mem:SI (match_dup 1)))])
1851 (define_expand "call"
1852 [(parallel [(call (match_operand:SI 0 "" "")
1853 (match_operand 1 "" ""))
1854 (use (match_operand 2 "" ""))])]
1855 ""
1856 {
1857 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
1858 DONE;
1859 })
1861 (define_expand "sibcall"
1862 [(parallel [(call (match_operand:SI 0 "" "")
1863 (match_operand 1 "" ""))
1864 (use (match_operand 2 "" ""))
1865 (return)])]
1866 ""
1867 {
1868 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
1869 DONE;
1870 })
1872 (define_expand "call_value"
1873 [(parallel [(set (match_operand 0 "register_operand" "")
1874 (call (match_operand:SI 1 "" "")
1875 (match_operand 2 "" "")))
1876 (use (match_operand 3 "" ""))])]
1877 ""
1878 {
1879 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
1880 DONE;
1881 })
1883 (define_expand "sibcall_value"
1884 [(parallel [(set (match_operand 0 "register_operand" "")
1885 (call (match_operand:SI 1 "" "")
1886 (match_operand 2 "" "")))
1887 (use (match_operand 3 "" ""))
1888 (return)])]
1889 ""
1890 {
1891 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
1892 DONE;
1893 })
1895 (define_insn "*call_symbol_fdpic"
1896 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1897 (match_operand 1 "general_operand" "g"))
1898 (use (match_operand:SI 2 "register_operand" "Z"))
1899 (use (match_operand 3 "" ""))]
1900 "! SIBLING_CALL_P (insn)
1901 && GET_CODE (operands[0]) == SYMBOL_REF
1902 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1903 "call %0;"
1904 [(set_attr "type" "call")
1905 (set_attr "length" "4")])
1907 (define_insn "*sibcall_symbol_fdpic"
1908 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1909 (match_operand 1 "general_operand" "g"))
1910 (use (match_operand:SI 2 "register_operand" "Z"))
1911 (use (match_operand 3 "" ""))
1912 (return)]
1913 "SIBLING_CALL_P (insn)
1914 && GET_CODE (operands[0]) == SYMBOL_REF
1915 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1916 "jump.l %0;"
1917 [(set_attr "type" "br")
1918 (set_attr "length" "4")])
1920 (define_insn "*call_value_symbol_fdpic"
1921 [(set (match_operand 0 "register_operand" "=d")
1922 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1923 (match_operand 2 "general_operand" "g")))
1924 (use (match_operand:SI 3 "register_operand" "Z"))
1925 (use (match_operand 4 "" ""))]
1926 "! SIBLING_CALL_P (insn)
1927 && GET_CODE (operands[1]) == SYMBOL_REF
1928 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1929 "call %1;"
1930 [(set_attr "type" "call")
1931 (set_attr "length" "4")])
1933 (define_insn "*sibcall_value_symbol_fdpic"
1934 [(set (match_operand 0 "register_operand" "=d")
1935 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1936 (match_operand 2 "general_operand" "g")))
1937 (use (match_operand:SI 3 "register_operand" "Z"))
1938 (use (match_operand 4 "" ""))
1939 (return)]
1940 "SIBLING_CALL_P (insn)
1941 && GET_CODE (operands[1]) == SYMBOL_REF
1942 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1943 "jump.l %1;"
1944 [(set_attr "type" "br")
1945 (set_attr "length" "4")])
1947 (define_insn "*call_insn_fdpic"
1948 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1949 (match_operand 1 "general_operand" "g"))
1950 (use (match_operand:SI 2 "register_operand" "Z"))
1951 (use (match_operand 3 "" ""))]
1952 "! SIBLING_CALL_P (insn)"
1953 "call (%0);"
1954 [(set_attr "type" "call")
1955 (set_attr "length" "2")])
1957 (define_insn "*sibcall_insn_fdpic"
1958 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1959 (match_operand 1 "general_operand" "g"))
1960 (use (match_operand:SI 2 "register_operand" "Z"))
1961 (use (match_operand 3 "" ""))
1962 (return)]
1963 "SIBLING_CALL_P (insn)"
1964 "jump (%0);"
1965 [(set_attr "type" "br")
1966 (set_attr "length" "2")])
1968 (define_insn "*call_value_insn_fdpic"
1969 [(set (match_operand 0 "register_operand" "=d")
1970 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1971 (match_operand 2 "general_operand" "g")))
1972 (use (match_operand:SI 3 "register_operand" "Z"))
1973 (use (match_operand 4 "" ""))]
1974 "! SIBLING_CALL_P (insn)"
1975 "call (%1);"
1976 [(set_attr "type" "call")
1977 (set_attr "length" "2")])
1979 (define_insn "*sibcall_value_insn_fdpic"
1980 [(set (match_operand 0 "register_operand" "=d")
1981 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1982 (match_operand 2 "general_operand" "g")))
1983 (use (match_operand:SI 3 "register_operand" "Z"))
1984 (use (match_operand 4 "" ""))
1985 (return)]
1986 "SIBLING_CALL_P (insn)"
1987 "jump (%1);"
1988 [(set_attr "type" "br")
1989 (set_attr "length" "2")])
1991 (define_insn "*call_symbol"
1992 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1993 (match_operand 1 "general_operand" "g"))
1994 (use (match_operand 2 "" ""))]
1995 "! SIBLING_CALL_P (insn)
1996 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1997 && GET_CODE (operands[0]) == SYMBOL_REF
1998 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1999 "call %0;"
2000 [(set_attr "type" "call")
2001 (set_attr "length" "4")])
2003 (define_insn "*sibcall_symbol"
2004 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2005 (match_operand 1 "general_operand" "g"))
2006 (use (match_operand 2 "" ""))
2007 (return)]
2008 "SIBLING_CALL_P (insn)
2009 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2010 && GET_CODE (operands[0]) == SYMBOL_REF
2011 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
2012 "jump.l %0;"
2013 [(set_attr "type" "br")
2014 (set_attr "length" "4")])
2016 (define_insn "*call_value_symbol"
2017 [(set (match_operand 0 "register_operand" "=d")
2018 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2019 (match_operand 2 "general_operand" "g")))
2020 (use (match_operand 3 "" ""))]
2021 "! SIBLING_CALL_P (insn)
2022 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2023 && GET_CODE (operands[1]) == SYMBOL_REF
2024 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2025 "call %1;"
2026 [(set_attr "type" "call")
2027 (set_attr "length" "4")])
2029 (define_insn "*sibcall_value_symbol"
2030 [(set (match_operand 0 "register_operand" "=d")
2031 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2032 (match_operand 2 "general_operand" "g")))
2033 (use (match_operand 3 "" ""))
2034 (return)]
2035 "SIBLING_CALL_P (insn)
2036 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2037 && GET_CODE (operands[1]) == SYMBOL_REF
2038 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2039 "jump.l %1;"
2040 [(set_attr "type" "br")
2041 (set_attr "length" "4")])
2043 (define_insn "*call_insn"
2044 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
2045 (match_operand 1 "general_operand" "g"))
2046 (use (match_operand 2 "" ""))]
2047 "! SIBLING_CALL_P (insn)"
2048 "call (%0);"
2049 [(set_attr "type" "call")
2050 (set_attr "length" "2")])
2052 (define_insn "*sibcall_insn"
2053 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
2054 (match_operand 1 "general_operand" "g"))
2055 (use (match_operand 2 "" ""))
2056 (return)]
2057 "SIBLING_CALL_P (insn)"
2058 "jump (%0);"
2059 [(set_attr "type" "br")
2060 (set_attr "length" "2")])
2062 (define_insn "*call_value_insn"
2063 [(set (match_operand 0 "register_operand" "=d")
2064 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
2065 (match_operand 2 "general_operand" "g")))
2066 (use (match_operand 3 "" ""))]
2067 "! SIBLING_CALL_P (insn)"
2068 "call (%1);"
2069 [(set_attr "type" "call")
2070 (set_attr "length" "2")])
2072 (define_insn "*sibcall_value_insn"
2073 [(set (match_operand 0 "register_operand" "=d")
2074 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
2075 (match_operand 2 "general_operand" "g")))
2076 (use (match_operand 3 "" ""))
2077 (return)]
2078 "SIBLING_CALL_P (insn)"
2079 "jump (%1);"
2080 [(set_attr "type" "br")
2081 (set_attr "length" "2")])
2083 ;; Block move patterns
2085 ;; We cheat. This copies one more word than operand 2 indicates.
2087 (define_insn "rep_movsi"
2088 [(set (match_operand:SI 0 "register_operand" "=&a")
2089 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2090 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2091 (const_int 2)))
2092 (const_int 4)))
2093 (set (match_operand:SI 1 "register_operand" "=&b")
2094 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2095 (ashift:SI (match_dup 2) (const_int 2)))
2096 (const_int 4)))
2097 (set (mem:BLK (match_dup 3))
2098 (mem:BLK (match_dup 4)))
2099 (use (match_dup 2))
2100 (clobber (match_scratch:HI 5 "=&d"))
2101 (clobber (reg:SI REG_LT1))
2102 (clobber (reg:SI REG_LC1))
2103 (clobber (reg:SI REG_LB1))]
2104 ""
2105 "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
2106 [(set_attr "type" "misc")
2107 (set_attr "length" "16")
2108 (set_attr "seq_insns" "multi")])
2110 (define_insn "rep_movhi"
2111 [(set (match_operand:SI 0 "register_operand" "=&a")
2112 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2113 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2114 (const_int 1)))
2115 (const_int 2)))
2116 (set (match_operand:SI 1 "register_operand" "=&b")
2117 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2118 (ashift:SI (match_dup 2) (const_int 1)))
2119 (const_int 2)))
2120 (set (mem:BLK (match_dup 3))
2121 (mem:BLK (match_dup 4)))
2122 (use (match_dup 2))
2123 (clobber (match_scratch:HI 5 "=&d"))
2124 (clobber (reg:SI REG_LT1))
2125 (clobber (reg:SI REG_LC1))
2126 (clobber (reg:SI REG_LB1))]
2127 ""
2128 "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
2129 [(set_attr "type" "misc")
2130 (set_attr "length" "16")
2131 (set_attr "seq_insns" "multi")])
2133 (define_expand "movmemsi"
2134 [(match_operand:BLK 0 "general_operand" "")
2135 (match_operand:BLK 1 "general_operand" "")
2136 (match_operand:SI 2 "const_int_operand" "")
2137 (match_operand:SI 3 "const_int_operand" "")]
2138 ""
2139 {
2140 if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
2141 DONE;
2142 FAIL;
2143 })
2145 ;; Conditional branch patterns
2146 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
2148 ;; The only outcome of this pattern is that global variables
2149 ;; bfin_compare_op[01] are set for use in bcond patterns.
2151 (define_expand "cmpbi"
2152 [(set (cc0) (compare (match_operand:BI 0 "register_operand" "")
2153 (match_operand:BI 1 "immediate_operand" "")))]
2154 ""
2155 {
2156 bfin_compare_op0 = operands[0];
2157 bfin_compare_op1 = operands[1];
2158 DONE;
2159 })
2161 (define_expand "cmpsi"
2162 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2163 (match_operand:SI 1 "reg_or_const_int_operand" "")))]
2164 ""
2165 {
2166 bfin_compare_op0 = operands[0];
2167 bfin_compare_op1 = operands[1];
2168 DONE;
2169 })
2171 (define_insn "compare_eq"
2172 [(set (match_operand:BI 0 "register_operand" "=C,C")
2173 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
2174 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2175 ""
2176 "cc =%1==%2;"
2177 [(set_attr "type" "compare")])
2179 (define_insn "compare_ne"
2180 [(set (match_operand:BI 0 "register_operand" "=C,C")
2181 (ne:BI (match_operand:SI 1 "register_operand" "d,a")
2182 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2183 "0"
2184 "cc =%1!=%2;"
2185 [(set_attr "type" "compare")])
2187 (define_insn "compare_lt"
2188 [(set (match_operand:BI 0 "register_operand" "=C,C")
2189 (lt:BI (match_operand:SI 1 "register_operand" "d,a")
2190 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2191 ""
2192 "cc =%1<%2;"
2193 [(set_attr "type" "compare")])
2195 (define_insn "compare_le"
2196 [(set (match_operand:BI 0 "register_operand" "=C,C")
2197 (le:BI (match_operand:SI 1 "register_operand" "d,a")
2198 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2199 ""
2200 "cc =%1<=%2;"
2201 [(set_attr "type" "compare")])
2203 (define_insn "compare_leu"
2204 [(set (match_operand:BI 0 "register_operand" "=C,C")
2205 (leu:BI (match_operand:SI 1 "register_operand" "d,a")
2206 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2207 ""
2208 "cc =%1<=%2 (iu);"
2209 [(set_attr "type" "compare")])
2211 (define_insn "compare_ltu"
2212 [(set (match_operand:BI 0 "register_operand" "=C,C")
2213 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
2214 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2215 ""
2216 "cc =%1<%2 (iu);"
2217 [(set_attr "type" "compare")])
2219 (define_expand "beq"
2220 [(set (match_dup 1) (match_dup 2))
2221 (set (pc)
2222 (if_then_else (match_dup 3)
2223 (label_ref (match_operand 0 "" ""))
2224 (pc)))]
2225 ""
2226 {
2227 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2228 operands[1] = bfin_cc_rtx; /* hard register: CC */
2229 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2230 /* If we have a BImode input, then we already have a compare result, and
2231 do not need to emit another comparison. */
2232 if (GET_MODE (bfin_compare_op0) == BImode)
2233 {
2234 gcc_assert (bfin_compare_op1 == const0_rtx);
2235 emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0]));
2236 DONE;
2237 }
2239 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2240 })
2242 (define_expand "bne"
2243 [(set (match_dup 1) (match_dup 2))
2244 (set (pc)
2245 (if_then_else (match_dup 3)
2246 (label_ref (match_operand 0 "" ""))
2247 (pc)))]
2248 ""
2249 {
2250 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2251 /* If we have a BImode input, then we already have a compare result, and
2252 do not need to emit another comparison. */
2253 if (GET_MODE (bfin_compare_op0) == BImode)
2254 {
2255 rtx cmp = gen_rtx_NE (BImode, op0, op1);
2257 gcc_assert (bfin_compare_op1 == const0_rtx);
2258 emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
2259 DONE;
2260 }
2262 operands[1] = bfin_cc_rtx; /* hard register: CC */
2263 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2264 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2265 })
2267 (define_expand "bgt"
2268 [(set (match_dup 1) (match_dup 2))
2269 (set (pc)
2270 (if_then_else (match_dup 3)
2271 (label_ref (match_operand 0 "" ""))
2272 (pc)))]
2273 ""
2274 {
2275 operands[1] = bfin_cc_rtx;
2276 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2277 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2278 })
2280 (define_expand "bgtu"
2281 [(set (match_dup 1) (match_dup 2))
2282 (set (pc)
2283 (if_then_else (match_dup 3)
2284 (label_ref (match_operand 0 "" ""))
2285 (pc)))]
2286 ""
2287 {
2288 operands[1] = bfin_cc_rtx;
2289 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2290 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2291 })
2293 (define_expand "blt"
2294 [(set (match_dup 1) (match_dup 2))
2295 (set (pc)
2296 (if_then_else (match_dup 3)
2297 (label_ref (match_operand 0 "" ""))
2298 (pc)))]
2299 ""
2300 {
2301 operands[1] = bfin_cc_rtx;
2302 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2303 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2304 })
2306 (define_expand "bltu"
2307 [(set (match_dup 1) (match_dup 2))
2308 (set (pc)
2309 (if_then_else (match_dup 3)
2310 (label_ref (match_operand 0 "" ""))
2311 (pc)))]
2312 ""
2313 {
2314 operands[1] = bfin_cc_rtx;
2315 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2316 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2317 })
2320 (define_expand "bge"
2321 [(set (match_dup 1) (match_dup 2))
2322 (set (pc)
2323 (if_then_else (match_dup 3)
2324 (label_ref (match_operand 0 "" ""))
2325 (pc)))]
2326 ""
2327 {
2328 operands[1] = bfin_cc_rtx;
2329 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2330 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2331 })
2333 (define_expand "bgeu"
2334 [(set (match_dup 1) (match_dup 2))
2335 (set (pc)
2336 (if_then_else (match_dup 3)
2337 (label_ref (match_operand 0 "" ""))
2338 (pc)))]
2339 ""
2340 {
2341 operands[1] = bfin_cc_rtx;
2342 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2343 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2344 })
2346 (define_expand "ble"
2347 [(set (match_dup 1) (match_dup 2))
2348 (set (pc)
2349 (if_then_else (match_dup 3)
2350 (label_ref (match_operand 0 "" ""))
2351 (pc)))]
2352 ""
2353 {
2354 operands[1] = bfin_cc_rtx;
2355 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2356 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2357 })
2359 (define_expand "bleu"
2360 [(set (match_dup 1) (match_dup 2))
2361 (set (pc)
2362 (if_then_else (match_dup 3)
2363 (label_ref (match_operand 0 "" ""))
2364 (pc)))
2365 ]
2366 ""
2367 {
2368 operands[1] = bfin_cc_rtx;
2369 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2370 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2371 })
2373 (define_insn "cbranchbi4"
2374 [(set (pc)
2375 (if_then_else
2376 (match_operator 0 "bfin_cbranch_operator"
2377 [(match_operand:BI 1 "register_operand" "C")
2378 (match_operand:BI 2 "immediate_operand" "P0")])
2379 (label_ref (match_operand 3 "" ""))
2380 (pc)))]
2381 ""
2382 {
2383 asm_conditional_branch (insn, operands, 0, 0);
2384 return "";
2385 }
2386 [(set_attr "type" "brcc")])
2388 ;; Special cbranch patterns to deal with the speculative load problem - see
2389 ;; bfin_reorg for details.
2391 (define_insn "cbranch_predicted_taken"
2392 [(set (pc)
2393 (if_then_else
2394 (match_operator 0 "bfin_cbranch_operator"
2395 [(match_operand:BI 1 "register_operand" "C")
2396 (match_operand:BI 2 "immediate_operand" "P0")])
2397 (label_ref (match_operand 3 "" ""))
2398 (pc)))
2399 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2400 ""
2401 {
2402 asm_conditional_branch (insn, operands, 0, 1);
2403 return "";
2404 }
2405 [(set_attr "type" "brcc")])
2407 (define_insn "cbranch_with_nops"
2408 [(set (pc)
2409 (if_then_else
2410 (match_operator 0 "bfin_cbranch_operator"
2411 [(match_operand:BI 1 "register_operand" "C")
2412 (match_operand:BI 2 "immediate_operand" "P0")])
2413 (label_ref (match_operand 3 "" ""))
2414 (pc)))
2415 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2416 "reload_completed"
2417 {
2418 asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
2419 return "";
2420 }
2421 [(set_attr "type" "brcc")
2422 (set_attr "length" "6")])
2424 ;; setcc insns. */
2425 (define_expand "seq"
2426 [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3)))
2427 (set (match_operand:SI 0 "register_operand" "")
2428 (ne:SI (match_dup 1) (const_int 0)))]
2429 ""
2430 {
2431 operands[2] = bfin_compare_op0;
2432 operands[3] = bfin_compare_op1;
2433 operands[1] = bfin_cc_rtx;
2434 })
2436 (define_expand "slt"
2437 [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3)))
2438 (set (match_operand:SI 0 "register_operand" "")
2439 (ne:SI (match_dup 1) (const_int 0)))]
2440 ""
2441 {
2442 operands[2] = bfin_compare_op0;
2443 operands[3] = bfin_compare_op1;
2444 operands[1] = bfin_cc_rtx;
2445 })
2447 (define_expand "sle"
2448 [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3)))
2449 (set (match_operand:SI 0 "register_operand" "")
2450 (ne:SI (match_dup 1) (const_int 0)))]
2451 ""
2452 {
2453 operands[2] = bfin_compare_op0;
2454 operands[3] = bfin_compare_op1;
2455 operands[1] = bfin_cc_rtx;
2456 })
2458 (define_expand "sltu"
2459 [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3)))
2460 (set (match_operand:SI 0 "register_operand" "")
2461 (ne:SI (match_dup 1) (const_int 0)))]
2462 ""
2463 {
2464 operands[2] = bfin_compare_op0;
2465 operands[3] = bfin_compare_op1;
2466 operands[1] = bfin_cc_rtx;
2467 })
2469 (define_expand "sleu"
2470 [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
2471 (set (match_operand:SI 0 "register_operand" "")
2472 (ne:SI (match_dup 1) (const_int 0)))]
2473 ""
2474 {
2475 operands[2] = bfin_compare_op0;
2476 operands[3] = bfin_compare_op1;
2477 operands[1] = bfin_cc_rtx;
2478 })
2480 (define_insn "nop"
2481 [(const_int 0)]
2482 ""
2483 "nop;")
2485 (define_insn "mnop"
2486 [(unspec [(const_int 0)] UNSPEC_32BIT)]
2487 ""
2488 "mnop%!"
2489 [(set_attr "type" "dsp32")])
2491 ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
2492 (define_insn "movsibi"
2493 [(set (match_operand:BI 0 "register_operand" "=C")
2494 (ne:BI (match_operand:SI 1 "register_operand" "d")
2495 (const_int 0)))]
2496 ""
2497 "CC = %1;"
2498 [(set_attr "length" "2")])
2500 (define_insn "movbisi"
2501 [(set (match_operand:SI 0 "register_operand" "=d")
2502 (ne:SI (match_operand:BI 1 "register_operand" "C")
2503 (const_int 0)))]
2504 ""
2505 "%0 = CC;"
2506 [(set_attr "length" "2")])
2508 (define_insn ""
2509 [(set (match_operand:BI 0 "register_operand" "=C")
2510 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2511 (const_int 0)))]
2512 ""
2513 "%0 = ! %0;" /* NOT CC;" */
2514 [(set_attr "type" "compare")])
2516 ;; Vector and DSP insns
2518 (define_insn ""
2519 [(set (match_operand:SI 0 "register_operand" "=d")
2520 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2521 (const_int 24))
2522 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2523 (const_int 8))))]
2524 ""
2525 "%0 = ALIGN8(%1, %2)%!"
2526 [(set_attr "type" "dsp32")])
2528 (define_insn ""
2529 [(set (match_operand:SI 0 "register_operand" "=d")
2530 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2531 (const_int 16))
2532 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2533 (const_int 16))))]
2534 ""
2535 "%0 = ALIGN16(%1, %2)%!"
2536 [(set_attr "type" "dsp32")])
2538 (define_insn ""
2539 [(set (match_operand:SI 0 "register_operand" "=d")
2540 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2541 (const_int 8))
2542 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2543 (const_int 24))))]
2544 ""
2545 "%0 = ALIGN24(%1, %2)%!"
2546 [(set_attr "type" "dsp32")])
2548 ;; Prologue and epilogue.
2550 (define_expand "prologue"
2551 [(const_int 1)]
2552 ""
2553 "bfin_expand_prologue (); DONE;")
2555 (define_expand "epilogue"
2556 [(const_int 1)]
2557 ""
2558 "bfin_expand_epilogue (1, 0); DONE;")
2560 (define_expand "sibcall_epilogue"
2561 [(const_int 1)]
2562 ""
2563 "bfin_expand_epilogue (0, 0); DONE;")
2565 (define_expand "eh_return"
2566 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")]
2567 UNSPEC_VOLATILE_EH_RETURN)]
2568 ""
2569 {
2570 emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]);
2571 emit_jump_insn (gen_eh_return_internal ());
2572 emit_barrier ();
2573 DONE;
2574 })
2576 (define_insn_and_split "eh_return_internal"
2577 [(set (pc)
2578 (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))]
2579 ""
2580 "#"
2581 "reload_completed"
2582 [(const_int 1)]
2583 "bfin_expand_epilogue (1, 1); DONE;")
2585 (define_insn "link"
2586 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2587 (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
2588 (set (reg:SI REG_FP)
2589 (plus:SI (reg:SI REG_SP) (const_int -8)))
2590 (set (reg:SI REG_SP)
2591 (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
2592 ""
2593 "LINK %Z0;"
2594 [(set_attr "length" "4")])
2596 (define_insn "unlink"
2597 [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
2598 (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
2599 (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
2600 ""
2601 "UNLINK;"
2602 [(set_attr "length" "4")])
2604 ;; This pattern is slightly clumsy. The stack adjust must be the final SET in
2605 ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
2606 ;; where on the stack, since it goes through all elements of the parallel in
2607 ;; sequence.
2608 (define_insn "push_multiple"
2609 [(match_parallel 0 "push_multiple_operation"
2610 [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
2611 ""
2612 {
2613 output_push_multiple (insn, operands);
2614 return "";
2615 })
2617 (define_insn "pop_multiple"
2618 [(match_parallel 0 "pop_multiple_operation"
2619 [(set (reg:SI REG_SP)
2620 (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
2621 ""
2622 {
2623 output_pop_multiple (insn, operands);
2624 return "";
2625 })
2627 (define_insn "return_internal"
2628 [(return)
2629 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)]
2630 "reload_completed"
2631 {
2632 switch (INTVAL (operands[0]))
2633 {
2634 case EXCPT_HANDLER:
2635 return "rtx;";
2636 case NMI_HANDLER:
2637 return "rtn;";
2638 case INTERRUPT_HANDLER:
2639 return "rti;";
2640 case SUBROUTINE:
2641 return "rts;";
2642 }
2643 gcc_unreachable ();
2644 })
2646 (define_insn "csync"
2647 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2648 ""
2649 "csync;"
2650 [(set_attr "type" "sync")])
2652 (define_insn "ssync"
2653 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
2654 ""
2655 "ssync;"
2656 [(set_attr "type" "sync")])
2658 (define_insn "trap"
2659 [(trap_if (const_int 1) (const_int 3))]
2660 ""
2661 "excpt 3;"
2662 [(set_attr "type" "misc")
2663 (set_attr "length" "2")])
2665 (define_insn "trapifcc"
2666 [(trap_if (reg:BI REG_CC) (const_int 3))]
2667 ""
2668 "if !cc jump 4 (bp); excpt 3;"
2669 [(set_attr "type" "misc")
2670 (set_attr "length" "4")
2671 (set_attr "seq_insns" "multi")])
2673 ;;; Vector instructions
2675 ;; First, all sorts of move variants
2677 (define_insn "movhi_low2high"
2678 [(set (match_operand:V2HI 0 "register_operand" "=d")
2679 (vec_concat:V2HI
2680 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2681 (parallel [(const_int 0)]))
2682 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2683 (parallel [(const_int 0)]))))]
2684 ""
2685 "%d0 = %h2 << 0%!"
2686 [(set_attr "type" "dsp32")])
2688 (define_insn "movhi_high2high"
2689 [(set (match_operand:V2HI 0 "register_operand" "=d")
2690 (vec_concat:V2HI
2691 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2692 (parallel [(const_int 0)]))
2693 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2694 (parallel [(const_int 1)]))))]
2695 ""
2696 "%d0 = %d2 << 0%!"
2697 [(set_attr "type" "dsp32")])
2699 (define_insn "movhi_low2low"
2700 [(set (match_operand:V2HI 0 "register_operand" "=d")
2701 (vec_concat:V2HI
2702 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2703 (parallel [(const_int 0)]))
2704 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2705 (parallel [(const_int 1)]))))]
2706 ""
2707 "%h0 = %h2 << 0%!"
2708 [(set_attr "type" "dsp32")])
2710 (define_insn "movhi_high2low"
2711 [(set (match_operand:V2HI 0 "register_operand" "=d")
2712 (vec_concat:V2HI
2713 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2714 (parallel [(const_int 1)]))
2715 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2716 (parallel [(const_int 1)]))))]
2717 ""
2718 "%h0 = %d2 << 0%!"
2719 [(set_attr "type" "dsp32")])
2721 (define_insn "movhiv2hi_low"
2722 [(set (match_operand:V2HI 0 "register_operand" "=d")
2723 (vec_concat:V2HI
2724 (match_operand:HI 2 "register_operand" "d")
2725 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2726 (parallel [(const_int 1)]))))]
2727 ""
2728 "%h0 = %h2 << 0%!"
2729 [(set_attr "type" "dsp32")])
2731 (define_insn "movhiv2hi_high"
2732 [(set (match_operand:V2HI 0 "register_operand" "=d")
2733 (vec_concat:V2HI
2734 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2735 (parallel [(const_int 0)]))
2736 (match_operand:HI 2 "register_operand" "d")))]
2737 ""
2738 "%d0 = %h2 << 0%!"
2739 [(set_attr "type" "dsp32")])
2741 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2742 ;; The order of operands is intentional to match the VDSP builtin (high word
2743 ;; is passed first).
2744 (define_insn_and_split "composev2hi"
2745 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
2746 (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
2747 (match_operand:HI 1 "register_operand" "d,d")))]
2748 ""
2749 "@
2750 %d0 = %h2 << 0%!
2751 #"
2752 "reload_completed"
2753 [(set (match_dup 0)
2754 (vec_concat:V2HI
2755 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
2756 (match_dup 2)))
2757 (set (match_dup 0)
2758 (vec_concat:V2HI
2759 (match_dup 1)
2760 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2761 ""
2762 [(set_attr "type" "dsp32")])
2764 ; Like composev2hi, but operating on elements of V2HI vectors.
2765 ; Useful on its own, and as a combiner bridge for the multiply and
2766 ; mac patterns.
2767 (define_insn "packv2hi"
2768 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d")
2769 (vec_concat:V2HI (vec_select:HI
2770 (match_operand:V2HI 1 "register_operand" "d,d,d,d")
2771 (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")]))
2772 (vec_select:HI
2773 (match_operand:V2HI 2 "register_operand" "d,d,d,d")
2774 (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))]
2775 ""
2776 "@
2777 %0 = PACK (%h2,%h1)%!
2778 %0 = PACK (%h2,%d1)%!
2779 %0 = PACK (%d2,%h1)%!
2780 %0 = PACK (%d2,%d1)%!"
2781 [(set_attr "type" "dsp32")])
2783 (define_insn "movv2hi_hi"
2784 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2785 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2786 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2787 ""
2788 "@
2789 /* optimized out */
2790 %h0 = %h1 << 0%!
2791 %h0 = %d1 << 0%!"
2792 [(set_attr "type" "dsp32")])
2794 (define_expand "movv2hi_hi_low"
2795 [(set (match_operand:HI 0 "register_operand" "")
2796 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2797 (parallel [(const_int 0)])))]
2798 ""
2799 "")
2801 (define_expand "movv2hi_hi_high"
2802 [(set (match_operand:HI 0 "register_operand" "")
2803 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2804 (parallel [(const_int 1)])))]
2805 ""
2806 "")
2808 ;; Unusual arithmetic operations on 16-bit registers.
2810 (define_insn "ssaddhi3"
2811 [(set (match_operand:HI 0 "register_operand" "=d")
2812 (ss_plus:HI (match_operand:HI 1 "register_operand" "d")
2813 (match_operand:HI 2 "register_operand" "d")))]
2814 ""
2815 "%h0 = %h1 + %h2 (S)%!"
2816 [(set_attr "type" "dsp32")])
2818 (define_insn "sssubhi3"
2819 [(set (match_operand:HI 0 "register_operand" "=d")
2820 (ss_minus:HI (match_operand:HI 1 "register_operand" "d")
2821 (match_operand:HI 2 "register_operand" "d")))]
2822 ""
2823 "%h0 = %h1 - %h2 (S)%!"
2824 [(set_attr "type" "dsp32")])
2826 ;; V2HI vector insns
2828 (define_insn "addv2hi3"
2829 [(set (match_operand:V2HI 0 "register_operand" "=d")
2830 (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2831 (match_operand:V2HI 2 "register_operand" "d")))]
2832 ""
2833 "%0 = %1 +|+ %2%!"
2834 [(set_attr "type" "dsp32")])
2836 (define_insn "ssaddv2hi3"
2837 [(set (match_operand:V2HI 0 "register_operand" "=d")
2838 (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2839 (match_operand:V2HI 2 "register_operand" "d")))]
2840 ""
2841 "%0 = %1 +|+ %2 (S)%!"
2842 [(set_attr "type" "dsp32")])
2844 (define_insn "subv2hi3"
2845 [(set (match_operand:V2HI 0 "register_operand" "=d")
2846 (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2847 (match_operand:V2HI 2 "register_operand" "d")))]
2848 ""
2849 "%0 = %1 -|- %2%!"
2850 [(set_attr "type" "dsp32")])
2852 (define_insn "sssubv2hi3"
2853 [(set (match_operand:V2HI 0 "register_operand" "=d")
2854 (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2855 (match_operand:V2HI 2 "register_operand" "d")))]
2856 ""
2857 "%0 = %1 -|- %2 (S)%!"
2858 [(set_attr "type" "dsp32")])
2860 (define_insn "addsubv2hi3"
2861 [(set (match_operand:V2HI 0 "register_operand" "=d")
2862 (vec_concat:V2HI
2863 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2864 (parallel [(const_int 0)]))
2865 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2866 (parallel [(const_int 0)])))
2867 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2868 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2869 ""
2870 "%0 = %1 +|- %2%!"
2871 [(set_attr "type" "dsp32")])
2873 (define_insn "subaddv2hi3"
2874 [(set (match_operand:V2HI 0 "register_operand" "=d")
2875 (vec_concat:V2HI
2876 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2877 (parallel [(const_int 0)]))
2878 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2879 (parallel [(const_int 0)])))
2880 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2881 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2882 ""
2883 "%0 = %1 -|+ %2%!"
2884 [(set_attr "type" "dsp32")])
2886 (define_insn "ssaddsubv2hi3"
2887 [(set (match_operand:V2HI 0 "register_operand" "=d")
2888 (vec_concat:V2HI
2889 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2890 (parallel [(const_int 0)]))
2891 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2892 (parallel [(const_int 0)])))
2893 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2894 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2895 ""
2896 "%0 = %1 +|- %2 (S)%!"
2897 [(set_attr "type" "dsp32")])
2899 (define_insn "sssubaddv2hi3"
2900 [(set (match_operand:V2HI 0 "register_operand" "=d")
2901 (vec_concat:V2HI
2902 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2903 (parallel [(const_int 0)]))
2904 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2905 (parallel [(const_int 0)])))
2906 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2907 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2908 ""
2909 "%0 = %1 -|+ %2 (S)%!"
2910 [(set_attr "type" "dsp32")])
2912 (define_insn "sublohiv2hi3"
2913 [(set (match_operand:HI 0 "register_operand" "=d")
2914 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2915 (parallel [(const_int 1)]))
2916 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2917 (parallel [(const_int 0)]))))]
2918 ""
2919 "%h0 = %d1 - %h2%!"
2920 [(set_attr "type" "dsp32")])
2922 (define_insn "subhilov2hi3"
2923 [(set (match_operand:HI 0 "register_operand" "=d")
2924 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2925 (parallel [(const_int 0)]))
2926 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2927 (parallel [(const_int 1)]))))]
2928 ""
2929 "%h0 = %h1 - %d2%!"
2930 [(set_attr "type" "dsp32")])
2932 (define_insn "sssublohiv2hi3"
2933 [(set (match_operand:HI 0 "register_operand" "=d")
2934 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2935 (parallel [(const_int 1)]))
2936 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2937 (parallel [(const_int 0)]))))]
2938 ""
2939 "%h0 = %d1 - %h2 (S)%!"
2940 [(set_attr "type" "dsp32")])
2942 (define_insn "sssubhilov2hi3"
2943 [(set (match_operand:HI 0 "register_operand" "=d")
2944 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2945 (parallel [(const_int 0)]))
2946 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2947 (parallel [(const_int 1)]))))]
2948 ""
2949 "%h0 = %h1 - %d2 (S)%!"
2950 [(set_attr "type" "dsp32")])
2952 (define_insn "addlohiv2hi3"
2953 [(set (match_operand:HI 0 "register_operand" "=d")
2954 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2955 (parallel [(const_int 1)]))
2956 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2957 (parallel [(const_int 0)]))))]
2958 ""
2959 "%h0 = %d1 + %h2%!"
2960 [(set_attr "type" "dsp32")])
2962 (define_insn "addhilov2hi3"
2963 [(set (match_operand:HI 0 "register_operand" "=d")
2964 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2965 (parallel [(const_int 0)]))
2966 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2967 (parallel [(const_int 1)]))))]
2968 ""
2969 "%h0 = %h1 + %d2%!"
2970 [(set_attr "type" "dsp32")])
2972 (define_insn "ssaddlohiv2hi3"
2973 [(set (match_operand:HI 0 "register_operand" "=d")
2974 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2975 (parallel [(const_int 1)]))
2976 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2977 (parallel [(const_int 0)]))))]
2978 ""
2979 "%h0 = %d1 + %h2 (S)%!"
2980 [(set_attr "type" "dsp32")])
2982 (define_insn "ssaddhilov2hi3"
2983 [(set (match_operand:HI 0 "register_operand" "=d")
2984 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2985 (parallel [(const_int 0)]))
2986 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2987 (parallel [(const_int 1)]))))]
2988 ""
2989 "%h0 = %h1 + %d2 (S)%!"
2990 [(set_attr "type" "dsp32")])
2992 (define_insn "sminv2hi3"
2993 [(set (match_operand:V2HI 0 "register_operand" "=d")
2994 (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
2995 (match_operand:V2HI 2 "register_operand" "d")))]
2996 ""
2997 "%0 = MIN (%1, %2) (V)%!"
2998 [(set_attr "type" "dsp32")])
3000 (define_insn "smaxv2hi3"
3001 [(set (match_operand:V2HI 0 "register_operand" "=d")
3002 (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
3003 (match_operand:V2HI 2 "register_operand" "d")))]
3004 ""
3005 "%0 = MAX (%1, %2) (V)%!"
3006 [(set_attr "type" "dsp32")])
3008 ;; Multiplications.
3010 ;; The Blackfin allows a lot of different options, and we need many patterns to
3011 ;; cover most of the hardware's abilities.
3012 ;; There are a few simple patterns using MULT rtx codes, but most of them use
3013 ;; an unspec with a const_int operand that determines which flag to use in the
3014 ;; instruction.
3015 ;; There are variants for single and parallel multiplications.
3016 ;; There are variants which just use 16-bit lowparts as inputs, and variants
3017 ;; which allow the user to choose just which halves to use as input values.
3018 ;; There are variants which set D registers, variants which set accumulators,
3019 ;; variants which set both, some of them optionally using the accumulators as
3020 ;; inputs for multiply-accumulate operations.
3022 (define_insn "flag_mulhi"
3023 [(set (match_operand:HI 0 "register_operand" "=d")
3024 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
3025 (match_operand:HI 2 "register_operand" "d")
3026 (match_operand 3 "const_int_operand" "n")]
3027 UNSPEC_MUL_WITH_FLAG))]
3028 ""
3029 "%h0 = %h1 * %h2 %M3%!"
3030 [(set_attr "type" "dsp32")])
3032 (define_insn "flag_mulhisi"
3033 [(set (match_operand:SI 0 "register_operand" "=d")
3034 (unspec:SI [(match_operand:HI 1 "register_operand" "d")
3035 (match_operand:HI 2 "register_operand" "d")
3036 (match_operand 3 "const_int_operand" "n")]
3037 UNSPEC_MUL_WITH_FLAG))]
3038 ""
3039 "%0 = %h1 * %h2 %M3%!"
3040 [(set_attr "type" "dsp32")])
3042 (define_insn "flag_mulhisi_parts"
3043 [(set (match_operand:SI 0 "register_operand" "=d")
3044 (unspec:SI [(vec_select:HI
3045 (match_operand:V2HI 1 "register_operand" "d")
3046 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3047 (vec_select:HI
3048 (match_operand:V2HI 2 "register_operand" "d")
3049 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
3050 (match_operand 5 "const_int_operand" "n")]
3051 UNSPEC_MUL_WITH_FLAG))]
3052 ""
3053 {
3054 const char *templates[] = {
3055 "%0 = %h1 * %h2 %M5%!",
3056 "%0 = %d1 * %h2 %M5%!",
3057 "%0 = %h1 * %d2 %M5%!",
3058 "%0 = %d1 * %d2 %M5%!" };
3059 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3060 return templates[alt];
3061 }
3062 [(set_attr "type" "dsp32")])
3064 ;; Three alternatives here to cover all possible allocations:
3065 ;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG
3066 ;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG
3067 ;; 2. mac flag is usable in any accumulator - use A1 and odd DREG
3068 ;; Other patterns which don't have a DREG destination can collapse cases
3069 ;; 1 and 2 into one.
3070 (define_insn "flag_machi"
3071 [(set (match_operand:HI 0 "register_operand" "=W,D,W")
3072 (unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d")
3073 (match_operand:HI 3 "register_operand" "d,d,d")
3074 (match_operand 4 "register_operand" "1,1,1")
3075 (match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")
3076 (match_operand 6 "const_int_operand" "PB,PA,PA")]
3077 UNSPEC_MAC_WITH_FLAG))
3078 (set (match_operand:PDI 1 "register_operand" "=B,A,B")
3079 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
3080 (match_dup 4) (match_dup 5)]
3081 UNSPEC_MAC_WITH_FLAG))]
3082 ""
3083 "%h0 = (%1 %b5 %h2 * %h3) %M6%!"
3084 [(set_attr "type" "dsp32")])
3086 (define_insn "flag_machi_acconly"
3087 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3088 (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
3089 (match_operand:HI 2 "register_operand" "d,d")
3090 (match_operand 3 "register_operand" "0,0")
3091 (match_operand 4 "const01_operand" "P0P1,P0P1")
3092 (match_operand 5 "const_int_operand" "PB,PA")]
3093 UNSPEC_MAC_WITH_FLAG))]
3094 ""
3095 "%0 %b4 %h1 * %h2 %M5%!"
3096 [(set_attr "type" "dsp32")])
3098 (define_insn "flag_machi_parts_acconly"
3099 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3100 (unspec:PDI [(vec_select:HI
3101 (match_operand:V2HI 1 "register_operand" "d,d")
3102 (parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")]))
3103 (vec_select:HI
3104 (match_operand:V2HI 2 "register_operand" "d,d")
3105 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")]))
3106 (match_operand:PDI 5 "register_operand" "0,0")
3107 (match_operand 6 "const01_operand" "P0P1,P0P1")
3108 (match_operand 7 "const_int_operand" "PB,PA")]
3109 UNSPEC_MAC_WITH_FLAG))]
3110 ""
3111 {
3112 const char *templates[] = {
3113 "%0 %b6 %h1 * %h2 %M7%!",
3114 "%0 %b6 %d1 * %h2 %M7%!",
3115 "%0 %b6 %h1 * %d2 %M7%!",
3116 "%0 %b6 %d1 * %d2 %M7%!"
3117 };
3118 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3119 return templates[alt];
3120 }
3121 [(set_attr "type" "dsp32")])
3123 (define_insn "flag_macinithi"
3124 [(set (match_operand:HI 0 "register_operand" "=W,D,W")
3125 (unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d")
3126 (match_operand:HI 2 "register_operand" "d,d,d")
3127 (match_operand 3 "const_int_operand" "PB,PA,PA")]
3128 UNSPEC_MAC_WITH_FLAG))
3129 (set (match_operand:PDI 4 "register_operand" "=B,A,B")
3130 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
3131 UNSPEC_MAC_WITH_FLAG))]
3132 ""
3133 "%h0 = (%4 = %h1 * %h2) %M3%!"
3134 [(set_attr "type" "dsp32")])
3136 (define_insn "flag_macinit1hi"
3137 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3138 (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
3139 (match_operand:HI 2 "register_operand" "d,d")
3140 (match_operand 3 "const_int_operand" "PB,PA")]
3141 UNSPEC_MAC_WITH_FLAG))]
3142 ""
3143 "%0 = %h1 * %h2 %M3%!"
3144 [(set_attr "type" "dsp32")])
3146 (define_insn "mulv2hi3"
3147 [(set (match_operand:V2HI 0 "register_operand" "=d")
3148 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
3149 (match_operand:V2HI 2 "register_operand" "d")))]
3150 ""
3151 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!"
3152 [(set_attr "type" "dsp32")])
3154 (define_insn "flag_mulv2hi"
3155 [(set (match_operand:V2HI 0 "register_operand" "=d")
3156 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
3157 (match_operand:V2HI 2 "register_operand" "d")
3158 (match_operand 3 "const_int_operand" "n")]
3159 UNSPEC_MUL_WITH_FLAG))]
3160 ""
3161 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!"
3162 [(set_attr "type" "dsp32")])
3164 (define_insn "flag_mulv2hi_parts"
3165 [(set (match_operand:V2HI 0 "register_operand" "=d")
3166 (unspec:V2HI [(vec_concat:V2HI
3167 (vec_select:HI
3168 (match_operand:V2HI 1 "register_operand" "d")
3169 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3170 (vec_select:HI
3171 (match_dup 1)
3172 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3173 (vec_concat:V2HI
3174 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3175 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3176 (vec_select:HI (match_dup 2)
3177 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3178 (match_operand 7 "const_int_operand" "n")]
3179 UNSPEC_MUL_WITH_FLAG))]
3180 ""
3181 {
3182 const char *templates[] = {
3183 "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!",
3184 "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!",
3185 "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!",
3186 "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!",
3187 "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!",
3188 "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!",
3189 "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!",
3190 "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!",
3191 "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!",
3192 "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!",
3193 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!",
3194 "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!",
3195 "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!",
3196 "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!",
3197 "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!",
3198 "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" };
3199 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3200 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3201 return templates[alt];
3202 }
3203 [(set_attr "type" "dsp32")])
3205 ;; A slightly complicated pattern.
3206 ;; Operand 0 is the halfword output; operand 11 is the accumulator output
3207 ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
3208 ;; parts of these 2x16 bit registers to use.
3209 ;; Operand 7 is the accumulator input.
3210 ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
3211 ;; Operand 10 is the macflag to be used.
3212 (define_insn "flag_macv2hi_parts"
3213 [(set (match_operand:V2HI 0 "register_operand" "=d")
3214 (unspec:V2HI [(vec_concat:V2HI
3215 (vec_select:HI
3216 (match_operand:V2HI 1 "register_operand" "d")
3217 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3218 (vec_select:HI
3219 (match_dup 1)
3220 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3221 (vec_concat:V2HI
3222 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3223 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3224 (vec_select:HI (match_dup 2)
3225 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3226 (match_operand:V2PDI 7 "register_operand" "e")
3227 (match_operand 8 "const01_operand" "P0P1")
3228 (match_operand 9 "const01_operand" "P0P1")
3229 (match_operand 10 "const_int_operand" "n")]
3230 UNSPEC_MAC_WITH_FLAG))
3231 (set (match_operand:V2PDI 11 "register_operand" "=e")
3232 (unspec:V2PDI [(vec_concat:V2HI
3233 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3234 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3235 (vec_concat:V2HI
3236 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3237 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3238 (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
3239 UNSPEC_MAC_WITH_FLAG))]
3240 ""
3241 {
3242 const char *templates[] = {
3243 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3244 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3245 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3246 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3247 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3248 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3249 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3250 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3251 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3252 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3253 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3254 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3255 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3256 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3257 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3258 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" };
3259 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3260 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3261 return templates[alt];
3262 }
3263 [(set_attr "type" "dsp32")])
3265 (define_insn "flag_macv2hi_parts_acconly"
3266 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3267 (unspec:V2PDI [(vec_concat:V2HI
3268 (vec_select:HI
3269 (match_operand:V2HI 1 "register_operand" "d")
3270 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3271 (vec_select:HI
3272 (match_dup 1)
3273 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3274 (vec_concat:V2HI
3275 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3276 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3277 (vec_select:HI (match_dup 2)
3278 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3279 (match_operand:V2PDI 7 "register_operand" "e")
3280 (match_operand 8 "const01_operand" "P0P1")
3281 (match_operand 9 "const01_operand" "P0P1")
3282 (match_operand 10 "const_int_operand" "n")]
3283 UNSPEC_MAC_WITH_FLAG))]
3284 ""
3285 {
3286 const char *templates[] = {
3287 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3288 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3289 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3290 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3291 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3292 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3293 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3294 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3295 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3296 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3297 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3298 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3299 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3300 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3301 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!",
3302 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" };
3303 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3304 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3305 return templates[alt];
3306 }
3307 [(set_attr "type" "dsp32")])
3309 ;; Same as above, but initializing the accumulators and therefore a couple fewer
3310 ;; necessary operands.
3311 (define_insn "flag_macinitv2hi_parts"
3312 [(set (match_operand:V2HI 0 "register_operand" "=d")
3313 (unspec:V2HI [(vec_concat:V2HI
3314 (vec_select:HI
3315 (match_operand:V2HI 1 "register_operand" "d")
3316 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3317 (vec_select:HI
3318 (match_dup 1)
3319 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3320 (vec_concat:V2HI
3321 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3322 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3323 (vec_select:HI (match_dup 2)
3324 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3325 (match_operand 7 "const_int_operand" "n")]
3326 UNSPEC_MAC_WITH_FLAG))
3327 (set (match_operand:V2PDI 8 "register_operand" "=e")
3328 (unspec:V2PDI [(vec_concat:V2HI
3329 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3330 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3331 (vec_concat:V2HI
3332 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3333 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3334 (match_dup 7)]
3335 UNSPEC_MAC_WITH_FLAG))]
3336 ""
3337 {
3338 const char *templates[] = {
3339 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3340 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3341 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3342 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3343 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3344 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3345 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3346 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3347 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3348 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3349 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3350 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3351 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3352 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3353 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!",
3354 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" };
3355 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3356 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3357 return templates[alt];
3358 }
3359 [(set_attr "type" "dsp32")])
3361 (define_insn "flag_macinit1v2hi_parts"
3362 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3363 (unspec:V2PDI [(vec_concat:V2HI
3364 (vec_select:HI
3365 (match_operand:V2HI 1 "register_operand" "d")
3366 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3367 (vec_select:HI
3368 (match_dup 1)
3369 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3370 (vec_concat:V2HI
3371 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3372 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3373 (vec_select:HI (match_dup 2)
3374 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3375 (match_operand 7 "const_int_operand" "n")]
3376 UNSPEC_MAC_WITH_FLAG))]
3377 ""
3378 {
3379 const char *templates[] = {
3380 "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!",
3381 "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!",
3382 "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!",
3383 "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!",
3384 "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!",
3385 "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!",
3386 "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!",
3387 "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!",
3388 "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!",
3389 "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!",
3390 "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!",
3391 "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!",
3392 "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!",
3393 "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!",
3394 "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!",
3395 "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" };
3396 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3397 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3398 return templates[alt];
3399 }
3400 [(set_attr "type" "dsp32")])
3402 ;; A mixture of multiply and multiply-accumulate for when we only want to
3403 ;; initialize one part.
3404 (define_insn "flag_mul_macv2hi_parts_acconly"
3405 [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
3406 (unspec:PDI [(vec_select:HI
3407 (match_operand:V2HI 2 "register_operand" "d,d,d")
3408 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
3409 (vec_select:HI
3410 (match_operand:V2HI 3 "register_operand" "d,d,d")
3411 (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
3412 (match_operand 10 "const_int_operand" "PB,PA,PA")]
3413 UNSPEC_MUL_WITH_FLAG))
3414 (set (match_operand:PDI 1 "register_operand" "=B,e,e")
3415 (unspec:PDI [(vec_select:HI
3416 (match_dup 2)
3417 (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
3418 (vec_select:HI
3419 (match_dup 3)
3420 (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
3421 (match_operand:PDI 8 "register_operand" "1,1,1")
3422 (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
3423 (match_operand 11 "const_int_operand" "PA,PB,PA")]
3424 UNSPEC_MAC_WITH_FLAG))]
3425 "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
3426 {
3427 rtx xops[6];
3428 const char *templates[] = {
3429 "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
3430 "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
3431 "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
3432 "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
3433 "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
3434 "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
3435 "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
3436 "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
3437 "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
3438 "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
3439 "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
3440 "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
3441 "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
3442 "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
3443 "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!",
3444 "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" };
3445 int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
3446 + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
3447 xops[0] = operands[0];
3448 xops[1] = operands[1];
3449 xops[2] = operands[2];
3450 xops[3] = operands[3];
3451 xops[4] = operands[9];
3452 xops[5] = which_alternative == 0 ? operands[10] : operands[11];
3453 output_asm_insn (templates[alt], xops);
3454 return "";
3455 }
3456 [(set_attr "type" "dsp32")])
3459 (define_code_macro s_or_u [sign_extend zero_extend])
3460 (define_code_attr su_optab [(sign_extend "mul")
3461 (zero_extend "umul")])
3462 (define_code_attr su_modifier [(sign_extend "IS")
3463 (zero_extend "FU")])
3465 (define_insn "<su_optab>hisi_ll"
3466 [(set (match_operand:SI 0 "register_operand" "=d")
3467 (mult:SI (s_or_u:SI
3468 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3469 (parallel [(const_int 0)])))
3470 (s_or_u:SI
3471 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3472 (parallel [(const_int 0)])))))]
3473 ""
3474 "%0 = %h1 * %h2 (<su_modifier>)%!"
3475 [(set_attr "type" "dsp32")])
3477 (define_insn "<su_optab>hisi_lh"
3478 [(set (match_operand:SI 0 "register_operand" "=d")
3479 (mult:SI (s_or_u:SI
3480 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3481 (parallel [(const_int 0)])))
3482 (s_or_u:SI
3483 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3484 (parallel [(const_int 1)])))))]
3485 ""
3486 "%0 = %h1 * %d2 (<su_modifier>)%!"
3487 [(set_attr "type" "dsp32")])
3489 (define_insn "<su_optab>hisi_hl"
3490 [(set (match_operand:SI 0 "register_operand" "=d")
3491 (mult:SI (s_or_u:SI
3492 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3493 (parallel [(const_int 1)])))
3494 (s_or_u:SI
3495 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3496 (parallel [(const_int 0)])))))]
3497 ""
3498 "%0 = %d1 * %h2 (<su_modifier>)%!"
3499 [(set_attr "type" "dsp32")])
3501 (define_insn "<su_optab>hisi_hh"
3502 [(set (match_operand:SI 0 "register_operand" "=d")
3503 (mult:SI (s_or_u:SI
3504 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3505 (parallel [(const_int 1)])))
3506 (s_or_u:SI
3507 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3508 (parallel [(const_int 1)])))))]
3509 ""
3510 "%0 = %d1 * %d2 (<su_modifier>)%!"
3511 [(set_attr "type" "dsp32")])
3513 ;; Additional variants for signed * unsigned multiply.
3515 (define_insn "usmulhisi_ull"
3516 [(set (match_operand:SI 0 "register_operand" "=W")
3517 (mult:SI (zero_extend:SI
3518 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3519 (parallel [(const_int 0)])))
3520 (sign_extend:SI
3521 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3522 (parallel [(const_int 0)])))))]
3523 ""
3524 "%0 = %h2 * %h1 (IS,M)%!"
3525 [(set_attr "type" "dsp32")])
3527 (define_insn "usmulhisi_ulh"
3528 [(set (match_operand:SI 0 "register_operand" "=W")
3529 (mult:SI (zero_extend:SI
3530 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3531 (parallel [(const_int 0)])))
3532 (sign_extend:SI
3533 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3534 (parallel [(const_int 1)])))))]
3535 ""
3536 "%0 = %d2 * %h1 (IS,M)%!"
3537 [(set_attr "type" "dsp32")])
3539 (define_insn "usmulhisi_uhl"
3540 [(set (match_operand:SI 0 "register_operand" "=W")
3541 (mult:SI (zero_extend:SI
3542 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3543 (parallel [(const_int 1)])))
3544 (sign_extend:SI
3545 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3546 (parallel [(const_int 0)])))))]
3547 ""
3548 "%0 = %h2 * %d1 (IS,M)%!"
3549 [(set_attr "type" "dsp32")])
3551 (define_insn "usmulhisi_uhh"
3552 [(set (match_operand:SI 0 "register_operand" "=W")
3553 (mult:SI (zero_extend:SI
3554 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3555 (parallel [(const_int 1)])))
3556 (sign_extend:SI
3557 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3558 (parallel [(const_int 1)])))))]
3559 ""
3560 "%0 = %d2 * %d1 (IS,M)%!"
3561 [(set_attr "type" "dsp32")])
3563 ;; Parallel versions of these operations. First, normal signed or unsigned
3564 ;; multiplies.
3566 (define_insn "<su_optab>hisi_ll_lh"
3567 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3568 (mult:SI (s_or_u:SI
3569 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3570 (parallel [(const_int 0)])))
3571 (s_or_u:SI
3572 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3573 (parallel [(const_int 0)])))))
3574 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3575 (mult:SI (s_or_u:SI
3576 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3577 (s_or_u:SI
3578 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3579 ""
3580 "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
3581 [(set_attr "type" "dsp32")])
3583 (define_insn "<su_optab>hisi_ll_hl"
3584 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3585 (mult:SI (s_or_u:SI
3586 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3587 (parallel [(const_int 0)])))
3588 (s_or_u:SI
3589 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3590 (parallel [(const_int 0)])))))
3591 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3592 (mult:SI (s_or_u:SI
3593 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3594 (s_or_u:SI
3595 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3596 ""
3597 "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
3598 [(set_attr "type" "dsp32")])
3600 (define_insn "<su_optab>hisi_ll_hh"
3601 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3602 (mult:SI (s_or_u:SI
3603 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3604 (parallel [(const_int 0)])))
3605 (s_or_u:SI
3606 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3607 (parallel [(const_int 0)])))))
3608 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3609 (mult:SI (s_or_u:SI
3610 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3611 (s_or_u:SI
3612 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3613 ""
3614 "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3615 [(set_attr "type" "dsp32")])
3617 (define_insn "<su_optab>hisi_lh_hl"
3618 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3619 (mult:SI (s_or_u:SI
3620 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3621 (parallel [(const_int 0)])))
3622 (s_or_u:SI
3623 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3624 (parallel [(const_int 1)])))))
3625 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3626 (mult:SI (s_or_u:SI
3627 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3628 (s_or_u:SI
3629 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3630 ""
3631 "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
3632 [(set_attr "type" "dsp32")])
3634 (define_insn "<su_optab>hisi_lh_hh"
3635 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3636 (mult:SI (s_or_u:SI
3637 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3638 (parallel [(const_int 0)])))
3639 (s_or_u:SI
3640 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3641 (parallel [(const_int 1)])))))
3642 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3643 (mult:SI (s_or_u:SI
3644 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3645 (s_or_u:SI
3646 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3647 ""
3648 "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
3649 [(set_attr "type" "dsp32")])
3651 (define_insn "<su_optab>hisi_hl_hh"
3652 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3653 (mult:SI (s_or_u:SI
3654 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3655 (parallel [(const_int 1)])))
3656 (s_or_u:SI
3657 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3658 (parallel [(const_int 0)])))))
3659 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3660 (mult:SI (s_or_u:SI
3661 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3662 (s_or_u:SI
3663 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3664 ""
3665 "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3666 [(set_attr "type" "dsp32")])
3668 ;; Special signed * unsigned variants.
3670 (define_insn "usmulhisi_ll_lul"
3671 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3672 (mult:SI (sign_extend:SI
3673 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3674 (parallel [(const_int 0)])))
3675 (sign_extend:SI
3676 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3677 (parallel [(const_int 0)])))))
3678 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3679 (mult:SI (sign_extend:SI
3680 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3681 (zero_extend:SI
3682 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3683 ""
3684 "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3685 [(set_attr "type" "dsp32")])
3687 (define_insn "usmulhisi_ll_luh"
3688 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3689 (mult:SI (sign_extend:SI
3690 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3691 (parallel [(const_int 0)])))
3692 (sign_extend:SI
3693 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3694 (parallel [(const_int 0)])))))
3695 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3696 (mult:SI (sign_extend:SI
3697 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3698 (zero_extend:SI
3699 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3700 ""
3701 "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3702 [(set_attr "type" "dsp32")])
3704 (define_insn "usmulhisi_ll_hul"
3705 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3706 (mult:SI (sign_extend:SI
3707 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3708 (parallel [(const_int 0)])))
3709 (sign_extend:SI
3710 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3711 (parallel [(const_int 0)])))))
3712 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3713 (mult:SI (sign_extend:SI
3714 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3715 (zero_extend:SI
3716 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3717 ""
3718 "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3719 [(set_attr "type" "dsp32")])
3721 (define_insn "usmulhisi_ll_huh"
3722 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3723 (mult:SI (sign_extend:SI
3724 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3725 (parallel [(const_int 0)])))
3726 (sign_extend:SI
3727 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3728 (parallel [(const_int 0)])))))
3729 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3730 (mult:SI (sign_extend:SI
3731 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3732 (zero_extend:SI
3733 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3734 ""
3735 "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3736 [(set_attr "type" "dsp32")])
3738 (define_insn "usmulhisi_lh_lul"
3739 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3740 (mult:SI (sign_extend:SI
3741 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3742 (parallel [(const_int 0)])))
3743 (sign_extend:SI
3744 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3745 (parallel [(const_int 1)])))))
3746 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3747 (mult:SI (sign_extend:SI
3748 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3749 (zero_extend:SI
3750 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3751 ""
3752 "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3753 [(set_attr "type" "dsp32")])
3755 (define_insn "usmulhisi_lh_luh"
3756 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3757 (mult:SI (sign_extend:SI
3758 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3759 (parallel [(const_int 0)])))
3760 (sign_extend:SI
3761 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3762 (parallel [(const_int 1)])))))
3763 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3764 (mult:SI (sign_extend:SI
3765 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3766 (zero_extend:SI
3767 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3768 ""
3769 "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3770 [(set_attr "type" "dsp32")])
3772 (define_insn "usmulhisi_lh_hul"
3773 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3774 (mult:SI (sign_extend:SI
3775 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3776 (parallel [(const_int 0)])))
3777 (sign_extend:SI
3778 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3779 (parallel [(const_int 1)])))))
3780 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3781 (mult:SI (sign_extend:SI
3782 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3783 (zero_extend:SI
3784 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3785 ""
3786 "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3787 [(set_attr "type" "dsp32")])
3789 (define_insn "usmulhisi_lh_huh"
3790 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3791 (mult:SI (sign_extend:SI
3792 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3793 (parallel [(const_int 0)])))
3794 (sign_extend:SI
3795 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3796 (parallel [(const_int 1)])))))
3797 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3798 (mult:SI (sign_extend:SI
3799 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3800 (zero_extend:SI
3801 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3802 ""
3803 "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
3804 [(set_attr "type" "dsp32")])
3806 (define_insn "usmulhisi_hl_lul"
3807 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3808 (mult:SI (sign_extend:SI
3809 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3810 (parallel [(const_int 1)])))
3811 (sign_extend:SI
3812 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3813 (parallel [(const_int 0)])))))
3814 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3815 (mult:SI (sign_extend:SI
3816 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3817 (zero_extend:SI
3818 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3819 ""
3820 "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3821 [(set_attr "type" "dsp32")])
3823 (define_insn "usmulhisi_hl_luh"
3824 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3825 (mult:SI (sign_extend:SI
3826 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3827 (parallel [(const_int 1)])))
3828 (sign_extend:SI
3829 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3830 (parallel [(const_int 0)])))))
3831 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3832 (mult:SI (sign_extend:SI
3833 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3834 (zero_extend:SI
3835 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3836 ""
3837 "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3838 [(set_attr "type" "dsp32")])
3840 (define_insn "usmulhisi_hl_hul"
3841 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3842 (mult:SI (sign_extend:SI
3843 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3844 (parallel [(const_int 1)])))
3845 (sign_extend:SI
3846 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3847 (parallel [(const_int 0)])))))
3848 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3849 (mult:SI (sign_extend:SI
3850 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3851 (zero_extend:SI
3852 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3853 ""
3854 "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3855 [(set_attr "type" "dsp32")])
3857 (define_insn "usmulhisi_hl_huh"
3858 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3859 (mult:SI (sign_extend:SI
3860 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3861 (parallel [(const_int 1)])))
3862 (sign_extend:SI
3863 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3864 (parallel [(const_int 0)])))))
3865 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3866 (mult:SI (sign_extend:SI
3867 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3868 (zero_extend:SI
3869 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3870 ""
3871 "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3872 [(set_attr "type" "dsp32")])
3874 (define_insn "usmulhisi_hh_lul"
3875 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3876 (mult:SI (sign_extend:SI
3877 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3878 (parallel [(const_int 1)])))
3879 (sign_extend:SI
3880 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3881 (parallel [(const_int 1)])))))
3882 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3883 (mult:SI (sign_extend:SI
3884 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3885 (zero_extend:SI
3886 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3887 ""
3888 "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3889 [(set_attr "type" "dsp32")])
3891 (define_insn "usmulhisi_hh_luh"
3892 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3893 (mult:SI (sign_extend:SI
3894 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3895 (parallel [(const_int 1)])))
3896 (sign_extend:SI
3897 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3898 (parallel [(const_int 1)])))))
3899 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3900 (mult:SI (sign_extend:SI
3901 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3902 (zero_extend:SI
3903 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3904 ""
3905 "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3906 [(set_attr "type" "dsp32")])
3908 (define_insn "usmulhisi_hh_hul"
3909 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3910 (mult:SI (sign_extend:SI
3911 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3912 (parallel [(const_int 1)])))
3913 (sign_extend:SI
3914 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3915 (parallel [(const_int 1)])))))
3916 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3917 (mult:SI (sign_extend:SI
3918 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3919 (zero_extend:SI
3920 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3921 ""
3922 "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3923 [(set_attr "type" "dsp32")])
3925 (define_insn "usmulhisi_hh_huh"
3926 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3927 (mult:SI (sign_extend:SI
3928 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3929 (parallel [(const_int 1)])))
3930 (sign_extend:SI
3931 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3932 (parallel [(const_int 1)])))))
3933 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3934 (mult:SI (sign_extend:SI
3935 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3936 (zero_extend:SI
3937 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3938 ""
3939 "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
3940 [(set_attr "type" "dsp32")])
3942 ;; Vector neg/abs.
3944 (define_insn "ssnegv2hi2"
3945 [(set (match_operand:V2HI 0 "register_operand" "=d")
3946 (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3947 ""
3948 "%0 = - %1 (V)%!"
3949 [(set_attr "type" "dsp32")])
3951 (define_insn "absv2hi2"
3952 [(set (match_operand:V2HI 0 "register_operand" "=d")
3953 (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3954 ""
3955 "%0 = ABS %1 (V)%!"
3956 [(set_attr "type" "dsp32")])
3958 ;; Shifts.
3960 (define_insn "ssashiftv2hi3"
3961 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3962 (if_then_else:V2HI
3963 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3964 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3965 (match_dup 2))
3966 (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
3967 ""
3968 "@
3969 %0 = ASHIFT %1 BY %h2 (V, S)%!
3970 %0 = %1 << %2 (V,S)%!
3971 %0 = %1 >>> %N2 (V,S)%!"
3972 [(set_attr "type" "dsp32")])
3974 (define_insn "ssashifthi3"
3975 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3976 (if_then_else:HI
3977 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3978 (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3979 (match_dup 2))
3980 (ss_ashift:HI (match_dup 1) (match_dup 2))))]
3981 ""
3982 "@
3983 %0 = ASHIFT %1 BY %h2 (V, S)%!
3984 %0 = %1 << %2 (V,S)%!
3985 %0 = %1 >>> %N2 (V,S)%!"
3986 [(set_attr "type" "dsp32")])
3988 (define_insn "lshiftv2hi3"
3989 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3990 (if_then_else:V2HI
3991 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3992 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3993 (match_dup 2))
3994 (ashift:V2HI (match_dup 1) (match_dup 2))))]
3995 ""
3996 "@
3997 %0 = LSHIFT %1 BY %h2 (V)%!
3998 %0 = %1 << %2 (V)%!
3999 %0 = %1 >> %N2 (V)%!"
4000 [(set_attr "type" "dsp32")])
4002 (define_insn "lshifthi3"
4003 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4004 (if_then_else:HI
4005 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4006 (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
4007 (match_dup 2))
4008 (ashift:HI (match_dup 1) (match_dup 2))))]
4009 ""
4010 "@
4011 %0 = LSHIFT %1 BY %h2 (V)%!
4012 %0 = %1 << %2 (V)%!
4013 %0 = %1 >> %N2 (V)%!"
4014 [(set_attr "type" "dsp32")])