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2004-07-09 David S. Miller <davem@nuts.davemloft.net>
[official-gcc/alias-decl.git] / gcc / config / sparc / sparc.c
blobe87b29e994d67cc4974390cb93d08f025e8bef39
1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "function.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "recog.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "tm_p.h"
46 #include "debug.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
51
52 /* Processor costs */
53 static const
54 struct processor_costs cypress_costs = {
55 COSTS_N_INSNS (2), /* int load */
56 COSTS_N_INSNS (2), /* int signed load */
57 COSTS_N_INSNS (2), /* int zeroed load */
58 COSTS_N_INSNS (2), /* float load */
59 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
60 COSTS_N_INSNS (5), /* fadd, fsub */
61 COSTS_N_INSNS (1), /* fcmp */
62 COSTS_N_INSNS (1), /* fmov, fmovr */
63 COSTS_N_INSNS (7), /* fmul */
64 COSTS_N_INSNS (37), /* fdivs */
65 COSTS_N_INSNS (37), /* fdivd */
66 COSTS_N_INSNS (63), /* fsqrts */
67 COSTS_N_INSNS (63), /* fsqrtd */
68 COSTS_N_INSNS (1), /* imul */
69 COSTS_N_INSNS (1), /* imulX */
70 0, /* imul bit factor */
71 COSTS_N_INSNS (1), /* idiv */
72 COSTS_N_INSNS (1), /* idivX */
73 COSTS_N_INSNS (1), /* movcc/movr */
74 0, /* shift penalty */
75 };
76
77 static const
78 struct processor_costs supersparc_costs = {
79 COSTS_N_INSNS (1), /* int load */
80 COSTS_N_INSNS (1), /* int signed load */
81 COSTS_N_INSNS (1), /* int zeroed load */
82 COSTS_N_INSNS (0), /* float load */
83 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
84 COSTS_N_INSNS (3), /* fadd, fsub */
85 COSTS_N_INSNS (3), /* fcmp */
86 COSTS_N_INSNS (1), /* fmov, fmovr */
87 COSTS_N_INSNS (3), /* fmul */
88 COSTS_N_INSNS (6), /* fdivs */
89 COSTS_N_INSNS (9), /* fdivd */
90 COSTS_N_INSNS (12), /* fsqrts */
91 COSTS_N_INSNS (12), /* fsqrtd */
92 COSTS_N_INSNS (4), /* imul */
93 COSTS_N_INSNS (4), /* imulX */
94 0, /* imul bit factor */
95 COSTS_N_INSNS (4), /* idiv */
96 COSTS_N_INSNS (4), /* idivX */
97 COSTS_N_INSNS (1), /* movcc/movr */
98 1, /* shift penalty */
99 };
100
101 static const
102 struct processor_costs hypersparc_costs = {
103 COSTS_N_INSNS (1), /* int load */
104 COSTS_N_INSNS (1), /* int signed load */
105 COSTS_N_INSNS (1), /* int zeroed load */
106 COSTS_N_INSNS (1), /* float load */
107 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
108 COSTS_N_INSNS (1), /* fadd, fsub */
109 COSTS_N_INSNS (1), /* fcmp */
110 COSTS_N_INSNS (1), /* fmov, fmovr */
111 COSTS_N_INSNS (1), /* fmul */
112 COSTS_N_INSNS (8), /* fdivs */
113 COSTS_N_INSNS (12), /* fdivd */
114 COSTS_N_INSNS (17), /* fsqrts */
115 COSTS_N_INSNS (17), /* fsqrtd */
116 COSTS_N_INSNS (17), /* imul */
117 COSTS_N_INSNS (17), /* imulX */
118 0, /* imul bit factor */
119 COSTS_N_INSNS (17), /* idiv */
120 COSTS_N_INSNS (17), /* idivX */
121 COSTS_N_INSNS (1), /* movcc/movr */
122 0, /* shift penalty */
123 };
124
125 static const
126 struct processor_costs sparclet_costs = {
127 COSTS_N_INSNS (3), /* int load */
128 COSTS_N_INSNS (3), /* int signed load */
129 COSTS_N_INSNS (1), /* int zeroed load */
130 COSTS_N_INSNS (1), /* float load */
131 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
132 COSTS_N_INSNS (1), /* fadd, fsub */
133 COSTS_N_INSNS (1), /* fcmp */
134 COSTS_N_INSNS (1), /* fmov, fmovr */
135 COSTS_N_INSNS (1), /* fmul */
136 COSTS_N_INSNS (1), /* fdivs */
137 COSTS_N_INSNS (1), /* fdivd */
138 COSTS_N_INSNS (1), /* fsqrts */
139 COSTS_N_INSNS (1), /* fsqrtd */
140 COSTS_N_INSNS (5), /* imul */
141 COSTS_N_INSNS (5), /* imulX */
142 0, /* imul bit factor */
143 COSTS_N_INSNS (5), /* idiv */
144 COSTS_N_INSNS (5), /* idivX */
145 COSTS_N_INSNS (1), /* movcc/movr */
146 0, /* shift penalty */
147 };
148
149 static const
150 struct processor_costs ultrasparc_costs = {
151 COSTS_N_INSNS (2), /* int load */
152 COSTS_N_INSNS (3), /* int signed load */
153 COSTS_N_INSNS (2), /* int zeroed load */
154 COSTS_N_INSNS (2), /* float load */
155 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
156 COSTS_N_INSNS (4), /* fadd, fsub */
157 COSTS_N_INSNS (1), /* fcmp */
158 COSTS_N_INSNS (2), /* fmov, fmovr */
159 COSTS_N_INSNS (4), /* fmul */
160 COSTS_N_INSNS (13), /* fdivs */
161 COSTS_N_INSNS (23), /* fdivd */
162 COSTS_N_INSNS (13), /* fsqrts */
163 COSTS_N_INSNS (23), /* fsqrtd */
164 COSTS_N_INSNS (4), /* imul */
165 COSTS_N_INSNS (4), /* imulX */
166 2, /* imul bit factor */
167 COSTS_N_INSNS (37), /* idiv */
168 COSTS_N_INSNS (68), /* idivX */
169 COSTS_N_INSNS (2), /* movcc/movr */
170 2, /* shift penalty */
171 };
172
173 static const
174 struct processor_costs ultrasparc3_costs = {
175 COSTS_N_INSNS (2), /* int load */
176 COSTS_N_INSNS (3), /* int signed load */
177 COSTS_N_INSNS (3), /* int zeroed load */
178 COSTS_N_INSNS (2), /* float load */
179 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
180 COSTS_N_INSNS (4), /* fadd, fsub */
181 COSTS_N_INSNS (5), /* fcmp */
182 COSTS_N_INSNS (3), /* fmov, fmovr */
183 COSTS_N_INSNS (4), /* fmul */
184 COSTS_N_INSNS (17), /* fdivs */
185 COSTS_N_INSNS (20), /* fdivd */
186 COSTS_N_INSNS (20), /* fsqrts */
187 COSTS_N_INSNS (29), /* fsqrtd */
188 COSTS_N_INSNS (6), /* imul */
189 COSTS_N_INSNS (6), /* imulX */
190 0, /* imul bit factor */
191 COSTS_N_INSNS (40), /* idiv */
192 COSTS_N_INSNS (71), /* idivX */
193 COSTS_N_INSNS (2), /* movcc/movr */
194 0, /* shift penalty */
195 };
196
197 const struct processor_costs *sparc_costs = &cypress_costs;
198
199 #ifdef HAVE_AS_RELAX_OPTION
200 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
201 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
202 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
203 somebody does not branch between the sethi and jmp. */
204 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
205 #else
206 #define LEAF_SIBCALL_SLOT_RESERVED_P \
207 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
208 #endif
209
210 /* Global variables for machine-dependent things. */
211
212 /* Size of frame. Need to know this to emit return insns from leaf procedures.
213 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
214 reload pass. This is important as the value is later used for scheduling
215 (to see what can go in a delay slot).
216 APPARENT_FSIZE is the size of the stack less the register save area and less
217 the outgoing argument area. It is used when saving call preserved regs. */
218 static HOST_WIDE_INT apparent_fsize;
219 static HOST_WIDE_INT actual_fsize;
220
221 /* Number of live general or floating point registers needed to be
222 saved (as 4-byte quantities). */
223 static int num_gfregs;
224
225 /* The alias set for prologue/epilogue register save/restore. */
226 static GTY(()) int sparc_sr_alias_set;
227
228 /* Save the operands last given to a compare for use when we
229 generate a scc or bcc insn. */
230 rtx sparc_compare_op0, sparc_compare_op1;
231
232 /* Vector to say how input registers are mapped to output registers.
233 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
234 eliminate it. You must use -fomit-frame-pointer to get that. */
235 char leaf_reg_remap[] =
236 { 0, 1, 2, 3, 4, 5, 6, 7,
237 -1, -1, -1, -1, -1, -1, 14, -1,
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 8, 9, 10, 11, 12, 13, -1, 15,
240
241 32, 33, 34, 35, 36, 37, 38, 39,
242 40, 41, 42, 43, 44, 45, 46, 47,
243 48, 49, 50, 51, 52, 53, 54, 55,
244 56, 57, 58, 59, 60, 61, 62, 63,
245 64, 65, 66, 67, 68, 69, 70, 71,
246 72, 73, 74, 75, 76, 77, 78, 79,
247 80, 81, 82, 83, 84, 85, 86, 87,
248 88, 89, 90, 91, 92, 93, 94, 95,
249 96, 97, 98, 99, 100};
250
251 /* Vector, indexed by hard register number, which contains 1
252 for a register that is allowable in a candidate for leaf
253 function treatment. */
254 char sparc_leaf_regs[] =
255 { 1, 1, 1, 1, 1, 1, 1, 1,
256 0, 0, 0, 0, 0, 0, 1, 0,
257 0, 0, 0, 0, 0, 0, 0, 0,
258 1, 1, 1, 1, 1, 1, 0, 1,
259 1, 1, 1, 1, 1, 1, 1, 1,
260 1, 1, 1, 1, 1, 1, 1, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1};
268
269 struct machine_function GTY(())
270 {
271 /* Some local-dynamic TLS symbol name. */
272 const char *some_ld_name;
273 };
274
275 /* Register we pretend to think the frame pointer is allocated to.
276 Normally, this is %fp, but if we are in a leaf procedure, this
277 is %sp+"something". We record "something" separately as it may
278 be too big for reg+constant addressing. */
279
280 static rtx frame_base_reg;
281 static HOST_WIDE_INT frame_base_offset;
282
283 static void sparc_init_modes (void);
284 static void scan_record_type (tree, int *, int *, int *);
285 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
286 tree, int, int, int *, int *);
287
288 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
289 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
290
291 static void sparc_output_addr_vec (rtx);
292 static void sparc_output_addr_diff_vec (rtx);
293 static void sparc_output_deferred_case_vectors (void);
294 static rtx sparc_builtin_saveregs (void);
295 static int epilogue_renumber (rtx *, int);
296 static bool sparc_assemble_integer (rtx, unsigned int, int);
297 static int set_extends (rtx);
298 static void load_pic_register (void);
299 static int save_or_restore_regs (int, int, rtx, int, int);
300 static void emit_save_regs (void);
301 static void emit_restore_regs (void);
302 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
303 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
304 #ifdef OBJECT_FORMAT_ELF
305 static void sparc_elf_asm_named_section (const char *, unsigned int);
306 #endif
307
308 static int sparc_adjust_cost (rtx, rtx, rtx, int);
309 static int sparc_issue_rate (void);
310 static void sparc_sched_init (FILE *, int, int);
311 static int sparc_use_sched_lookahead (void);
312
313 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
314 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
315 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
316 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
317 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
318
319 static bool sparc_function_ok_for_sibcall (tree, tree);
320 static void sparc_init_libfuncs (void);
321 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
322 HOST_WIDE_INT, tree);
323 static struct machine_function * sparc_init_machine_status (void);
324 static bool sparc_cannot_force_const_mem (rtx);
325 static rtx sparc_tls_get_addr (void);
326 static rtx sparc_tls_got (void);
327 static const char *get_some_local_dynamic_name (void);
328 static int get_some_local_dynamic_name_1 (rtx *, void *);
329 static bool sparc_rtx_costs (rtx, int, int, int *);
330 static bool sparc_promote_prototypes (tree);
331 static rtx sparc_struct_value_rtx (tree, int);
332 static bool sparc_return_in_memory (tree, tree);
333 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
334 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
335 \f
336 /* Option handling. */
337
338 /* Code model option as passed by user. */
339 const char *sparc_cmodel_string;
340 /* Parsed value. */
341 enum cmodel sparc_cmodel;
342
343 char sparc_hard_reg_printed[8];
344
345 struct sparc_cpu_select sparc_select[] =
346 {
347 /* switch name, tune arch */
348 { (char *)0, "default", 1, 1 },
349 { (char *)0, "-mcpu=", 1, 1 },
350 { (char *)0, "-mtune=", 1, 0 },
351 { 0, 0, 0, 0 }
352 };
353
354 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
355 enum processor_type sparc_cpu;
356 \f
357 /* Initialize the GCC target structure. */
358
359 /* The sparc default is to use .half rather than .short for aligned
360 HI objects. Use .word instead of .long on non-ELF systems. */
361 #undef TARGET_ASM_ALIGNED_HI_OP
362 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
363 #ifndef OBJECT_FORMAT_ELF
364 #undef TARGET_ASM_ALIGNED_SI_OP
365 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
366 #endif
367
368 #undef TARGET_ASM_UNALIGNED_HI_OP
369 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
370 #undef TARGET_ASM_UNALIGNED_SI_OP
371 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
372 #undef TARGET_ASM_UNALIGNED_DI_OP
373 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
374
375 /* The target hook has to handle DI-mode values. */
376 #undef TARGET_ASM_INTEGER
377 #define TARGET_ASM_INTEGER sparc_assemble_integer
378
379 #undef TARGET_ASM_FUNCTION_PROLOGUE
380 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
381 #undef TARGET_ASM_FUNCTION_EPILOGUE
382 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
383
384 #undef TARGET_SCHED_ADJUST_COST
385 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
386 #undef TARGET_SCHED_ISSUE_RATE
387 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
388 #undef TARGET_SCHED_INIT
389 #define TARGET_SCHED_INIT sparc_sched_init
390 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
391 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
392 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
393 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
394
395 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
396 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
397
398 #undef TARGET_INIT_LIBFUNCS
399 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
400
401 #ifdef HAVE_AS_TLS
402 #undef TARGET_HAVE_TLS
403 #define TARGET_HAVE_TLS true
404 #endif
405 #undef TARGET_CANNOT_FORCE_CONST_MEM
406 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
407
408 #undef TARGET_ASM_OUTPUT_MI_THUNK
409 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
410 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
411 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
412
413 #undef TARGET_RTX_COSTS
414 #define TARGET_RTX_COSTS sparc_rtx_costs
415 #undef TARGET_ADDRESS_COST
416 #define TARGET_ADDRESS_COST hook_int_rtx_0
417
418 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
419 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
420 test for this value. */
421 #undef TARGET_PROMOTE_FUNCTION_ARGS
422 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
423
424 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
425 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
426 test for this value. */
427 #undef TARGET_PROMOTE_FUNCTION_RETURN
428 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
429
430 #undef TARGET_PROMOTE_PROTOTYPES
431 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
432
433 #undef TARGET_STRUCT_VALUE_RTX
434 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
435 #undef TARGET_RETURN_IN_MEMORY
436 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
437
438 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
439 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
440 #undef TARGET_STRICT_ARGUMENT_NAMING
441 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
442
443 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
444 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
445
446 #undef TARGET_LATE_RTL_PROLOGUE_EPILOGUE
447 #define TARGET_LATE_RTL_PROLOGUE_EPILOGUE true
448
449 struct gcc_target targetm = TARGET_INITIALIZER;
450 \f
451 /* Validate and override various options, and do some machine dependent
452 initialization. */
453
454 void
455 sparc_override_options (void)
456 {
457 static struct code_model {
458 const char *const name;
459 const int value;
460 } const cmodels[] = {
461 { "32", CM_32 },
462 { "medlow", CM_MEDLOW },
463 { "medmid", CM_MEDMID },
464 { "medany", CM_MEDANY },
465 { "embmedany", CM_EMBMEDANY },
466 { 0, 0 }
467 };
468 const struct code_model *cmodel;
469 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
470 static struct cpu_default {
471 const int cpu;
472 const char *const name;
473 } const cpu_default[] = {
474 /* There must be one entry here for each TARGET_CPU value. */
475 { TARGET_CPU_sparc, "cypress" },
476 { TARGET_CPU_sparclet, "tsc701" },
477 { TARGET_CPU_sparclite, "f930" },
478 { TARGET_CPU_v8, "v8" },
479 { TARGET_CPU_hypersparc, "hypersparc" },
480 { TARGET_CPU_sparclite86x, "sparclite86x" },
481 { TARGET_CPU_supersparc, "supersparc" },
482 { TARGET_CPU_v9, "v9" },
483 { TARGET_CPU_ultrasparc, "ultrasparc" },
484 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
485 { 0, 0 }
486 };
487 const struct cpu_default *def;
488 /* Table of values for -m{cpu,tune}=. */
489 static struct cpu_table {
490 const char *const name;
491 const enum processor_type processor;
492 const int disable;
493 const int enable;
494 } const cpu_table[] = {
495 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
496 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
497 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
498 /* TI TMS390Z55 supersparc */
499 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
500 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
501 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
502 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
503 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
504 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
505 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
506 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
507 MASK_SPARCLITE },
508 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
509 /* TEMIC sparclet */
510 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
511 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
512 /* TI ultrasparc I, II, IIi */
513 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
514 /* Although insns using %y are deprecated, it is a clear win on current
515 ultrasparcs. */
516 |MASK_DEPRECATED_V8_INSNS},
517 /* TI ultrasparc III */
518 /* ??? Check if %y issue still holds true in ultra3. */
519 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
520 { 0, 0, 0, 0 }
521 };
522 const struct cpu_table *cpu;
523 const struct sparc_cpu_select *sel;
524 int fpu;
525
526 #ifndef SPARC_BI_ARCH
527 /* Check for unsupported architecture size. */
528 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
529 error ("%s is not supported by this configuration",
530 DEFAULT_ARCH32_P ? "-m64" : "-m32");
531 #endif
532
533 /* We force all 64bit archs to use 128 bit long double */
534 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
535 {
536 error ("-mlong-double-64 not allowed with -m64");
537 target_flags |= MASK_LONG_DOUBLE_128;
538 }
539
540 /* Code model selection. */
541 sparc_cmodel = SPARC_DEFAULT_CMODEL;
542
543 #ifdef SPARC_BI_ARCH
544 if (TARGET_ARCH32)
545 sparc_cmodel = CM_32;
546 #endif
547
548 if (sparc_cmodel_string != NULL)
549 {
550 if (TARGET_ARCH64)
551 {
552 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
553 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
554 break;
555 if (cmodel->name == NULL)
556 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
557 else
558 sparc_cmodel = cmodel->value;
559 }
560 else
561 error ("-mcmodel= is not supported on 32 bit systems");
562 }
563
564 fpu = TARGET_FPU; /* save current -mfpu status */
565
566 /* Set the default CPU. */
567 for (def = &cpu_default[0]; def->name; ++def)
568 if (def->cpu == TARGET_CPU_DEFAULT)
569 break;
570 if (! def->name)
571 abort ();
572 sparc_select[0].string = def->name;
573
574 for (sel = &sparc_select[0]; sel->name; ++sel)
575 {
576 if (sel->string)
577 {
578 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
579 if (! strcmp (sel->string, cpu->name))
580 {
581 if (sel->set_tune_p)
582 sparc_cpu = cpu->processor;
583
584 if (sel->set_arch_p)
585 {
586 target_flags &= ~cpu->disable;
587 target_flags |= cpu->enable;
588 }
589 break;
590 }
591
592 if (! cpu->name)
593 error ("bad value (%s) for %s switch", sel->string, sel->name);
594 }
595 }
596
597 /* If -mfpu or -mno-fpu was explicitly used, don't override with
598 the processor default. Clear MASK_FPU_SET to avoid confusing
599 the reverse mapping from switch values to names. */
600 if (TARGET_FPU_SET)
601 {
602 target_flags = (target_flags & ~MASK_FPU) | fpu;
603 target_flags &= ~MASK_FPU_SET;
604 }
605
606 /* Don't allow -mvis if FPU is disabled. */
607 if (! TARGET_FPU)
608 target_flags &= ~MASK_VIS;
609
610 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
611 are available.
612 -m64 also implies v9. */
613 if (TARGET_VIS || TARGET_ARCH64)
614 {
615 target_flags |= MASK_V9;
616 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
617 }
618
619 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
620 if (TARGET_V9 && TARGET_ARCH32)
621 target_flags |= MASK_DEPRECATED_V8_INSNS;
622
623 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
624 if (! TARGET_V9 || TARGET_ARCH64)
625 target_flags &= ~MASK_V8PLUS;
626
627 /* Don't use stack biasing in 32 bit mode. */
628 if (TARGET_ARCH32)
629 target_flags &= ~MASK_STACK_BIAS;
630
631 /* Supply a default value for align_functions. */
632 if (align_functions == 0
633 && (sparc_cpu == PROCESSOR_ULTRASPARC
634 || sparc_cpu == PROCESSOR_ULTRASPARC3))
635 align_functions = 32;
636
637 /* Validate PCC_STRUCT_RETURN. */
638 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
639 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
640
641 /* Only use .uaxword when compiling for a 64-bit target. */
642 if (!TARGET_ARCH64)
643 targetm.asm_out.unaligned_op.di = NULL;
644
645 /* Do various machine dependent initializations. */
646 sparc_init_modes ();
647
648 /* Acquire a unique set number for our register saves and restores. */
649 sparc_sr_alias_set = new_alias_set ();
650
651 /* Set up function hooks. */
652 init_machine_status = sparc_init_machine_status;
653
654 switch (sparc_cpu)
655 {
656 case PROCESSOR_V7:
657 case PROCESSOR_CYPRESS:
658 sparc_costs = &cypress_costs;
659 break;
660 case PROCESSOR_V8:
661 case PROCESSOR_SPARCLITE:
662 case PROCESSOR_SUPERSPARC:
663 sparc_costs = &supersparc_costs;
664 break;
665 case PROCESSOR_F930:
666 case PROCESSOR_F934:
667 case PROCESSOR_HYPERSPARC:
668 case PROCESSOR_SPARCLITE86X:
669 sparc_costs = &hypersparc_costs;
670 break;
671 case PROCESSOR_SPARCLET:
672 case PROCESSOR_TSC701:
673 sparc_costs = &sparclet_costs;
674 break;
675 case PROCESSOR_V9:
676 case PROCESSOR_ULTRASPARC:
677 sparc_costs = &ultrasparc_costs;
678 break;
679 case PROCESSOR_ULTRASPARC3:
680 sparc_costs = &ultrasparc3_costs;
681 break;
682 };
683 }
684 \f
685 /* Miscellaneous utilities. */
686
687 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
688 or branch on register contents instructions. */
689
690 int
691 v9_regcmp_p (enum rtx_code code)
692 {
693 return (code == EQ || code == NE || code == GE || code == LT
694 || code == LE || code == GT);
695 }
696
697 \f
698 /* Operand constraints. */
699
700 /* Return nonzero only if OP is a register of mode MODE,
701 or const0_rtx. */
702
703 int
704 reg_or_0_operand (rtx op, enum machine_mode mode)
705 {
706 if (register_operand (op, mode))
707 return 1;
708 if (op == const0_rtx)
709 return 1;
710 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
711 && CONST_DOUBLE_HIGH (op) == 0
712 && CONST_DOUBLE_LOW (op) == 0)
713 return 1;
714 if (fp_zero_operand (op, mode))
715 return 1;
716 return 0;
717 }
718
719 /* Return nonzero only if OP is const1_rtx. */
720
721 int
722 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
723 {
724 return op == const1_rtx;
725 }
726
727 /* Nonzero if OP is a floating point value with value 0.0. */
728
729 int
730 fp_zero_operand (rtx op, enum machine_mode mode)
731 {
732 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
733 return 0;
734 return op == CONST0_RTX (mode);
735 }
736
737 /* Nonzero if OP is a register operand in floating point register. */
738
739 int
740 fp_register_operand (rtx op, enum machine_mode mode)
741 {
742 if (! register_operand (op, mode))
743 return 0;
744 if (GET_CODE (op) == SUBREG)
745 op = SUBREG_REG (op);
746 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
747 }
748
749 /* Nonzero if OP is a floating point constant which can
750 be loaded into an integer register using a single
751 sethi instruction. */
752
753 int
754 fp_sethi_p (rtx op)
755 {
756 if (GET_CODE (op) == CONST_DOUBLE)
757 {
758 REAL_VALUE_TYPE r;
759 long i;
760
761 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
762 if (REAL_VALUES_EQUAL (r, dconst0) &&
763 ! REAL_VALUE_MINUS_ZERO (r))
764 return 0;
765 REAL_VALUE_TO_TARGET_SINGLE (r, i);
766 if (SPARC_SETHI_P (i))
767 return 1;
768 }
769
770 return 0;
771 }
772
773 /* Nonzero if OP is a floating point constant which can
774 be loaded into an integer register using a single
775 mov instruction. */
776
777 int
778 fp_mov_p (rtx op)
779 {
780 if (GET_CODE (op) == CONST_DOUBLE)
781 {
782 REAL_VALUE_TYPE r;
783 long i;
784
785 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
786 if (REAL_VALUES_EQUAL (r, dconst0) &&
787 ! REAL_VALUE_MINUS_ZERO (r))
788 return 0;
789 REAL_VALUE_TO_TARGET_SINGLE (r, i);
790 if (SPARC_SIMM13_P (i))
791 return 1;
792 }
793
794 return 0;
795 }
796
797 /* Nonzero if OP is a floating point constant which can
798 be loaded into an integer register using a high/losum
799 instruction sequence. */
800
801 int
802 fp_high_losum_p (rtx op)
803 {
804 /* The constraints calling this should only be in
805 SFmode move insns, so any constant which cannot
806 be moved using a single insn will do. */
807 if (GET_CODE (op) == CONST_DOUBLE)
808 {
809 REAL_VALUE_TYPE r;
810 long i;
811
812 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
813 if (REAL_VALUES_EQUAL (r, dconst0) &&
814 ! REAL_VALUE_MINUS_ZERO (r))
815 return 0;
816 REAL_VALUE_TO_TARGET_SINGLE (r, i);
817 if (! SPARC_SETHI_P (i)
818 && ! SPARC_SIMM13_P (i))
819 return 1;
820 }
821
822 return 0;
823 }
824
825 /* Nonzero if OP is an integer register. */
826
827 int
828 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
829 {
830 return (register_operand (op, SImode)
831 || (TARGET_ARCH64 && register_operand (op, DImode)));
832 }
833
834 /* Nonzero if OP is a floating point condition code register. */
835
836 int
837 fcc_reg_operand (rtx op, enum machine_mode mode)
838 {
839 /* This can happen when recog is called from combine. Op may be a MEM.
840 Fail instead of calling abort in this case. */
841 if (GET_CODE (op) != REG)
842 return 0;
843
844 if (mode != VOIDmode && mode != GET_MODE (op))
845 return 0;
846 if (mode == VOIDmode
847 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
848 return 0;
849
850 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
851 if (reg_renumber == 0)
852 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
853 return REGNO_OK_FOR_CCFP_P (REGNO (op));
854 #else
855 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
856 #endif
857 }
858
859 /* Nonzero if OP is a floating point condition code fcc0 register. */
860
861 int
862 fcc0_reg_operand (rtx op, enum machine_mode mode)
863 {
864 /* This can happen when recog is called from combine. Op may be a MEM.
865 Fail instead of calling abort in this case. */
866 if (GET_CODE (op) != REG)
867 return 0;
868
869 if (mode != VOIDmode && mode != GET_MODE (op))
870 return 0;
871 if (mode == VOIDmode
872 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
873 return 0;
874
875 return REGNO (op) == SPARC_FCC_REG;
876 }
877
878 /* Nonzero if OP is an integer or floating point condition code register. */
879
880 int
881 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
882 {
883 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
884 {
885 if (mode != VOIDmode && mode != GET_MODE (op))
886 return 0;
887 if (mode == VOIDmode
888 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
889 return 0;
890 return 1;
891 }
892
893 return fcc_reg_operand (op, mode);
894 }
895
896 /* Call insn on SPARC can take a PC-relative constant address, or any regular
897 memory address. */
898
899 int
900 call_operand (rtx op, enum machine_mode mode)
901 {
902 if (GET_CODE (op) != MEM)
903 abort ();
904 op = XEXP (op, 0);
905 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
906 }
907
908 int
909 call_operand_address (rtx op, enum machine_mode mode)
910 {
911 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
912 }
913
914 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
915 otherwise return 0. */
916
917 int
918 tls_symbolic_operand (rtx op)
919 {
920 if (GET_CODE (op) != SYMBOL_REF)
921 return 0;
922 return SYMBOL_REF_TLS_MODEL (op);
923 }
924
925 int
926 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
927 {
928 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
929 }
930
931 int
932 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
933 {
934 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
935 }
936
937 int
938 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
939 {
940 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
941 }
942
943 int
944 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
945 {
946 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
947 }
948
949 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
950 reference and a constant. */
951
952 int
953 symbolic_operand (register rtx op, enum machine_mode mode)
954 {
955 enum machine_mode omode = GET_MODE (op);
956
957 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
958 return 0;
959
960 switch (GET_CODE (op))
961 {
962 case SYMBOL_REF:
963 return !SYMBOL_REF_TLS_MODEL (op);
964
965 case LABEL_REF:
966 return 1;
967
968 case CONST:
969 op = XEXP (op, 0);
970 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
971 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
972 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
973 && GET_CODE (XEXP (op, 1)) == CONST_INT);
974
975 default:
976 return 0;
977 }
978 }
979
980 /* Return truth value of statement that OP is a symbolic memory
981 operand of mode MODE. */
982
983 int
984 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
985 {
986 if (GET_CODE (op) == SUBREG)
987 op = SUBREG_REG (op);
988 if (GET_CODE (op) != MEM)
989 return 0;
990 op = XEXP (op, 0);
991 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
992 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
993 || GET_CODE (op) == LABEL_REF);
994 }
995
996 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
997
998 int
999 label_ref_operand (rtx op, enum machine_mode mode)
1000 {
1001 if (GET_CODE (op) != LABEL_REF)
1002 return 0;
1003 if (GET_MODE (op) != mode)
1004 return 0;
1005 return 1;
1006 }
1007
1008 /* Return 1 if the operand is an argument used in generating pic references
1009 in either the medium/low or medium/anywhere code models of sparc64. */
1010
1011 int
1012 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1013 {
1014 /* Check for (const (minus (symbol_ref:GOT)
1015 (const (minus (label) (pc))))). */
1016 if (GET_CODE (op) != CONST)
1017 return 0;
1018 op = XEXP (op, 0);
1019 if (GET_CODE (op) != MINUS)
1020 return 0;
1021 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1022 return 0;
1023 /* ??? Ensure symbol is GOT. */
1024 if (GET_CODE (XEXP (op, 1)) != CONST)
1025 return 0;
1026 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1027 return 0;
1028 return 1;
1029 }
1030
1031 /* Return 1 if the operand is a data segment reference. This includes
1032 the readonly data segment, or in other words anything but the text segment.
1033 This is needed in the medium/anywhere code model on v9. These values
1034 are accessed with EMBMEDANY_BASE_REG. */
1035
1036 int
1037 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1038 {
1039 switch (GET_CODE (op))
1040 {
1041 case SYMBOL_REF :
1042 return ! SYMBOL_REF_FUNCTION_P (op);
1043 case PLUS :
1044 /* Assume canonical format of symbol + constant.
1045 Fall through. */
1046 case CONST :
1047 return data_segment_operand (XEXP (op, 0), VOIDmode);
1048 default :
1049 return 0;
1050 }
1051 }
1052
1053 /* Return 1 if the operand is a text segment reference.
1054 This is needed in the medium/anywhere code model on v9. */
1055
1056 int
1057 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1058 {
1059 switch (GET_CODE (op))
1060 {
1061 case LABEL_REF :
1062 return 1;
1063 case SYMBOL_REF :
1064 return SYMBOL_REF_FUNCTION_P (op);
1065 case PLUS :
1066 /* Assume canonical format of symbol + constant.
1067 Fall through. */
1068 case CONST :
1069 return text_segment_operand (XEXP (op, 0), VOIDmode);
1070 default :
1071 return 0;
1072 }
1073 }
1074
1075 /* Return 1 if the operand is either a register or a memory operand that is
1076 not symbolic. */
1077
1078 int
1079 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1080 {
1081 if (register_operand (op, mode))
1082 return 1;
1083
1084 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1085 return 1;
1086
1087 return 0;
1088 }
1089
1090 int
1091 splittable_symbolic_memory_operand (rtx op,
1092 enum machine_mode mode ATTRIBUTE_UNUSED)
1093 {
1094 if (GET_CODE (op) != MEM)
1095 return 0;
1096 if (! symbolic_operand (XEXP (op, 0), Pmode))
1097 return 0;
1098 return 1;
1099 }
1100
1101 int
1102 splittable_immediate_memory_operand (rtx op,
1103 enum machine_mode mode ATTRIBUTE_UNUSED)
1104 {
1105 if (GET_CODE (op) != MEM)
1106 return 0;
1107 if (! immediate_operand (XEXP (op, 0), Pmode))
1108 return 0;
1109 return 1;
1110 }
1111
1112 /* Return truth value of whether OP is EQ or NE. */
1113
1114 int
1115 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1116 {
1117 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1118 }
1119
1120 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1121 or LTU for non-floating-point. We handle those specially. */
1122
1123 int
1124 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1125 {
1126 enum rtx_code code;
1127
1128 if (!COMPARISON_P (op))
1129 return 0;
1130
1131 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1132 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1133 return 1;
1134
1135 code = GET_CODE (op);
1136 return (code != NE && code != EQ && code != GEU && code != LTU);
1137 }
1138
1139 /* Return 1 if this is a comparison operator. This allows the use of
1140 MATCH_OPERATOR to recognize all the branch insns. */
1141
1142 int
1143 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1144 {
1145 enum rtx_code code;
1146
1147 if (!COMPARISON_P (op))
1148 return 0;
1149
1150 code = GET_CODE (op);
1151 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1152 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1153 /* These are the only branches which work with CC_NOOVmode. */
1154 return (code == EQ || code == NE || code == GE || code == LT);
1155 return 1;
1156 }
1157
1158 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1159 MATCH_OPERATOR to recognize all the branch insns. */
1160
1161 int
1162 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1163 {
1164 enum rtx_code code;
1165
1166 if (! TARGET_V9)
1167 return 0;
1168
1169 if (!COMPARISON_P (op))
1170 return 0;
1171
1172 code = GET_CODE (op);
1173 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1174 /* These are the only branches which work with CCX_NOOVmode. */
1175 return (code == EQ || code == NE || code == GE || code == LT);
1176 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1177 }
1178
1179 /* Nonzero if OP is a comparison operator suitable for use in v9
1180 conditional move or branch on register contents instructions. */
1181
1182 int
1183 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1184 {
1185 enum rtx_code code;
1186
1187 if (!COMPARISON_P (op))
1188 return 0;
1189
1190 code = GET_CODE (op);
1191 return v9_regcmp_p (code);
1192 }
1193
1194 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1195
1196 int
1197 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1198 {
1199 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1200 }
1201
1202 /* Return nonzero if OP is an operator of mode MODE which can set
1203 the condition codes explicitly. We do not include PLUS and MINUS
1204 because these require CC_NOOVmode, which we handle explicitly. */
1205
1206 int
1207 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1208 {
1209 if (GET_CODE (op) == AND
1210 || GET_CODE (op) == IOR
1211 || GET_CODE (op) == XOR)
1212 return 1;
1213
1214 return 0;
1215 }
1216
1217 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1218 complement its second operand and set the condition codes explicitly. */
1219
1220 int
1221 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1222 {
1223 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1224 and (xor ... (not ...)) to (not (xor ...)). */
1225 return (GET_CODE (op) == AND
1226 || GET_CODE (op) == IOR);
1227 }
1228 \f
1229 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1230 signed 13 bit immediate field. This is an acceptable SImode operand for
1231 most 3 address instructions. */
1232
1233 int
1234 arith_operand (rtx op, enum machine_mode mode)
1235 {
1236 if (register_operand (op, mode))
1237 return 1;
1238 if (GET_CODE (op) != CONST_INT)
1239 return 0;
1240 return SMALL_INT32 (op);
1241 }
1242
1243 /* Return true if OP is a constant 4096 */
1244
1245 int
1246 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1247 {
1248 if (GET_CODE (op) != CONST_INT)
1249 return 0;
1250 else
1251 return INTVAL (op) == 4096;
1252 }
1253
1254 /* Return true if OP is suitable as second operand for add/sub */
1255
1256 int
1257 arith_add_operand (rtx op, enum machine_mode mode)
1258 {
1259 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1260 }
1261
1262 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1263 immediate field of OR and XOR instructions. Used for 64-bit
1264 constant formation patterns. */
1265 int
1266 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1267 {
1268 return ((GET_CODE (op) == CONST_INT
1269 && SPARC_SIMM13_P (INTVAL (op)))
1270 #if HOST_BITS_PER_WIDE_INT != 64
1271 || (GET_CODE (op) == CONST_DOUBLE
1272 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1273 && (CONST_DOUBLE_HIGH (op) ==
1274 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1275 (HOST_WIDE_INT)-1 : 0)))
1276 #endif
1277 );
1278 }
1279
1280 /* The same, but only for sethi instructions. */
1281 int
1282 const64_high_operand (rtx op, enum machine_mode mode)
1283 {
1284 return ((GET_CODE (op) == CONST_INT
1285 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1286 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1287 )
1288 || (GET_CODE (op) == CONST_DOUBLE
1289 && CONST_DOUBLE_HIGH (op) == 0
1290 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1291 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1292 }
1293
1294 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1295 signed 11 bit immediate field. This is an acceptable SImode operand for
1296 the movcc instructions. */
1297
1298 int
1299 arith11_operand (rtx op, enum machine_mode mode)
1300 {
1301 return (register_operand (op, mode)
1302 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1303 }
1304
1305 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1306 signed 10 bit immediate field. This is an acceptable SImode operand for
1307 the movrcc instructions. */
1308
1309 int
1310 arith10_operand (rtx op, enum machine_mode mode)
1311 {
1312 return (register_operand (op, mode)
1313 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1314 }
1315
1316 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1317 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1318 immediate field.
1319 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1320 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1321 for most 3 address instructions. */
1322
1323 int
1324 arith_double_operand (rtx op, enum machine_mode mode)
1325 {
1326 return (register_operand (op, mode)
1327 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1328 || (! TARGET_ARCH64
1329 && GET_CODE (op) == CONST_DOUBLE
1330 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1331 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1332 || (TARGET_ARCH64
1333 && GET_CODE (op) == CONST_DOUBLE
1334 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1335 && ((CONST_DOUBLE_HIGH (op) == -1
1336 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1337 || (CONST_DOUBLE_HIGH (op) == 0
1338 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1339 }
1340
1341 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1342
1343 int
1344 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1345 {
1346 return (TARGET_ARCH64 &&
1347 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1348 (GET_CODE (op) == CONST_DOUBLE &&
1349 CONST_DOUBLE_LOW (op) == 4096 &&
1350 CONST_DOUBLE_HIGH (op) == 0)));
1351 }
1352
1353 /* Return true if OP is suitable as second operand for add/sub in DImode */
1354
1355 int
1356 arith_double_add_operand (rtx op, enum machine_mode mode)
1357 {
1358 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1359 }
1360
1361 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1362 can fit in an 11 bit immediate field. This is an acceptable DImode
1363 operand for the movcc instructions. */
1364 /* ??? Replace with arith11_operand? */
1365
1366 int
1367 arith11_double_operand (rtx op, enum machine_mode mode)
1368 {
1369 return (register_operand (op, mode)
1370 || (GET_CODE (op) == CONST_DOUBLE
1371 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1372 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1373 && ((CONST_DOUBLE_HIGH (op) == -1
1374 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1375 || (CONST_DOUBLE_HIGH (op) == 0
1376 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1377 || (GET_CODE (op) == CONST_INT
1378 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1379 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1380 }
1381
1382 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1383 can fit in an 10 bit immediate field. This is an acceptable DImode
1384 operand for the movrcc instructions. */
1385 /* ??? Replace with arith10_operand? */
1386
1387 int
1388 arith10_double_operand (rtx op, enum machine_mode mode)
1389 {
1390 return (register_operand (op, mode)
1391 || (GET_CODE (op) == CONST_DOUBLE
1392 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1393 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1394 && ((CONST_DOUBLE_HIGH (op) == -1
1395 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1396 || (CONST_DOUBLE_HIGH (op) == 0
1397 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1398 || (GET_CODE (op) == CONST_INT
1399 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1400 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1401 }
1402
1403 /* Return truth value of whether OP is an integer which fits the
1404 range constraining immediate operands in most three-address insns,
1405 which have a 13 bit immediate field. */
1406
1407 int
1408 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1409 {
1410 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1411 }
1412
1413 int
1414 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1415 {
1416 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1417 || (GET_CODE (op) == CONST_DOUBLE
1418 && CONST_DOUBLE_HIGH (op) == 0
1419 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1420 }
1421
1422 /* Recognize operand values for the umul instruction. That instruction sign
1423 extends immediate values just like all other sparc instructions, but
1424 interprets the extended result as an unsigned number. */
1425
1426 int
1427 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1428 {
1429 #if HOST_BITS_PER_WIDE_INT > 32
1430 /* All allowed constants will fit a CONST_INT. */
1431 return (GET_CODE (op) == CONST_INT
1432 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1433 || (INTVAL (op) >= 0xFFFFF000
1434 && INTVAL (op) <= 0xFFFFFFFF)));
1435 #else
1436 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1437 || (GET_CODE (op) == CONST_DOUBLE
1438 && CONST_DOUBLE_HIGH (op) == 0
1439 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1440 #endif
1441 }
1442
1443 int
1444 uns_arith_operand (rtx op, enum machine_mode mode)
1445 {
1446 return register_operand (op, mode) || uns_small_int (op, mode);
1447 }
1448
1449 /* Return truth value of statement that OP is a call-clobbered register. */
1450 int
1451 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1452 {
1453 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1454 }
1455
1456 /* Return 1 if OP is a valid operand for the source of a move insn. */
1457
1458 int
1459 input_operand (rtx op, enum machine_mode mode)
1460 {
1461 /* If both modes are non-void they must be the same. */
1462 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1463 return 0;
1464
1465 /* Allow any one instruction integer constant, and all CONST_INT
1466 variants when we are working in DImode and !arch64. */
1467 if (GET_MODE_CLASS (mode) == MODE_INT
1468 && ((GET_CODE (op) == CONST_INT
1469 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1470 || SPARC_SIMM13_P (INTVAL (op))
1471 || (mode == DImode
1472 && ! TARGET_ARCH64)))
1473 || (TARGET_ARCH64
1474 && GET_CODE (op) == CONST_DOUBLE
1475 && ((CONST_DOUBLE_HIGH (op) == 0
1476 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1477 ||
1478 #if HOST_BITS_PER_WIDE_INT == 64
1479 (CONST_DOUBLE_HIGH (op) == 0
1480 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1481 #else
1482 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1483 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1484 && CONST_DOUBLE_HIGH (op) == 0)
1485 || (CONST_DOUBLE_HIGH (op) == -1
1486 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1487 #endif
1488 ))))
1489 return 1;
1490
1491 /* If !arch64 and this is a DImode const, allow it so that
1492 the splits can be generated. */
1493 if (! TARGET_ARCH64
1494 && mode == DImode
1495 && GET_CODE (op) == CONST_DOUBLE)
1496 return 1;
1497
1498 if (register_operand (op, mode))
1499 return 1;
1500
1501 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1502 && GET_CODE (op) == CONST_DOUBLE)
1503 return 1;
1504
1505 /* If this is a SUBREG, look inside so that we handle
1506 paradoxical ones. */
1507 if (GET_CODE (op) == SUBREG)
1508 op = SUBREG_REG (op);
1509
1510 /* Check for valid MEM forms. */
1511 if (GET_CODE (op) == MEM)
1512 {
1513 rtx inside = XEXP (op, 0);
1514
1515 if (GET_CODE (inside) == LO_SUM)
1516 {
1517 /* We can't allow these because all of the splits
1518 (eventually as they trickle down into DFmode
1519 splits) require offsettable memory references. */
1520 if (! TARGET_V9
1521 && GET_MODE (op) == TFmode)
1522 return 0;
1523
1524 return (register_operand (XEXP (inside, 0), Pmode)
1525 && CONSTANT_P (XEXP (inside, 1)));
1526 }
1527 return memory_address_p (mode, inside);
1528 }
1529
1530 return 0;
1531 }
1532
1533 /* Return 1 if OP is valid for the lhs of a compare insn. */
1534
1535 int
1536 compare_operand (rtx op, enum machine_mode mode)
1537 {
1538 if (GET_CODE (op) == ZERO_EXTRACT)
1539 return (register_operand (XEXP (op, 0), mode)
1540 && small_int_or_double (XEXP (op, 1), mode)
1541 && small_int_or_double (XEXP (op, 2), mode)
1542 /* This matches cmp_zero_extract. */
1543 && ((mode == SImode
1544 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1545 && INTVAL (XEXP (op, 2)) > 19)
1546 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1547 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1548 /* This matches cmp_zero_extract_sp64. */
1549 || (mode == DImode
1550 && TARGET_ARCH64
1551 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1552 && INTVAL (XEXP (op, 2)) > 51)
1553 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1554 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1555 else
1556 return register_operand (op, mode);
1557 }
1558
1559 \f
1560 /* We know it can't be done in one insn when we get here,
1561 the movsi expander guarantees this. */
1562 void
1563 sparc_emit_set_const32 (rtx op0, rtx op1)
1564 {
1565 enum machine_mode mode = GET_MODE (op0);
1566 rtx temp;
1567
1568 if (GET_CODE (op1) == CONST_INT)
1569 {
1570 HOST_WIDE_INT value = INTVAL (op1);
1571
1572 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1573 || SPARC_SIMM13_P (value))
1574 abort ();
1575 }
1576
1577 /* Full 2-insn decomposition is needed. */
1578 if (reload_in_progress || reload_completed)
1579 temp = op0;
1580 else
1581 temp = gen_reg_rtx (mode);
1582
1583 if (GET_CODE (op1) == CONST_INT)
1584 {
1585 /* Emit them as real moves instead of a HIGH/LO_SUM,
1586 this way CSE can see everything and reuse intermediate
1587 values if it wants. */
1588 if (TARGET_ARCH64
1589 && HOST_BITS_PER_WIDE_INT != 64
1590 && (INTVAL (op1) & 0x80000000) != 0)
1591 emit_insn (gen_rtx_SET
1592 (VOIDmode, temp,
1593 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1594 0, DImode)));
1595 else
1596 emit_insn (gen_rtx_SET (VOIDmode, temp,
1597 GEN_INT (INTVAL (op1)
1598 & ~(HOST_WIDE_INT)0x3ff)));
1599
1600 emit_insn (gen_rtx_SET (VOIDmode,
1601 op0,
1602 gen_rtx_IOR (mode, temp,
1603 GEN_INT (INTVAL (op1) & 0x3ff))));
1604 }
1605 else
1606 {
1607 /* A symbol, emit in the traditional way. */
1608 emit_insn (gen_rtx_SET (VOIDmode, temp,
1609 gen_rtx_HIGH (mode, op1)));
1610 emit_insn (gen_rtx_SET (VOIDmode,
1611 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1612
1613 }
1614 }
1615
1616 \f
1617 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1618 If TEMP is non-zero, we are forbidden to use any other scratch
1619 registers. Otherwise, we are allowed to generate them as needed.
1620
1621 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1622 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1623 void
1624 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1625 {
1626 rtx temp1, temp2, temp3, temp4, temp5;
1627 rtx ti_temp = 0;
1628
1629 if (temp && GET_MODE (temp) == TImode)
1630 {
1631 ti_temp = temp;
1632 temp = gen_rtx_REG (DImode, REGNO (temp));
1633 }
1634
1635 /* SPARC-V9 code-model support. */
1636 switch (sparc_cmodel)
1637 {
1638 case CM_MEDLOW:
1639 /* The range spanned by all instructions in the object is less
1640 than 2^31 bytes (2GB) and the distance from any instruction
1641 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1642 than 2^31 bytes (2GB).
1643
1644 The executable must be in the low 4TB of the virtual address
1645 space.
1646
1647 sethi %hi(symbol), %temp1
1648 or %temp1, %lo(symbol), %reg */
1649 if (temp)
1650 temp1 = temp; /* op0 is allowed. */
1651 else
1652 temp1 = gen_reg_rtx (DImode);
1653
1654 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1655 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1656 break;
1657
1658 case CM_MEDMID:
1659 /* The range spanned by all instructions in the object is less
1660 than 2^31 bytes (2GB) and the distance from any instruction
1661 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1662 than 2^31 bytes (2GB).
1663
1664 The executable must be in the low 16TB of the virtual address
1665 space.
1666
1667 sethi %h44(symbol), %temp1
1668 or %temp1, %m44(symbol), %temp2
1669 sllx %temp2, 12, %temp3
1670 or %temp3, %l44(symbol), %reg */
1671 if (temp)
1672 {
1673 temp1 = op0;
1674 temp2 = op0;
1675 temp3 = temp; /* op0 is allowed. */
1676 }
1677 else
1678 {
1679 temp1 = gen_reg_rtx (DImode);
1680 temp2 = gen_reg_rtx (DImode);
1681 temp3 = gen_reg_rtx (DImode);
1682 }
1683
1684 emit_insn (gen_seth44 (temp1, op1));
1685 emit_insn (gen_setm44 (temp2, temp1, op1));
1686 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1687 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1688 emit_insn (gen_setl44 (op0, temp3, op1));
1689 break;
1690
1691 case CM_MEDANY:
1692 /* The range spanned by all instructions in the object is less
1693 than 2^31 bytes (2GB) and the distance from any instruction
1694 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1695 than 2^31 bytes (2GB).
1696
1697 The executable can be placed anywhere in the virtual address
1698 space.
1699
1700 sethi %hh(symbol), %temp1
1701 sethi %lm(symbol), %temp2
1702 or %temp1, %hm(symbol), %temp3
1703 sllx %temp3, 32, %temp4
1704 or %temp4, %temp2, %temp5
1705 or %temp5, %lo(symbol), %reg */
1706 if (temp)
1707 {
1708 /* It is possible that one of the registers we got for operands[2]
1709 might coincide with that of operands[0] (which is why we made
1710 it TImode). Pick the other one to use as our scratch. */
1711 if (rtx_equal_p (temp, op0))
1712 {
1713 if (ti_temp)
1714 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1715 else
1716 abort();
1717 }
1718 temp1 = op0;
1719 temp2 = temp; /* op0 is _not_ allowed, see above. */
1720 temp3 = op0;
1721 temp4 = op0;
1722 temp5 = op0;
1723 }
1724 else
1725 {
1726 temp1 = gen_reg_rtx (DImode);
1727 temp2 = gen_reg_rtx (DImode);
1728 temp3 = gen_reg_rtx (DImode);
1729 temp4 = gen_reg_rtx (DImode);
1730 temp5 = gen_reg_rtx (DImode);
1731 }
1732
1733 emit_insn (gen_sethh (temp1, op1));
1734 emit_insn (gen_setlm (temp2, op1));
1735 emit_insn (gen_sethm (temp3, temp1, op1));
1736 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1737 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1738 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1739 gen_rtx_PLUS (DImode, temp4, temp2)));
1740 emit_insn (gen_setlo (op0, temp5, op1));
1741 break;
1742
1743 case CM_EMBMEDANY:
1744 /* Old old old backwards compatibility kruft here.
1745 Essentially it is MEDLOW with a fixed 64-bit
1746 virtual base added to all data segment addresses.
1747 Text-segment stuff is computed like MEDANY, we can't
1748 reuse the code above because the relocation knobs
1749 look different.
1750
1751 Data segment: sethi %hi(symbol), %temp1
1752 add %temp1, EMBMEDANY_BASE_REG, %temp2
1753 or %temp2, %lo(symbol), %reg */
1754 if (data_segment_operand (op1, GET_MODE (op1)))
1755 {
1756 if (temp)
1757 {
1758 temp1 = temp; /* op0 is allowed. */
1759 temp2 = op0;
1760 }
1761 else
1762 {
1763 temp1 = gen_reg_rtx (DImode);
1764 temp2 = gen_reg_rtx (DImode);
1765 }
1766
1767 emit_insn (gen_embmedany_sethi (temp1, op1));
1768 emit_insn (gen_embmedany_brsum (temp2, temp1));
1769 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1770 }
1771
1772 /* Text segment: sethi %uhi(symbol), %temp1
1773 sethi %hi(symbol), %temp2
1774 or %temp1, %ulo(symbol), %temp3
1775 sllx %temp3, 32, %temp4
1776 or %temp4, %temp2, %temp5
1777 or %temp5, %lo(symbol), %reg */
1778 else
1779 {
1780 if (temp)
1781 {
1782 /* It is possible that one of the registers we got for operands[2]
1783 might coincide with that of operands[0] (which is why we made
1784 it TImode). Pick the other one to use as our scratch. */
1785 if (rtx_equal_p (temp, op0))
1786 {
1787 if (ti_temp)
1788 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1789 else
1790 abort();
1791 }
1792 temp1 = op0;
1793 temp2 = temp; /* op0 is _not_ allowed, see above. */
1794 temp3 = op0;
1795 temp4 = op0;
1796 temp5 = op0;
1797 }
1798 else
1799 {
1800 temp1 = gen_reg_rtx (DImode);
1801 temp2 = gen_reg_rtx (DImode);
1802 temp3 = gen_reg_rtx (DImode);
1803 temp4 = gen_reg_rtx (DImode);
1804 temp5 = gen_reg_rtx (DImode);
1805 }
1806
1807 emit_insn (gen_embmedany_textuhi (temp1, op1));
1808 emit_insn (gen_embmedany_texthi (temp2, op1));
1809 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1810 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1811 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1812 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1813 gen_rtx_PLUS (DImode, temp4, temp2)));
1814 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1815 }
1816 break;
1817
1818 default:
1819 abort();
1820 }
1821 }
1822
1823 /* These avoid problems when cross compiling. If we do not
1824 go through all this hair then the optimizer will see
1825 invalid REG_EQUAL notes or in some cases none at all. */
1826 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1827 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1828 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1829 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1830
1831 #if HOST_BITS_PER_WIDE_INT == 64
1832 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1833 #define GEN_INT64(__x) GEN_INT (__x)
1834 #else
1835 #define GEN_HIGHINT64(__x) \
1836 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1837 #define GEN_INT64(__x) \
1838 immed_double_const ((__x) & 0xffffffff, \
1839 ((__x) & 0x80000000 ? -1 : 0), DImode)
1840 #endif
1841
1842 /* The optimizer is not to assume anything about exactly
1843 which bits are set for a HIGH, they are unspecified.
1844 Unfortunately this leads to many missed optimizations
1845 during CSE. We mask out the non-HIGH bits, and matches
1846 a plain movdi, to alleviate this problem. */
1847 static void
1848 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1849 {
1850 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1851 }
1852
1853 static rtx
1854 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1855 {
1856 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1857 }
1858
1859 static rtx
1860 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1861 {
1862 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1863 }
1864
1865 static rtx
1866 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1867 {
1868 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1869 }
1870
1871 /* Worker routines for 64-bit constant formation on arch64.
1872 One of the key things to be doing in these emissions is
1873 to create as many temp REGs as possible. This makes it
1874 possible for half-built constants to be used later when
1875 such values are similar to something required later on.
1876 Without doing this, the optimizer cannot see such
1877 opportunities. */
1878
1879 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1880 unsigned HOST_WIDE_INT, int);
1881
1882 static void
1883 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1884 unsigned HOST_WIDE_INT low_bits, int is_neg)
1885 {
1886 unsigned HOST_WIDE_INT high_bits;
1887
1888 if (is_neg)
1889 high_bits = (~low_bits) & 0xffffffff;
1890 else
1891 high_bits = low_bits;
1892
1893 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1894 if (!is_neg)
1895 {
1896 emit_insn (gen_rtx_SET (VOIDmode, op0,
1897 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1898 }
1899 else
1900 {
1901 /* If we are XOR'ing with -1, then we should emit a one's complement
1902 instead. This way the combiner will notice logical operations
1903 such as ANDN later on and substitute. */
1904 if ((low_bits & 0x3ff) == 0x3ff)
1905 {
1906 emit_insn (gen_rtx_SET (VOIDmode, op0,
1907 gen_rtx_NOT (DImode, temp)));
1908 }
1909 else
1910 {
1911 emit_insn (gen_rtx_SET (VOIDmode, op0,
1912 gen_safe_XOR64 (temp,
1913 (-(HOST_WIDE_INT)0x400
1914 | (low_bits & 0x3ff)))));
1915 }
1916 }
1917 }
1918
1919 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1920 unsigned HOST_WIDE_INT, int);
1921
1922 static void
1923 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1924 unsigned HOST_WIDE_INT high_bits,
1925 unsigned HOST_WIDE_INT low_immediate,
1926 int shift_count)
1927 {
1928 rtx temp2 = op0;
1929
1930 if ((high_bits & 0xfffffc00) != 0)
1931 {
1932 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1933 if ((high_bits & ~0xfffffc00) != 0)
1934 emit_insn (gen_rtx_SET (VOIDmode, op0,
1935 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1936 else
1937 temp2 = temp;
1938 }
1939 else
1940 {
1941 emit_insn (gen_safe_SET64 (temp, high_bits));
1942 temp2 = temp;
1943 }
1944
1945 /* Now shift it up into place. */
1946 emit_insn (gen_rtx_SET (VOIDmode, op0,
1947 gen_rtx_ASHIFT (DImode, temp2,
1948 GEN_INT (shift_count))));
1949
1950 /* If there is a low immediate part piece, finish up by
1951 putting that in as well. */
1952 if (low_immediate != 0)
1953 emit_insn (gen_rtx_SET (VOIDmode, op0,
1954 gen_safe_OR64 (op0, low_immediate)));
1955 }
1956
1957 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1958 unsigned HOST_WIDE_INT);
1959
1960 /* Full 64-bit constant decomposition. Even though this is the
1961 'worst' case, we still optimize a few things away. */
1962 static void
1963 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1964 unsigned HOST_WIDE_INT high_bits,
1965 unsigned HOST_WIDE_INT low_bits)
1966 {
1967 rtx sub_temp;
1968
1969 if (reload_in_progress || reload_completed)
1970 sub_temp = op0;
1971 else
1972 sub_temp = gen_reg_rtx (DImode);
1973
1974 if ((high_bits & 0xfffffc00) != 0)
1975 {
1976 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1977 if ((high_bits & ~0xfffffc00) != 0)
1978 emit_insn (gen_rtx_SET (VOIDmode,
1979 sub_temp,
1980 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1981 else
1982 sub_temp = temp;
1983 }
1984 else
1985 {
1986 emit_insn (gen_safe_SET64 (temp, high_bits));
1987 sub_temp = temp;
1988 }
1989
1990 if (!reload_in_progress && !reload_completed)
1991 {
1992 rtx temp2 = gen_reg_rtx (DImode);
1993 rtx temp3 = gen_reg_rtx (DImode);
1994 rtx temp4 = gen_reg_rtx (DImode);
1995
1996 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1997 gen_rtx_ASHIFT (DImode, sub_temp,
1998 GEN_INT (32))));
1999
2000 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2001 if ((low_bits & ~0xfffffc00) != 0)
2002 {
2003 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2004 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2005 emit_insn (gen_rtx_SET (VOIDmode, op0,
2006 gen_rtx_PLUS (DImode, temp4, temp3)));
2007 }
2008 else
2009 {
2010 emit_insn (gen_rtx_SET (VOIDmode, op0,
2011 gen_rtx_PLUS (DImode, temp4, temp2)));
2012 }
2013 }
2014 else
2015 {
2016 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2017 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2018 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2019 int to_shift = 12;
2020
2021 /* We are in the middle of reload, so this is really
2022 painful. However we do still make an attempt to
2023 avoid emitting truly stupid code. */
2024 if (low1 != const0_rtx)
2025 {
2026 emit_insn (gen_rtx_SET (VOIDmode, op0,
2027 gen_rtx_ASHIFT (DImode, sub_temp,
2028 GEN_INT (to_shift))));
2029 emit_insn (gen_rtx_SET (VOIDmode, op0,
2030 gen_rtx_IOR (DImode, op0, low1)));
2031 sub_temp = op0;
2032 to_shift = 12;
2033 }
2034 else
2035 {
2036 to_shift += 12;
2037 }
2038 if (low2 != const0_rtx)
2039 {
2040 emit_insn (gen_rtx_SET (VOIDmode, op0,
2041 gen_rtx_ASHIFT (DImode, sub_temp,
2042 GEN_INT (to_shift))));
2043 emit_insn (gen_rtx_SET (VOIDmode, op0,
2044 gen_rtx_IOR (DImode, op0, low2)));
2045 sub_temp = op0;
2046 to_shift = 8;
2047 }
2048 else
2049 {
2050 to_shift += 8;
2051 }
2052 emit_insn (gen_rtx_SET (VOIDmode, op0,
2053 gen_rtx_ASHIFT (DImode, sub_temp,
2054 GEN_INT (to_shift))));
2055 if (low3 != const0_rtx)
2056 emit_insn (gen_rtx_SET (VOIDmode, op0,
2057 gen_rtx_IOR (DImode, op0, low3)));
2058 /* phew... */
2059 }
2060 }
2061
2062 /* Analyze a 64-bit constant for certain properties. */
2063 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2064 unsigned HOST_WIDE_INT,
2065 int *, int *, int *);
2066
2067 static void
2068 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2069 unsigned HOST_WIDE_INT low_bits,
2070 int *hbsp, int *lbsp, int *abbasp)
2071 {
2072 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2073 int i;
2074
2075 lowest_bit_set = highest_bit_set = -1;
2076 i = 0;
2077 do
2078 {
2079 if ((lowest_bit_set == -1)
2080 && ((low_bits >> i) & 1))
2081 lowest_bit_set = i;
2082 if ((highest_bit_set == -1)
2083 && ((high_bits >> (32 - i - 1)) & 1))
2084 highest_bit_set = (64 - i - 1);
2085 }
2086 while (++i < 32
2087 && ((highest_bit_set == -1)
2088 || (lowest_bit_set == -1)));
2089 if (i == 32)
2090 {
2091 i = 0;
2092 do
2093 {
2094 if ((lowest_bit_set == -1)
2095 && ((high_bits >> i) & 1))
2096 lowest_bit_set = i + 32;
2097 if ((highest_bit_set == -1)
2098 && ((low_bits >> (32 - i - 1)) & 1))
2099 highest_bit_set = 32 - i - 1;
2100 }
2101 while (++i < 32
2102 && ((highest_bit_set == -1)
2103 || (lowest_bit_set == -1)));
2104 }
2105 /* If there are no bits set this should have gone out
2106 as one instruction! */
2107 if (lowest_bit_set == -1
2108 || highest_bit_set == -1)
2109 abort ();
2110 all_bits_between_are_set = 1;
2111 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2112 {
2113 if (i < 32)
2114 {
2115 if ((low_bits & (1 << i)) != 0)
2116 continue;
2117 }
2118 else
2119 {
2120 if ((high_bits & (1 << (i - 32))) != 0)
2121 continue;
2122 }
2123 all_bits_between_are_set = 0;
2124 break;
2125 }
2126 *hbsp = highest_bit_set;
2127 *lbsp = lowest_bit_set;
2128 *abbasp = all_bits_between_are_set;
2129 }
2130
2131 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2132
2133 static int
2134 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2135 unsigned HOST_WIDE_INT low_bits)
2136 {
2137 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2138
2139 if (high_bits == 0
2140 || high_bits == 0xffffffff)
2141 return 1;
2142
2143 analyze_64bit_constant (high_bits, low_bits,
2144 &highest_bit_set, &lowest_bit_set,
2145 &all_bits_between_are_set);
2146
2147 if ((highest_bit_set == 63
2148 || lowest_bit_set == 0)
2149 && all_bits_between_are_set != 0)
2150 return 1;
2151
2152 if ((highest_bit_set - lowest_bit_set) < 21)
2153 return 1;
2154
2155 return 0;
2156 }
2157
2158 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2159 unsigned HOST_WIDE_INT,
2160 int, int);
2161
2162 static unsigned HOST_WIDE_INT
2163 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2164 unsigned HOST_WIDE_INT low_bits,
2165 int lowest_bit_set, int shift)
2166 {
2167 HOST_WIDE_INT hi, lo;
2168
2169 if (lowest_bit_set < 32)
2170 {
2171 lo = (low_bits >> lowest_bit_set) << shift;
2172 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2173 }
2174 else
2175 {
2176 lo = 0;
2177 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2178 }
2179 if (hi & lo)
2180 abort ();
2181 return (hi | lo);
2182 }
2183
2184 /* Here we are sure to be arch64 and this is an integer constant
2185 being loaded into a register. Emit the most efficient
2186 insn sequence possible. Detection of all the 1-insn cases
2187 has been done already. */
2188 void
2189 sparc_emit_set_const64 (rtx op0, rtx op1)
2190 {
2191 unsigned HOST_WIDE_INT high_bits, low_bits;
2192 int lowest_bit_set, highest_bit_set;
2193 int all_bits_between_are_set;
2194 rtx temp = 0;
2195
2196 /* Sanity check that we know what we are working with. */
2197 if (! TARGET_ARCH64)
2198 abort ();
2199
2200 if (GET_CODE (op0) != SUBREG)
2201 {
2202 if (GET_CODE (op0) != REG
2203 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2204 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2205 abort ();
2206 }
2207
2208 if (reload_in_progress || reload_completed)
2209 temp = op0;
2210
2211 if (GET_CODE (op1) != CONST_DOUBLE
2212 && GET_CODE (op1) != CONST_INT)
2213 {
2214 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2215 return;
2216 }
2217
2218 if (! temp)
2219 temp = gen_reg_rtx (DImode);
2220
2221 if (GET_CODE (op1) == CONST_DOUBLE)
2222 {
2223 #if HOST_BITS_PER_WIDE_INT == 64
2224 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2225 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2226 #else
2227 high_bits = CONST_DOUBLE_HIGH (op1);
2228 low_bits = CONST_DOUBLE_LOW (op1);
2229 #endif
2230 }
2231 else
2232 {
2233 #if HOST_BITS_PER_WIDE_INT == 64
2234 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2235 low_bits = (INTVAL (op1) & 0xffffffff);
2236 #else
2237 high_bits = ((INTVAL (op1) < 0) ?
2238 0xffffffff :
2239 0x00000000);
2240 low_bits = INTVAL (op1);
2241 #endif
2242 }
2243
2244 /* low_bits bits 0 --> 31
2245 high_bits bits 32 --> 63 */
2246
2247 analyze_64bit_constant (high_bits, low_bits,
2248 &highest_bit_set, &lowest_bit_set,
2249 &all_bits_between_are_set);
2250
2251 /* First try for a 2-insn sequence. */
2252
2253 /* These situations are preferred because the optimizer can
2254 * do more things with them:
2255 * 1) mov -1, %reg
2256 * sllx %reg, shift, %reg
2257 * 2) mov -1, %reg
2258 * srlx %reg, shift, %reg
2259 * 3) mov some_small_const, %reg
2260 * sllx %reg, shift, %reg
2261 */
2262 if (((highest_bit_set == 63
2263 || lowest_bit_set == 0)
2264 && all_bits_between_are_set != 0)
2265 || ((highest_bit_set - lowest_bit_set) < 12))
2266 {
2267 HOST_WIDE_INT the_const = -1;
2268 int shift = lowest_bit_set;
2269
2270 if ((highest_bit_set != 63
2271 && lowest_bit_set != 0)
2272 || all_bits_between_are_set == 0)
2273 {
2274 the_const =
2275 create_simple_focus_bits (high_bits, low_bits,
2276 lowest_bit_set, 0);
2277 }
2278 else if (lowest_bit_set == 0)
2279 shift = -(63 - highest_bit_set);
2280
2281 if (! SPARC_SIMM13_P (the_const))
2282 abort ();
2283
2284 emit_insn (gen_safe_SET64 (temp, the_const));
2285 if (shift > 0)
2286 emit_insn (gen_rtx_SET (VOIDmode,
2287 op0,
2288 gen_rtx_ASHIFT (DImode,
2289 temp,
2290 GEN_INT (shift))));
2291 else if (shift < 0)
2292 emit_insn (gen_rtx_SET (VOIDmode,
2293 op0,
2294 gen_rtx_LSHIFTRT (DImode,
2295 temp,
2296 GEN_INT (-shift))));
2297 else
2298 abort ();
2299 return;
2300 }
2301
2302 /* Now a range of 22 or less bits set somewhere.
2303 * 1) sethi %hi(focus_bits), %reg
2304 * sllx %reg, shift, %reg
2305 * 2) sethi %hi(focus_bits), %reg
2306 * srlx %reg, shift, %reg
2307 */
2308 if ((highest_bit_set - lowest_bit_set) < 21)
2309 {
2310 unsigned HOST_WIDE_INT focus_bits =
2311 create_simple_focus_bits (high_bits, low_bits,
2312 lowest_bit_set, 10);
2313
2314 if (! SPARC_SETHI_P (focus_bits))
2315 abort ();
2316
2317 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2318
2319 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2320 if (lowest_bit_set < 10)
2321 emit_insn (gen_rtx_SET (VOIDmode,
2322 op0,
2323 gen_rtx_LSHIFTRT (DImode, temp,
2324 GEN_INT (10 - lowest_bit_set))));
2325 else if (lowest_bit_set > 10)
2326 emit_insn (gen_rtx_SET (VOIDmode,
2327 op0,
2328 gen_rtx_ASHIFT (DImode, temp,
2329 GEN_INT (lowest_bit_set - 10))));
2330 else
2331 abort ();
2332 return;
2333 }
2334
2335 /* 1) sethi %hi(low_bits), %reg
2336 * or %reg, %lo(low_bits), %reg
2337 * 2) sethi %hi(~low_bits), %reg
2338 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2339 */
2340 if (high_bits == 0
2341 || high_bits == 0xffffffff)
2342 {
2343 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2344 (high_bits == 0xffffffff));
2345 return;
2346 }
2347
2348 /* Now, try 3-insn sequences. */
2349
2350 /* 1) sethi %hi(high_bits), %reg
2351 * or %reg, %lo(high_bits), %reg
2352 * sllx %reg, 32, %reg
2353 */
2354 if (low_bits == 0)
2355 {
2356 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2357 return;
2358 }
2359
2360 /* We may be able to do something quick
2361 when the constant is negated, so try that. */
2362 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2363 (~low_bits) & 0xfffffc00))
2364 {
2365 /* NOTE: The trailing bits get XOR'd so we need the
2366 non-negated bits, not the negated ones. */
2367 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2368
2369 if ((((~high_bits) & 0xffffffff) == 0
2370 && ((~low_bits) & 0x80000000) == 0)
2371 || (((~high_bits) & 0xffffffff) == 0xffffffff
2372 && ((~low_bits) & 0x80000000) != 0))
2373 {
2374 int fast_int = (~low_bits & 0xffffffff);
2375
2376 if ((SPARC_SETHI_P (fast_int)
2377 && (~high_bits & 0xffffffff) == 0)
2378 || SPARC_SIMM13_P (fast_int))
2379 emit_insn (gen_safe_SET64 (temp, fast_int));
2380 else
2381 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2382 }
2383 else
2384 {
2385 rtx negated_const;
2386 #if HOST_BITS_PER_WIDE_INT == 64
2387 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2388 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2389 #else
2390 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2391 (~high_bits) & 0xffffffff,
2392 DImode);
2393 #endif
2394 sparc_emit_set_const64 (temp, negated_const);
2395 }
2396
2397 /* If we are XOR'ing with -1, then we should emit a one's complement
2398 instead. This way the combiner will notice logical operations
2399 such as ANDN later on and substitute. */
2400 if (trailing_bits == 0x3ff)
2401 {
2402 emit_insn (gen_rtx_SET (VOIDmode, op0,
2403 gen_rtx_NOT (DImode, temp)));
2404 }
2405 else
2406 {
2407 emit_insn (gen_rtx_SET (VOIDmode,
2408 op0,
2409 gen_safe_XOR64 (temp,
2410 (-0x400 | trailing_bits))));
2411 }
2412 return;
2413 }
2414
2415 /* 1) sethi %hi(xxx), %reg
2416 * or %reg, %lo(xxx), %reg
2417 * sllx %reg, yyy, %reg
2418 *
2419 * ??? This is just a generalized version of the low_bits==0
2420 * thing above, FIXME...
2421 */
2422 if ((highest_bit_set - lowest_bit_set) < 32)
2423 {
2424 unsigned HOST_WIDE_INT focus_bits =
2425 create_simple_focus_bits (high_bits, low_bits,
2426 lowest_bit_set, 0);
2427
2428 /* We can't get here in this state. */
2429 if (highest_bit_set < 32
2430 || lowest_bit_set >= 32)
2431 abort ();
2432
2433 /* So what we know is that the set bits straddle the
2434 middle of the 64-bit word. */
2435 sparc_emit_set_const64_quick2 (op0, temp,
2436 focus_bits, 0,
2437 lowest_bit_set);
2438 return;
2439 }
2440
2441 /* 1) sethi %hi(high_bits), %reg
2442 * or %reg, %lo(high_bits), %reg
2443 * sllx %reg, 32, %reg
2444 * or %reg, low_bits, %reg
2445 */
2446 if (SPARC_SIMM13_P(low_bits)
2447 && ((int)low_bits > 0))
2448 {
2449 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2450 return;
2451 }
2452
2453 /* The easiest way when all else fails, is full decomposition. */
2454 #if 0
2455 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2456 high_bits, low_bits, ~high_bits, ~low_bits);
2457 #endif
2458 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2459 }
2460
2461 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2462 return the mode to be used for the comparison. For floating-point,
2463 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2464 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2465 processing is needed. */
2466
2467 enum machine_mode
2468 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2469 {
2470 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2471 {
2472 switch (op)
2473 {
2474 case EQ:
2475 case NE:
2476 case UNORDERED:
2477 case ORDERED:
2478 case UNLT:
2479 case UNLE:
2480 case UNGT:
2481 case UNGE:
2482 case UNEQ:
2483 case LTGT:
2484 return CCFPmode;
2485
2486 case LT:
2487 case LE:
2488 case GT:
2489 case GE:
2490 return CCFPEmode;
2491
2492 default:
2493 abort ();
2494 }
2495 }
2496 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2497 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2498 {
2499 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2500 return CCX_NOOVmode;
2501 else
2502 return CC_NOOVmode;
2503 }
2504 else
2505 {
2506 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2507 return CCXmode;
2508 else
2509 return CCmode;
2510 }
2511 }
2512
2513 /* X and Y are two things to compare using CODE. Emit the compare insn and
2514 return the rtx for the cc reg in the proper mode. */
2515
2516 rtx
2517 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2518 {
2519 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2520 rtx cc_reg;
2521
2522 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2523 fcc regs (cse can't tell they're really call clobbered regs and will
2524 remove a duplicate comparison even if there is an intervening function
2525 call - it will then try to reload the cc reg via an int reg which is why
2526 we need the movcc patterns). It is possible to provide the movcc
2527 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2528 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2529 to tell cse that CCFPE mode registers (even pseudos) are call
2530 clobbered. */
2531
2532 /* ??? This is an experiment. Rather than making changes to cse which may
2533 or may not be easy/clean, we do our own cse. This is possible because
2534 we will generate hard registers. Cse knows they're call clobbered (it
2535 doesn't know the same thing about pseudos). If we guess wrong, no big
2536 deal, but if we win, great! */
2537
2538 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2539 #if 1 /* experiment */
2540 {
2541 int reg;
2542 /* We cycle through the registers to ensure they're all exercised. */
2543 static int next_fcc_reg = 0;
2544 /* Previous x,y for each fcc reg. */
2545 static rtx prev_args[4][2];
2546
2547 /* Scan prev_args for x,y. */
2548 for (reg = 0; reg < 4; reg++)
2549 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2550 break;
2551 if (reg == 4)
2552 {
2553 reg = next_fcc_reg;
2554 prev_args[reg][0] = x;
2555 prev_args[reg][1] = y;
2556 next_fcc_reg = (next_fcc_reg + 1) & 3;
2557 }
2558 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2559 }
2560 #else
2561 cc_reg = gen_reg_rtx (mode);
2562 #endif /* ! experiment */
2563 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2564 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2565 else
2566 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2567
2568 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2569 gen_rtx_COMPARE (mode, x, y)));
2570
2571 return cc_reg;
2572 }
2573
2574 /* This function is used for v9 only.
2575 CODE is the code for an Scc's comparison.
2576 OPERANDS[0] is the target of the Scc insn.
2577 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2578 been generated yet).
2579
2580 This function is needed to turn
2581
2582 (set (reg:SI 110)
2583 (gt (reg:CCX 100 %icc)
2584 (const_int 0)))
2585 into
2586 (set (reg:SI 110)
2587 (gt:DI (reg:CCX 100 %icc)
2588 (const_int 0)))
2589
2590 IE: The instruction recognizer needs to see the mode of the comparison to
2591 find the right instruction. We could use "gt:DI" right in the
2592 define_expand, but leaving it out allows us to handle DI, SI, etc.
2593
2594 We refer to the global sparc compare operands sparc_compare_op0 and
2595 sparc_compare_op1. */
2596
2597 int
2598 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2599 {
2600 rtx temp, op0, op1;
2601
2602 if (! TARGET_ARCH64
2603 && (GET_MODE (sparc_compare_op0) == DImode
2604 || GET_MODE (operands[0]) == DImode))
2605 return 0;
2606
2607 op0 = sparc_compare_op0;
2608 op1 = sparc_compare_op1;
2609
2610 /* Try to use the movrCC insns. */
2611 if (TARGET_ARCH64
2612 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2613 && op1 == const0_rtx
2614 && v9_regcmp_p (compare_code))
2615 {
2616 /* Special case for op0 != 0. This can be done with one instruction if
2617 operands[0] == sparc_compare_op0. */
2618
2619 if (compare_code == NE
2620 && GET_MODE (operands[0]) == DImode
2621 && rtx_equal_p (op0, operands[0]))
2622 {
2623 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2624 gen_rtx_IF_THEN_ELSE (DImode,
2625 gen_rtx_fmt_ee (compare_code, DImode,
2626 op0, const0_rtx),
2627 const1_rtx,
2628 operands[0])));
2629 return 1;
2630 }
2631
2632 if (reg_overlap_mentioned_p (operands[0], op0))
2633 {
2634 /* Handle the case where operands[0] == sparc_compare_op0.
2635 We "early clobber" the result. */
2636 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2637 emit_move_insn (op0, sparc_compare_op0);
2638 }
2639
2640 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2641 if (GET_MODE (op0) != DImode)
2642 {
2643 temp = gen_reg_rtx (DImode);
2644 convert_move (temp, op0, 0);
2645 }
2646 else
2647 temp = op0;
2648 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2649 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2650 gen_rtx_fmt_ee (compare_code, DImode,
2651 temp, const0_rtx),
2652 const1_rtx,
2653 operands[0])));
2654 return 1;
2655 }
2656 else
2657 {
2658 operands[1] = gen_compare_reg (compare_code, op0, op1);
2659
2660 switch (GET_MODE (operands[1]))
2661 {
2662 case CCmode :
2663 case CCXmode :
2664 case CCFPEmode :
2665 case CCFPmode :
2666 break;
2667 default :
2668 abort ();
2669 }
2670 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2671 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2672 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2673 gen_rtx_fmt_ee (compare_code,
2674 GET_MODE (operands[1]),
2675 operands[1], const0_rtx),
2676 const1_rtx, operands[0])));
2677 return 1;
2678 }
2679 }
2680
2681 /* Emit a conditional jump insn for the v9 architecture using comparison code
2682 CODE and jump target LABEL.
2683 This function exists to take advantage of the v9 brxx insns. */
2684
2685 void
2686 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2687 {
2688 emit_jump_insn (gen_rtx_SET (VOIDmode,
2689 pc_rtx,
2690 gen_rtx_IF_THEN_ELSE (VOIDmode,
2691 gen_rtx_fmt_ee (code, GET_MODE (op0),
2692 op0, const0_rtx),
2693 gen_rtx_LABEL_REF (VOIDmode, label),
2694 pc_rtx)));
2695 }
2696
2697 /* Generate a DFmode part of a hard TFmode register.
2698 REG is the TFmode hard register, LOW is 1 for the
2699 low 64bit of the register and 0 otherwise.
2700 */
2701 rtx
2702 gen_df_reg (rtx reg, int low)
2703 {
2704 int regno = REGNO (reg);
2705
2706 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2707 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2708 return gen_rtx_REG (DFmode, regno);
2709 }
2710 \f
2711 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2712 Unlike normal calls, TFmode operands are passed by reference. It is
2713 assumed that no more than 3 operands are required. */
2714
2715 static void
2716 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2717 {
2718 rtx ret_slot = NULL, arg[3], func_sym;
2719 int i;
2720
2721 /* We only expect to be called for conversions, unary, and binary ops. */
2722 if (nargs < 2 || nargs > 3)
2723 abort ();
2724
2725 for (i = 0; i < nargs; ++i)
2726 {
2727 rtx this_arg = operands[i];
2728 rtx this_slot;
2729
2730 /* TFmode arguments and return values are passed by reference. */
2731 if (GET_MODE (this_arg) == TFmode)
2732 {
2733 int force_stack_temp;
2734
2735 force_stack_temp = 0;
2736 if (TARGET_BUGGY_QP_LIB && i == 0)
2737 force_stack_temp = 1;
2738
2739 if (GET_CODE (this_arg) == MEM
2740 && ! force_stack_temp)
2741 this_arg = XEXP (this_arg, 0);
2742 else if (CONSTANT_P (this_arg)
2743 && ! force_stack_temp)
2744 {
2745 this_slot = force_const_mem (TFmode, this_arg);
2746 this_arg = XEXP (this_slot, 0);
2747 }
2748 else
2749 {
2750 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2751
2752 /* Operand 0 is the return value. We'll copy it out later. */
2753 if (i > 0)
2754 emit_move_insn (this_slot, this_arg);
2755 else
2756 ret_slot = this_slot;
2757
2758 this_arg = XEXP (this_slot, 0);
2759 }
2760 }
2761
2762 arg[i] = this_arg;
2763 }
2764
2765 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2766
2767 if (GET_MODE (operands[0]) == TFmode)
2768 {
2769 if (nargs == 2)
2770 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2771 arg[0], GET_MODE (arg[0]),
2772 arg[1], GET_MODE (arg[1]));
2773 else
2774 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2775 arg[0], GET_MODE (arg[0]),
2776 arg[1], GET_MODE (arg[1]),
2777 arg[2], GET_MODE (arg[2]));
2778
2779 if (ret_slot)
2780 emit_move_insn (operands[0], ret_slot);
2781 }
2782 else
2783 {
2784 rtx ret;
2785
2786 if (nargs != 2)
2787 abort ();
2788
2789 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2790 GET_MODE (operands[0]), 1,
2791 arg[1], GET_MODE (arg[1]));
2792
2793 if (ret != operands[0])
2794 emit_move_insn (operands[0], ret);
2795 }
2796 }
2797
2798 /* Expand soft-float TFmode calls to sparc abi routines. */
2799
2800 static void
2801 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2802 {
2803 const char *func;
2804
2805 switch (code)
2806 {
2807 case PLUS:
2808 func = "_Qp_add";
2809 break;
2810 case MINUS:
2811 func = "_Qp_sub";
2812 break;
2813 case MULT:
2814 func = "_Qp_mul";
2815 break;
2816 case DIV:
2817 func = "_Qp_div";
2818 break;
2819 default:
2820 abort ();
2821 }
2822
2823 emit_soft_tfmode_libcall (func, 3, operands);
2824 }
2825
2826 static void
2827 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2828 {
2829 const char *func;
2830
2831 switch (code)
2832 {
2833 case SQRT:
2834 func = "_Qp_sqrt";
2835 break;
2836 default:
2837 abort ();
2838 }
2839
2840 emit_soft_tfmode_libcall (func, 2, operands);
2841 }
2842
2843 static void
2844 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2845 {
2846 const char *func;
2847
2848 switch (code)
2849 {
2850 case FLOAT_EXTEND:
2851 switch (GET_MODE (operands[1]))
2852 {
2853 case SFmode:
2854 func = "_Qp_stoq";
2855 break;
2856 case DFmode:
2857 func = "_Qp_dtoq";
2858 break;
2859 default:
2860 abort ();
2861 }
2862 break;
2863
2864 case FLOAT_TRUNCATE:
2865 switch (GET_MODE (operands[0]))
2866 {
2867 case SFmode:
2868 func = "_Qp_qtos";
2869 break;
2870 case DFmode:
2871 func = "_Qp_qtod";
2872 break;
2873 default:
2874 abort ();
2875 }
2876 break;
2877
2878 case FLOAT:
2879 switch (GET_MODE (operands[1]))
2880 {
2881 case SImode:
2882 func = "_Qp_itoq";
2883 break;
2884 case DImode:
2885 func = "_Qp_xtoq";
2886 break;
2887 default:
2888 abort ();
2889 }
2890 break;
2891
2892 case UNSIGNED_FLOAT:
2893 switch (GET_MODE (operands[1]))
2894 {
2895 case SImode:
2896 func = "_Qp_uitoq";
2897 break;
2898 case DImode:
2899 func = "_Qp_uxtoq";
2900 break;
2901 default:
2902 abort ();
2903 }
2904 break;
2905
2906 case FIX:
2907 switch (GET_MODE (operands[0]))
2908 {
2909 case SImode:
2910 func = "_Qp_qtoi";
2911 break;
2912 case DImode:
2913 func = "_Qp_qtox";
2914 break;
2915 default:
2916 abort ();
2917 }
2918 break;
2919
2920 case UNSIGNED_FIX:
2921 switch (GET_MODE (operands[0]))
2922 {
2923 case SImode:
2924 func = "_Qp_qtoui";
2925 break;
2926 case DImode:
2927 func = "_Qp_qtoux";
2928 break;
2929 default:
2930 abort ();
2931 }
2932 break;
2933
2934 default:
2935 abort ();
2936 }
2937
2938 emit_soft_tfmode_libcall (func, 2, operands);
2939 }
2940
2941 /* Expand a hard-float tfmode operation. All arguments must be in
2942 registers. */
2943
2944 static void
2945 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2946 {
2947 rtx op, dest;
2948
2949 if (GET_RTX_CLASS (code) == RTX_UNARY)
2950 {
2951 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2952 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2953 }
2954 else
2955 {
2956 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2957 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2958 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2959 operands[1], operands[2]);
2960 }
2961
2962 if (register_operand (operands[0], VOIDmode))
2963 dest = operands[0];
2964 else
2965 dest = gen_reg_rtx (GET_MODE (operands[0]));
2966
2967 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2968
2969 if (dest != operands[0])
2970 emit_move_insn (operands[0], dest);
2971 }
2972
2973 void
2974 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2975 {
2976 if (TARGET_HARD_QUAD)
2977 emit_hard_tfmode_operation (code, operands);
2978 else
2979 emit_soft_tfmode_binop (code, operands);
2980 }
2981
2982 void
2983 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2984 {
2985 if (TARGET_HARD_QUAD)
2986 emit_hard_tfmode_operation (code, operands);
2987 else
2988 emit_soft_tfmode_unop (code, operands);
2989 }
2990
2991 void
2992 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2993 {
2994 if (TARGET_HARD_QUAD)
2995 emit_hard_tfmode_operation (code, operands);
2996 else
2997 emit_soft_tfmode_cvt (code, operands);
2998 }
2999 \f
3000 /* Return nonzero if a branch/jump/call instruction will be emitting
3001 nop into its delay slot. */
3002
3003 int
3004 empty_delay_slot (rtx insn)
3005 {
3006 rtx seq;
3007
3008 /* If no previous instruction (should not happen), return true. */
3009 if (PREV_INSN (insn) == NULL)
3010 return 1;
3011
3012 seq = NEXT_INSN (PREV_INSN (insn));
3013 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3014 return 0;
3015
3016 return 1;
3017 }
3018
3019 /* Return nonzero if TRIAL can go into the call delay slot. */
3020
3021 int
3022 tls_call_delay (rtx trial)
3023 {
3024 rtx pat, unspec;
3025
3026 /* Binutils allows
3027 call __tls_get_addr, %tgd_call (foo)
3028 add %l7, %o0, %o0, %tgd_add (foo)
3029 while Sun as/ld does not. */
3030 if (TARGET_GNU_TLS || !TARGET_TLS)
3031 return 1;
3032
3033 pat = PATTERN (trial);
3034 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3035 return 1;
3036
3037 unspec = XEXP (SET_DEST (pat), 1);
3038 if (GET_CODE (unspec) != UNSPEC
3039 || (XINT (unspec, 1) != UNSPEC_TLSGD
3040 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3041 return 1;
3042
3043 return 0;
3044 }
3045
3046 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3047 instruction. RETURN_P is true if the v9 variant 'return' is to be
3048 considered in the test too.
3049
3050 TRIAL must be a SET whose destination is a REG appropriate for the
3051 'restore' instruction or, if RETURN_P is true, for the 'return'
3052 instruction. */
3053
3054 static int
3055 eligible_for_restore_insn (rtx trial, bool return_p)
3056 {
3057 rtx pat = PATTERN (trial);
3058 rtx src = SET_SRC (pat);
3059
3060 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3061 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3062 && arith_operand (src, GET_MODE (src)))
3063 {
3064 if (TARGET_ARCH64)
3065 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3066 else
3067 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3068 }
3069
3070 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3071 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3072 && arith_double_operand (src, GET_MODE (src)))
3073 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3074
3075 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3076 else if (! TARGET_FPU && register_operand (src, SFmode))
3077 return 1;
3078
3079 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3080 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3081 return 1;
3082
3083 /* If we have the 'return' instruction, anything that does not use
3084 local or output registers and can go into a delay slot wins. */
3085 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3086 && (get_attr_in_uncond_branch_delay (trial)
3087 == IN_UNCOND_BRANCH_DELAY_TRUE))
3088 return 1;
3089
3090 /* The 'restore src1,src2,dest' pattern for SImode. */
3091 else if (GET_CODE (src) == PLUS
3092 && register_operand (XEXP (src, 0), SImode)
3093 && arith_operand (XEXP (src, 1), SImode))
3094 return 1;
3095
3096 /* The 'restore src1,src2,dest' pattern for DImode. */
3097 else if (GET_CODE (src) == PLUS
3098 && register_operand (XEXP (src, 0), DImode)
3099 && arith_double_operand (XEXP (src, 1), DImode))
3100 return 1;
3101
3102 /* The 'restore src1,%lo(src2),dest' pattern. */
3103 else if (GET_CODE (src) == LO_SUM
3104 && ! TARGET_CM_MEDMID
3105 && ((register_operand (XEXP (src, 0), SImode)
3106 && immediate_operand (XEXP (src, 1), SImode))
3107 || (TARGET_ARCH64
3108 && register_operand (XEXP (src, 0), DImode)
3109 && immediate_operand (XEXP (src, 1), DImode))))
3110 return 1;
3111
3112 /* The 'restore src,src,dest' pattern. */
3113 else if (GET_CODE (src) == ASHIFT
3114 && (register_operand (XEXP (src, 0), SImode)
3115 || register_operand (XEXP (src, 0), DImode))
3116 && XEXP (src, 1) == const1_rtx)
3117 return 1;
3118
3119 return 0;
3120 }
3121
3122 /* Return nonzero if TRIAL can go into the function return's
3123 delay slot. */
3124
3125 int
3126 eligible_for_return_delay (rtx trial)
3127 {
3128 int leaf_function_p = current_function_uses_only_leaf_regs;
3129 rtx pat;
3130
3131 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3132 return 0;
3133
3134 if (get_attr_length (trial) != 1)
3135 return 0;
3136
3137 /* If there are any call-saved registers, we should scan TRIAL if it
3138 does not reference them. For now just make it easy. */
3139 if (num_gfregs)
3140 return 0;
3141
3142 /* If the function uses __builtin_eh_return, the eh_return machinery
3143 occupies the delay slot. */
3144 if (current_function_calls_eh_return)
3145 return 0;
3146
3147 /* In the case of a true leaf function, anything can go into the slot. */
3148 if (leaf_function_p)
3149 return get_attr_in_uncond_branch_delay (trial)
3150 == IN_UNCOND_BRANCH_DELAY_TRUE;
3151
3152 pat = PATTERN (trial);
3153
3154 /* Otherwise, only operations which can be done in tandem with
3155 a `restore' or `return' insn can go into the delay slot. */
3156 if (GET_CODE (SET_DEST (pat)) != REG
3157 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3158 return 0;
3159
3160 /* If this instruction sets up floating point register and we have a return
3161 instruction, it can probably go in. But restore will not work
3162 with FP_REGS. */
3163 if (REGNO (SET_DEST (pat)) >= 32)
3164 return (TARGET_V9
3165 && ! epilogue_renumber (&pat, 1)
3166 && (get_attr_in_uncond_branch_delay (trial)
3167 == IN_UNCOND_BRANCH_DELAY_TRUE));
3168
3169 return eligible_for_restore_insn (trial, true);
3170 }
3171
3172 /* Return nonzero if TRIAL can go into the sibling call's
3173 delay slot. */
3174
3175 int
3176 eligible_for_sibcall_delay (rtx trial)
3177 {
3178 int leaf_function_p = current_function_uses_only_leaf_regs;
3179 rtx pat;
3180
3181 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3182 return 0;
3183
3184 if (get_attr_length (trial) != 1)
3185 return 0;
3186
3187 pat = PATTERN (trial);
3188
3189 if (leaf_function_p)
3190 {
3191 /* If the tail call is done using the call instruction,
3192 we have to restore %o7 in the delay slot. */
3193 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3194 return 0;
3195
3196 /* %g1 is used to build the function address */
3197 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3198 return 0;
3199
3200 return 1;
3201 }
3202
3203 /* Otherwise, only operations which can be done in tandem with
3204 a `restore' insn can go into the delay slot. */
3205 if (GET_CODE (SET_DEST (pat)) != REG
3206 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3207 || REGNO (SET_DEST (pat)) >= 32)
3208 return 0;
3209
3210 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3211 in most cases. */
3212 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3213 return 0;
3214
3215 return eligible_for_restore_insn (trial, false);
3216 }
3217
3218 int
3219 short_branch (int uid1, int uid2)
3220 {
3221 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3222
3223 /* Leave a few words of "slop". */
3224 if (delta >= -1023 && delta <= 1022)
3225 return 1;
3226
3227 return 0;
3228 }
3229
3230 /* Return nonzero if REG is not used after INSN.
3231 We assume REG is a reload reg, and therefore does
3232 not live past labels or calls or jumps. */
3233 int
3234 reg_unused_after (rtx reg, rtx insn)
3235 {
3236 enum rtx_code code, prev_code = UNKNOWN;
3237
3238 while ((insn = NEXT_INSN (insn)))
3239 {
3240 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3241 return 1;
3242
3243 code = GET_CODE (insn);
3244 if (GET_CODE (insn) == CODE_LABEL)
3245 return 1;
3246
3247 if (INSN_P (insn))
3248 {
3249 rtx set = single_set (insn);
3250 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3251 if (set && in_src)
3252 return 0;
3253 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3254 return 1;
3255 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3256 return 0;
3257 }
3258 prev_code = code;
3259 }
3260 return 1;
3261 }
3262 \f
3263 /* Determine if it's legal to put X into the constant pool. This
3264 is not possible if X contains the address of a symbol that is
3265 not constant (TLS) or not known at final link time (PIC). */
3266
3267 static bool
3268 sparc_cannot_force_const_mem (rtx x)
3269 {
3270 switch (GET_CODE (x))
3271 {
3272 case CONST_INT:
3273 case CONST_DOUBLE:
3274 /* Accept all non-symbolic constants. */
3275 return false;
3276
3277 case LABEL_REF:
3278 /* Labels are OK iff we are non-PIC. */
3279 return flag_pic != 0;
3280
3281 case SYMBOL_REF:
3282 /* 'Naked' TLS symbol references are never OK,
3283 non-TLS symbols are OK iff we are non-PIC. */
3284 if (SYMBOL_REF_TLS_MODEL (x))
3285 return true;
3286 else
3287 return flag_pic != 0;
3288
3289 case CONST:
3290 return sparc_cannot_force_const_mem (XEXP (x, 0));
3291 case PLUS:
3292 case MINUS:
3293 return sparc_cannot_force_const_mem (XEXP (x, 0))
3294 || sparc_cannot_force_const_mem (XEXP (x, 1));
3295 case UNSPEC:
3296 return true;
3297 default:
3298 abort ();
3299 }
3300 }
3301 \f
3302 /* The table we use to reference PIC data. */
3303 static GTY(()) rtx global_offset_table;
3304
3305 /* The function we use to get at it. */
3306 static GTY(()) rtx add_pc_to_pic_symbol;
3307 static GTY(()) char add_pc_to_pic_symbol_name[256];
3308
3309 /* Ensure that we are not using patterns that are not OK with PIC. */
3310
3311 int
3312 check_pic (int i)
3313 {
3314 switch (flag_pic)
3315 {
3316 case 1:
3317 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3318 || (GET_CODE (recog_data.operand[i]) == CONST
3319 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3320 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3321 == global_offset_table)
3322 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3323 == CONST))))
3324 abort ();
3325 case 2:
3326 default:
3327 return 1;
3328 }
3329 }
3330
3331 /* Return true if X is an address which needs a temporary register when
3332 reloaded while generating PIC code. */
3333
3334 int
3335 pic_address_needs_scratch (rtx x)
3336 {
3337 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3338 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3339 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3340 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3341 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3342 return 1;
3343
3344 return 0;
3345 }
3346
3347 /* Determine if a given RTX is a valid constant. We already know this
3348 satisfies CONSTANT_P. */
3349
3350 bool
3351 legitimate_constant_p (rtx x)
3352 {
3353 rtx inner;
3354
3355 switch (GET_CODE (x))
3356 {
3357 case SYMBOL_REF:
3358 /* TLS symbols are not constant. */
3359 if (SYMBOL_REF_TLS_MODEL (x))
3360 return false;
3361 break;
3362
3363 case CONST:
3364 inner = XEXP (x, 0);
3365
3366 /* Offsets of TLS symbols are never valid.
3367 Discourage CSE from creating them. */
3368 if (GET_CODE (inner) == PLUS
3369 && tls_symbolic_operand (XEXP (inner, 0)))
3370 return false;
3371 break;
3372
3373 case CONST_DOUBLE:
3374 if (GET_MODE (x) == VOIDmode)
3375 return true;
3376
3377 /* Floating point constants are generally not ok.
3378 The only exception is 0.0 in VIS. */
3379 if (TARGET_VIS
3380 && (GET_MODE (x) == SFmode
3381 || GET_MODE (x) == DFmode
3382 || GET_MODE (x) == TFmode)
3383 && fp_zero_operand (x, GET_MODE (x)))
3384 return true;
3385
3386 return false;
3387
3388 default:
3389 break;
3390 }
3391
3392 return true;
3393 }
3394
3395 /* Determine if a given RTX is a valid constant address. */
3396
3397 bool
3398 constant_address_p (rtx x)
3399 {
3400 switch (GET_CODE (x))
3401 {
3402 case LABEL_REF:
3403 case CONST_INT:
3404 case HIGH:
3405 return true;
3406
3407 case CONST:
3408 if (flag_pic && pic_address_needs_scratch (x))
3409 return false;
3410 return legitimate_constant_p (x);
3411
3412 case SYMBOL_REF:
3413 return !flag_pic && legitimate_constant_p (x);
3414
3415 default:
3416 return false;
3417 }
3418 }
3419
3420 /* Nonzero if the constant value X is a legitimate general operand
3421 when generating PIC code. It is given that flag_pic is on and
3422 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3423
3424 bool
3425 legitimate_pic_operand_p (rtx x)
3426 {
3427 if (pic_address_needs_scratch (x))
3428 return false;
3429 if (tls_symbolic_operand (x)
3430 || (GET_CODE (x) == CONST
3431 && GET_CODE (XEXP (x, 0)) == PLUS
3432 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3433 return false;
3434 return true;
3435 }
3436
3437 /* Return nonzero if ADDR is a valid memory address.
3438 STRICT specifies whether strict register checking applies. */
3439
3440 int
3441 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3442 {
3443 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3444
3445 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3446 rs1 = addr;
3447 else if (GET_CODE (addr) == PLUS)
3448 {
3449 rs1 = XEXP (addr, 0);
3450 rs2 = XEXP (addr, 1);
3451
3452 /* Canonicalize. REG comes first, if there are no regs,
3453 LO_SUM comes first. */
3454 if (!REG_P (rs1)
3455 && GET_CODE (rs1) != SUBREG
3456 && (REG_P (rs2)
3457 || GET_CODE (rs2) == SUBREG
3458 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3459 {
3460 rs1 = XEXP (addr, 1);
3461 rs2 = XEXP (addr, 0);
3462 }
3463
3464 if ((flag_pic == 1
3465 && rs1 == pic_offset_table_rtx
3466 && !REG_P (rs2)
3467 && GET_CODE (rs2) != SUBREG
3468 && GET_CODE (rs2) != LO_SUM
3469 && GET_CODE (rs2) != MEM
3470 && !tls_symbolic_operand (rs2)
3471 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3472 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3473 || ((REG_P (rs1)
3474 || GET_CODE (rs1) == SUBREG)
3475 && RTX_OK_FOR_OFFSET_P (rs2)))
3476 {
3477 imm1 = rs2;
3478 rs2 = NULL;
3479 }
3480 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3481 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3482 {
3483 /* We prohibit REG + REG for TFmode when there are no instructions
3484 which accept REG+REG instructions. We do this because REG+REG
3485 is not an offsetable address. If we get the situation in reload
3486 where source and destination of a movtf pattern are both MEMs with
3487 REG+REG address, then only one of them gets converted to an
3488 offsetable address. */
3489 if (mode == TFmode
3490 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3491 && TARGET_HARD_QUAD))
3492 return 0;
3493
3494 /* We prohibit REG + REG on ARCH32 if not optimizing for
3495 DFmode/DImode because then mem_min_alignment is likely to be zero
3496 after reload and the forced split would lack a matching splitter
3497 pattern. */
3498 if (TARGET_ARCH32 && !optimize
3499 && (mode == DFmode || mode == DImode))
3500 return 0;
3501 }
3502 else if (USE_AS_OFFSETABLE_LO10
3503 && GET_CODE (rs1) == LO_SUM
3504 && TARGET_ARCH64
3505 && ! TARGET_CM_MEDMID
3506 && RTX_OK_FOR_OLO10_P (rs2))
3507 {
3508 imm2 = rs2;
3509 rs2 = NULL;
3510 imm1 = XEXP (rs1, 1);
3511 rs1 = XEXP (rs1, 0);
3512 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3513 return 0;
3514 }
3515 }
3516 else if (GET_CODE (addr) == LO_SUM)
3517 {
3518 rs1 = XEXP (addr, 0);
3519 imm1 = XEXP (addr, 1);
3520
3521 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3522 return 0;
3523
3524 /* We can't allow TFmode, because an offset greater than or equal to the
3525 alignment (8) may cause the LO_SUM to overflow if !v9. */
3526 if (mode == TFmode && !TARGET_V9)
3527 return 0;
3528 }
3529 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3530 return 1;
3531 else
3532 return 0;
3533
3534 if (GET_CODE (rs1) == SUBREG)
3535 rs1 = SUBREG_REG (rs1);
3536 if (!REG_P (rs1))
3537 return 0;
3538
3539 if (rs2)
3540 {
3541 if (GET_CODE (rs2) == SUBREG)
3542 rs2 = SUBREG_REG (rs2);
3543 if (!REG_P (rs2))
3544 return 0;
3545 }
3546
3547 if (strict)
3548 {
3549 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3550 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3551 return 0;
3552 }
3553 else
3554 {
3555 if ((REGNO (rs1) >= 32
3556 && REGNO (rs1) != FRAME_POINTER_REGNUM
3557 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3558 || (rs2
3559 && (REGNO (rs2) >= 32
3560 && REGNO (rs2) != FRAME_POINTER_REGNUM
3561 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3562 return 0;
3563 }
3564 return 1;
3565 }
3566
3567 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3568
3569 static GTY(()) rtx sparc_tls_symbol;
3570 static rtx
3571 sparc_tls_get_addr (void)
3572 {
3573 if (!sparc_tls_symbol)
3574 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3575
3576 return sparc_tls_symbol;
3577 }
3578
3579 static rtx
3580 sparc_tls_got (void)
3581 {
3582 rtx temp;
3583 if (flag_pic)
3584 {
3585 current_function_uses_pic_offset_table = 1;
3586 return pic_offset_table_rtx;
3587 }
3588
3589 if (!global_offset_table)
3590 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3591 temp = gen_reg_rtx (Pmode);
3592 emit_move_insn (temp, global_offset_table);
3593 return temp;
3594 }
3595
3596
3597 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3598 this (thread-local) address. */
3599
3600 rtx
3601 legitimize_tls_address (rtx addr)
3602 {
3603 rtx temp1, temp2, temp3, ret, o0, got, insn;
3604
3605 if (no_new_pseudos)
3606 abort ();
3607
3608 if (GET_CODE (addr) == SYMBOL_REF)
3609 switch (SYMBOL_REF_TLS_MODEL (addr))
3610 {
3611 case TLS_MODEL_GLOBAL_DYNAMIC:
3612 start_sequence ();
3613 temp1 = gen_reg_rtx (SImode);
3614 temp2 = gen_reg_rtx (SImode);
3615 ret = gen_reg_rtx (Pmode);
3616 o0 = gen_rtx_REG (Pmode, 8);
3617 got = sparc_tls_got ();
3618 emit_insn (gen_tgd_hi22 (temp1, addr));
3619 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3620 if (TARGET_ARCH32)
3621 {
3622 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3623 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3624 addr, const1_rtx));
3625 }
3626 else
3627 {
3628 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3629 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3630 addr, const1_rtx));
3631 }
3632 CALL_INSN_FUNCTION_USAGE (insn)
3633 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3634 CALL_INSN_FUNCTION_USAGE (insn));
3635 insn = get_insns ();
3636 end_sequence ();
3637 emit_libcall_block (insn, ret, o0, addr);
3638 break;
3639
3640 case TLS_MODEL_LOCAL_DYNAMIC:
3641 start_sequence ();
3642 temp1 = gen_reg_rtx (SImode);
3643 temp2 = gen_reg_rtx (SImode);
3644 temp3 = gen_reg_rtx (Pmode);
3645 ret = gen_reg_rtx (Pmode);
3646 o0 = gen_rtx_REG (Pmode, 8);
3647 got = sparc_tls_got ();
3648 emit_insn (gen_tldm_hi22 (temp1));
3649 emit_insn (gen_tldm_lo10 (temp2, temp1));
3650 if (TARGET_ARCH32)
3651 {
3652 emit_insn (gen_tldm_add32 (o0, got, temp2));
3653 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3654 const1_rtx));
3655 }
3656 else
3657 {
3658 emit_insn (gen_tldm_add64 (o0, got, temp2));
3659 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3660 const1_rtx));
3661 }
3662 CALL_INSN_FUNCTION_USAGE (insn)
3663 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3664 CALL_INSN_FUNCTION_USAGE (insn));
3665 insn = get_insns ();
3666 end_sequence ();
3667 emit_libcall_block (insn, temp3, o0,
3668 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3669 UNSPEC_TLSLD_BASE));
3670 temp1 = gen_reg_rtx (SImode);
3671 temp2 = gen_reg_rtx (SImode);
3672 emit_insn (gen_tldo_hix22 (temp1, addr));
3673 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3674 if (TARGET_ARCH32)
3675 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3676 else
3677 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3678 break;
3679
3680 case TLS_MODEL_INITIAL_EXEC:
3681 temp1 = gen_reg_rtx (SImode);
3682 temp2 = gen_reg_rtx (SImode);
3683 temp3 = gen_reg_rtx (Pmode);
3684 got = sparc_tls_got ();
3685 emit_insn (gen_tie_hi22 (temp1, addr));
3686 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3687 if (TARGET_ARCH32)
3688 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3689 else
3690 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3691 if (TARGET_SUN_TLS)
3692 {
3693 ret = gen_reg_rtx (Pmode);
3694 if (TARGET_ARCH32)
3695 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3696 temp3, addr));
3697 else
3698 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3699 temp3, addr));
3700 }
3701 else
3702 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3703 break;
3704
3705 case TLS_MODEL_LOCAL_EXEC:
3706 temp1 = gen_reg_rtx (Pmode);
3707 temp2 = gen_reg_rtx (Pmode);
3708 if (TARGET_ARCH32)
3709 {
3710 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3711 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3712 }
3713 else
3714 {
3715 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3716 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3717 }
3718 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3719 break;
3720
3721 default:
3722 abort ();
3723 }
3724
3725 else
3726 abort (); /* for now ... */
3727
3728 return ret;
3729 }
3730
3731
3732 /* Legitimize PIC addresses. If the address is already position-independent,
3733 we return ORIG. Newly generated position-independent addresses go into a
3734 reg. This is REG if nonzero, otherwise we allocate register(s) as
3735 necessary. */
3736
3737 rtx
3738 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3739 rtx reg)
3740 {
3741 if (GET_CODE (orig) == SYMBOL_REF)
3742 {
3743 rtx pic_ref, address;
3744 rtx insn;
3745
3746 if (reg == 0)
3747 {
3748 if (reload_in_progress || reload_completed)
3749 abort ();
3750 else
3751 reg = gen_reg_rtx (Pmode);
3752 }
3753
3754 if (flag_pic == 2)
3755 {
3756 /* If not during reload, allocate another temp reg here for loading
3757 in the address, so that these instructions can be optimized
3758 properly. */
3759 rtx temp_reg = ((reload_in_progress || reload_completed)
3760 ? reg : gen_reg_rtx (Pmode));
3761
3762 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3763 won't get confused into thinking that these two instructions
3764 are loading in the true address of the symbol. If in the
3765 future a PIC rtx exists, that should be used instead. */
3766 if (Pmode == SImode)
3767 {
3768 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3769 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3770 }
3771 else
3772 {
3773 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3774 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3775 }
3776 address = temp_reg;
3777 }
3778 else
3779 address = orig;
3780
3781 pic_ref = gen_rtx_MEM (Pmode,
3782 gen_rtx_PLUS (Pmode,
3783 pic_offset_table_rtx, address));
3784 current_function_uses_pic_offset_table = 1;
3785 RTX_UNCHANGING_P (pic_ref) = 1;
3786 insn = emit_move_insn (reg, pic_ref);
3787 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3788 by loop. */
3789 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3790 REG_NOTES (insn));
3791 return reg;
3792 }
3793 else if (GET_CODE (orig) == CONST)
3794 {
3795 rtx base, offset;
3796
3797 if (GET_CODE (XEXP (orig, 0)) == PLUS
3798 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3799 return orig;
3800
3801 if (reg == 0)
3802 {
3803 if (reload_in_progress || reload_completed)
3804 abort ();
3805 else
3806 reg = gen_reg_rtx (Pmode);
3807 }
3808
3809 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3810 {
3811 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3812 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3813 base == reg ? 0 : reg);
3814 }
3815 else
3816 abort ();
3817
3818 if (GET_CODE (offset) == CONST_INT)
3819 {
3820 if (SMALL_INT (offset))
3821 return plus_constant (base, INTVAL (offset));
3822 else if (! reload_in_progress && ! reload_completed)
3823 offset = force_reg (Pmode, offset);
3824 else
3825 /* If we reach here, then something is seriously wrong. */
3826 abort ();
3827 }
3828 return gen_rtx_PLUS (Pmode, base, offset);
3829 }
3830 else if (GET_CODE (orig) == LABEL_REF)
3831 /* ??? Why do we do this? */
3832 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3833 the register is live instead, in case it is eliminated. */
3834 current_function_uses_pic_offset_table = 1;
3835
3836 return orig;
3837 }
3838
3839 /* Try machine-dependent ways of modifying an illegitimate address X
3840 to be legitimate. If we find one, return the new, valid address.
3841
3842 OLDX is the address as it was before break_out_memory_refs was called.
3843 In some cases it is useful to look at this to decide what needs to be done.
3844
3845 MODE is the mode of the operand pointed to by X. */
3846
3847 rtx
3848 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3849 {
3850 rtx orig_x = x;
3851
3852 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3853 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3854 force_operand (XEXP (x, 0), NULL_RTX));
3855 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3856 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3857 force_operand (XEXP (x, 1), NULL_RTX));
3858 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3859 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3860 XEXP (x, 1));
3861 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3862 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3863 force_operand (XEXP (x, 1), NULL_RTX));
3864
3865 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3866 return x;
3867
3868 if (tls_symbolic_operand (x))
3869 x = legitimize_tls_address (x);
3870 else if (flag_pic)
3871 x = legitimize_pic_address (x, mode, 0);
3872 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3873 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3874 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3875 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3876 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3877 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3878 else if (GET_CODE (x) == SYMBOL_REF
3879 || GET_CODE (x) == CONST
3880 || GET_CODE (x) == LABEL_REF)
3881 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3882 return x;
3883 }
3884
3885 /* Emit the special PIC prologue. */
3886
3887 static void
3888 load_pic_register (void)
3889 {
3890 int orig_flag_pic = flag_pic;
3891
3892 /* If we haven't emitted the special helper function, do so now. */
3893 if (add_pc_to_pic_symbol_name[0] == 0)
3894 {
3895 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3896 int align;
3897
3898 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3899 text_section ();
3900
3901 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3902 if (align > 0)
3903 ASM_OUTPUT_ALIGN (asm_out_file, align);
3904 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3905 if (flag_delayed_branch)
3906 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3907 pic_name, pic_name);
3908 else
3909 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3910 pic_name, pic_name);
3911 }
3912
3913 /* Initialize every time through, since we can't easily
3914 know this to be permanent. */
3915 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3916 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3917
3918 flag_pic = 0;
3919 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3920 add_pc_to_pic_symbol));
3921 flag_pic = orig_flag_pic;
3922
3923 /* Need to emit this whether or not we obey regdecls,
3924 since setjmp/longjmp can cause life info to screw up.
3925 ??? In the case where we don't obey regdecls, this is not sufficient
3926 since we may not fall out the bottom. */
3927 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3928 }
3929 \f
3930 /* Return 1 if RTX is a MEM which is known to be aligned to at
3931 least a DESIRED byte boundary. */
3932
3933 int
3934 mem_min_alignment (rtx mem, int desired)
3935 {
3936 rtx addr, base, offset;
3937
3938 /* If it's not a MEM we can't accept it. */
3939 if (GET_CODE (mem) != MEM)
3940 return 0;
3941
3942 addr = XEXP (mem, 0);
3943 base = offset = NULL_RTX;
3944 if (GET_CODE (addr) == PLUS)
3945 {
3946 if (GET_CODE (XEXP (addr, 0)) == REG)
3947 {
3948 base = XEXP (addr, 0);
3949
3950 /* What we are saying here is that if the base
3951 REG is aligned properly, the compiler will make
3952 sure any REG based index upon it will be so
3953 as well. */
3954 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3955 offset = XEXP (addr, 1);
3956 else
3957 offset = const0_rtx;
3958 }
3959 }
3960 else if (GET_CODE (addr) == REG)
3961 {
3962 base = addr;
3963 offset = const0_rtx;
3964 }
3965
3966 if (base != NULL_RTX)
3967 {
3968 int regno = REGNO (base);
3969
3970 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3971 {
3972 /* Check if the compiler has recorded some information
3973 about the alignment of the base REG. If reload has
3974 completed, we already matched with proper alignments.
3975 If not running global_alloc, reload might give us
3976 unaligned pointer to local stack though. */
3977 if (((cfun != 0
3978 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3979 || (optimize && reload_completed))
3980 && (INTVAL (offset) & (desired - 1)) == 0)
3981 return 1;
3982 }
3983 else
3984 {
3985 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3986 return 1;
3987 }
3988 }
3989 else if (! TARGET_UNALIGNED_DOUBLES
3990 || CONSTANT_P (addr)
3991 || GET_CODE (addr) == LO_SUM)
3992 {
3993 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3994 is true, in which case we can only assume that an access is aligned if
3995 it is to a constant address, or the address involves a LO_SUM. */
3996 return 1;
3997 }
3998
3999 /* An obviously unaligned address. */
4000 return 0;
4001 }
4002
4003 \f
4004 /* Vectors to keep interesting information about registers where it can easily
4005 be got. We used to use the actual mode value as the bit number, but there
4006 are more than 32 modes now. Instead we use two tables: one indexed by
4007 hard register number, and one indexed by mode. */
4008
4009 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4010 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4011 mapped into one sparc_mode_class mode. */
4012
4013 enum sparc_mode_class {
4014 S_MODE, D_MODE, T_MODE, O_MODE,
4015 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4016 CC_MODE, CCFP_MODE
4017 };
4018
4019 /* Modes for single-word and smaller quantities. */
4020 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4021
4022 /* Modes for double-word and smaller quantities. */
4023 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4024
4025 /* Modes for quad-word and smaller quantities. */
4026 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4027
4028 /* Modes for 8-word and smaller quantities. */
4029 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4030
4031 /* Modes for single-float quantities. We must allow any single word or
4032 smaller quantity. This is because the fix/float conversion instructions
4033 take integer inputs/outputs from the float registers. */
4034 #define SF_MODES (S_MODES)
4035
4036 /* Modes for double-float and smaller quantities. */
4037 #define DF_MODES (S_MODES | D_MODES)
4038
4039 /* Modes for double-float only quantities. */
4040 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4041
4042 /* Modes for quad-float only quantities. */
4043 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4044
4045 /* Modes for quad-float and smaller quantities. */
4046 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4047
4048 /* Modes for quad-float and double-float quantities. */
4049 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4050
4051 /* Modes for quad-float pair only quantities. */
4052 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4053
4054 /* Modes for quad-float pairs and smaller quantities. */
4055 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4056
4057 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4058
4059 /* Modes for condition codes. */
4060 #define CC_MODES (1 << (int) CC_MODE)
4061 #define CCFP_MODES (1 << (int) CCFP_MODE)
4062
4063 /* Value is 1 if register/mode pair is acceptable on sparc.
4064 The funny mixture of D and T modes is because integer operations
4065 do not specially operate on tetra quantities, so non-quad-aligned
4066 registers can hold quadword quantities (except %o4 and %i4 because
4067 they cross fixed registers). */
4068
4069 /* This points to either the 32 bit or the 64 bit version. */
4070 const int *hard_regno_mode_classes;
4071
4072 static const int hard_32bit_mode_classes[] = {
4073 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4074 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4075 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4076 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4077
4078 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4079 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4080 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4081 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4082
4083 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4084 and none can hold SFmode/SImode values. */
4085 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4086 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4087 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4088 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4089
4090 /* %fcc[0123] */
4091 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4092
4093 /* %icc */
4094 CC_MODES
4095 };
4096
4097 static const int hard_64bit_mode_classes[] = {
4098 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4099 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4100 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4101 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4102
4103 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4104 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4105 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4106 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4107
4108 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4109 and none can hold SFmode/SImode values. */
4110 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4111 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4112 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4113 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4114
4115 /* %fcc[0123] */
4116 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4117
4118 /* %icc */
4119 CC_MODES
4120 };
4121
4122 int sparc_mode_class [NUM_MACHINE_MODES];
4123
4124 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4125
4126 static void
4127 sparc_init_modes (void)
4128 {
4129 int i;
4130
4131 for (i = 0; i < NUM_MACHINE_MODES; i++)
4132 {
4133 switch (GET_MODE_CLASS (i))
4134 {
4135 case MODE_INT:
4136 case MODE_PARTIAL_INT:
4137 case MODE_COMPLEX_INT:
4138 if (GET_MODE_SIZE (i) <= 4)
4139 sparc_mode_class[i] = 1 << (int) S_MODE;
4140 else if (GET_MODE_SIZE (i) == 8)
4141 sparc_mode_class[i] = 1 << (int) D_MODE;
4142 else if (GET_MODE_SIZE (i) == 16)
4143 sparc_mode_class[i] = 1 << (int) T_MODE;
4144 else if (GET_MODE_SIZE (i) == 32)
4145 sparc_mode_class[i] = 1 << (int) O_MODE;
4146 else
4147 sparc_mode_class[i] = 0;
4148 break;
4149 case MODE_FLOAT:
4150 case MODE_COMPLEX_FLOAT:
4151 if (GET_MODE_SIZE (i) <= 4)
4152 sparc_mode_class[i] = 1 << (int) SF_MODE;
4153 else if (GET_MODE_SIZE (i) == 8)
4154 sparc_mode_class[i] = 1 << (int) DF_MODE;
4155 else if (GET_MODE_SIZE (i) == 16)
4156 sparc_mode_class[i] = 1 << (int) TF_MODE;
4157 else if (GET_MODE_SIZE (i) == 32)
4158 sparc_mode_class[i] = 1 << (int) OF_MODE;
4159 else
4160 sparc_mode_class[i] = 0;
4161 break;
4162 case MODE_CC:
4163 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4164 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4165 else
4166 sparc_mode_class[i] = 1 << (int) CC_MODE;
4167 break;
4168 default:
4169 sparc_mode_class[i] = 0;
4170 break;
4171 }
4172 }
4173
4174 if (TARGET_ARCH64)
4175 hard_regno_mode_classes = hard_64bit_mode_classes;
4176 else
4177 hard_regno_mode_classes = hard_32bit_mode_classes;
4178
4179 /* Initialize the array used by REGNO_REG_CLASS. */
4180 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4181 {
4182 if (i < 16 && TARGET_V8PLUS)
4183 sparc_regno_reg_class[i] = I64_REGS;
4184 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4185 sparc_regno_reg_class[i] = GENERAL_REGS;
4186 else if (i < 64)
4187 sparc_regno_reg_class[i] = FP_REGS;
4188 else if (i < 96)
4189 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4190 else if (i < 100)
4191 sparc_regno_reg_class[i] = FPCC_REGS;
4192 else
4193 sparc_regno_reg_class[i] = NO_REGS;
4194 }
4195 }
4196 \f
4197 /* Compute the frame size required by the function. This function is called
4198 during the reload pass and also by sparc_expand_prologue. */
4199
4200 HOST_WIDE_INT
4201 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4202 {
4203 int outgoing_args_size = (current_function_outgoing_args_size
4204 + REG_PARM_STACK_SPACE (current_function_decl));
4205 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4206 int i;
4207
4208 if (TARGET_ARCH64)
4209 {
4210 for (i = 0; i < 8; i++)
4211 if (regs_ever_live[i] && ! call_used_regs[i])
4212 n_regs += 2;
4213 }
4214 else
4215 {
4216 for (i = 0; i < 8; i += 2)
4217 if ((regs_ever_live[i] && ! call_used_regs[i])
4218 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4219 n_regs += 2;
4220 }
4221
4222 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4223 if ((regs_ever_live[i] && ! call_used_regs[i])
4224 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4225 n_regs += 2;
4226
4227 /* Set up values for use in prologue and epilogue. */
4228 num_gfregs = n_regs;
4229
4230 if (leaf_function_p
4231 && n_regs == 0
4232 && size == 0
4233 && current_function_outgoing_args_size == 0)
4234 actual_fsize = apparent_fsize = 0;
4235 else
4236 {
4237 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4238 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4239 apparent_fsize += n_regs * 4;
4240 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4241 }
4242
4243 /* Make sure nothing can clobber our register windows.
4244 If a SAVE must be done, or there is a stack-local variable,
4245 the register window area must be allocated.
4246 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4247 if (! leaf_function_p || size > 0)
4248 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4249
4250 return SPARC_STACK_ALIGN (actual_fsize);
4251 }
4252
4253 /* Output any necessary .register pseudo-ops. */
4254
4255 void
4256 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4257 {
4258 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4259 int i;
4260
4261 if (TARGET_ARCH32)
4262 return;
4263
4264 /* Check if %g[2367] were used without
4265 .register being printed for them already. */
4266 for (i = 2; i < 8; i++)
4267 {
4268 if (regs_ever_live [i]
4269 && ! sparc_hard_reg_printed [i])
4270 {
4271 sparc_hard_reg_printed [i] = 1;
4272 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4273 }
4274 if (i == 3) i = 5;
4275 }
4276 #endif
4277 }
4278
4279 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4280 as needed. LOW should be double-word aligned for 32-bit registers.
4281 Return the new OFFSET. */
4282
4283 #define SORR_SAVE 0
4284 #define SORR_RESTORE 1
4285
4286 static int
4287 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4288 {
4289 rtx mem, insn;
4290 int i;
4291
4292 if (TARGET_ARCH64 && high <= 32)
4293 {
4294 for (i = low; i < high; i++)
4295 {
4296 if (regs_ever_live[i] && ! call_used_regs[i])
4297 {
4298 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4299 set_mem_alias_set (mem, sparc_sr_alias_set);
4300 if (action == SORR_SAVE)
4301 {
4302 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4303 RTX_FRAME_RELATED_P (insn) = 1;
4304 }
4305 else /* action == SORR_RESTORE */
4306 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4307 offset += 8;
4308 }
4309 }
4310 }
4311 else
4312 {
4313 for (i = low; i < high; i += 2)
4314 {
4315 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4316 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4317 enum machine_mode mode;
4318 int regno;
4319
4320 if (reg0 && reg1)
4321 {
4322 mode = i < 32 ? DImode : DFmode;
4323 regno = i;
4324 }
4325 else if (reg0)
4326 {
4327 mode = i < 32 ? SImode : SFmode;
4328 regno = i;
4329 }
4330 else if (reg1)
4331 {
4332 mode = i < 32 ? SImode : SFmode;
4333 regno = i + 1;
4334 offset += 4;
4335 }
4336 else
4337 continue;
4338
4339 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4340 set_mem_alias_set (mem, sparc_sr_alias_set);
4341 if (action == SORR_SAVE)
4342 {
4343 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4344 RTX_FRAME_RELATED_P (insn) = 1;
4345 }
4346 else /* action == SORR_RESTORE */
4347 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4348
4349 /* Always preserve double-word alignment. */
4350 offset = (offset + 7) & -8;
4351 }
4352 }
4353
4354 return offset;
4355 }
4356
4357 /* Emit code to save call-saved registers. */
4358
4359 static void
4360 emit_save_regs (void)
4361 {
4362 HOST_WIDE_INT offset;
4363 rtx base;
4364
4365 offset = frame_base_offset - apparent_fsize;
4366
4367 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4368 {
4369 /* ??? This might be optimized a little as %g1 might already have a
4370 value close enough that a single add insn will do. */
4371 /* ??? Although, all of this is probably only a temporary fix
4372 because if %g1 can hold a function result, then
4373 sparc_expand_epilogue will lose (the result will be
4374 clobbered). */
4375 base = gen_rtx_REG (Pmode, 1);
4376 emit_move_insn (base, GEN_INT (offset));
4377 emit_insn (gen_rtx_SET (VOIDmode,
4378 base,
4379 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4380 offset = 0;
4381 }
4382 else
4383 base = frame_base_reg;
4384
4385 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4386 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4387 }
4388
4389 /* Emit code to restore call-saved registers. */
4390
4391 static void
4392 emit_restore_regs (void)
4393 {
4394 HOST_WIDE_INT offset;
4395 rtx base;
4396
4397 offset = frame_base_offset - apparent_fsize;
4398
4399 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4400 {
4401 base = gen_rtx_REG (Pmode, 1);
4402 emit_move_insn (base, GEN_INT (offset));
4403 emit_insn (gen_rtx_SET (VOIDmode,
4404 base,
4405 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4406 offset = 0;
4407 }
4408 else
4409 base = frame_base_reg;
4410
4411 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4412 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4413 }
4414
4415 /* Emit an increment for the stack pointer. */
4416
4417 static void
4418 emit_stack_pointer_increment (rtx increment)
4419 {
4420 if (TARGET_ARCH64)
4421 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4422 else
4423 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4424 }
4425
4426 /* Emit a decrement for the stack pointer. */
4427
4428 static void
4429 emit_stack_pointer_decrement (rtx decrement)
4430 {
4431 if (TARGET_ARCH64)
4432 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4433 else
4434 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4435 }
4436
4437 /* Expand the function prologue. The prologue is responsible for reserving
4438 storage for the frame, saving the call-saved registers and loading the
4439 PIC register if needed. */
4440
4441 void
4442 sparc_expand_prologue (void)
4443 {
4444 int leaf_function_p = current_function_uses_only_leaf_regs;
4445
4446 /* Need to use actual_fsize, since we are also allocating
4447 space for our callee (and our own register save area). */
4448 actual_fsize = sparc_compute_frame_size (get_frame_size(), leaf_function_p);
4449
4450 if (leaf_function_p)
4451 {
4452 frame_base_reg = stack_pointer_rtx;
4453 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4454 }
4455 else
4456 {
4457 frame_base_reg = hard_frame_pointer_rtx;
4458 frame_base_offset = SPARC_STACK_BIAS;
4459 }
4460
4461 if (actual_fsize == 0)
4462 /* do nothing. */ ;
4463 else if (leaf_function_p)
4464 {
4465 if (actual_fsize <= 4096)
4466 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4467 else if (actual_fsize <= 8192)
4468 {
4469 emit_stack_pointer_increment (GEN_INT (-4096));
4470 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4471 }
4472 else
4473 {
4474 rtx reg = gen_rtx_REG (Pmode, 1);
4475 emit_move_insn (reg, GEN_INT (-actual_fsize));
4476 emit_stack_pointer_increment (reg);
4477 }
4478 }
4479 else
4480 {
4481 if (actual_fsize <= 4096)
4482 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4483 else if (actual_fsize <= 8192)
4484 {
4485 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4486 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4487 }
4488 else
4489 {
4490 rtx reg = gen_rtx_REG (Pmode, 1);
4491 emit_move_insn (reg, GEN_INT (-actual_fsize));
4492 emit_insn (gen_save_register_window (reg));
4493 }
4494 }
4495
4496 /* Call-saved registers are saved just above the outgoing argument area. */
4497 if (num_gfregs)
4498 emit_save_regs ();
4499
4500 /* Load the PIC register if needed. */
4501 if (flag_pic && current_function_uses_pic_offset_table)
4502 load_pic_register ();
4503 }
4504
4505 /* This function generates the assembly code for function entry, which boils
4506 down to emitting the necessary .register directives. It also informs the
4507 DWARF-2 back-end on the layout of the frame.
4508
4509 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4510 an 8-byte block of memory. If any fpu reg is used in the function, we
4511 allocate such a block here, at the bottom of the frame, just in case it's
4512 needed." Could this explain the -8 in emit_restore_regs? */
4513
4514 static void
4515 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4516 {
4517 int leaf_function_p = current_function_uses_only_leaf_regs;
4518
4519 sparc_output_scratch_registers (file);
4520
4521 if (dwarf2out_do_frame () && actual_fsize)
4522 {
4523 char *label = dwarf2out_cfi_label ();
4524
4525 /* The canonical frame address refers to the top of the frame. */
4526 dwarf2out_def_cfa (label,
4527 leaf_function_p
4528 ? STACK_POINTER_REGNUM
4529 : HARD_FRAME_POINTER_REGNUM,
4530 frame_base_offset);
4531
4532 if (! leaf_function_p)
4533 {
4534 /* Note the register window save. This tells the unwinder that
4535 it needs to restore the window registers from the previous
4536 frame's window save area at 0(cfa). */
4537 dwarf2out_window_save (label);
4538
4539 /* The return address (-8) is now in %i7. */
4540 dwarf2out_return_reg (label, 31);
4541 }
4542 }
4543 }
4544
4545 /* Expand the function epilogue, either normal or part of a sibcall.
4546 We emit all the instructions except the return or the call. */
4547
4548 void
4549 sparc_expand_epilogue (void)
4550 {
4551 int leaf_function_p = current_function_uses_only_leaf_regs;
4552
4553 if (num_gfregs)
4554 emit_restore_regs ();
4555
4556 if (actual_fsize == 0)
4557 /* do nothing. */ ;
4558 else if (leaf_function_p)
4559 {
4560 if (actual_fsize <= 4096)
4561 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4562 else if (actual_fsize <= 8192)
4563 {
4564 emit_stack_pointer_decrement (GEN_INT (-4096));
4565 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4566 }
4567 else
4568 {
4569 rtx reg = gen_rtx_REG (Pmode, 1);
4570 emit_move_insn (reg, GEN_INT (-actual_fsize));
4571 emit_stack_pointer_decrement (reg);
4572 }
4573 }
4574 }
4575
4576 /* This function generates the assembly code for function exit. */
4577
4578 static void
4579 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4580 {
4581 /* If code does not drop into the epilogue, we have to still output
4582 a dummy nop for the sake of sane backtraces. Otherwise, if the
4583 last two instructions of a function were "call foo; dslot;" this
4584 can make the return PC of foo (ie. address of call instruction
4585 plus 8) point to the first instruction in the next function. */
4586
4587 rtx insn, last_real_insn;
4588
4589 insn = get_last_insn ();
4590
4591 last_real_insn = prev_real_insn (insn);
4592 if (last_real_insn
4593 && GET_CODE (last_real_insn) == INSN
4594 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4595 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4596
4597 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4598 fputs("\tnop\n", file);
4599
4600 sparc_output_deferred_case_vectors ();
4601 }
4602
4603 /* Output a 'restore' instruction. */
4604
4605 static void
4606 output_restore (rtx pat)
4607 {
4608 rtx operands[3];
4609
4610 if (! pat)
4611 {
4612 fputs ("\t restore\n", asm_out_file);
4613 return;
4614 }
4615
4616 if (GET_CODE (pat) != SET)
4617 abort ();
4618
4619 operands[0] = SET_DEST (pat);
4620 pat = SET_SRC (pat);
4621
4622 switch (GET_CODE (pat))
4623 {
4624 case PLUS:
4625 operands[1] = XEXP (pat, 0);
4626 operands[2] = XEXP (pat, 1);
4627 output_asm_insn (" restore %r1, %2, %Y0", operands);
4628 break;
4629 case LO_SUM:
4630 operands[1] = XEXP (pat, 0);
4631 operands[2] = XEXP (pat, 1);
4632 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4633 break;
4634 case ASHIFT:
4635 operands[1] = XEXP (pat, 0);
4636 if (XEXP (pat, 1) != const1_rtx)
4637 abort();
4638 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4639 break;
4640 default:
4641 operands[1] = pat;
4642 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4643 break;
4644 }
4645 }
4646
4647 /* Output a return. */
4648
4649 const char *
4650 output_return (rtx insn)
4651 {
4652 int leaf_function_p = current_function_uses_only_leaf_regs;
4653 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4654 /* True if the caller has placed an "unimp" insn immediately after the call.
4655 This insn is used in the 32-bit ABI when calling a function that returns
4656 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4657 to have this test be the same as that used on the call. */
4658 bool sparc_skip_caller_unimp
4659 = ! TARGET_ARCH64
4660 && current_function_returns_struct
4661 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4662 == INTEGER_CST)
4663 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4664
4665 if (leaf_function_p)
4666 {
4667 /* This is a leaf function so we don't have to bother restoring the
4668 register window, which frees us from dealing with the convoluted
4669 semantics of restore/return. We simply output the jump to the
4670 return address and the insn in the delay slot, which usually is
4671 the substraction restoring the stack pointer %sp. */
4672
4673 if (current_function_calls_eh_return)
4674 abort ();
4675
4676 fprintf (asm_out_file, "\tjmp\t%%o7+%d\n", sparc_skip_caller_unimp ? 12 : 8);
4677
4678 if (delay_slot_filled_p)
4679 {
4680 rtx delay = NEXT_INSN (insn);
4681 if (! delay)
4682 abort ();
4683
4684 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4685 PATTERN (delay) = gen_blockage ();
4686 INSN_CODE (delay) = -1;
4687 }
4688 else
4689 fputs ("\t nop\n", asm_out_file);
4690 }
4691 else
4692 {
4693 /* This is a regular function so we have to restore the register window.
4694 We may have a pending insn for the delay slot, which will be either
4695 combined with the 'restore' instruction or put in the delay slot of
4696 the 'return' instruction. */
4697
4698 if (current_function_calls_eh_return)
4699 {
4700 /* If the function uses __builtin_eh_return, the eh_return
4701 machinery occupies the delay slot. */
4702 if (delay_slot_filled_p || sparc_skip_caller_unimp)
4703 abort ();
4704
4705 if (! flag_delayed_branch)
4706 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4707
4708 if (TARGET_V9)
4709 fputs ("\treturn\t%i7+8\n", asm_out_file);
4710 else
4711 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4712
4713 if (flag_delayed_branch)
4714 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4715 else
4716 fputs ("\t nop\n", asm_out_file);
4717 }
4718 else if (delay_slot_filled_p)
4719 {
4720 rtx delay, pat;
4721
4722 delay = NEXT_INSN (insn);
4723 if (! delay)
4724 abort ();
4725
4726 pat = PATTERN (delay);
4727
4728 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4729 {
4730 epilogue_renumber (&pat, 0);
4731 fprintf (asm_out_file, "\treturn\t%%i7+%d\n",
4732 sparc_skip_caller_unimp ? 12 : 8);
4733 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4734 }
4735 else
4736 {
4737 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n",
4738 sparc_skip_caller_unimp ? 12 : 8);
4739 output_restore (pat);
4740 }
4741
4742 PATTERN (delay) = gen_blockage ();
4743 INSN_CODE (delay) = -1;
4744 }
4745 else
4746 {
4747 /* The delay slot is empty. */
4748 if (TARGET_V9)
4749 fprintf (asm_out_file, "\treturn\t%%i7+%d\n\t nop\n",
4750 sparc_skip_caller_unimp ? 12 : 8);
4751 else if (flag_delayed_branch)
4752 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n\t restore\n",
4753 sparc_skip_caller_unimp ? 12 : 8);
4754 else
4755 fprintf (asm_out_file, "\trestore\n\tjmp\t%%o7+%d\n\t nop\n",
4756 sparc_skip_caller_unimp ? 12 : 8);
4757 }
4758 }
4759
4760 return "";
4761 }
4762
4763 /* Output a sibling call. */
4764
4765 const char *
4766 output_sibcall (rtx insn, rtx call_operand)
4767 {
4768 int leaf_function_p = current_function_uses_only_leaf_regs;
4769 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4770 rtx operands[1];
4771
4772 if (! flag_delayed_branch)
4773 abort();
4774
4775 operands[0] = call_operand;
4776
4777 if (leaf_function_p)
4778 {
4779 /* This is a leaf function so we don't have to bother restoring the
4780 register window. We simply output the jump to the function and
4781 the insn in the delay slot (if any). */
4782
4783 if (LEAF_SIBCALL_SLOT_RESERVED_P && delay_slot_filled_p)
4784 abort();
4785
4786 if (delay_slot_filled_p)
4787 {
4788 rtx delay = NEXT_INSN (insn);
4789 if (! delay)
4790 abort ();
4791
4792 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4793 output_asm_insn ("jmp\t%%g1 + %%lo(%a0)", operands);
4794 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4795
4796 PATTERN (delay) = gen_blockage ();
4797 INSN_CODE (delay) = -1;
4798 }
4799 else
4800 {
4801 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4802 it into branch if possible. */
4803 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4804 output_asm_insn ("call\t%a0, 0", operands);
4805 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4806 }
4807 }
4808 else
4809 {
4810 /* This is a regular function so we have to restore the register window.
4811 We may have a pending insn for the delay slot, which will be combined
4812 with the 'restore' instruction. */
4813
4814 output_asm_insn ("call\t%a0, 0", operands);
4815
4816 if (delay_slot_filled_p)
4817 {
4818 rtx delay = NEXT_INSN (insn);
4819 if (! delay)
4820 abort ();
4821
4822 output_restore (PATTERN (delay));
4823
4824 PATTERN (delay) = gen_blockage ();
4825 INSN_CODE (delay) = -1;
4826 }
4827 else
4828 output_restore (NULL_RTX);
4829 }
4830
4831 return "";
4832 }
4833 \f
4834 /* Functions for handling argument passing.
4835
4836 For 32-bit, the first 6 args are normally in registers and the rest are
4837 pushed. Any arg that starts within the first 6 words is at least
4838 partially passed in a register unless its data type forbids.
4839
4840 For 64-bit, the argument registers are laid out as an array of 16 elements
4841 and arguments are added sequentially. The first 6 int args and up to the
4842 first 16 fp args (depending on size) are passed in regs.
4843
4844 Slot Stack Integral Float Float in structure Double Long Double
4845 ---- ----- -------- ----- ------------------ ------ -----------
4846 15 [SP+248] %f31 %f30,%f31 %d30
4847 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4848 13 [SP+232] %f27 %f26,%f27 %d26
4849 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4850 11 [SP+216] %f23 %f22,%f23 %d22
4851 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4852 9 [SP+200] %f19 %f18,%f19 %d18
4853 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4854 7 [SP+184] %f15 %f14,%f15 %d14
4855 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4856 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4857 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4858 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4859 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4860 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4861 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4862
4863 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4864
4865 Integral arguments are always passed as 64-bit quantities appropriately
4866 extended.
4867
4868 Passing of floating point values is handled as follows.
4869 If a prototype is in scope:
4870 If the value is in a named argument (i.e. not a stdarg function or a
4871 value not part of the `...') then the value is passed in the appropriate
4872 fp reg.
4873 If the value is part of the `...' and is passed in one of the first 6
4874 slots then the value is passed in the appropriate int reg.
4875 If the value is part of the `...' and is not passed in one of the first 6
4876 slots then the value is passed in memory.
4877 If a prototype is not in scope:
4878 If the value is one of the first 6 arguments the value is passed in the
4879 appropriate integer reg and the appropriate fp reg.
4880 If the value is not one of the first 6 arguments the value is passed in
4881 the appropriate fp reg and in memory.
4882
4883
4884 Summary of the calling conventions implemented by GCC on SPARC:
4885
4886 32-bit ABI:
4887 size argument return value
4888
4889 small integer <4 int. reg. int. reg.
4890 word 4 int. reg. int. reg.
4891 double word 8 int. reg. int. reg.
4892
4893 _Complex small integer <8 int. reg. int. reg.
4894 _Complex word 8 int. reg. int. reg.
4895 _Complex double word 16 memory int. reg.
4896
4897 vector integer <=8 int. reg. FP reg.
4898 vector integer >8 memory memory
4899
4900 float 4 int. reg. FP reg.
4901 double 8 int. reg. FP reg.
4902 long double 16 memory memory
4903
4904 _Complex float 8 memory FP reg.
4905 _Complex double 16 memory FP reg.
4906 _Complex long double 32 memory FP reg.
4907
4908 vector float <=32 memory FP reg.
4909 vector float >32 memory memory
4910
4911 aggregate any memory memory
4912
4913
4914
4915 64-bit ABI:
4916 size argument return value
4917
4918 small integer <8 int. reg. int. reg.
4919 word 8 int. reg. int. reg.
4920 double word 16 int. reg. int. reg.
4921
4922 _Complex small integer <16 int. reg. int. reg.
4923 _Complex word 16 int. reg. int. reg.
4924 _Complex double word 32 memory int. reg.
4925
4926 vector integer <=16 FP reg. FP reg.
4927 vector integer 16<s<=32 memory FP reg.
4928 vector integer >32 memory memory
4929
4930 float 4 FP reg. FP reg.
4931 double 8 FP reg. FP reg.
4932 long double 16 FP reg. FP reg.
4933
4934 _Complex float 8 FP reg. FP reg.
4935 _Complex double 16 FP reg. FP reg.
4936 _Complex long double 32 memory FP reg.
4937
4938 vector float <=16 FP reg. FP reg.
4939 vector float 16<s<=32 memory FP reg.
4940 vector float >32 memory memory
4941
4942 aggregate <=16 reg. reg.
4943 aggregate 16<s<=32 memory reg.
4944 aggregate >32 memory memory
4945
4946
4947
4948 Note #1: complex floating-point types follow the extended SPARC ABIs as
4949 implemented by the Sun compiler.
4950
4951 Note #2: integral vector types follow the scalar floating-point types
4952 conventions to match what is implemented by the Sun VIS SDK.
4953
4954 Note #3: floating-point vector types follow the complex floating-point
4955 types conventions. */
4956
4957
4958 /* Maximum number of int regs for args. */
4959 #define SPARC_INT_ARG_MAX 6
4960 /* Maximum number of fp regs for args. */
4961 #define SPARC_FP_ARG_MAX 16
4962
4963 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4964
4965 /* Handle the INIT_CUMULATIVE_ARGS macro.
4966 Initialize a variable CUM of type CUMULATIVE_ARGS
4967 for a call to a function whose data type is FNTYPE.
4968 For a library call, FNTYPE is 0. */
4969
4970 void
4971 init_cumulative_args (struct sparc_args *cum, tree fntype,
4972 rtx libname ATTRIBUTE_UNUSED,
4973 tree fndecl ATTRIBUTE_UNUSED)
4974 {
4975 cum->words = 0;
4976 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4977 cum->libcall_p = fntype == 0;
4978 }
4979
4980 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4981 When a prototype says `char' or `short', really pass an `int'. */
4982
4983 static bool
4984 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4985 {
4986 return TARGET_ARCH32 ? true : false;
4987 }
4988
4989 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4990
4991 static bool
4992 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4993 {
4994 return TARGET_ARCH64 ? true : false;
4995 }
4996
4997 /* Scan the record type TYPE and return the following predicates:
4998 - INTREGS_P: the record contains at least one field or sub-field
4999 that is eligible for promotion in integer registers.
5000 - FP_REGS_P: the record contains at least one field or sub-field
5001 that is eligible for promotion in floating-point registers.
5002 - PACKED_P: the record contains at least one field that is packed.
5003
5004 Sub-fields are not taken into account for the PACKED_P predicate. */
5005
5006 static void
5007 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5008 {
5009 tree field;
5010
5011 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5012 {
5013 if (TREE_CODE (field) == FIELD_DECL)
5014 {
5015 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5016 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5017 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
5018 *fpregs_p = 1;
5019 else
5020 *intregs_p = 1;
5021
5022 if (packed_p && DECL_PACKED (field))
5023 *packed_p = 1;
5024 }
5025 }
5026 }
5027
5028 /* Compute the slot number to pass an argument in.
5029 Return the slot number or -1 if passing on the stack.
5030
5031 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5032 the preceding args and about the function being called.
5033 MODE is the argument's machine mode.
5034 TYPE is the data type of the argument (as a tree).
5035 This is null for libcalls where that information may
5036 not be available.
5037 NAMED is nonzero if this argument is a named parameter
5038 (otherwise it is an extra parameter matching an ellipsis).
5039 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5040 *PREGNO records the register number to use if scalar type.
5041 *PPADDING records the amount of padding needed in words. */
5042
5043 static int
5044 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5045 tree type, int named, int incoming_p,
5046 int *pregno, int *ppadding)
5047 {
5048 int regbase = (incoming_p
5049 ? SPARC_INCOMING_INT_ARG_FIRST
5050 : SPARC_OUTGOING_INT_ARG_FIRST);
5051 int slotno = cum->words;
5052 int regno;
5053
5054 *ppadding = 0;
5055
5056 if (type && TREE_ADDRESSABLE (type))
5057 return -1;
5058
5059 if (TARGET_ARCH32
5060 && mode == BLKmode
5061 && type
5062 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5063 return -1;
5064
5065 /* For SPARC64, objects requiring 16-byte alignment get it. */
5066 if (TARGET_ARCH64
5067 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5068 && (slotno & 1) != 0)
5069 slotno++, *ppadding = 1;
5070
5071 switch (GET_MODE_CLASS (mode))
5072 {
5073 case MODE_FLOAT:
5074 case MODE_COMPLEX_FLOAT:
5075 case MODE_VECTOR_INT:
5076 case MODE_VECTOR_FLOAT:
5077 if (TARGET_ARCH64 && TARGET_FPU && named)
5078 {
5079 if (slotno >= SPARC_FP_ARG_MAX)
5080 return -1;
5081 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5082 /* Arguments filling only one single FP register are
5083 right-justified in the outer double FP register. */
5084 if (GET_MODE_SIZE (mode) <= 4)
5085 regno++;
5086 break;
5087 }
5088 /* fallthrough */
5089
5090 case MODE_INT:
5091 case MODE_COMPLEX_INT:
5092 if (slotno >= SPARC_INT_ARG_MAX)
5093 return -1;
5094 regno = regbase + slotno;
5095 break;
5096
5097 case MODE_RANDOM:
5098 if (mode == VOIDmode)
5099 /* MODE is VOIDmode when generating the actual call. */
5100 return -1;
5101
5102 if (mode != BLKmode)
5103 abort ();
5104
5105 /* For SPARC64, objects requiring 16-byte alignment get it. */
5106 if (TARGET_ARCH64
5107 && type
5108 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5109 && (slotno & 1) != 0)
5110 slotno++, *ppadding = 1;
5111
5112 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5113 {
5114 if (slotno >= SPARC_INT_ARG_MAX)
5115 return -1;
5116 regno = regbase + slotno;
5117 }
5118 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5119 {
5120 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5121
5122 /* First see what kinds of registers we would need. */
5123 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5124
5125 /* The ABI obviously doesn't specify how packed structures
5126 are passed. These are defined to be passed in int regs
5127 if possible, otherwise memory. */
5128 if (packed_p || !named)
5129 fpregs_p = 0, intregs_p = 1;
5130
5131 /* If all arg slots are filled, then must pass on stack. */
5132 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5133 return -1;
5134
5135 /* If there are only int args and all int arg slots are filled,
5136 then must pass on stack. */
5137 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5138 return -1;
5139
5140 /* Note that even if all int arg slots are filled, fp members may
5141 still be passed in regs if such regs are available.
5142 *PREGNO isn't set because there may be more than one, it's up
5143 to the caller to compute them. */
5144 return slotno;
5145 }
5146 break;
5147
5148 default :
5149 abort ();
5150 }
5151
5152 *pregno = regno;
5153 return slotno;
5154 }
5155
5156 /* Handle recursive register counting for structure field layout. */
5157
5158 struct function_arg_record_value_parms
5159 {
5160 rtx ret; /* return expression being built. */
5161 int slotno; /* slot number of the argument. */
5162 int named; /* whether the argument is named. */
5163 int regbase; /* regno of the base register. */
5164 int stack; /* 1 if part of the argument is on the stack. */
5165 int intoffset; /* offset of the first pending integer field. */
5166 unsigned int nregs; /* number of words passed in registers. */
5167 };
5168
5169 static void function_arg_record_value_3
5170 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5171 static void function_arg_record_value_2
5172 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5173 static void function_arg_record_value_1
5174 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5175 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5176 static rtx function_arg_union_value (int, enum machine_mode, int);
5177
5178 /* A subroutine of function_arg_record_value. Traverse the structure
5179 recursively and determine how many registers will be required. */
5180
5181 static void
5182 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5183 struct function_arg_record_value_parms *parms,
5184 bool packed_p)
5185 {
5186 tree field;
5187
5188 /* We need to compute how many registers are needed so we can
5189 allocate the PARALLEL but before we can do that we need to know
5190 whether there are any packed fields. The ABI obviously doesn't
5191 specify how structures are passed in this case, so they are
5192 defined to be passed in int regs if possible, otherwise memory,
5193 regardless of whether there are fp values present. */
5194
5195 if (! packed_p)
5196 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5197 {
5198 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5199 {
5200 packed_p = true;
5201 break;
5202 }
5203 }
5204
5205 /* Compute how many registers we need. */
5206 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5207 {
5208 if (TREE_CODE (field) == FIELD_DECL)
5209 {
5210 HOST_WIDE_INT bitpos = startbitpos;
5211
5212 if (DECL_SIZE (field) != 0
5213 && host_integerp (bit_position (field), 1))
5214 bitpos += int_bit_position (field);
5215
5216 /* ??? FIXME: else assume zero offset. */
5217
5218 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5219 function_arg_record_value_1 (TREE_TYPE (field),
5220 bitpos,
5221 parms,
5222 packed_p);
5223 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5224 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5225 && TARGET_FPU
5226 && parms->named
5227 && ! packed_p)
5228 {
5229 if (parms->intoffset != -1)
5230 {
5231 unsigned int startbit, endbit;
5232 int intslots, this_slotno;
5233
5234 startbit = parms->intoffset & -BITS_PER_WORD;
5235 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5236
5237 intslots = (endbit - startbit) / BITS_PER_WORD;
5238 this_slotno = parms->slotno + parms->intoffset
5239 / BITS_PER_WORD;
5240
5241 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5242 {
5243 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5244 /* We need to pass this field on the stack. */
5245 parms->stack = 1;
5246 }
5247
5248 parms->nregs += intslots;
5249 parms->intoffset = -1;
5250 }
5251
5252 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5253 If it wasn't true we wouldn't be here. */
5254 parms->nregs += 1;
5255 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5256 parms->nregs += 1;
5257 }
5258 else
5259 {
5260 if (parms->intoffset == -1)
5261 parms->intoffset = bitpos;
5262 }
5263 }
5264 }
5265 }
5266
5267 /* A subroutine of function_arg_record_value. Assign the bits of the
5268 structure between parms->intoffset and bitpos to integer registers. */
5269
5270 static void
5271 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5272 struct function_arg_record_value_parms *parms)
5273 {
5274 enum machine_mode mode;
5275 unsigned int regno;
5276 unsigned int startbit, endbit;
5277 int this_slotno, intslots, intoffset;
5278 rtx reg;
5279
5280 if (parms->intoffset == -1)
5281 return;
5282
5283 intoffset = parms->intoffset;
5284 parms->intoffset = -1;
5285
5286 startbit = intoffset & -BITS_PER_WORD;
5287 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5288 intslots = (endbit - startbit) / BITS_PER_WORD;
5289 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5290
5291 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5292 if (intslots <= 0)
5293 return;
5294
5295 /* If this is the trailing part of a word, only load that much into
5296 the register. Otherwise load the whole register. Note that in
5297 the latter case we may pick up unwanted bits. It's not a problem
5298 at the moment but may wish to revisit. */
5299
5300 if (intoffset % BITS_PER_WORD != 0)
5301 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5302 MODE_INT, 0);
5303 else
5304 mode = word_mode;
5305
5306 intoffset /= BITS_PER_UNIT;
5307 do
5308 {
5309 regno = parms->regbase + this_slotno;
5310 reg = gen_rtx_REG (mode, regno);
5311 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5312 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5313
5314 this_slotno += 1;
5315 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5316 mode = word_mode;
5317 parms->nregs += 1;
5318 intslots -= 1;
5319 }
5320 while (intslots > 0);
5321 }
5322
5323 /* A subroutine of function_arg_record_value. Traverse the structure
5324 recursively and assign bits to floating point registers. Track which
5325 bits in between need integer registers; invoke function_arg_record_value_3
5326 to make that happen. */
5327
5328 static void
5329 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5330 struct function_arg_record_value_parms *parms,
5331 bool packed_p)
5332 {
5333 tree field;
5334
5335 if (! packed_p)
5336 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5337 {
5338 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5339 {
5340 packed_p = true;
5341 break;
5342 }
5343 }
5344
5345 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5346 {
5347 if (TREE_CODE (field) == FIELD_DECL)
5348 {
5349 HOST_WIDE_INT bitpos = startbitpos;
5350
5351 if (DECL_SIZE (field) != 0
5352 && host_integerp (bit_position (field), 1))
5353 bitpos += int_bit_position (field);
5354
5355 /* ??? FIXME: else assume zero offset. */
5356
5357 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5358 function_arg_record_value_2 (TREE_TYPE (field),
5359 bitpos,
5360 parms,
5361 packed_p);
5362 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5363 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5364 && TARGET_FPU
5365 && parms->named
5366 && ! packed_p)
5367 {
5368 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5369 int regno;
5370 enum machine_mode mode = DECL_MODE (field);
5371 rtx reg;
5372
5373 function_arg_record_value_3 (bitpos, parms);
5374 switch (mode)
5375 {
5376 case SCmode: mode = SFmode; break;
5377 case DCmode: mode = DFmode; break;
5378 case TCmode: mode = TFmode; break;
5379 default: break;
5380 }
5381 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5382 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5383 regno++;
5384 reg = gen_rtx_REG (mode, regno);
5385 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5386 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5387 GEN_INT (bitpos / BITS_PER_UNIT));
5388 parms->nregs += 1;
5389 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5390 {
5391 regno += GET_MODE_SIZE (mode) / 4;
5392 reg = gen_rtx_REG (mode, regno);
5393 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5394 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5395 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5396 / BITS_PER_UNIT));
5397 parms->nregs += 1;
5398 }
5399 }
5400 else
5401 {
5402 if (parms->intoffset == -1)
5403 parms->intoffset = bitpos;
5404 }
5405 }
5406 }
5407 }
5408
5409 /* Used by function_arg and function_value to implement the complex
5410 conventions of the 64-bit ABI for passing and returning structures.
5411 Return an expression valid as a return value for the two macros
5412 FUNCTION_ARG and FUNCTION_VALUE.
5413
5414 TYPE is the data type of the argument (as a tree).
5415 This is null for libcalls where that information may
5416 not be available.
5417 MODE is the argument's machine mode.
5418 SLOTNO is the index number of the argument's slot in the parameter array.
5419 NAMED is nonzero if this argument is a named parameter
5420 (otherwise it is an extra parameter matching an ellipsis).
5421 REGBASE is the regno of the base register for the parameter array. */
5422
5423 static rtx
5424 function_arg_record_value (tree type, enum machine_mode mode,
5425 int slotno, int named, int regbase)
5426 {
5427 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5428 struct function_arg_record_value_parms parms;
5429 unsigned int nregs;
5430
5431 parms.ret = NULL_RTX;
5432 parms.slotno = slotno;
5433 parms.named = named;
5434 parms.regbase = regbase;
5435 parms.stack = 0;
5436
5437 /* Compute how many registers we need. */
5438 parms.nregs = 0;
5439 parms.intoffset = 0;
5440 function_arg_record_value_1 (type, 0, &parms, false);
5441
5442 /* Take into account pending integer fields. */
5443 if (parms.intoffset != -1)
5444 {
5445 unsigned int startbit, endbit;
5446 int intslots, this_slotno;
5447
5448 startbit = parms.intoffset & -BITS_PER_WORD;
5449 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5450 intslots = (endbit - startbit) / BITS_PER_WORD;
5451 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5452
5453 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5454 {
5455 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5456 /* We need to pass this field on the stack. */
5457 parms.stack = 1;
5458 }
5459
5460 parms.nregs += intslots;
5461 }
5462 nregs = parms.nregs;
5463
5464 /* Allocate the vector and handle some annoying special cases. */
5465 if (nregs == 0)
5466 {
5467 /* ??? Empty structure has no value? Duh? */
5468 if (typesize <= 0)
5469 {
5470 /* Though there's nothing really to store, return a word register
5471 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5472 leads to breakage due to the fact that there are zero bytes to
5473 load. */
5474 return gen_rtx_REG (mode, regbase);
5475 }
5476 else
5477 {
5478 /* ??? C++ has structures with no fields, and yet a size. Give up
5479 for now and pass everything back in integer registers. */
5480 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5481 }
5482 if (nregs + slotno > SPARC_INT_ARG_MAX)
5483 nregs = SPARC_INT_ARG_MAX - slotno;
5484 }
5485 if (nregs == 0)
5486 abort ();
5487
5488 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5489
5490 /* If at least one field must be passed on the stack, generate
5491 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5492 also be passed on the stack. We can't do much better because the
5493 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5494 of structures for which the fields passed exclusively in registers
5495 are not at the beginning of the structure. */
5496 if (parms.stack)
5497 XVECEXP (parms.ret, 0, 0)
5498 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5499
5500 /* Fill in the entries. */
5501 parms.nregs = 0;
5502 parms.intoffset = 0;
5503 function_arg_record_value_2 (type, 0, &parms, false);
5504 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5505
5506 if (parms.nregs != nregs)
5507 abort ();
5508
5509 return parms.ret;
5510 }
5511
5512 /* Used by function_arg and function_value to implement the conventions
5513 of the 64-bit ABI for passing and returning unions.
5514 Return an expression valid as a return value for the two macros
5515 FUNCTION_ARG and FUNCTION_VALUE.
5516
5517 SIZE is the size in bytes of the union.
5518 MODE is the argument's machine mode.
5519 REGNO is the hard register the union will be passed in. */
5520
5521 static rtx
5522 function_arg_union_value (int size, enum machine_mode mode, int regno)
5523 {
5524 int nwords = ROUND_ADVANCE (size), i;
5525 rtx regs;
5526
5527 /* Unions are passed left-justified. */
5528 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5529
5530 for (i = 0; i < nwords; i++)
5531 XVECEXP (regs, 0, i)
5532 = gen_rtx_EXPR_LIST (VOIDmode,
5533 gen_rtx_REG (word_mode, regno + i),
5534 GEN_INT (UNITS_PER_WORD * i));
5535
5536 return regs;
5537 }
5538
5539 /* Handle the FUNCTION_ARG macro.
5540 Determine where to put an argument to a function.
5541 Value is zero to push the argument on the stack,
5542 or a hard register in which to store the argument.
5543
5544 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5545 the preceding args and about the function being called.
5546 MODE is the argument's machine mode.
5547 TYPE is the data type of the argument (as a tree).
5548 This is null for libcalls where that information may
5549 not be available.
5550 NAMED is nonzero if this argument is a named parameter
5551 (otherwise it is an extra parameter matching an ellipsis).
5552 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5553
5554 rtx
5555 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5556 tree type, int named, int incoming_p)
5557 {
5558 int regbase = (incoming_p
5559 ? SPARC_INCOMING_INT_ARG_FIRST
5560 : SPARC_OUTGOING_INT_ARG_FIRST);
5561 int slotno, regno, padding;
5562 rtx reg;
5563
5564 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5565 &regno, &padding);
5566
5567 if (slotno == -1)
5568 return 0;
5569
5570 if (TARGET_ARCH32)
5571 {
5572 reg = gen_rtx_REG (mode, regno);
5573 return reg;
5574 }
5575
5576 if (type && TREE_CODE (type) == RECORD_TYPE)
5577 {
5578 /* Structures up to 16 bytes in size are passed in arg slots on the
5579 stack and are promoted to registers where possible. */
5580
5581 if (int_size_in_bytes (type) > 16)
5582 abort (); /* shouldn't get here */
5583
5584 return function_arg_record_value (type, mode, slotno, named, regbase);
5585 }
5586 else if (type && TREE_CODE (type) == UNION_TYPE)
5587 {
5588 HOST_WIDE_INT size = int_size_in_bytes (type);
5589
5590 if (size > 16)
5591 abort (); /* shouldn't get here */
5592
5593 return function_arg_union_value (size, mode, regno);
5594 }
5595 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5596 but also have the slot allocated for them.
5597 If no prototype is in scope fp values in register slots get passed
5598 in two places, either fp regs and int regs or fp regs and memory. */
5599 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5600 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5601 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5602 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5603 && SPARC_FP_REG_P (regno))
5604 {
5605 reg = gen_rtx_REG (mode, regno);
5606 if (cum->prototype_p || cum->libcall_p)
5607 {
5608 /* "* 2" because fp reg numbers are recorded in 4 byte
5609 quantities. */
5610 #if 0
5611 /* ??? This will cause the value to be passed in the fp reg and
5612 in the stack. When a prototype exists we want to pass the
5613 value in the reg but reserve space on the stack. That's an
5614 optimization, and is deferred [for a bit]. */
5615 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5616 return gen_rtx_PARALLEL (mode,
5617 gen_rtvec (2,
5618 gen_rtx_EXPR_LIST (VOIDmode,
5619 NULL_RTX, const0_rtx),
5620 gen_rtx_EXPR_LIST (VOIDmode,
5621 reg, const0_rtx)));
5622 else
5623 #else
5624 /* ??? It seems that passing back a register even when past
5625 the area declared by REG_PARM_STACK_SPACE will allocate
5626 space appropriately, and will not copy the data onto the
5627 stack, exactly as we desire.
5628
5629 This is due to locate_and_pad_parm being called in
5630 expand_call whenever reg_parm_stack_space > 0, which
5631 while beneficial to our example here, would seem to be
5632 in error from what had been intended. Ho hum... -- r~ */
5633 #endif
5634 return reg;
5635 }
5636 else
5637 {
5638 rtx v0, v1;
5639
5640 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5641 {
5642 int intreg;
5643
5644 /* On incoming, we don't need to know that the value
5645 is passed in %f0 and %i0, and it confuses other parts
5646 causing needless spillage even on the simplest cases. */
5647 if (incoming_p)
5648 return reg;
5649
5650 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5651 + (regno - SPARC_FP_ARG_FIRST) / 2);
5652
5653 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5654 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5655 const0_rtx);
5656 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5657 }
5658 else
5659 {
5660 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5661 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5662 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5663 }
5664 }
5665 }
5666 else
5667 {
5668 /* Scalar or complex int. */
5669 reg = gen_rtx_REG (mode, regno);
5670 }
5671
5672 return reg;
5673 }
5674
5675 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5676 For an arg passed partly in registers and partly in memory,
5677 this is the number of registers used.
5678 For args passed entirely in registers or entirely in memory, zero.
5679
5680 Any arg that starts in the first 6 regs but won't entirely fit in them
5681 needs partial registers on v8. On v9, structures with integer
5682 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5683 values that begin in the last fp reg [where "last fp reg" varies with the
5684 mode] will be split between that reg and memory. */
5685
5686 int
5687 function_arg_partial_nregs (const struct sparc_args *cum,
5688 enum machine_mode mode, tree type, int named)
5689 {
5690 int slotno, regno, padding;
5691
5692 /* We pass 0 for incoming_p here, it doesn't matter. */
5693 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5694
5695 if (slotno == -1)
5696 return 0;
5697
5698 if (TARGET_ARCH32)
5699 {
5700 if ((slotno + (mode == BLKmode
5701 ? ROUND_ADVANCE (int_size_in_bytes (type))
5702 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5703 > SPARC_INT_ARG_MAX)
5704 return SPARC_INT_ARG_MAX - slotno;
5705 }
5706 else
5707 {
5708 /* We are guaranteed by function_arg_pass_by_reference that the size
5709 of the argument is not greater than 16 bytes, so we only need to
5710 return 1 if the argument is partially passed in registers. */
5711
5712 if (type && AGGREGATE_TYPE_P (type))
5713 {
5714 int size = int_size_in_bytes (type);
5715
5716 if (size > UNITS_PER_WORD
5717 && slotno == SPARC_INT_ARG_MAX - 1)
5718 return 1;
5719 }
5720 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5721 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5722 && ! (TARGET_FPU && named)))
5723 {
5724 /* The complex types are passed as packed types. */
5725 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5726 && slotno == SPARC_INT_ARG_MAX - 1)
5727 return 1;
5728 }
5729 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5730 {
5731 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5732 > SPARC_FP_ARG_MAX)
5733 return 1;
5734 }
5735 }
5736
5737 return 0;
5738 }
5739
5740 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5741 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5742 quad-precision floats by invisible reference.
5743 v9: Aggregates greater than 16 bytes are passed by reference.
5744 For Pascal, also pass arrays by reference. */
5745
5746 int
5747 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5748 enum machine_mode mode, tree type,
5749 int named ATTRIBUTE_UNUSED)
5750 {
5751 if (TARGET_ARCH32)
5752 {
5753 return ((type && AGGREGATE_TYPE_P (type))
5754 /* Extended ABI (as implemented by the Sun compiler) says
5755 that all complex floats are passed in memory. */
5756 || mode == SCmode
5757 /* Enforce the 2-word cap for passing arguments in registers.
5758 This affects CDImode, TFmode, DCmode, TCmode and large
5759 vector modes. */
5760 || GET_MODE_SIZE (mode) > 8);
5761 }
5762 else
5763 {
5764 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5765 || (type
5766 && AGGREGATE_TYPE_P (type)
5767 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5768 /* Enforce the 2-word cap for passing arguments in registers.
5769 This affects CTImode, TCmode and large vector modes. */
5770 || GET_MODE_SIZE (mode) > 16);
5771 }
5772 }
5773
5774 /* Handle the FUNCTION_ARG_ADVANCE macro.
5775 Update the data in CUM to advance over an argument
5776 of mode MODE and data type TYPE.
5777 TYPE is null for libcalls where that information may not be available. */
5778
5779 void
5780 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5781 tree type, int named)
5782 {
5783 int slotno, regno, padding;
5784
5785 /* We pass 0 for incoming_p here, it doesn't matter. */
5786 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5787
5788 /* If register required leading padding, add it. */
5789 if (slotno != -1)
5790 cum->words += padding;
5791
5792 if (TARGET_ARCH32)
5793 {
5794 cum->words += (mode != BLKmode
5795 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5796 : ROUND_ADVANCE (int_size_in_bytes (type)));
5797 }
5798 else
5799 {
5800 if (type && AGGREGATE_TYPE_P (type))
5801 {
5802 int size = int_size_in_bytes (type);
5803
5804 if (size <= 8)
5805 ++cum->words;
5806 else if (size <= 16)
5807 cum->words += 2;
5808 else /* passed by reference */
5809 ++cum->words;
5810 }
5811 else
5812 {
5813 cum->words += (mode != BLKmode
5814 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5815 : ROUND_ADVANCE (int_size_in_bytes (type)));
5816 }
5817 }
5818 }
5819
5820 /* Handle the FUNCTION_ARG_PADDING macro.
5821 For the 64 bit ABI structs are always stored left shifted in their
5822 argument slot. */
5823
5824 enum direction
5825 function_arg_padding (enum machine_mode mode, tree type)
5826 {
5827 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5828 return upward;
5829
5830 /* Fall back to the default. */
5831 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5832 }
5833
5834 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5835 Specify whether to return the return value in memory. */
5836
5837 static bool
5838 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5839 {
5840 if (TARGET_ARCH32)
5841 /* Original SPARC 32-bit ABI says that quad-precision floats
5842 and all structures are returned in memory. Extended ABI
5843 (as implemented by the Sun compiler) says that all complex
5844 floats are returned in registers (8 FP registers at most
5845 for '_Complex long double'). Return all complex integers
5846 in registers (4 at most for '_Complex long long'). */
5847 return (TYPE_MODE (type) == BLKmode
5848 || TYPE_MODE (type) == TFmode
5849 /* Integral vector types follow the scalar FP types conventions. */
5850 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5851 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5852 /* FP vector types follow the complex FP types conventions. */
5853 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5854 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5855 else
5856 /* Original SPARC 64-bit ABI says that structures and unions
5857 smaller than 32 bytes are returned in registers. Extended
5858 ABI (as implemented by the Sun compiler) says that all complex
5859 floats are returned in registers (8 FP registers at most
5860 for '_Complex long double'). Return all complex integers
5861 in registers (4 at most for '_Complex TItype'). */
5862 return ((TYPE_MODE (type) == BLKmode
5863 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5864 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5865 }
5866
5867 /* Handle the TARGET_STRUCT_VALUE target hook.
5868 Return where to find the structure return value address. */
5869
5870 static rtx
5871 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5872 {
5873 if (TARGET_ARCH64)
5874 return 0;
5875 else
5876 {
5877 if (incoming)
5878 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5879 STRUCT_VALUE_OFFSET));
5880 else
5881 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5882 STRUCT_VALUE_OFFSET));
5883 }
5884 }
5885
5886 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5887 For v9, function return values are subject to the same rules as arguments,
5888 except that up to 32 bytes may be returned in registers. */
5889
5890 rtx
5891 function_value (tree type, enum machine_mode mode, int incoming_p)
5892 {
5893 /* Beware that the two values are swapped here wrt function_arg. */
5894 int regbase = (incoming_p
5895 ? SPARC_OUTGOING_INT_ARG_FIRST
5896 : SPARC_INCOMING_INT_ARG_FIRST);
5897 int regno;
5898
5899 if (TARGET_ARCH64 && type)
5900 {
5901 if (TREE_CODE (type) == RECORD_TYPE)
5902 {
5903 /* Structures up to 32 bytes in size are passed in registers,
5904 promoted to fp registers where possible. */
5905
5906 if (int_size_in_bytes (type) > 32)
5907 abort (); /* shouldn't get here */
5908
5909 return function_arg_record_value (type, mode, 0, 1, regbase);
5910 }
5911 else if (TREE_CODE (type) == UNION_TYPE)
5912 {
5913 HOST_WIDE_INT size = int_size_in_bytes (type);
5914
5915 if (size > 32)
5916 abort (); /* shouldn't get here */
5917
5918 return function_arg_union_value (size, mode, regbase);
5919 }
5920 else if (AGGREGATE_TYPE_P (type))
5921 {
5922 /* All other aggregate types are passed in an integer register
5923 in a mode corresponding to the size of the type. */
5924 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5925
5926 if (bytes > 32)
5927 abort (); /* shouldn't get here */
5928
5929 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5930
5931 /* ??? We probably should have made the same ABI change in
5932 3.4.0 as the one we made for unions. The latter was
5933 required by the SCD though, while the former is not
5934 specified, so we favored compatibility and efficiency.
5935
5936 Now we're stuck for aggregates larger than 16 bytes,
5937 because OImode vanished in the meantime. Let's not
5938 try to be unduly clever, and simply follow the ABI
5939 for unions in that case. */
5940 if (mode == BLKmode)
5941 return function_arg_union_value (bytes, mode, regbase);
5942 }
5943 else if (GET_MODE_CLASS (mode) == MODE_INT
5944 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5945 mode = word_mode;
5946 }
5947
5948 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5949 regno = SPARC_FP_ARG_FIRST;
5950 else
5951 regno = regbase;
5952
5953 return gen_rtx_REG (mode, regno);
5954 }
5955
5956 /* Do what is necessary for `va_start'. We look at the current function
5957 to determine if stdarg or varargs is used and return the address of
5958 the first unnamed parameter. */
5959
5960 static rtx
5961 sparc_builtin_saveregs (void)
5962 {
5963 int first_reg = current_function_args_info.words;
5964 rtx address;
5965 int regno;
5966
5967 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5968 emit_move_insn (gen_rtx_MEM (word_mode,
5969 gen_rtx_PLUS (Pmode,
5970 frame_pointer_rtx,
5971 GEN_INT (FIRST_PARM_OFFSET (0)
5972 + (UNITS_PER_WORD
5973 * regno)))),
5974 gen_rtx_REG (word_mode,
5975 SPARC_INCOMING_INT_ARG_FIRST + regno));
5976
5977 address = gen_rtx_PLUS (Pmode,
5978 frame_pointer_rtx,
5979 GEN_INT (FIRST_PARM_OFFSET (0)
5980 + UNITS_PER_WORD * first_reg));
5981
5982 return address;
5983 }
5984
5985 /* Implement `va_start' for stdarg. */
5986
5987 void
5988 sparc_va_start (tree valist, rtx nextarg)
5989 {
5990 nextarg = expand_builtin_saveregs ();
5991 std_expand_builtin_va_start (valist, nextarg);
5992 }
5993
5994 /* Implement `va_arg' for stdarg. */
5995
5996 static tree
5997 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5998 {
5999 HOST_WIDE_INT size, rsize, align;
6000 tree addr, incr;
6001 bool indirect;
6002 tree ptrtype = build_pointer_type (type);
6003
6004 if (function_arg_pass_by_reference (0, TYPE_MODE (type), type, 0))
6005 {
6006 indirect = true;
6007 size = rsize = UNITS_PER_WORD;
6008 align = 0;
6009 }
6010 else
6011 {
6012 indirect = false;
6013 size = int_size_in_bytes (type);
6014 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6015 align = 0;
6016
6017 if (TARGET_ARCH64)
6018 {
6019 /* For SPARC64, objects requiring 16-byte alignment get it. */
6020 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6021 align = 2 * UNITS_PER_WORD;
6022
6023 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6024 are given whole slots as needed. */
6025 if (AGGREGATE_TYPE_P (type))
6026 {
6027 if (size == 0)
6028 size = rsize = UNITS_PER_WORD;
6029 else
6030 size = rsize;
6031 }
6032 }
6033 }
6034
6035 incr = valist;
6036 if (align)
6037 {
6038 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6039 ssize_int (align - 1)));
6040 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6041 ssize_int (-align)));
6042 }
6043
6044 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6045 addr = incr;
6046
6047 if (BYTES_BIG_ENDIAN && size < rsize)
6048 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6049 ssize_int (rsize - size)));
6050
6051 if (indirect)
6052 {
6053 addr = fold_convert (build_pointer_type (ptrtype), addr);
6054 addr = build_fold_indirect_ref (addr);
6055 }
6056 /* If the address isn't aligned properly for the type,
6057 we may need to copy to a temporary.
6058 FIXME: This is inefficient. Usually we can do this
6059 in registers. */
6060 else if (align == 0
6061 && TYPE_ALIGN (type) > BITS_PER_WORD)
6062 {
6063 tree tmp = create_tmp_var (type, "va_arg_tmp");
6064 tree dest_addr = build_fold_addr_expr (tmp);
6065
6066 tree copy = build_function_call_expr
6067 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6068 tree_cons (NULL_TREE, dest_addr,
6069 tree_cons (NULL_TREE, addr,
6070 tree_cons (NULL_TREE, size_int (rsize),
6071 NULL_TREE))));
6072
6073 gimplify_and_add (copy, pre_p);
6074 addr = dest_addr;
6075 }
6076 else
6077 addr = fold_convert (ptrtype, addr);
6078
6079 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6080 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6081 gimplify_and_add (incr, post_p);
6082
6083 return build_fold_indirect_ref (addr);
6084 }
6085 \f
6086 /* Return the string to output a conditional branch to LABEL, which is
6087 the operand number of the label. OP is the conditional expression.
6088 XEXP (OP, 0) is assumed to be a condition code register (integer or
6089 floating point) and its mode specifies what kind of comparison we made.
6090
6091 REVERSED is nonzero if we should reverse the sense of the comparison.
6092
6093 ANNUL is nonzero if we should generate an annulling branch.
6094
6095 NOOP is nonzero if we have to follow this branch by a noop.
6096
6097 INSN, if set, is the insn. */
6098
6099 const char *
6100 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6101 int noop, rtx insn)
6102 {
6103 static char string[64];
6104 enum rtx_code code = GET_CODE (op);
6105 rtx cc_reg = XEXP (op, 0);
6106 enum machine_mode mode = GET_MODE (cc_reg);
6107 const char *labelno, *branch;
6108 int spaces = 8, far;
6109 char *p;
6110
6111 /* v9 branches are limited to +-1MB. If it is too far away,
6112 change
6113
6114 bne,pt %xcc, .LC30
6115
6116 to
6117
6118 be,pn %xcc, .+12
6119 nop
6120 ba .LC30
6121
6122 and
6123
6124 fbne,a,pn %fcc2, .LC29
6125
6126 to
6127
6128 fbe,pt %fcc2, .+16
6129 nop
6130 ba .LC29 */
6131
6132 far = get_attr_length (insn) >= 3;
6133 if (reversed ^ far)
6134 {
6135 /* Reversal of FP compares takes care -- an ordered compare
6136 becomes an unordered compare and vice versa. */
6137 if (mode == CCFPmode || mode == CCFPEmode)
6138 code = reverse_condition_maybe_unordered (code);
6139 else
6140 code = reverse_condition (code);
6141 }
6142
6143 /* Start by writing the branch condition. */
6144 if (mode == CCFPmode || mode == CCFPEmode)
6145 {
6146 switch (code)
6147 {
6148 case NE:
6149 branch = "fbne";
6150 break;
6151 case EQ:
6152 branch = "fbe";
6153 break;
6154 case GE:
6155 branch = "fbge";
6156 break;
6157 case GT:
6158 branch = "fbg";
6159 break;
6160 case LE:
6161 branch = "fble";
6162 break;
6163 case LT:
6164 branch = "fbl";
6165 break;
6166 case UNORDERED:
6167 branch = "fbu";
6168 break;
6169 case ORDERED:
6170 branch = "fbo";
6171 break;
6172 case UNGT:
6173 branch = "fbug";
6174 break;
6175 case UNLT:
6176 branch = "fbul";
6177 break;
6178 case UNEQ:
6179 branch = "fbue";
6180 break;
6181 case UNGE:
6182 branch = "fbuge";
6183 break;
6184 case UNLE:
6185 branch = "fbule";
6186 break;
6187 case LTGT:
6188 branch = "fblg";
6189 break;
6190
6191 default:
6192 abort ();
6193 }
6194
6195 /* ??? !v9: FP branches cannot be preceded by another floating point
6196 insn. Because there is currently no concept of pre-delay slots,
6197 we can fix this only by always emitting a nop before a floating
6198 point branch. */
6199
6200 string[0] = '\0';
6201 if (! TARGET_V9)
6202 strcpy (string, "nop\n\t");
6203 strcat (string, branch);
6204 }
6205 else
6206 {
6207 switch (code)
6208 {
6209 case NE:
6210 branch = "bne";
6211 break;
6212 case EQ:
6213 branch = "be";
6214 break;
6215 case GE:
6216 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6217 branch = "bpos";
6218 else
6219 branch = "bge";
6220 break;
6221 case GT:
6222 branch = "bg";
6223 break;
6224 case LE:
6225 branch = "ble";
6226 break;
6227 case LT:
6228 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6229 branch = "bneg";
6230 else
6231 branch = "bl";
6232 break;
6233 case GEU:
6234 branch = "bgeu";
6235 break;
6236 case GTU:
6237 branch = "bgu";
6238 break;
6239 case LEU:
6240 branch = "bleu";
6241 break;
6242 case LTU:
6243 branch = "blu";
6244 break;
6245
6246 default:
6247 abort ();
6248 }
6249 strcpy (string, branch);
6250 }
6251 spaces -= strlen (branch);
6252 p = strchr (string, '\0');
6253
6254 /* Now add the annulling, the label, and a possible noop. */
6255 if (annul && ! far)
6256 {
6257 strcpy (p, ",a");
6258 p += 2;
6259 spaces -= 2;
6260 }
6261
6262 if (! TARGET_V9)
6263 labelno = "";
6264 else
6265 {
6266 rtx note;
6267 int v8 = 0;
6268
6269 if (! far && insn && INSN_ADDRESSES_SET_P ())
6270 {
6271 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6272 - INSN_ADDRESSES (INSN_UID (insn)));
6273 /* Leave some instructions for "slop". */
6274 if (delta < -260000 || delta >= 260000)
6275 v8 = 1;
6276 }
6277
6278 if (mode == CCFPmode || mode == CCFPEmode)
6279 {
6280 static char v9_fcc_labelno[] = "%%fccX, ";
6281 /* Set the char indicating the number of the fcc reg to use. */
6282 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6283 labelno = v9_fcc_labelno;
6284 if (v8)
6285 {
6286 if (REGNO (cc_reg) == SPARC_FCC_REG)
6287 labelno = "";
6288 else
6289 abort ();
6290 }
6291 }
6292 else if (mode == CCXmode || mode == CCX_NOOVmode)
6293 {
6294 labelno = "%%xcc, ";
6295 if (v8)
6296 abort ();
6297 }
6298 else
6299 {
6300 labelno = "%%icc, ";
6301 if (v8)
6302 labelno = "";
6303 }
6304
6305 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6306 {
6307 strcpy (p,
6308 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6309 ? ",pt" : ",pn");
6310 p += 3;
6311 spaces -= 3;
6312 }
6313 }
6314 if (spaces > 0)
6315 *p++ = '\t';
6316 else
6317 *p++ = ' ';
6318 strcpy (p, labelno);
6319 p = strchr (p, '\0');
6320 if (far)
6321 {
6322 strcpy (p, ".+12\n\t nop\n\tb\t");
6323 if (annul || noop)
6324 p[3] = '6';
6325 p += 14;
6326 }
6327 *p++ = '%';
6328 *p++ = 'l';
6329 /* Set the char indicating the number of the operand containing the
6330 label_ref. */
6331 *p++ = label + '0';
6332 *p = '\0';
6333 if (noop)
6334 strcpy (p, "\n\t nop");
6335
6336 return string;
6337 }
6338
6339 /* Emit a library call comparison between floating point X and Y.
6340 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6341 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6342 values as arguments instead of the TFmode registers themselves,
6343 that's why we cannot call emit_float_lib_cmp. */
6344 void
6345 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6346 {
6347 const char *qpfunc;
6348 rtx slot0, slot1, result, tem, tem2;
6349 enum machine_mode mode;
6350
6351 switch (comparison)
6352 {
6353 case EQ:
6354 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6355 break;
6356
6357 case NE:
6358 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6359 break;
6360
6361 case GT:
6362 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6363 break;
6364
6365 case GE:
6366 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6367 break;
6368
6369 case LT:
6370 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6371 break;
6372
6373 case LE:
6374 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6375 break;
6376
6377 case ORDERED:
6378 case UNORDERED:
6379 case UNGT:
6380 case UNLT:
6381 case UNEQ:
6382 case UNGE:
6383 case UNLE:
6384 case LTGT:
6385 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6386 break;
6387
6388 default:
6389 abort();
6390 break;
6391 }
6392
6393 if (TARGET_ARCH64)
6394 {
6395 if (GET_CODE (x) != MEM)
6396 {
6397 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6398 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6399 }
6400 else
6401 slot0 = x;
6402
6403 if (GET_CODE (y) != MEM)
6404 {
6405 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6406 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6407 }
6408 else
6409 slot1 = y;
6410
6411 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6412 DImode, 2,
6413 XEXP (slot0, 0), Pmode,
6414 XEXP (slot1, 0), Pmode);
6415
6416 mode = DImode;
6417 }
6418 else
6419 {
6420 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6421 SImode, 2,
6422 x, TFmode, y, TFmode);
6423
6424 mode = SImode;
6425 }
6426
6427
6428 /* Immediately move the result of the libcall into a pseudo
6429 register so reload doesn't clobber the value if it needs
6430 the return register for a spill reg. */
6431 result = gen_reg_rtx (mode);
6432 emit_move_insn (result, hard_libcall_value (mode));
6433
6434 switch (comparison)
6435 {
6436 default:
6437 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6438 break;
6439 case ORDERED:
6440 case UNORDERED:
6441 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6442 NULL_RTX, mode, 0);
6443 break;
6444 case UNGT:
6445 case UNGE:
6446 emit_cmp_insn (result, const1_rtx,
6447 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6448 break;
6449 case UNLE:
6450 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6451 break;
6452 case UNLT:
6453 tem = gen_reg_rtx (mode);
6454 if (TARGET_ARCH32)
6455 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6456 else
6457 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6458 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6459 break;
6460 case UNEQ:
6461 case LTGT:
6462 tem = gen_reg_rtx (mode);
6463 if (TARGET_ARCH32)
6464 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6465 else
6466 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6467 tem2 = gen_reg_rtx (mode);
6468 if (TARGET_ARCH32)
6469 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6470 else
6471 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6472 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6473 NULL_RTX, mode, 0);
6474 break;
6475 }
6476 }
6477
6478 /* Generate an unsigned DImode to FP conversion. This is the same code
6479 optabs would emit if we didn't have TFmode patterns. */
6480
6481 void
6482 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6483 {
6484 rtx neglab, donelab, i0, i1, f0, in, out;
6485
6486 out = operands[0];
6487 in = force_reg (DImode, operands[1]);
6488 neglab = gen_label_rtx ();
6489 donelab = gen_label_rtx ();
6490 i0 = gen_reg_rtx (DImode);
6491 i1 = gen_reg_rtx (DImode);
6492 f0 = gen_reg_rtx (mode);
6493
6494 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6495
6496 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6497 emit_jump_insn (gen_jump (donelab));
6498 emit_barrier ();
6499
6500 emit_label (neglab);
6501
6502 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6503 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6504 emit_insn (gen_iordi3 (i0, i0, i1));
6505 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6506 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6507
6508 emit_label (donelab);
6509 }
6510
6511 /* Generate an FP to unsigned DImode conversion. This is the same code
6512 optabs would emit if we didn't have TFmode patterns. */
6513
6514 void
6515 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6516 {
6517 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6518
6519 out = operands[0];
6520 in = force_reg (mode, operands[1]);
6521 neglab = gen_label_rtx ();
6522 donelab = gen_label_rtx ();
6523 i0 = gen_reg_rtx (DImode);
6524 i1 = gen_reg_rtx (DImode);
6525 limit = gen_reg_rtx (mode);
6526 f0 = gen_reg_rtx (mode);
6527
6528 emit_move_insn (limit,
6529 CONST_DOUBLE_FROM_REAL_VALUE (
6530 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6531 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6532
6533 emit_insn (gen_rtx_SET (VOIDmode,
6534 out,
6535 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6536 emit_jump_insn (gen_jump (donelab));
6537 emit_barrier ();
6538
6539 emit_label (neglab);
6540
6541 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6542 emit_insn (gen_rtx_SET (VOIDmode,
6543 i0,
6544 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6545 emit_insn (gen_movdi (i1, const1_rtx));
6546 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6547 emit_insn (gen_xordi3 (out, i0, i1));
6548
6549 emit_label (donelab);
6550 }
6551
6552 /* Return the string to output a conditional branch to LABEL, testing
6553 register REG. LABEL is the operand number of the label; REG is the
6554 operand number of the reg. OP is the conditional expression. The mode
6555 of REG says what kind of comparison we made.
6556
6557 REVERSED is nonzero if we should reverse the sense of the comparison.
6558
6559 ANNUL is nonzero if we should generate an annulling branch.
6560
6561 NOOP is nonzero if we have to follow this branch by a noop. */
6562
6563 const char *
6564 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6565 int annul, int noop, rtx insn)
6566 {
6567 static char string[64];
6568 enum rtx_code code = GET_CODE (op);
6569 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6570 rtx note;
6571 int far;
6572 char *p;
6573
6574 /* branch on register are limited to +-128KB. If it is too far away,
6575 change
6576
6577 brnz,pt %g1, .LC30
6578
6579 to
6580
6581 brz,pn %g1, .+12
6582 nop
6583 ba,pt %xcc, .LC30
6584
6585 and
6586
6587 brgez,a,pn %o1, .LC29
6588
6589 to
6590
6591 brlz,pt %o1, .+16
6592 nop
6593 ba,pt %xcc, .LC29 */
6594
6595 far = get_attr_length (insn) >= 3;
6596
6597 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6598 if (reversed ^ far)
6599 code = reverse_condition (code);
6600
6601 /* Only 64 bit versions of these instructions exist. */
6602 if (mode != DImode)
6603 abort ();
6604
6605 /* Start by writing the branch condition. */
6606
6607 switch (code)
6608 {
6609 case NE:
6610 strcpy (string, "brnz");
6611 break;
6612
6613 case EQ:
6614 strcpy (string, "brz");
6615 break;
6616
6617 case GE:
6618 strcpy (string, "brgez");
6619 break;
6620
6621 case LT:
6622 strcpy (string, "brlz");
6623 break;
6624
6625 case LE:
6626 strcpy (string, "brlez");
6627 break;
6628
6629 case GT:
6630 strcpy (string, "brgz");
6631 break;
6632
6633 default:
6634 abort ();
6635 }
6636
6637 p = strchr (string, '\0');
6638
6639 /* Now add the annulling, reg, label, and nop. */
6640 if (annul && ! far)
6641 {
6642 strcpy (p, ",a");
6643 p += 2;
6644 }
6645
6646 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6647 {
6648 strcpy (p,
6649 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6650 ? ",pt" : ",pn");
6651 p += 3;
6652 }
6653
6654 *p = p < string + 8 ? '\t' : ' ';
6655 p++;
6656 *p++ = '%';
6657 *p++ = '0' + reg;
6658 *p++ = ',';
6659 *p++ = ' ';
6660 if (far)
6661 {
6662 int veryfar = 1, delta;
6663
6664 if (INSN_ADDRESSES_SET_P ())
6665 {
6666 delta = (INSN_ADDRESSES (INSN_UID (dest))
6667 - INSN_ADDRESSES (INSN_UID (insn)));
6668 /* Leave some instructions for "slop". */
6669 if (delta >= -260000 && delta < 260000)
6670 veryfar = 0;
6671 }
6672
6673 strcpy (p, ".+12\n\t nop\n\t");
6674 if (annul || noop)
6675 p[3] = '6';
6676 p += 12;
6677 if (veryfar)
6678 {
6679 strcpy (p, "b\t");
6680 p += 2;
6681 }
6682 else
6683 {
6684 strcpy (p, "ba,pt\t%%xcc, ");
6685 p += 13;
6686 }
6687 }
6688 *p++ = '%';
6689 *p++ = 'l';
6690 *p++ = '0' + label;
6691 *p = '\0';
6692
6693 if (noop)
6694 strcpy (p, "\n\t nop");
6695
6696 return string;
6697 }
6698
6699 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6700 Such instructions cannot be used in the delay slot of return insn on v9.
6701 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6702 */
6703
6704 static int
6705 epilogue_renumber (register rtx *where, int test)
6706 {
6707 register const char *fmt;
6708 register int i;
6709 register enum rtx_code code;
6710
6711 if (*where == 0)
6712 return 0;
6713
6714 code = GET_CODE (*where);
6715
6716 switch (code)
6717 {
6718 case REG:
6719 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6720 return 1;
6721 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6722 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6723 case SCRATCH:
6724 case CC0:
6725 case PC:
6726 case CONST_INT:
6727 case CONST_DOUBLE:
6728 return 0;
6729
6730 /* Do not replace the frame pointer with the stack pointer because
6731 it can cause the delayed instruction to load below the stack.
6732 This occurs when instructions like:
6733
6734 (set (reg/i:SI 24 %i0)
6735 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6736 (const_int -20 [0xffffffec])) 0))
6737
6738 are in the return delayed slot. */
6739 case PLUS:
6740 if (GET_CODE (XEXP (*where, 0)) == REG
6741 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6742 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6743 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6744 return 1;
6745 break;
6746
6747 case MEM:
6748 if (SPARC_STACK_BIAS
6749 && GET_CODE (XEXP (*where, 0)) == REG
6750 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6751 return 1;
6752 break;
6753
6754 default:
6755 break;
6756 }
6757
6758 fmt = GET_RTX_FORMAT (code);
6759
6760 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6761 {
6762 if (fmt[i] == 'E')
6763 {
6764 register int j;
6765 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6766 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6767 return 1;
6768 }
6769 else if (fmt[i] == 'e'
6770 && epilogue_renumber (&(XEXP (*where, i)), test))
6771 return 1;
6772 }
6773 return 0;
6774 }
6775 \f
6776 /* Leaf functions and non-leaf functions have different needs. */
6777
6778 static const int
6779 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6780
6781 static const int
6782 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6783
6784 static const int *const reg_alloc_orders[] = {
6785 reg_leaf_alloc_order,
6786 reg_nonleaf_alloc_order};
6787
6788 void
6789 order_regs_for_local_alloc (void)
6790 {
6791 static int last_order_nonleaf = 1;
6792
6793 if (regs_ever_live[15] != last_order_nonleaf)
6794 {
6795 last_order_nonleaf = !last_order_nonleaf;
6796 memcpy ((char *) reg_alloc_order,
6797 (const char *) reg_alloc_orders[last_order_nonleaf],
6798 FIRST_PSEUDO_REGISTER * sizeof (int));
6799 }
6800 }
6801 \f
6802 /* Return 1 if REG and MEM are legitimate enough to allow the various
6803 mem<-->reg splits to be run. */
6804
6805 int
6806 sparc_splitdi_legitimate (rtx reg, rtx mem)
6807 {
6808 /* Punt if we are here by mistake. */
6809 if (! reload_completed)
6810 abort ();
6811
6812 /* We must have an offsettable memory reference. */
6813 if (! offsettable_memref_p (mem))
6814 return 0;
6815
6816 /* If we have legitimate args for ldd/std, we do not want
6817 the split to happen. */
6818 if ((REGNO (reg) % 2) == 0
6819 && mem_min_alignment (mem, 8))
6820 return 0;
6821
6822 /* Success. */
6823 return 1;
6824 }
6825
6826 /* Return 1 if x and y are some kind of REG and they refer to
6827 different hard registers. This test is guaranteed to be
6828 run after reload. */
6829
6830 int
6831 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6832 {
6833 if (GET_CODE (x) != REG)
6834 return 0;
6835 if (GET_CODE (y) != REG)
6836 return 0;
6837 if (REGNO (x) == REGNO (y))
6838 return 0;
6839 return 1;
6840 }
6841
6842 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6843 This makes them candidates for using ldd and std insns.
6844
6845 Note reg1 and reg2 *must* be hard registers. */
6846
6847 int
6848 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6849 {
6850 /* We might have been passed a SUBREG. */
6851 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6852 return 0;
6853
6854 if (REGNO (reg1) % 2 != 0)
6855 return 0;
6856
6857 /* Integer ldd is deprecated in SPARC V9 */
6858 if (TARGET_V9 && REGNO (reg1) < 32)
6859 return 0;
6860
6861 return (REGNO (reg1) == REGNO (reg2) - 1);
6862 }
6863
6864 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6865 an ldd or std insn.
6866
6867 This can only happen when addr1 and addr2, the addresses in mem1
6868 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6869 addr1 must also be aligned on a 64-bit boundary.
6870
6871 Also iff dependent_reg_rtx is not null it should not be used to
6872 compute the address for mem1, i.e. we cannot optimize a sequence
6873 like:
6874 ld [%o0], %o0
6875 ld [%o0 + 4], %o1
6876 to
6877 ldd [%o0], %o0
6878 nor:
6879 ld [%g3 + 4], %g3
6880 ld [%g3], %g2
6881 to
6882 ldd [%g3], %g2
6883
6884 But, note that the transformation from:
6885 ld [%g2 + 4], %g3
6886 ld [%g2], %g2
6887 to
6888 ldd [%g2], %g2
6889 is perfectly fine. Thus, the peephole2 patterns always pass us
6890 the destination register of the first load, never the second one.
6891
6892 For stores we don't have a similar problem, so dependent_reg_rtx is
6893 NULL_RTX. */
6894
6895 int
6896 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6897 {
6898 rtx addr1, addr2;
6899 unsigned int reg1;
6900 HOST_WIDE_INT offset1;
6901
6902 /* The mems cannot be volatile. */
6903 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6904 return 0;
6905
6906 /* MEM1 should be aligned on a 64-bit boundary. */
6907 if (MEM_ALIGN (mem1) < 64)
6908 return 0;
6909
6910 addr1 = XEXP (mem1, 0);
6911 addr2 = XEXP (mem2, 0);
6912
6913 /* Extract a register number and offset (if used) from the first addr. */
6914 if (GET_CODE (addr1) == PLUS)
6915 {
6916 /* If not a REG, return zero. */
6917 if (GET_CODE (XEXP (addr1, 0)) != REG)
6918 return 0;
6919 else
6920 {
6921 reg1 = REGNO (XEXP (addr1, 0));
6922 /* The offset must be constant! */
6923 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6924 return 0;
6925 offset1 = INTVAL (XEXP (addr1, 1));
6926 }
6927 }
6928 else if (GET_CODE (addr1) != REG)
6929 return 0;
6930 else
6931 {
6932 reg1 = REGNO (addr1);
6933 /* This was a simple (mem (reg)) expression. Offset is 0. */
6934 offset1 = 0;
6935 }
6936
6937 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6938 if (GET_CODE (addr2) != PLUS)
6939 return 0;
6940
6941 if (GET_CODE (XEXP (addr2, 0)) != REG
6942 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6943 return 0;
6944
6945 if (reg1 != REGNO (XEXP (addr2, 0)))
6946 return 0;
6947
6948 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6949 return 0;
6950
6951 /* The first offset must be evenly divisible by 8 to ensure the
6952 address is 64 bit aligned. */
6953 if (offset1 % 8 != 0)
6954 return 0;
6955
6956 /* The offset for the second addr must be 4 more than the first addr. */
6957 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6958 return 0;
6959
6960 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6961 instructions. */
6962 return 1;
6963 }
6964
6965 /* Return 1 if reg is a pseudo, or is the first register in
6966 a hard register pair. This makes it a candidate for use in
6967 ldd and std insns. */
6968
6969 int
6970 register_ok_for_ldd (rtx reg)
6971 {
6972 /* We might have been passed a SUBREG. */
6973 if (GET_CODE (reg) != REG)
6974 return 0;
6975
6976 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6977 return (REGNO (reg) % 2 == 0);
6978 else
6979 return 1;
6980 }
6981 \f
6982 /* Print operand X (an rtx) in assembler syntax to file FILE.
6983 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6984 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6985
6986 void
6987 print_operand (FILE *file, rtx x, int code)
6988 {
6989 switch (code)
6990 {
6991 case '#':
6992 /* Output a 'nop' if there's nothing for the delay slot. */
6993 if (dbr_sequence_length () == 0)
6994 fputs ("\n\t nop", file);
6995 return;
6996 case '*':
6997 /* Output an annul flag if there's nothing for the delay slot and we
6998 are optimizing. This is always used with '(' below. */
6999 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7000 this is a dbx bug. So, we only do this when optimizing. */
7001 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7002 Always emit a nop in case the next instruction is a branch. */
7003 if (dbr_sequence_length () == 0
7004 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7005 fputs (",a", file);
7006 return;
7007 case '(':
7008 /* Output a 'nop' if there's nothing for the delay slot and we are
7009 not optimizing. This is always used with '*' above. */
7010 if (dbr_sequence_length () == 0
7011 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7012 fputs ("\n\t nop", file);
7013 return;
7014 case '_':
7015 /* Output the Embedded Medium/Anywhere code model base register. */
7016 fputs (EMBMEDANY_BASE_REG, file);
7017 return;
7018 case '@':
7019 /* Print out what we are using as the frame pointer. This might
7020 be %fp, or might be %sp+offset. */
7021 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
7022 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC,
7023 reg_names[REGNO (frame_base_reg)], frame_base_offset);
7024 return;
7025 case '&':
7026 /* Print some local dynamic TLS name. */
7027 assemble_name (file, get_some_local_dynamic_name ());
7028 return;
7029 case 'Y':
7030 /* Adjust the operand to take into account a RESTORE operation. */
7031 if (GET_CODE (x) == CONST_INT)
7032 break;
7033 else if (GET_CODE (x) != REG)
7034 output_operand_lossage ("invalid %%Y operand");
7035 else if (REGNO (x) < 8)
7036 fputs (reg_names[REGNO (x)], file);
7037 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7038 fputs (reg_names[REGNO (x)-16], file);
7039 else
7040 output_operand_lossage ("invalid %%Y operand");
7041 return;
7042 case 'L':
7043 /* Print out the low order register name of a register pair. */
7044 if (WORDS_BIG_ENDIAN)
7045 fputs (reg_names[REGNO (x)+1], file);
7046 else
7047 fputs (reg_names[REGNO (x)], file);
7048 return;
7049 case 'H':
7050 /* Print out the high order register name of a register pair. */
7051 if (WORDS_BIG_ENDIAN)
7052 fputs (reg_names[REGNO (x)], file);
7053 else
7054 fputs (reg_names[REGNO (x)+1], file);
7055 return;
7056 case 'R':
7057 /* Print out the second register name of a register pair or quad.
7058 I.e., R (%o0) => %o1. */
7059 fputs (reg_names[REGNO (x)+1], file);
7060 return;
7061 case 'S':
7062 /* Print out the third register name of a register quad.
7063 I.e., S (%o0) => %o2. */
7064 fputs (reg_names[REGNO (x)+2], file);
7065 return;
7066 case 'T':
7067 /* Print out the fourth register name of a register quad.
7068 I.e., T (%o0) => %o3. */
7069 fputs (reg_names[REGNO (x)+3], file);
7070 return;
7071 case 'x':
7072 /* Print a condition code register. */
7073 if (REGNO (x) == SPARC_ICC_REG)
7074 {
7075 /* We don't handle CC[X]_NOOVmode because they're not supposed
7076 to occur here. */
7077 if (GET_MODE (x) == CCmode)
7078 fputs ("%icc", file);
7079 else if (GET_MODE (x) == CCXmode)
7080 fputs ("%xcc", file);
7081 else
7082 abort ();
7083 }
7084 else
7085 /* %fccN register */
7086 fputs (reg_names[REGNO (x)], file);
7087 return;
7088 case 'm':
7089 /* Print the operand's address only. */
7090 output_address (XEXP (x, 0));
7091 return;
7092 case 'r':
7093 /* In this case we need a register. Use %g0 if the
7094 operand is const0_rtx. */
7095 if (x == const0_rtx
7096 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7097 {
7098 fputs ("%g0", file);
7099 return;
7100 }
7101 else
7102 break;
7103
7104 case 'A':
7105 switch (GET_CODE (x))
7106 {
7107 case IOR: fputs ("or", file); break;
7108 case AND: fputs ("and", file); break;
7109 case XOR: fputs ("xor", file); break;
7110 default: output_operand_lossage ("invalid %%A operand");
7111 }
7112 return;
7113
7114 case 'B':
7115 switch (GET_CODE (x))
7116 {
7117 case IOR: fputs ("orn", file); break;
7118 case AND: fputs ("andn", file); break;
7119 case XOR: fputs ("xnor", file); break;
7120 default: output_operand_lossage ("invalid %%B operand");
7121 }
7122 return;
7123
7124 /* These are used by the conditional move instructions. */
7125 case 'c' :
7126 case 'C':
7127 {
7128 enum rtx_code rc = GET_CODE (x);
7129
7130 if (code == 'c')
7131 {
7132 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7133 if (mode == CCFPmode || mode == CCFPEmode)
7134 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7135 else
7136 rc = reverse_condition (GET_CODE (x));
7137 }
7138 switch (rc)
7139 {
7140 case NE: fputs ("ne", file); break;
7141 case EQ: fputs ("e", file); break;
7142 case GE: fputs ("ge", file); break;
7143 case GT: fputs ("g", file); break;
7144 case LE: fputs ("le", file); break;
7145 case LT: fputs ("l", file); break;
7146 case GEU: fputs ("geu", file); break;
7147 case GTU: fputs ("gu", file); break;
7148 case LEU: fputs ("leu", file); break;
7149 case LTU: fputs ("lu", file); break;
7150 case LTGT: fputs ("lg", file); break;
7151 case UNORDERED: fputs ("u", file); break;
7152 case ORDERED: fputs ("o", file); break;
7153 case UNLT: fputs ("ul", file); break;
7154 case UNLE: fputs ("ule", file); break;
7155 case UNGT: fputs ("ug", file); break;
7156 case UNGE: fputs ("uge", file); break;
7157 case UNEQ: fputs ("ue", file); break;
7158 default: output_operand_lossage (code == 'c'
7159 ? "invalid %%c operand"
7160 : "invalid %%C operand");
7161 }
7162 return;
7163 }
7164
7165 /* These are used by the movr instruction pattern. */
7166 case 'd':
7167 case 'D':
7168 {
7169 enum rtx_code rc = (code == 'd'
7170 ? reverse_condition (GET_CODE (x))
7171 : GET_CODE (x));
7172 switch (rc)
7173 {
7174 case NE: fputs ("ne", file); break;
7175 case EQ: fputs ("e", file); break;
7176 case GE: fputs ("gez", file); break;
7177 case LT: fputs ("lz", file); break;
7178 case LE: fputs ("lez", file); break;
7179 case GT: fputs ("gz", file); break;
7180 default: output_operand_lossage (code == 'd'
7181 ? "invalid %%d operand"
7182 : "invalid %%D operand");
7183 }
7184 return;
7185 }
7186
7187 case 'b':
7188 {
7189 /* Print a sign-extended character. */
7190 int i = trunc_int_for_mode (INTVAL (x), QImode);
7191 fprintf (file, "%d", i);
7192 return;
7193 }
7194
7195 case 'f':
7196 /* Operand must be a MEM; write its address. */
7197 if (GET_CODE (x) != MEM)
7198 output_operand_lossage ("invalid %%f operand");
7199 output_address (XEXP (x, 0));
7200 return;
7201
7202 case 's':
7203 {
7204 /* Print a sign-extended 32-bit value. */
7205 HOST_WIDE_INT i;
7206 if (GET_CODE(x) == CONST_INT)
7207 i = INTVAL (x);
7208 else if (GET_CODE(x) == CONST_DOUBLE)
7209 i = CONST_DOUBLE_LOW (x);
7210 else
7211 {
7212 output_operand_lossage ("invalid %%s operand");
7213 return;
7214 }
7215 i = trunc_int_for_mode (i, SImode);
7216 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7217 return;
7218 }
7219
7220 case 0:
7221 /* Do nothing special. */
7222 break;
7223
7224 default:
7225 /* Undocumented flag. */
7226 output_operand_lossage ("invalid operand output code");
7227 }
7228
7229 if (GET_CODE (x) == REG)
7230 fputs (reg_names[REGNO (x)], file);
7231 else if (GET_CODE (x) == MEM)
7232 {
7233 fputc ('[', file);
7234 /* Poor Sun assembler doesn't understand absolute addressing. */
7235 if (CONSTANT_P (XEXP (x, 0)))
7236 fputs ("%g0+", file);
7237 output_address (XEXP (x, 0));
7238 fputc (']', file);
7239 }
7240 else if (GET_CODE (x) == HIGH)
7241 {
7242 fputs ("%hi(", file);
7243 output_addr_const (file, XEXP (x, 0));
7244 fputc (')', file);
7245 }
7246 else if (GET_CODE (x) == LO_SUM)
7247 {
7248 print_operand (file, XEXP (x, 0), 0);
7249 if (TARGET_CM_MEDMID)
7250 fputs ("+%l44(", file);
7251 else
7252 fputs ("+%lo(", file);
7253 output_addr_const (file, XEXP (x, 1));
7254 fputc (')', file);
7255 }
7256 else if (GET_CODE (x) == CONST_DOUBLE
7257 && (GET_MODE (x) == VOIDmode
7258 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7259 {
7260 if (CONST_DOUBLE_HIGH (x) == 0)
7261 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7262 else if (CONST_DOUBLE_HIGH (x) == -1
7263 && CONST_DOUBLE_LOW (x) < 0)
7264 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7265 else
7266 output_operand_lossage ("long long constant not a valid immediate operand");
7267 }
7268 else if (GET_CODE (x) == CONST_DOUBLE)
7269 output_operand_lossage ("floating point constant not a valid immediate operand");
7270 else { output_addr_const (file, x); }
7271 }
7272 \f
7273 /* Target hook for assembling integer objects. The sparc version has
7274 special handling for aligned DI-mode objects. */
7275
7276 static bool
7277 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7278 {
7279 /* ??? We only output .xword's for symbols and only then in environments
7280 where the assembler can handle them. */
7281 if (aligned_p && size == 8
7282 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7283 {
7284 if (TARGET_V9)
7285 {
7286 assemble_integer_with_op ("\t.xword\t", x);
7287 return true;
7288 }
7289 else
7290 {
7291 assemble_aligned_integer (4, const0_rtx);
7292 assemble_aligned_integer (4, x);
7293 return true;
7294 }
7295 }
7296 return default_assemble_integer (x, size, aligned_p);
7297 }
7298 \f
7299 /* Return the value of a code used in the .proc pseudo-op that says
7300 what kind of result this function returns. For non-C types, we pick
7301 the closest C type. */
7302
7303 #ifndef SHORT_TYPE_SIZE
7304 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7305 #endif
7306
7307 #ifndef INT_TYPE_SIZE
7308 #define INT_TYPE_SIZE BITS_PER_WORD
7309 #endif
7310
7311 #ifndef LONG_TYPE_SIZE
7312 #define LONG_TYPE_SIZE BITS_PER_WORD
7313 #endif
7314
7315 #ifndef LONG_LONG_TYPE_SIZE
7316 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7317 #endif
7318
7319 #ifndef FLOAT_TYPE_SIZE
7320 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7321 #endif
7322
7323 #ifndef DOUBLE_TYPE_SIZE
7324 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7325 #endif
7326
7327 #ifndef LONG_DOUBLE_TYPE_SIZE
7328 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7329 #endif
7330
7331 unsigned long
7332 sparc_type_code (register tree type)
7333 {
7334 register unsigned long qualifiers = 0;
7335 register unsigned shift;
7336
7337 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7338 setting more, since some assemblers will give an error for this. Also,
7339 we must be careful to avoid shifts of 32 bits or more to avoid getting
7340 unpredictable results. */
7341
7342 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7343 {
7344 switch (TREE_CODE (type))
7345 {
7346 case ERROR_MARK:
7347 return qualifiers;
7348
7349 case ARRAY_TYPE:
7350 qualifiers |= (3 << shift);
7351 break;
7352
7353 case FUNCTION_TYPE:
7354 case METHOD_TYPE:
7355 qualifiers |= (2 << shift);
7356 break;
7357
7358 case POINTER_TYPE:
7359 case REFERENCE_TYPE:
7360 case OFFSET_TYPE:
7361 qualifiers |= (1 << shift);
7362 break;
7363
7364 case RECORD_TYPE:
7365 return (qualifiers | 8);
7366
7367 case UNION_TYPE:
7368 case QUAL_UNION_TYPE:
7369 return (qualifiers | 9);
7370
7371 case ENUMERAL_TYPE:
7372 return (qualifiers | 10);
7373
7374 case VOID_TYPE:
7375 return (qualifiers | 16);
7376
7377 case INTEGER_TYPE:
7378 /* If this is a range type, consider it to be the underlying
7379 type. */
7380 if (TREE_TYPE (type) != 0)
7381 break;
7382
7383 /* Carefully distinguish all the standard types of C,
7384 without messing up if the language is not C. We do this by
7385 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7386 look at both the names and the above fields, but that's redundant.
7387 Any type whose size is between two C types will be considered
7388 to be the wider of the two types. Also, we do not have a
7389 special code to use for "long long", so anything wider than
7390 long is treated the same. Note that we can't distinguish
7391 between "int" and "long" in this code if they are the same
7392 size, but that's fine, since neither can the assembler. */
7393
7394 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7395 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7396
7397 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7398 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7399
7400 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7401 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7402
7403 else
7404 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7405
7406 case REAL_TYPE:
7407 /* If this is a range type, consider it to be the underlying
7408 type. */
7409 if (TREE_TYPE (type) != 0)
7410 break;
7411
7412 /* Carefully distinguish all the standard types of C,
7413 without messing up if the language is not C. */
7414
7415 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7416 return (qualifiers | 6);
7417
7418 else
7419 return (qualifiers | 7);
7420
7421 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7422 /* ??? We need to distinguish between double and float complex types,
7423 but I don't know how yet because I can't reach this code from
7424 existing front-ends. */
7425 return (qualifiers | 7); /* Who knows? */
7426
7427 case VECTOR_TYPE:
7428 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7429 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7430 case FILE_TYPE: /* GNU Pascal FILE type. */
7431 case SET_TYPE: /* GNU Pascal SET type. */
7432 case LANG_TYPE: /* ? */
7433 return qualifiers;
7434
7435 default:
7436 abort (); /* Not a type! */
7437 }
7438 }
7439
7440 return qualifiers;
7441 }
7442 \f
7443 /* Nested function support. */
7444
7445 /* Emit RTL insns to initialize the variable parts of a trampoline.
7446 FNADDR is an RTX for the address of the function's pure code.
7447 CXT is an RTX for the static chain value for the function.
7448
7449 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7450 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7451 (to store insns). This is a bit excessive. Perhaps a different
7452 mechanism would be better here.
7453
7454 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7455
7456 void
7457 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7458 {
7459 /* SPARC 32-bit trampoline:
7460
7461 sethi %hi(fn), %g1
7462 sethi %hi(static), %g2
7463 jmp %g1+%lo(fn)
7464 or %g2, %lo(static), %g2
7465
7466 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7467 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7468 */
7469
7470 emit_move_insn
7471 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7472 expand_binop (SImode, ior_optab,
7473 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7474 size_int (10), 0, 1),
7475 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7476 NULL_RTX, 1, OPTAB_DIRECT));
7477
7478 emit_move_insn
7479 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7480 expand_binop (SImode, ior_optab,
7481 expand_shift (RSHIFT_EXPR, SImode, cxt,
7482 size_int (10), 0, 1),
7483 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7484 NULL_RTX, 1, OPTAB_DIRECT));
7485
7486 emit_move_insn
7487 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7488 expand_binop (SImode, ior_optab,
7489 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7490 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7491 NULL_RTX, 1, OPTAB_DIRECT));
7492
7493 emit_move_insn
7494 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7495 expand_binop (SImode, ior_optab,
7496 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7497 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7498 NULL_RTX, 1, OPTAB_DIRECT));
7499
7500 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7501 aligned on a 16 byte boundary so one flush clears it all. */
7502 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7503 if (sparc_cpu != PROCESSOR_ULTRASPARC
7504 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7505 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7506 plus_constant (tramp, 8)))));
7507
7508 /* Call __enable_execute_stack after writing onto the stack to make sure
7509 the stack address is accessible. */
7510 #ifdef TRANSFER_FROM_TRAMPOLINE
7511 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7512 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7513 #endif
7514
7515 }
7516
7517 /* The 64-bit version is simpler because it makes more sense to load the
7518 values as "immediate" data out of the trampoline. It's also easier since
7519 we can read the PC without clobbering a register. */
7520
7521 void
7522 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7523 {
7524 /* SPARC 64-bit trampoline:
7525
7526 rd %pc, %g1
7527 ldx [%g1+24], %g5
7528 jmp %g5
7529 ldx [%g1+16], %g5
7530 +16 bytes data
7531 */
7532
7533 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7534 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7535 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7536 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7537 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7538 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7539 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7540 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7541 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7542 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7543 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7544
7545 if (sparc_cpu != PROCESSOR_ULTRASPARC
7546 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7547 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7548
7549 /* Call __enable_execute_stack after writing onto the stack to make sure
7550 the stack address is accessible. */
7551 #ifdef TRANSFER_FROM_TRAMPOLINE
7552 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7553 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7554 #endif
7555 }
7556 \f
7557 /* Adjust the cost of a scheduling dependency. Return the new cost of
7558 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7559
7560 static int
7561 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7562 {
7563 enum attr_type insn_type;
7564
7565 if (! recog_memoized (insn))
7566 return 0;
7567
7568 insn_type = get_attr_type (insn);
7569
7570 if (REG_NOTE_KIND (link) == 0)
7571 {
7572 /* Data dependency; DEP_INSN writes a register that INSN reads some
7573 cycles later. */
7574
7575 /* if a load, then the dependence must be on the memory address;
7576 add an extra "cycle". Note that the cost could be two cycles
7577 if the reg was written late in an instruction group; we ca not tell
7578 here. */
7579 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7580 return cost + 3;
7581
7582 /* Get the delay only if the address of the store is the dependence. */
7583 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7584 {
7585 rtx pat = PATTERN(insn);
7586 rtx dep_pat = PATTERN (dep_insn);
7587
7588 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7589 return cost; /* This should not happen! */
7590
7591 /* The dependency between the two instructions was on the data that
7592 is being stored. Assume that this implies that the address of the
7593 store is not dependent. */
7594 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7595 return cost;
7596
7597 return cost + 3; /* An approximation. */
7598 }
7599
7600 /* A shift instruction cannot receive its data from an instruction
7601 in the same cycle; add a one cycle penalty. */
7602 if (insn_type == TYPE_SHIFT)
7603 return cost + 3; /* Split before cascade into shift. */
7604 }
7605 else
7606 {
7607 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7608 INSN writes some cycles later. */
7609
7610 /* These are only significant for the fpu unit; writing a fp reg before
7611 the fpu has finished with it stalls the processor. */
7612
7613 /* Reusing an integer register causes no problems. */
7614 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7615 return 0;
7616 }
7617
7618 return cost;
7619 }
7620
7621 static int
7622 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7623 {
7624 enum attr_type insn_type, dep_type;
7625 rtx pat = PATTERN(insn);
7626 rtx dep_pat = PATTERN (dep_insn);
7627
7628 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7629 return cost;
7630
7631 insn_type = get_attr_type (insn);
7632 dep_type = get_attr_type (dep_insn);
7633
7634 switch (REG_NOTE_KIND (link))
7635 {
7636 case 0:
7637 /* Data dependency; DEP_INSN writes a register that INSN reads some
7638 cycles later. */
7639
7640 switch (insn_type)
7641 {
7642 case TYPE_STORE:
7643 case TYPE_FPSTORE:
7644 /* Get the delay iff the address of the store is the dependence. */
7645 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7646 return cost;
7647
7648 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7649 return cost;
7650 return cost + 3;
7651
7652 case TYPE_LOAD:
7653 case TYPE_SLOAD:
7654 case TYPE_FPLOAD:
7655 /* If a load, then the dependence must be on the memory address. If
7656 the addresses aren't equal, then it might be a false dependency */
7657 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7658 {
7659 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7660 || GET_CODE (SET_DEST (dep_pat)) != MEM
7661 || GET_CODE (SET_SRC (pat)) != MEM
7662 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7663 XEXP (SET_SRC (pat), 0)))
7664 return cost + 2;
7665
7666 return cost + 8;
7667 }
7668 break;
7669
7670 case TYPE_BRANCH:
7671 /* Compare to branch latency is 0. There is no benefit from
7672 separating compare and branch. */
7673 if (dep_type == TYPE_COMPARE)
7674 return 0;
7675 /* Floating point compare to branch latency is less than
7676 compare to conditional move. */
7677 if (dep_type == TYPE_FPCMP)
7678 return cost - 1;
7679 break;
7680 default:
7681 break;
7682 }
7683 break;
7684
7685 case REG_DEP_ANTI:
7686 /* Anti-dependencies only penalize the fpu unit. */
7687 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7688 return 0;
7689 break;
7690
7691 default:
7692 break;
7693 }
7694
7695 return cost;
7696 }
7697
7698 static int
7699 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7700 {
7701 switch (sparc_cpu)
7702 {
7703 case PROCESSOR_SUPERSPARC:
7704 cost = supersparc_adjust_cost (insn, link, dep, cost);
7705 break;
7706 case PROCESSOR_HYPERSPARC:
7707 case PROCESSOR_SPARCLITE86X:
7708 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7709 break;
7710 default:
7711 break;
7712 }
7713 return cost;
7714 }
7715
7716 static void
7717 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7718 int sched_verbose ATTRIBUTE_UNUSED,
7719 int max_ready ATTRIBUTE_UNUSED)
7720 {
7721 }
7722
7723 static int
7724 sparc_use_sched_lookahead (void)
7725 {
7726 if (sparc_cpu == PROCESSOR_ULTRASPARC
7727 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7728 return 4;
7729 if ((1 << sparc_cpu) &
7730 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7731 (1 << PROCESSOR_SPARCLITE86X)))
7732 return 3;
7733 return 0;
7734 }
7735
7736 static int
7737 sparc_issue_rate (void)
7738 {
7739 switch (sparc_cpu)
7740 {
7741 default:
7742 return 1;
7743 case PROCESSOR_V9:
7744 /* Assume V9 processors are capable of at least dual-issue. */
7745 return 2;
7746 case PROCESSOR_SUPERSPARC:
7747 return 3;
7748 case PROCESSOR_HYPERSPARC:
7749 case PROCESSOR_SPARCLITE86X:
7750 return 2;
7751 case PROCESSOR_ULTRASPARC:
7752 case PROCESSOR_ULTRASPARC3:
7753 return 4;
7754 }
7755 }
7756
7757 static int
7758 set_extends (rtx insn)
7759 {
7760 register rtx pat = PATTERN (insn);
7761
7762 switch (GET_CODE (SET_SRC (pat)))
7763 {
7764 /* Load and some shift instructions zero extend. */
7765 case MEM:
7766 case ZERO_EXTEND:
7767 /* sethi clears the high bits */
7768 case HIGH:
7769 /* LO_SUM is used with sethi. sethi cleared the high
7770 bits and the values used with lo_sum are positive */
7771 case LO_SUM:
7772 /* Store flag stores 0 or 1 */
7773 case LT: case LTU:
7774 case GT: case GTU:
7775 case LE: case LEU:
7776 case GE: case GEU:
7777 case EQ:
7778 case NE:
7779 return 1;
7780 case AND:
7781 {
7782 rtx op0 = XEXP (SET_SRC (pat), 0);
7783 rtx op1 = XEXP (SET_SRC (pat), 1);
7784 if (GET_CODE (op1) == CONST_INT)
7785 return INTVAL (op1) >= 0;
7786 if (GET_CODE (op0) != REG)
7787 return 0;
7788 if (sparc_check_64 (op0, insn) == 1)
7789 return 1;
7790 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7791 }
7792 case IOR:
7793 case XOR:
7794 {
7795 rtx op0 = XEXP (SET_SRC (pat), 0);
7796 rtx op1 = XEXP (SET_SRC (pat), 1);
7797 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7798 return 0;
7799 if (GET_CODE (op1) == CONST_INT)
7800 return INTVAL (op1) >= 0;
7801 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7802 }
7803 case LSHIFTRT:
7804 return GET_MODE (SET_SRC (pat)) == SImode;
7805 /* Positive integers leave the high bits zero. */
7806 case CONST_DOUBLE:
7807 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7808 case CONST_INT:
7809 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7810 case ASHIFTRT:
7811 case SIGN_EXTEND:
7812 return - (GET_MODE (SET_SRC (pat)) == SImode);
7813 case REG:
7814 return sparc_check_64 (SET_SRC (pat), insn);
7815 default:
7816 return 0;
7817 }
7818 }
7819
7820 /* We _ought_ to have only one kind per function, but... */
7821 static GTY(()) rtx sparc_addr_diff_list;
7822 static GTY(()) rtx sparc_addr_list;
7823
7824 void
7825 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7826 {
7827 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7828 if (diff)
7829 sparc_addr_diff_list
7830 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7831 else
7832 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7833 }
7834
7835 static void
7836 sparc_output_addr_vec (rtx vec)
7837 {
7838 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7839 int idx, vlen = XVECLEN (body, 0);
7840
7841 #ifdef ASM_OUTPUT_ADDR_VEC_START
7842 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7843 #endif
7844
7845 #ifdef ASM_OUTPUT_CASE_LABEL
7846 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7847 NEXT_INSN (lab));
7848 #else
7849 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7850 #endif
7851
7852 for (idx = 0; idx < vlen; idx++)
7853 {
7854 ASM_OUTPUT_ADDR_VEC_ELT
7855 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7856 }
7857
7858 #ifdef ASM_OUTPUT_ADDR_VEC_END
7859 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7860 #endif
7861 }
7862
7863 static void
7864 sparc_output_addr_diff_vec (rtx vec)
7865 {
7866 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7867 rtx base = XEXP (XEXP (body, 0), 0);
7868 int idx, vlen = XVECLEN (body, 1);
7869
7870 #ifdef ASM_OUTPUT_ADDR_VEC_START
7871 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7872 #endif
7873
7874 #ifdef ASM_OUTPUT_CASE_LABEL
7875 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7876 NEXT_INSN (lab));
7877 #else
7878 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7879 #endif
7880
7881 for (idx = 0; idx < vlen; idx++)
7882 {
7883 ASM_OUTPUT_ADDR_DIFF_ELT
7884 (asm_out_file,
7885 body,
7886 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7887 CODE_LABEL_NUMBER (base));
7888 }
7889
7890 #ifdef ASM_OUTPUT_ADDR_VEC_END
7891 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7892 #endif
7893 }
7894
7895 static void
7896 sparc_output_deferred_case_vectors (void)
7897 {
7898 rtx t;
7899 int align;
7900
7901 if (sparc_addr_list == NULL_RTX
7902 && sparc_addr_diff_list == NULL_RTX)
7903 return;
7904
7905 /* Align to cache line in the function's code section. */
7906 function_section (current_function_decl);
7907
7908 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7909 if (align > 0)
7910 ASM_OUTPUT_ALIGN (asm_out_file, align);
7911
7912 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7913 sparc_output_addr_vec (XEXP (t, 0));
7914 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7915 sparc_output_addr_diff_vec (XEXP (t, 0));
7916
7917 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7918 }
7919
7920 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7921 unknown. Return 1 if the high bits are zero, -1 if the register is
7922 sign extended. */
7923 int
7924 sparc_check_64 (rtx x, rtx insn)
7925 {
7926 /* If a register is set only once it is safe to ignore insns this
7927 code does not know how to handle. The loop will either recognize
7928 the single set and return the correct value or fail to recognize
7929 it and return 0. */
7930 int set_once = 0;
7931 rtx y = x;
7932
7933 if (GET_CODE (x) != REG)
7934 abort ();
7935
7936 if (GET_MODE (x) == DImode)
7937 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7938
7939 if (flag_expensive_optimizations
7940 && REG_N_SETS (REGNO (y)) == 1)
7941 set_once = 1;
7942
7943 if (insn == 0)
7944 {
7945 if (set_once)
7946 insn = get_last_insn_anywhere ();
7947 else
7948 return 0;
7949 }
7950
7951 while ((insn = PREV_INSN (insn)))
7952 {
7953 switch (GET_CODE (insn))
7954 {
7955 case JUMP_INSN:
7956 case NOTE:
7957 break;
7958 case CODE_LABEL:
7959 case CALL_INSN:
7960 default:
7961 if (! set_once)
7962 return 0;
7963 break;
7964 case INSN:
7965 {
7966 rtx pat = PATTERN (insn);
7967 if (GET_CODE (pat) != SET)
7968 return 0;
7969 if (rtx_equal_p (x, SET_DEST (pat)))
7970 return set_extends (insn);
7971 if (y && rtx_equal_p (y, SET_DEST (pat)))
7972 return set_extends (insn);
7973 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7974 return 0;
7975 }
7976 }
7977 }
7978 return 0;
7979 }
7980
7981 /* Returns assembly code to perform a DImode shift using
7982 a 64-bit global or out register on SPARC-V8+. */
7983 const char *
7984 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
7985 {
7986 static char asm_code[60];
7987
7988 /* The scratch register is only required when the destination
7989 register is not a 64-bit global or out register. */
7990 if (which_alternative != 2)
7991 operands[3] = operands[0];
7992
7993 /* We can only shift by constants <= 63. */
7994 if (GET_CODE (operands[2]) == CONST_INT)
7995 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7996
7997 if (GET_CODE (operands[1]) == CONST_INT)
7998 {
7999 output_asm_insn ("mov\t%1, %3", operands);
8000 }
8001 else
8002 {
8003 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8004 if (sparc_check_64 (operands[1], insn) <= 0)
8005 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8006 output_asm_insn ("or\t%L1, %3, %3", operands);
8007 }
8008
8009 strcpy(asm_code, opcode);
8010
8011 if (which_alternative != 2)
8012 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8013 else
8014 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8015 }
8016 \f
8017 /* Output rtl to increment the profiler label LABELNO
8018 for profiling a function entry. */
8019
8020 void
8021 sparc_profile_hook (int labelno)
8022 {
8023 char buf[32];
8024 rtx lab, fun;
8025
8026 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8027 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8028 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8029
8030 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8031 }
8032 \f
8033 #ifdef OBJECT_FORMAT_ELF
8034 static void
8035 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8036 {
8037 if (flags & SECTION_MERGE)
8038 {
8039 /* entsize cannot be expressed in this section attributes
8040 encoding style. */
8041 default_elf_asm_named_section (name, flags);
8042 return;
8043 }
8044
8045 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8046
8047 if (!(flags & SECTION_DEBUG))
8048 fputs (",#alloc", asm_out_file);
8049 if (flags & SECTION_WRITE)
8050 fputs (",#write", asm_out_file);
8051 if (flags & SECTION_TLS)
8052 fputs (",#tls", asm_out_file);
8053 if (flags & SECTION_CODE)
8054 fputs (",#execinstr", asm_out_file);
8055
8056 /* ??? Handle SECTION_BSS. */
8057
8058 fputc ('\n', asm_out_file);
8059 }
8060 #endif /* OBJECT_FORMAT_ELF */
8061
8062 /* We do not allow indirect calls to be optimized into sibling calls.
8063
8064 We cannot use sibling calls when delayed branches are disabled
8065 because they will likely require the call delay slot to be filled.
8066
8067 Also, on SPARC 32-bit we cannot emit a sibling call when the
8068 current function returns a structure. This is because the "unimp
8069 after call" convention would cause the callee to return to the
8070 wrong place. The generic code already disallows cases where the
8071 function being called returns a structure.
8072
8073 It may seem strange how this last case could occur. Usually there
8074 is code after the call which jumps to epilogue code which dumps the
8075 return value into the struct return area. That ought to invalidate
8076 the sibling call right? Well, in the C++ case we can end up passing
8077 the pointer to the struct return area to a constructor (which returns
8078 void) and then nothing else happens. Such a sibling call would look
8079 valid without the added check here. */
8080 static bool
8081 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8082 {
8083 return (decl
8084 && flag_delayed_branch
8085 && (TARGET_ARCH64 || ! current_function_returns_struct));
8086 }
8087 \f
8088 /* libfunc renaming. */
8089 #include "config/gofast.h"
8090
8091 static void
8092 sparc_init_libfuncs (void)
8093 {
8094 if (TARGET_ARCH32)
8095 {
8096 /* Use the subroutines that Sun's library provides for integer
8097 multiply and divide. The `*' prevents an underscore from
8098 being prepended by the compiler. .umul is a little faster
8099 than .mul. */
8100 set_optab_libfunc (smul_optab, SImode, "*.umul");
8101 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8102 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8103 set_optab_libfunc (smod_optab, SImode, "*.rem");
8104 set_optab_libfunc (umod_optab, SImode, "*.urem");
8105
8106 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8107 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8108 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8109 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8110 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8111 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8112
8113 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8114 is because with soft-float, the SFmode and DFmode sqrt
8115 instructions will be absent, and the compiler will notice and
8116 try to use the TFmode sqrt instruction for calls to the
8117 builtin function sqrt, but this fails. */
8118 if (TARGET_FPU)
8119 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8120
8121 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8122 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8123 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8124 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8125 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8126 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8127
8128 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8129 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8130 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8131 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8132
8133 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8134 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8135 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8136
8137 if (DITF_CONVERSION_LIBFUNCS)
8138 {
8139 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8140 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8141 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8142 }
8143
8144 if (SUN_CONVERSION_LIBFUNCS)
8145 {
8146 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8147 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8148 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8149 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8150 }
8151 }
8152 if (TARGET_ARCH64)
8153 {
8154 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8155 do not exist in the library. Make sure the compiler does not
8156 emit calls to them by accident. (It should always use the
8157 hardware instructions.) */
8158 set_optab_libfunc (smul_optab, SImode, 0);
8159 set_optab_libfunc (sdiv_optab, SImode, 0);
8160 set_optab_libfunc (udiv_optab, SImode, 0);
8161 set_optab_libfunc (smod_optab, SImode, 0);
8162 set_optab_libfunc (umod_optab, SImode, 0);
8163
8164 if (SUN_INTEGER_MULTIPLY_64)
8165 {
8166 set_optab_libfunc (smul_optab, DImode, "__mul64");
8167 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8168 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8169 set_optab_libfunc (smod_optab, DImode, "__rem64");
8170 set_optab_libfunc (umod_optab, DImode, "__urem64");
8171 }
8172
8173 if (SUN_CONVERSION_LIBFUNCS)
8174 {
8175 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8176 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8177 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8178 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8179 }
8180 }
8181
8182 gofast_maybe_init_libfuncs ();
8183 }
8184 \f
8185 int
8186 sparc_extra_constraint_check (rtx op, int c, int strict)
8187 {
8188 int reload_ok_mem;
8189
8190 if (TARGET_ARCH64
8191 && (c == 'T' || c == 'U'))
8192 return 0;
8193
8194 switch (c)
8195 {
8196 case 'Q':
8197 return fp_sethi_p (op);
8198
8199 case 'R':
8200 return fp_mov_p (op);
8201
8202 case 'S':
8203 return fp_high_losum_p (op);
8204
8205 case 'U':
8206 if (! strict
8207 || (GET_CODE (op) == REG
8208 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8209 || reg_renumber[REGNO (op)] >= 0)))
8210 return register_ok_for_ldd (op);
8211
8212 return 0;
8213
8214 case 'W':
8215 case 'T':
8216 break;
8217
8218 default:
8219 return 0;
8220 }
8221
8222 /* Our memory extra constraints have to emulate the
8223 behavior of 'm' and 'o' in order for reload to work
8224 correctly. */
8225 if (GET_CODE (op) == MEM)
8226 {
8227 reload_ok_mem = 0;
8228 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8229 && (! strict
8230 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8231 reload_ok_mem = 1;
8232 }
8233 else
8234 {
8235 reload_ok_mem = (reload_in_progress
8236 && GET_CODE (op) == REG
8237 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8238 && reg_renumber [REGNO (op)] < 0);
8239 }
8240
8241 return reload_ok_mem;
8242 }
8243
8244 /* ??? This duplicates information provided to the compiler by the
8245 ??? scheduler description. Some day, teach genautomata to output
8246 ??? the latencies and then CSE will just use that. */
8247
8248 static bool
8249 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8250 {
8251 enum machine_mode mode = GET_MODE (x);
8252 bool float_mode_p = FLOAT_MODE_P (mode);
8253
8254 switch (code)
8255 {
8256 case CONST_INT:
8257 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8258 {
8259 *total = 0;
8260 return true;
8261 }
8262 /* FALLTHRU */
8263
8264 case HIGH:
8265 *total = 2;
8266 return true;
8267
8268 case CONST:
8269 case LABEL_REF:
8270 case SYMBOL_REF:
8271 *total = 4;
8272 return true;
8273
8274 case CONST_DOUBLE:
8275 if (GET_MODE (x) == DImode
8276 && ((XINT (x, 3) == 0
8277 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8278 || (XINT (x, 3) == -1
8279 && XINT (x, 2) < 0
8280 && XINT (x, 2) >= -0x1000)))
8281 *total = 0;
8282 else
8283 *total = 8;
8284 return true;
8285
8286 case MEM:
8287 /* If outer-code was a sign or zero extension, a cost
8288 of COSTS_N_INSNS (1) was already added in. This is
8289 why we are subtracting it back out. */
8290 if (outer_code == ZERO_EXTEND)
8291 {
8292 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8293 }
8294 else if (outer_code == SIGN_EXTEND)
8295 {
8296 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8297 }
8298 else if (float_mode_p)
8299 {
8300 *total = sparc_costs->float_load;
8301 }
8302 else
8303 {
8304 *total = sparc_costs->int_load;
8305 }
8306
8307 return true;
8308
8309 case PLUS:
8310 case MINUS:
8311 if (float_mode_p)
8312 *total = sparc_costs->float_plusminus;
8313 else
8314 *total = COSTS_N_INSNS (1);
8315 return false;
8316
8317 case MULT:
8318 if (float_mode_p)
8319 *total = sparc_costs->float_mul;
8320 else
8321 {
8322 int bit_cost;
8323
8324 bit_cost = 0;
8325 if (sparc_costs->int_mul_bit_factor)
8326 {
8327 int nbits;
8328
8329 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8330 {
8331 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8332 for (nbits = 0; value != 0; value &= value - 1)
8333 nbits++;
8334 }
8335 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8336 && GET_MODE (XEXP (x, 1)) == DImode)
8337 {
8338 rtx x1 = XEXP (x, 1);
8339 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8340 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8341
8342 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8343 nbits++;
8344 for (; value2 != 0; value2 &= value2 - 1)
8345 nbits++;
8346 }
8347 else
8348 nbits = 7;
8349
8350 if (nbits < 3)
8351 nbits = 3;
8352 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8353 bit_cost = COSTS_N_INSNS (bit_cost);
8354 }
8355
8356 if (mode == DImode)
8357 *total = sparc_costs->int_mulX + bit_cost;
8358 else
8359 *total = sparc_costs->int_mul + bit_cost;
8360 }
8361 return false;
8362
8363 case ASHIFT:
8364 case ASHIFTRT:
8365 case LSHIFTRT:
8366 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8367 return false;
8368
8369 case DIV:
8370 case UDIV:
8371 case MOD:
8372 case UMOD:
8373 if (float_mode_p)
8374 {
8375 if (mode == DFmode)
8376 *total = sparc_costs->float_div_df;
8377 else
8378 *total = sparc_costs->float_div_sf;
8379 }
8380 else
8381 {
8382 if (mode == DImode)
8383 *total = sparc_costs->int_divX;
8384 else
8385 *total = sparc_costs->int_div;
8386 }
8387 return false;
8388
8389 case NEG:
8390 if (! float_mode_p)
8391 {
8392 *total = COSTS_N_INSNS (1);
8393 return false;
8394 }
8395 /* FALLTHRU */
8396
8397 case ABS:
8398 case FLOAT:
8399 case UNSIGNED_FLOAT:
8400 case FIX:
8401 case UNSIGNED_FIX:
8402 case FLOAT_EXTEND:
8403 case FLOAT_TRUNCATE:
8404 *total = sparc_costs->float_move;
8405 return false;
8406
8407 case SQRT:
8408 if (mode == DFmode)
8409 *total = sparc_costs->float_sqrt_df;
8410 else
8411 *total = sparc_costs->float_sqrt_sf;
8412 return false;
8413
8414 case COMPARE:
8415 if (float_mode_p)
8416 *total = sparc_costs->float_cmp;
8417 else
8418 *total = COSTS_N_INSNS (1);
8419 return false;
8420
8421 case IF_THEN_ELSE:
8422 if (float_mode_p)
8423 *total = sparc_costs->float_cmove;
8424 else
8425 *total = sparc_costs->int_cmove;
8426 return false;
8427
8428 default:
8429 return false;
8430 }
8431 }
8432
8433 /* Emit the sequence of insns SEQ while preserving the register REG. */
8434
8435 static void
8436 emit_and_preserve (rtx seq, rtx reg)
8437 {
8438 rtx slot = gen_rtx_MEM (word_mode,
8439 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8440
8441 emit_stack_pointer_decrement (GEN_INT (UNITS_PER_WORD));
8442 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8443 emit_insn (seq);
8444 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8445 emit_stack_pointer_increment (GEN_INT (UNITS_PER_WORD));
8446 }
8447
8448 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8449 Used for C++ multiple inheritance. */
8450
8451 static void
8452 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8453 HOST_WIDE_INT delta,
8454 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8455 tree function)
8456 {
8457 rtx this, insn, funexp, delta_rtx;
8458 unsigned int int_arg_first;
8459
8460 reload_completed = 1;
8461 epilogue_completed = 1;
8462 no_new_pseudos = 1;
8463 reset_block_changes ();
8464
8465 emit_note (NOTE_INSN_PROLOGUE_END);
8466
8467 if (flag_delayed_branch)
8468 {
8469 /* We will emit a regular sibcall below, so we need to instruct
8470 output_sibcall that we are in a leaf function. */
8471 current_function_uses_only_leaf_regs = 1;
8472
8473 /* This will cause final.c to invoke leaf_renumber_regs so we
8474 must behave as if we were in a not-yet-leafified function. */
8475 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8476 }
8477 else
8478 {
8479 /* We will emit the sibcall manually below, so we will need to
8480 manually spill non-leaf registers. */
8481 current_function_uses_only_leaf_regs = 0;
8482
8483 /* We really are in a leaf function. */
8484 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8485 }
8486
8487 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8488 returns a structure, the structure return pointer is there instead. */
8489 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8490 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8491 else
8492 this = gen_rtx_REG (Pmode, int_arg_first);
8493
8494 /* Add DELTA. When possible use a plain add, otherwise load it into
8495 a register first. */
8496 delta_rtx = GEN_INT (delta);
8497 if (!SPARC_SIMM13_P (delta))
8498 {
8499 rtx scratch = gen_rtx_REG (Pmode, 1);
8500
8501 if (input_operand (delta_rtx, GET_MODE (scratch)))
8502 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8503 else
8504 {
8505 if (TARGET_ARCH64)
8506 sparc_emit_set_const64 (scratch, delta_rtx);
8507 else
8508 sparc_emit_set_const32 (scratch, delta_rtx);
8509 }
8510
8511 delta_rtx = scratch;
8512 }
8513
8514 emit_insn (gen_rtx_SET (VOIDmode,
8515 this,
8516 gen_rtx_PLUS (Pmode, this, delta_rtx)));
8517
8518 /* Generate a tail call to the target function. */
8519 if (! TREE_USED (function))
8520 {
8521 assemble_external (function);
8522 TREE_USED (function) = 1;
8523 }
8524 funexp = XEXP (DECL_RTL (function), 0);
8525
8526 if (flag_delayed_branch)
8527 {
8528 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8529 insn = emit_call_insn (gen_sibcall (funexp));
8530 SIBLING_CALL_P (insn) = 1;
8531 }
8532 else
8533 {
8534 /* The hoops we have to jump through in order to generate a sibcall
8535 without using delay slots... */
8536 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8537
8538 if (flag_pic)
8539 {
8540 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8541 start_sequence ();
8542 load_pic_register (); /* clobbers %o7 */
8543 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8544 seq = get_insns ();
8545 end_sequence ();
8546 emit_and_preserve (seq, spill_reg);
8547 }
8548 else if (TARGET_ARCH32)
8549 {
8550 emit_insn (gen_rtx_SET (VOIDmode,
8551 scratch,
8552 gen_rtx_HIGH (SImode, funexp)));
8553 emit_insn (gen_rtx_SET (VOIDmode,
8554 scratch,
8555 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8556 }
8557 else /* TARGET_ARCH64 */
8558 {
8559 switch (sparc_cmodel)
8560 {
8561 case CM_MEDLOW:
8562 case CM_MEDMID:
8563 /* The destination can serve as a temporary. */
8564 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8565 break;
8566
8567 case CM_MEDANY:
8568 case CM_EMBMEDANY:
8569 /* The destination cannot serve as a temporary. */
8570 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8571 start_sequence ();
8572 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8573 seq = get_insns ();
8574 end_sequence ();
8575 emit_and_preserve (seq, spill_reg);
8576 break;
8577
8578 default:
8579 abort();
8580 }
8581 }
8582
8583 emit_jump_insn (gen_indirect_jump (scratch));
8584 }
8585
8586 emit_barrier ();
8587
8588 /* Run just enough of rest_of_compilation to get the insns emitted.
8589 There's not really enough bulk here to make other passes such as
8590 instruction scheduling worth while. Note that use_thunk calls
8591 assemble_start_function and assemble_end_function. */
8592 insn = get_insns ();
8593 insn_locators_initialize ();
8594 shorten_branches (insn);
8595 final_start_function (insn, file, 1);
8596 final (insn, file, 1, 0);
8597 final_end_function ();
8598
8599 reload_completed = 0;
8600 epilogue_completed = 0;
8601 no_new_pseudos = 0;
8602 }
8603
8604 /* How to allocate a 'struct machine_function'. */
8605
8606 static struct machine_function *
8607 sparc_init_machine_status (void)
8608 {
8609 return ggc_alloc_cleared (sizeof (struct machine_function));
8610 }
8611
8612 /* Locate some local-dynamic symbol still in use by this function
8613 so that we can print its name in local-dynamic base patterns. */
8614
8615 static const char *
8616 get_some_local_dynamic_name (void)
8617 {
8618 rtx insn;
8619
8620 if (cfun->machine->some_ld_name)
8621 return cfun->machine->some_ld_name;
8622
8623 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8624 if (INSN_P (insn)
8625 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8626 return cfun->machine->some_ld_name;
8627
8628 abort ();
8629 }
8630
8631 static int
8632 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8633 {
8634 rtx x = *px;
8635
8636 if (x
8637 && GET_CODE (x) == SYMBOL_REF
8638 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8639 {
8640 cfun->machine->some_ld_name = XSTR (x, 0);
8641 return 1;
8642 }
8643
8644 return 0;
8645 }
8646
8647 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8648 We need to emit DTP-relative relocations. */
8649
8650 void
8651 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8652 {
8653 switch (size)
8654 {
8655 case 4:
8656 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8657 break;
8658 case 8:
8659 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8660 break;
8661 default:
8662 abort ();
8663 }
8664 output_addr_const (file, x);
8665 fputs (")", file);
8666 }
8667
8668 #include "gt-sparc.h"