1 ;;- Machine description for Blackfin for GNU compiler
2 ;; Copyright 2005, 2006 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ; operand punctuation marks:
24 ; X -- integer value printed as log2
25 ; Y -- integer value printed as log2(~value) - for bitclear
26 ; h -- print half word register, low part
27 ; d -- print half word register, high part
28 ; D -- print operand as dregs pairs
29 ; w -- print operand as accumulator register word (a0w, a1w)
30 ; H -- high part of double mode operand
31 ; T -- byte register representation Oct. 02 2001
33 ; constant operand classes
35 ; J 2**N 5bit imm scaled
36 ; Ks7 -64 .. 63 signed 7bit imm
37 ; Ku5 0..31 unsigned 5bit imm
38 ; Ks4 -8 .. 7 signed 4bit imm
39 ; Ks3 -4 .. 3 signed 3bit imm
40 ; Ku3 0 .. 7 unsigned 3bit imm
41 ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
50 ; c (i0..i3,m0..m3) CIRCREGS
57 ;; Define constants for hard registers.
124 ;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
127 [(UNSPEC_CBRANCH_TAKEN 0)
128 (UNSPEC_CBRANCH_NOPS 1)
131 (UNSPEC_LIBRARY_OFFSET 4)
132 (UNSPEC_PUSH_MULTIPLE 5)
133 ;; Multiply or MAC with extra CONST_INT operand specifying the macflag
134 (UNSPEC_MUL_WITH_FLAG 6)
135 (UNSPEC_MAC_WITH_FLAG 7)
136 (UNSPEC_MOVE_FDPIC 8)
137 (UNSPEC_FUNCDESC_GOT17M4 9)
138 (UNSPEC_LSETUP_END 10)])
141 [(UNSPEC_VOLATILE_EH_RETURN 0)
142 (UNSPEC_VOLATILE_CSYNC 1)
143 (UNSPEC_VOLATILE_SSYNC 2)
144 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)])
160 "move,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
161 (const_string "misc"))
163 ;; Scheduling definitions
165 (define_automaton "bfin")
167 (define_cpu_unit "core" "bfin")
169 (define_insn_reservation "alu" 1
170 (eq_attr "type" "move,mvi,mcst,dsp32,alu0,shft,brcc,br,call,misc,sync,compare")
173 (define_insn_reservation "imul" 3
174 (eq_attr "type" "mult")
177 (define_insn_reservation "load" 1
178 (eq_attr "type" "mcld")
181 ;; Make sure genautomata knows about the maximum latency that can be produced
182 ;; by the adjust_cost function.
183 (define_insn_reservation "dummy" 5
184 (eq_attr "type" "mcld")
187 ;; Operand and operator predicates
189 (include "predicates.md")
192 ;;; FRIO branches have been optimized for code density
193 ;;; this comes at a slight cost of complexity when
194 ;;; a compiler needs to generate branches in the general
195 ;;; case. In order to generate the correct branching
196 ;;; mechanisms the compiler needs keep track of instruction
197 ;;; lengths. The follow table describes how to count instructions
198 ;;; for the FRIO architecture.
200 ;;; unconditional br are 12-bit imm pcrelative branches *2
201 ;;; conditional br are 10-bit imm pcrelative branches *2
203 ;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
205 ;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
206 ;;; NOTE : For brcc we generate instructions such as
207 ;;; if cc jmp; jump.[sl] offset
208 ;;; offset of jump.[sl] is from the jump instruction but
209 ;;; gcc calculates length from the if cc jmp instruction
210 ;;; furthermore gcc takes the end address of the branch instruction
211 ;;; as (pc) for a forward branch
212 ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
214 ;;; The way the (pc) rtx works in these calculations is somewhat odd;
215 ;;; for backward branches it's the address of the current instruction,
216 ;;; for forward branches it's the previously known address of the following
217 ;;; instruction - we have to take this into account by reducing the range
218 ;;; for a forward branch.
220 ;; Lengths for type "mvi" insns are always defined by the instructions
222 (define_attr "length" ""
223 (cond [(eq_attr "type" "mcld")
224 (if_then_else (match_operand 1 "effective_address_32bit_p" "")
225 (const_int 4) (const_int 2))
227 (eq_attr "type" "mcst")
228 (if_then_else (match_operand 0 "effective_address_32bit_p" "")
229 (const_int 4) (const_int 2))
231 (eq_attr "type" "move") (const_int 2)
233 (eq_attr "type" "dsp32") (const_int 4)
234 (eq_attr "type" "call") (const_int 4)
236 (eq_attr "type" "br")
238 (le (minus (match_dup 0) (pc)) (const_int 4092))
239 (ge (minus (match_dup 0) (pc)) (const_int -4096)))
243 (eq_attr "type" "brcc")
245 (le (minus (match_dup 3) (pc)) (const_int 1020))
246 (ge (minus (match_dup 3) (pc)) (const_int -1024)))
249 (le (minus (match_dup 3) (pc)) (const_int 4092))
250 (ge (minus (match_dup 3) (pc)) (const_int -4094)))
258 ;; Classify the insns into those that are one instruction and those that
259 ;; are more than one in sequence.
260 (define_attr "seq_insns" "single,multi"
261 (const_string "single"))
265 (define_expand "movsicc"
266 [(set (match_operand:SI 0 "register_operand" "")
267 (if_then_else:SI (match_operand 1 "comparison_operator" "")
268 (match_operand:SI 2 "register_operand" "")
269 (match_operand:SI 3 "register_operand" "")))]
272 operands[1] = bfin_gen_compare (operands[1], SImode);
275 (define_insn "*movsicc_insn1"
276 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
278 (eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
280 (match_operand:SI 1 "register_operand" "da,0,da")
281 (match_operand:SI 2 "register_operand" "0,da,da")))]
284 if !cc %0 =%1; /* movsicc-1a */
285 if cc %0 =%2; /* movsicc-1b */
286 if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */"
287 [(set_attr "length" "2,2,4")
288 (set_attr "type" "move")
289 (set_attr "seq_insns" "*,*,multi")])
291 (define_insn "*movsicc_insn2"
292 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
294 (ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
296 (match_operand:SI 1 "register_operand" "0,da,da")
297 (match_operand:SI 2 "register_operand" "da,0,da")))]
300 if !cc %0 =%2; /* movsicc-2b */
301 if cc %0 =%1; /* movsicc-2a */
302 if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */"
303 [(set_attr "length" "2,2,4")
304 (set_attr "type" "move")
305 (set_attr "seq_insns" "*,*,multi")])
307 ;; Insns to load HIGH and LO_SUM
309 (define_insn "movsi_high"
310 [(set (match_operand:SI 0 "register_operand" "=x")
311 (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
314 [(set_attr "type" "mvi")
315 (set_attr "length" "4")])
317 (define_insn "movstricthi_high"
318 [(set (match_operand:SI 0 "register_operand" "+x")
319 (ior:SI (and:SI (match_dup 0) (const_int 65535))
320 (match_operand:SI 1 "immediate_operand" "i")))]
323 [(set_attr "type" "mvi")
324 (set_attr "length" "4")])
326 (define_insn "movsi_low"
327 [(set (match_operand:SI 0 "register_operand" "=x")
328 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
329 (match_operand:SI 2 "immediate_operand" "i")))]
332 [(set_attr "type" "mvi")
333 (set_attr "length" "4")])
335 (define_insn "movsi_high_pic"
336 [(set (match_operand:SI 0 "register_operand" "=x")
337 (high:SI (unspec:SI [(match_operand:SI 1 "" "")]
341 [(set_attr "type" "mvi")
342 (set_attr "length" "4")])
344 (define_insn "movsi_low_pic"
345 [(set (match_operand:SI 0 "register_operand" "=x")
346 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
347 (unspec:SI [(match_operand:SI 2 "" "")]
350 "%h0 = %h2@GOT_HIGH;"
351 [(set_attr "type" "mvi")
352 (set_attr "length" "4")])
354 ;;; Move instructions
356 (define_insn_and_split "movdi_insn"
357 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
358 (match_operand:DI 1 "general_operand" "iFx,r,mx"))]
359 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
362 [(set (match_dup 2) (match_dup 3))
363 (set (match_dup 4) (match_dup 5))]
365 rtx lo_half[2], hi_half[2];
366 split_di (operands, 2, lo_half, hi_half);
368 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
370 operands[2] = hi_half[0];
371 operands[3] = hi_half[1];
372 operands[4] = lo_half[0];
373 operands[5] = lo_half[1];
377 operands[2] = lo_half[0];
378 operands[3] = lo_half[1];
379 operands[4] = hi_half[0];
380 operands[5] = hi_half[1];
385 [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
386 (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
396 R0 = R0 | R0; CC = AC0;"
397 [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
398 (set_attr "length" "2,2,*,*,2,2,4")
399 (set_attr "seq_insns" "*,*,*,*,*,*,multi")])
401 (define_insn "movpdi"
402 [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
403 (match_operand:PDI 1 "general_operand" " e,e,>"))]
409 [(set_attr "type" "move,mcst,mcld")
410 (set_attr "seq_insns" "*,multi,multi")])
412 (define_insn "load_accumulator"
413 [(set (match_operand:PDI 0 "register_operand" "=e")
414 (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
417 [(set_attr "type" "move")])
419 (define_insn_and_split "load_accumulator_pair"
420 [(set (match_operand:V2PDI 0 "register_operand" "=e")
421 (sign_extend:V2PDI (vec_concat:V2SI
422 (match_operand:SI 1 "register_operand" "d")
423 (match_operand:SI 2 "register_operand" "d"))))]
427 [(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
428 (set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
430 operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
431 operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
434 (define_insn "*pushsi_insn"
435 [(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
436 (match_operand:SI 0 "register_operand" "xy"))]
439 [(set_attr "type" "mcst")
440 (set_attr "length" "2")])
442 (define_insn "*popsi_insn"
443 [(set (match_operand:SI 0 "register_operand" "=xy")
444 (mem:SI (post_inc:SI (reg:SI REG_SP))))]
447 [(set_attr "type" "mcld")
448 (set_attr "length" "2")])
450 ;; The first alternative is used to make reload choose a limited register
451 ;; class when faced with a movsi_insn that had its input operand replaced
452 ;; with a PLUS. We generally require fewer secondary reloads this way.
454 (define_insn "*movsi_insn"
455 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr")
456 (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))]
457 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
469 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
470 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
472 (define_insn_and_split "*movv2hi_insn"
473 [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
474 (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
476 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
482 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
483 [(set (match_dup 0) (high:SI (match_dup 2)))
484 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
486 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
487 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
489 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
490 operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
492 [(set_attr "type" "move,move,mcld,mcst")
493 (set_attr "length" "2,2,*,*")])
495 (define_insn "*movhi_insn"
496 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
497 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
498 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
500 static const char *templates[] = {
509 int alt = which_alternative;
510 rtx mem = (MEM_P (operands[0]) ? operands[0]
511 : MEM_P (operands[1]) ? operands[1] : NULL_RTX);
512 if (mem && bfin_dsp_memref_p (mem))
514 return templates[alt];
516 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
517 (set_attr "length" "2,2,4,*,*")])
519 (define_insn "*movqi_insn"
520 [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
521 (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
522 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
529 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
530 (set_attr "length" "2,2,4,*,*")])
532 (define_insn "*movsf_insn"
533 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
534 (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
535 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
541 [(set_attr "type" "move,*,mcld,mcst")])
543 (define_insn_and_split "movdf_insn"
544 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
545 (match_operand:DF 1 "general_operand" "iFx,r,mx"))]
546 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
549 [(set (match_dup 2) (match_dup 3))
550 (set (match_dup 4) (match_dup 5))]
552 rtx lo_half[2], hi_half[2];
553 split_di (operands, 2, lo_half, hi_half);
555 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
557 operands[2] = hi_half[0];
558 operands[3] = hi_half[1];
559 operands[4] = lo_half[0];
560 operands[5] = lo_half[1];
564 operands[2] = lo_half[0];
565 operands[3] = lo_half[1];
566 operands[4] = hi_half[0];
567 operands[5] = hi_half[1];
571 ;; Storing halfwords.
572 (define_insn "*movsi_insv"
573 [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
576 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
581 [(set_attr "type" "dsp32,mvi")])
583 (define_expand "insv"
584 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
585 (match_operand:SI 1 "immediate_operand" "")
586 (match_operand:SI 2 "immediate_operand" ""))
587 (match_operand:SI 3 "nonmemory_operand" ""))]
590 if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
593 /* From mips.md: insert_bit_field doesn't verify that our source
594 matches the predicate, so check it again here. */
595 if (! register_operand (operands[0], VOIDmode))
599 ;; This is the main "hook" for PIC code. When generating
600 ;; PIC, movsi is responsible for determining when the source address
601 ;; needs PIC relocation and appropriately calling legitimize_pic_address
602 ;; to perform the actual relocation.
604 (define_expand "movsi"
605 [(set (match_operand:SI 0 "nonimmediate_operand" "")
606 (match_operand:SI 1 "general_operand" ""))]
608 "expand_move (operands, SImode);")
610 (define_expand "movv2hi"
611 [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
612 (match_operand:V2HI 1 "general_operand" ""))]
614 "expand_move (operands, V2HImode);")
616 (define_expand "movdi"
617 [(set (match_operand:DI 0 "nonimmediate_operand" "")
618 (match_operand:DI 1 "general_operand" ""))]
620 "expand_move (operands, DImode);")
622 (define_expand "movsf"
623 [(set (match_operand:SF 0 "nonimmediate_operand" "")
624 (match_operand:SF 1 "general_operand" ""))]
626 "expand_move (operands, SFmode);")
628 (define_expand "movdf"
629 [(set (match_operand:DF 0 "nonimmediate_operand" "")
630 (match_operand:DF 1 "general_operand" ""))]
632 "expand_move (operands, DFmode);")
634 (define_expand "movhi"
635 [(set (match_operand:HI 0 "nonimmediate_operand" "")
636 (match_operand:HI 1 "general_operand" ""))]
638 "expand_move (operands, HImode);")
640 (define_expand "movqi"
641 [(set (match_operand:QI 0 "nonimmediate_operand" "")
642 (match_operand:QI 1 "general_operand" ""))]
644 " expand_move (operands, QImode); ")
646 ;; Some define_splits to break up SI/SFmode loads of immediate constants.
649 [(set (match_operand:SI 0 "register_operand" "")
650 (match_operand:SI 1 "symbolic_or_const_operand" ""))]
652 /* Always split symbolic operands; split integer constants that are
653 too large for a single instruction. */
654 && (GET_CODE (operands[1]) != CONST_INT
655 || (INTVAL (operands[1]) < -32768
656 || INTVAL (operands[1]) >= 65536
657 || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
658 [(set (match_dup 0) (high:SI (match_dup 1)))
659 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
661 if (GET_CODE (operands[1]) == CONST_INT
662 && split_load_immediate (operands))
664 /* ??? Do something about TARGET_LOW_64K. */
668 [(set (match_operand:SF 0 "register_operand" "")
669 (match_operand:SF 1 "immediate_operand" ""))]
671 [(set (match_dup 2) (high:SI (match_dup 3)))
672 (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
675 REAL_VALUE_TYPE value;
677 gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
679 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
680 REAL_VALUE_TO_TARGET_SINGLE (value, values);
682 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
683 operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
684 if (values >= -32768 && values < 65536)
686 emit_move_insn (operands[2], operands[3]);
689 if (split_load_immediate (operands + 2))
693 ;; Sadly, this can't be a proper named movstrict pattern, since the compiler
694 ;; expects to be able to use registers for operand 1.
695 ;; Note that the asm instruction is defined by the manual to take an unsigned
696 ;; constant, but it doesn't matter to the assembler, and the compiler only
697 ;; deals with sign-extended constants. Hence "Ksh".
698 (define_insn "movstricthi_1"
699 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
700 (match_operand:HI 1 "immediate_operand" "Ksh"))]
703 [(set_attr "type" "mvi")
704 (set_attr "length" "4")])
706 ;; Sign and zero extensions
708 (define_insn_and_split "extendhisi2"
709 [(set (match_operand:SI 0 "register_operand" "=d, d")
710 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
715 "reload_completed && bfin_dsp_memref_p (operands[1])"
716 [(set (match_dup 2) (match_dup 1))
717 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
719 operands[2] = gen_lowpart (HImode, operands[0]);
721 [(set_attr "type" "alu0,mcld")])
723 (define_insn_and_split "zero_extendhisi2"
724 [(set (match_operand:SI 0 "register_operand" "=d, d")
725 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
730 "reload_completed && bfin_dsp_memref_p (operands[1])"
731 [(set (match_dup 2) (match_dup 1))
732 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
734 operands[2] = gen_lowpart (HImode, operands[0]);
736 [(set_attr "type" "alu0,mcld")])
738 (define_insn "zero_extendbisi2"
739 [(set (match_operand:SI 0 "register_operand" "=d")
740 (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
743 [(set_attr "type" "compare")])
745 (define_insn "extendqihi2"
746 [(set (match_operand:HI 0 "register_operand" "=d, d")
747 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
752 [(set_attr "type" "mcld,alu0")])
754 (define_insn "extendqisi2"
755 [(set (match_operand:SI 0 "register_operand" "=d, d")
756 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
761 [(set_attr "type" "mcld,alu0")])
764 (define_insn "zero_extendqihi2"
765 [(set (match_operand:HI 0 "register_operand" "=d, d")
766 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
771 [(set_attr "type" "mcld,alu0")])
774 (define_insn "zero_extendqisi2"
775 [(set (match_operand:SI 0 "register_operand" "=d, d")
776 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
781 [(set_attr "type" "mcld,alu0")])
783 ;; DImode logical operations
785 (define_code_macro any_logical [and ior xor])
786 (define_code_attr optab [(and "and")
789 (define_code_attr op [(and "&")
792 (define_code_attr high_result [(and "0")
796 (define_insn "<optab>di3"
797 [(set (match_operand:DI 0 "register_operand" "=d")
798 (any_logical:DI (match_operand:DI 1 "register_operand" "0")
799 (match_operand:DI 2 "register_operand" "d")))]
801 "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;"
802 [(set_attr "length" "4")
803 (set_attr "seq_insns" "multi")])
805 (define_insn "*<optab>di_zesidi_di"
806 [(set (match_operand:DI 0 "register_operand" "=d")
807 (any_logical:DI (zero_extend:DI
808 (match_operand:SI 2 "register_operand" "d"))
809 (match_operand:DI 1 "register_operand" "d")))]
811 "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;"
812 [(set_attr "length" "4")
813 (set_attr "seq_insns" "multi")])
815 (define_insn "*<optab>di_sesdi_di"
816 [(set (match_operand:DI 0 "register_operand" "=d")
817 (any_logical:DI (sign_extend:DI
818 (match_operand:SI 2 "register_operand" "d"))
819 (match_operand:DI 1 "register_operand" "0")))
820 (clobber (match_scratch:SI 3 "=&d"))]
822 "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;"
823 [(set_attr "length" "8")
824 (set_attr "seq_insns" "multi")])
826 (define_insn "negdi2"
827 [(set (match_operand:DI 0 "register_operand" "=d")
828 (neg:DI (match_operand:DI 1 "register_operand" "d")))
829 (clobber (match_scratch:SI 2 "=&d"))
830 (clobber (reg:CC REG_CC))]
832 "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;"
833 [(set_attr "length" "16")
834 (set_attr "seq_insns" "multi")])
836 (define_insn "one_cmpldi2"
837 [(set (match_operand:DI 0 "register_operand" "=d")
838 (not:DI (match_operand:DI 1 "register_operand" "d")))]
840 "%0 = ~%1;\\n\\t%H0 = ~%H1;"
841 [(set_attr "length" "4")
842 (set_attr "seq_insns" "multi")])
844 ;; DImode zero and sign extend patterns
846 (define_insn_and_split "zero_extendsidi2"
847 [(set (match_operand:DI 0 "register_operand" "=d")
848 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
852 [(set (match_dup 3) (const_int 0))]
854 split_di (operands, 1, operands + 2, operands + 3);
855 if (REGNO (operands[0]) != REGNO (operands[1]))
856 emit_move_insn (operands[2], operands[1]);
859 (define_insn "zero_extendqidi2"
860 [(set (match_operand:DI 0 "register_operand" "=d")
861 (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
863 "%0 = %T1 (Z);\\n\\t%H0 = 0;"
864 [(set_attr "length" "4")
865 (set_attr "seq_insns" "multi")])
867 (define_insn "zero_extendhidi2"
868 [(set (match_operand:DI 0 "register_operand" "=d")
869 (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
871 "%0 = %h1 (Z);\\n\\t%H0 = 0;"
872 [(set_attr "length" "4")
873 (set_attr "seq_insns" "multi")])
875 (define_insn_and_split "extendsidi2"
876 [(set (match_operand:DI 0 "register_operand" "=d")
877 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
881 [(set (match_dup 3) (match_dup 1))
882 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
884 split_di (operands, 1, operands + 2, operands + 3);
885 if (REGNO (operands[0]) != REGNO (operands[1]))
886 emit_move_insn (operands[2], operands[1]);
889 (define_insn_and_split "extendqidi2"
890 [(set (match_operand:DI 0 "register_operand" "=d")
891 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
895 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
896 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
897 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
899 split_di (operands, 1, operands + 2, operands + 3);
902 (define_insn_and_split "extendhidi2"
903 [(set (match_operand:DI 0 "register_operand" "=d")
904 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
908 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
909 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
910 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
912 split_di (operands, 1, operands + 2, operands + 3);
915 ;; DImode arithmetic operations
917 (define_insn "adddi3"
918 [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
919 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
920 (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d")))
921 (clobber (match_scratch:SI 3 "=&d,&d,&d"))
922 (clobber (reg:CC 34))]
925 %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3;
926 %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3;
927 %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;"
928 [(set_attr "type" "alu0")
929 (set_attr "length" "10,8,10")
930 (set_attr "seq_insns" "multi,multi,multi")])
932 (define_insn "subdi3"
933 [(set (match_operand:DI 0 "register_operand" "=&d")
934 (minus:DI (match_operand:DI 1 "register_operand" "0")
935 (match_operand:DI 2 "register_operand" "d")))
936 (clobber (reg:CC 34))]
938 "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
939 [(set_attr "length" "10")
940 (set_attr "seq_insns" "multi")])
942 (define_insn "*subdi_di_zesidi"
943 [(set (match_operand:DI 0 "register_operand" "=d")
944 (minus:DI (match_operand:DI 1 "register_operand" "0")
946 (match_operand:SI 2 "register_operand" "d"))))
947 (clobber (match_scratch:SI 3 "=&d"))
948 (clobber (reg:CC 34))]
950 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;"
951 [(set_attr "length" "10")
952 (set_attr "seq_insns" "multi")])
954 (define_insn "*subdi_zesidi_di"
955 [(set (match_operand:DI 0 "register_operand" "=d")
956 (minus:DI (zero_extend:DI
957 (match_operand:SI 2 "register_operand" "d"))
958 (match_operand:DI 1 "register_operand" "0")))
959 (clobber (match_scratch:SI 3 "=&d"))
960 (clobber (reg:CC 34))]
962 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1"
963 [(set_attr "length" "12")
964 (set_attr "seq_insns" "multi")])
966 (define_insn "*subdi_di_sesidi"
967 [(set (match_operand:DI 0 "register_operand" "=d")
968 (minus:DI (match_operand:DI 1 "register_operand" "0")
970 (match_operand:SI 2 "register_operand" "d"))))
971 (clobber (match_scratch:SI 3 "=&d"))
972 (clobber (reg:CC 34))]
974 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
975 [(set_attr "length" "14")
976 (set_attr "seq_insns" "multi")])
978 (define_insn "*subdi_sesidi_di"
979 [(set (match_operand:DI 0 "register_operand" "=d")
980 (minus:DI (sign_extend:DI
981 (match_operand:SI 2 "register_operand" "d"))
982 (match_operand:DI 1 "register_operand" "0")))
983 (clobber (match_scratch:SI 3 "=&d"))
984 (clobber (reg:CC 34))]
986 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
987 [(set_attr "length" "14")
988 (set_attr "seq_insns" "multi")])
990 ;; Combined shift/add instructions
993 [(set (match_operand:SI 0 "register_operand" "=a,d")
994 (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
995 (match_operand:SI 2 "register_operand" "a,d"))
996 (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
998 "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
999 [(set_attr "type" "alu0")])
1002 [(set (match_operand:SI 0 "register_operand" "=a")
1003 (plus:SI (match_operand:SI 1 "register_operand" "a")
1004 (mult:SI (match_operand:SI 2 "register_operand" "a")
1005 (match_operand:SI 3 "scale_by_operand" "i"))))]
1007 "%0 = %1 + (%2 << %X3);"
1008 [(set_attr "type" "alu0")])
1011 [(set (match_operand:SI 0 "register_operand" "=a")
1012 (plus:SI (match_operand:SI 1 "register_operand" "a")
1013 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1014 (match_operand:SI 3 "pos_scale_operand" "i"))))]
1016 "%0 = %1 + (%2 << %3);"
1017 [(set_attr "type" "alu0")])
1020 [(set (match_operand:SI 0 "register_operand" "=a")
1021 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
1022 (match_operand:SI 2 "scale_by_operand" "i"))
1023 (match_operand:SI 3 "register_operand" "a")))]
1025 "%0 = %3 + (%1 << %X2);"
1026 [(set_attr "type" "alu0")])
1029 [(set (match_operand:SI 0 "register_operand" "=a")
1030 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
1031 (match_operand:SI 2 "pos_scale_operand" "i"))
1032 (match_operand:SI 3 "register_operand" "a")))]
1034 "%0 = %3 + (%1 << %2);"
1035 [(set_attr "type" "alu0")])
1037 (define_insn "mulhisi3"
1038 [(set (match_operand:SI 0 "register_operand" "=d")
1039 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1040 (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1042 "%0 = %h1 * %h2 (IS);"
1043 [(set_attr "type" "dsp32")])
1045 (define_insn "umulhisi3"
1046 [(set (match_operand:SI 0 "register_operand" "=d")
1047 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1048 (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1050 "%0 = %h1 * %h2 (FU);"
1051 [(set_attr "type" "dsp32")])
1053 (define_insn "usmulhisi3"
1054 [(set (match_operand:SI 0 "register_operand" "=W")
1055 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
1056 (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
1058 "%0 = %h2 * %h1 (IS,M);"
1059 [(set_attr "type" "dsp32")])
1061 ;; The processor also supports ireg += mreg or ireg -= mreg, but these
1062 ;; are unusable if we don't ensure that the corresponding lreg is zero.
1063 ;; The same applies to the add/subtract constant versions involving
1066 (define_insn "addsi3"
1067 [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
1068 (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
1069 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
1075 [(set_attr "type" "alu0")
1076 (set_attr "length" "2,2,2")])
1078 (define_insn "ssaddsi3"
1079 [(set (match_operand:SI 0 "register_operand" "=d")
1080 (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1081 (match_operand:SI 2 "register_operand" "d")))]
1084 [(set_attr "type" "dsp32")])
1086 (define_expand "subsi3"
1087 [(set (match_operand:SI 0 "register_operand" "")
1088 (minus:SI (match_operand:SI 1 "register_operand" "")
1089 (match_operand:SI 2 "reg_or_7bit_operand" "")))]
1094 [(set (match_operand:SI 0 "register_operand" "=da,d,a")
1095 (minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
1096 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7,d,a")))]
1097 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -64"
1099 static const char *const strings_subsi3[] = {
1105 if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
1106 rtx tmp_op = operands[2];
1107 operands[2] = GEN_INT (-INTVAL (operands[2]));
1108 output_asm_insn ("%0 += %2;", operands);
1109 operands[2] = tmp_op;
1113 return strings_subsi3[which_alternative];
1115 [(set_attr "type" "alu0")])
1117 (define_insn "sssubsi3"
1118 [(set (match_operand:SI 0 "register_operand" "=d")
1119 (ss_minus:SI (match_operand:SI 1 "register_operand" "d")
1120 (match_operand:SI 2 "register_operand" "d")))]
1123 [(set_attr "type" "dsp32")])
1125 ;; Bit test instructions
1127 (define_insn "*not_bittst"
1128 [(set (match_operand:BI 0 "register_operand" "=C")
1129 (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1131 (match_operand:SI 2 "immediate_operand" "Ku5"))
1134 "cc = !BITTST (%1,%2);"
1135 [(set_attr "type" "alu0")])
1137 (define_insn "*bittst"
1138 [(set (match_operand:BI 0 "register_operand" "=C")
1139 (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1141 (match_operand:SI 2 "immediate_operand" "Ku5"))
1144 "cc = BITTST (%1,%2);"
1145 [(set_attr "type" "alu0")])
1147 (define_insn_and_split "*bit_extract"
1148 [(set (match_operand:SI 0 "register_operand" "=d")
1149 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1151 (match_operand:SI 2 "immediate_operand" "Ku5")))
1152 (clobber (reg:BI REG_CC))]
1156 [(set (reg:BI REG_CC)
1157 (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1160 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1162 (define_insn_and_split "*not_bit_extract"
1163 [(set (match_operand:SI 0 "register_operand" "=d")
1164 (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1166 (match_operand:SI 2 "immediate_operand" "Ku5")))
1167 (clobber (reg:BI REG_CC))]
1171 [(set (reg:BI REG_CC)
1172 (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1175 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1177 (define_insn "*andsi_insn"
1178 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1179 (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
1180 (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
1187 [(set_attr "type" "alu0")])
1189 (define_expand "andsi3"
1190 [(set (match_operand:SI 0 "register_operand" "")
1191 (and:SI (match_operand:SI 1 "register_operand" "")
1192 (match_operand:SI 2 "general_operand" "")))]
1195 if (highbits_operand (operands[2], SImode))
1197 operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
1198 emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
1199 emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
1202 if (! rhs_andsi3_operand (operands[2], SImode))
1203 operands[2] = force_reg (SImode, operands[2]);
1206 (define_insn "iorsi3"
1207 [(set (match_operand:SI 0 "register_operand" "=d,d")
1208 (ior:SI (match_operand:SI 1 "register_operand" "%0,d")
1209 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1214 [(set_attr "type" "alu0")])
1216 (define_insn "xorsi3"
1217 [(set (match_operand:SI 0 "register_operand" "=d,d")
1218 (xor:SI (match_operand:SI 1 "register_operand" "%0,d")
1219 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1224 [(set_attr "type" "alu0")])
1226 (define_insn "smaxsi3"
1227 [(set (match_operand:SI 0 "register_operand" "=d")
1228 (smax:SI (match_operand:SI 1 "register_operand" "d")
1229 (match_operand:SI 2 "register_operand" "d")))]
1232 [(set_attr "type" "dsp32")])
1234 (define_insn "sminsi3"
1235 [(set (match_operand:SI 0 "register_operand" "=d")
1236 (smin:SI (match_operand:SI 1 "register_operand" "d")
1237 (match_operand:SI 2 "register_operand" "d")))]
1240 [(set_attr "type" "dsp32")])
1242 (define_insn "abssi2"
1243 [(set (match_operand:SI 0 "register_operand" "=d")
1244 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1247 [(set_attr "type" "dsp32")])
1249 (define_insn "negsi2"
1250 [(set (match_operand:SI 0 "register_operand" "=d")
1251 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1254 [(set_attr "type" "alu0")])
1256 (define_insn "ssnegsi2"
1257 [(set (match_operand:SI 0 "register_operand" "=d")
1258 (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
1261 [(set_attr "type" "dsp32")])
1263 (define_insn "one_cmplsi2"
1264 [(set (match_operand:SI 0 "register_operand" "=d")
1265 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1268 [(set_attr "type" "alu0")])
1270 (define_insn "signbitssi2"
1271 [(set (match_operand:HI 0 "register_operand" "=d")
1273 (lt (match_operand:SI 1 "register_operand" "d") (const_int 0))
1274 (clz:HI (not:SI (match_dup 1)))
1275 (clz:HI (match_dup 1))))]
1277 "%h0 = signbits %1;"
1278 [(set_attr "type" "dsp32")])
1280 (define_insn "smaxhi3"
1281 [(set (match_operand:HI 0 "register_operand" "=d")
1282 (smax:HI (match_operand:HI 1 "register_operand" "d")
1283 (match_operand:HI 2 "register_operand" "d")))]
1285 "%0 = max(%1,%2) (V);"
1286 [(set_attr "type" "dsp32")])
1288 (define_insn "sminhi3"
1289 [(set (match_operand:HI 0 "register_operand" "=d")
1290 (smin:HI (match_operand:HI 1 "register_operand" "d")
1291 (match_operand:HI 2 "register_operand" "d")))]
1293 "%0 = min(%1,%2) (V);"
1294 [(set_attr "type" "dsp32")])
1296 (define_insn "abshi2"
1297 [(set (match_operand:HI 0 "register_operand" "=d")
1298 (abs:HI (match_operand:HI 1 "register_operand" "d")))]
1301 [(set_attr "type" "dsp32")])
1303 (define_insn "neghi2"
1304 [(set (match_operand:HI 0 "register_operand" "=d")
1305 (neg:HI (match_operand:HI 1 "register_operand" "d")))]
1308 [(set_attr "type" "dsp32")])
1310 (define_insn "ssneghi2"
1311 [(set (match_operand:HI 0 "register_operand" "=d")
1312 (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
1315 [(set_attr "type" "dsp32")])
1317 (define_insn "signbitshi2"
1318 [(set (match_operand:HI 0 "register_operand" "=d")
1320 (lt (match_operand:HI 1 "register_operand" "d") (const_int 0))
1321 (clz:HI (not:HI (match_dup 1)))
1322 (clz:HI (match_dup 1))))]
1324 "%h0 = signbits %h1;"
1325 [(set_attr "type" "dsp32")])
1327 (define_insn "mulsi3"
1328 [(set (match_operand:SI 0 "register_operand" "=d")
1329 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1330 (match_operand:SI 2 "register_operand" "d")))]
1333 [(set_attr "type" "mult")])
1335 (define_expand "ashlsi3"
1336 [(set (match_operand:SI 0 "register_operand" "")
1337 (ashift:SI (match_operand:SI 1 "register_operand" "")
1338 (match_operand:SI 2 "nonmemory_operand" "")))]
1341 if (GET_CODE (operands[2]) == CONST_INT
1342 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
1344 emit_insn (gen_movsi (operands[0], const0_rtx));
1349 (define_insn_and_split "*ashlsi3_insn"
1350 [(set (match_operand:SI 0 "register_operand" "=d,a,a,a")
1351 (ashift:SI (match_operand:SI 1 "register_operand" "0,a,a,a")
1352 (match_operand:SI 2 "nonmemory_operand" "dKu5,P1,P2,?P3P4")))]
1359 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1360 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1361 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1362 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1363 [(set_attr "type" "shft")])
1365 (define_insn "ashrsi3"
1366 [(set (match_operand:SI 0 "register_operand" "=d")
1367 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
1368 (match_operand:SI 2 "nonmemory_operand" "dKu5")))]
1371 [(set_attr "type" "shft")])
1373 (define_insn "ror_one"
1374 [(set (match_operand:SI 0 "register_operand" "=d")
1375 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1376 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1377 (set (reg:BI REG_CC)
1378 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1380 "%0 = ROT %1 BY -1;"
1381 [(set_attr "type" "shft")
1382 (set_attr "length" "4")])
1384 (define_insn "rol_one"
1385 [(set (match_operand:SI 0 "register_operand" "+d")
1386 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1387 (zero_extend:SI (reg:BI REG_CC))))
1388 (set (reg:BI REG_CC)
1389 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1392 [(set_attr "type" "shft")
1393 (set_attr "length" "4")])
1395 (define_expand "lshrdi3"
1396 [(set (match_operand:DI 0 "register_operand" "")
1397 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1398 (match_operand:DI 2 "general_operand" "")))]
1401 rtx lo_half[2], hi_half[2];
1403 if (operands[2] != const1_rtx)
1405 if (! rtx_equal_p (operands[0], operands[1]))
1406 emit_move_insn (operands[0], operands[1]);
1408 split_di (operands, 2, lo_half, hi_half);
1410 emit_move_insn (bfin_cc_rtx, const0_rtx);
1411 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1412 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1416 (define_expand "ashrdi3"
1417 [(set (match_operand:DI 0 "register_operand" "")
1418 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
1419 (match_operand:DI 2 "general_operand" "")))]
1422 rtx lo_half[2], hi_half[2];
1424 if (operands[2] != const1_rtx)
1426 if (! rtx_equal_p (operands[0], operands[1]))
1427 emit_move_insn (operands[0], operands[1]);
1429 split_di (operands, 2, lo_half, hi_half);
1431 emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
1432 hi_half[1], const0_rtx));
1433 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1434 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1438 (define_expand "ashldi3"
1439 [(set (match_operand:DI 0 "register_operand" "")
1440 (ashift:DI (match_operand:DI 1 "register_operand" "")
1441 (match_operand:DI 2 "general_operand" "")))]
1444 rtx lo_half[2], hi_half[2];
1446 if (operands[2] != const1_rtx)
1448 if (! rtx_equal_p (operands[0], operands[1]))
1449 emit_move_insn (operands[0], operands[1]);
1451 split_di (operands, 2, lo_half, hi_half);
1453 emit_move_insn (bfin_cc_rtx, const0_rtx);
1454 emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
1455 emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
1459 (define_insn "lshrsi3"
1460 [(set (match_operand:SI 0 "register_operand" "=d,a")
1461 (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0,a")
1462 (match_operand:SI 2 "nonmemory_operand" "dKu5,P1P2")))]
1467 [(set_attr "type" "shft")])
1469 ;; A pattern to reload the equivalent of
1470 ;; (set (Dreg) (plus (FP) (large_constant)))
1472 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1473 ;; using a scratch register
1474 (define_expand "reload_insi"
1475 [(parallel [(set (match_operand:SI 0 "register_operand" "=w")
1476 (match_operand:SI 1 "fp_plus_const_operand" ""))
1477 (clobber (match_operand:SI 2 "register_operand" "=&a"))])]
1480 rtx fp_op = XEXP (operands[1], 0);
1481 rtx const_op = XEXP (operands[1], 1);
1482 rtx primary = operands[0];
1483 rtx scratch = operands[2];
1485 emit_move_insn (scratch, const_op);
1486 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1487 emit_move_insn (primary, scratch);
1491 ;; Jump instructions
1495 (label_ref (match_operand 0 "" "")))]
1498 if (get_attr_length (insn) == 2)
1499 return "jump.s %0;";
1501 return "jump.l %0;";
1503 [(set_attr "type" "br")])
1505 (define_insn "indirect_jump"
1507 (match_operand:SI 0 "register_operand" "a"))]
1510 [(set_attr "type" "misc")])
1512 (define_expand "tablejump"
1513 [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1514 (use (label_ref (match_operand 1 "" "")))])]
1517 /* In PIC mode, the table entries are stored PC relative.
1518 Convert the relative address to an absolute address. */
1521 rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
1523 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
1524 op1, NULL_RTX, 0, OPTAB_DIRECT);
1528 (define_insn "*tablejump_internal"
1529 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1530 (use (label_ref (match_operand 1 "" "")))]
1533 [(set_attr "type" "misc")])
1537 ; operand 0 is the loop count pseudo register
1538 ; operand 1 is the number of loop iterations or 0 if it is unknown
1539 ; operand 2 is the maximum number of loop iterations
1540 ; operand 3 is the number of levels of enclosed loops
1541 ; operand 4 is the label to jump to at the top of the loop
1542 (define_expand "doloop_end"
1543 [(parallel [(set (pc) (if_then_else
1544 (ne (match_operand:SI 0 "" "")
1546 (label_ref (match_operand 4 "" ""))
1549 (plus:SI (match_dup 0)
1551 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1552 (clobber (match_scratch:SI 5 ""))])]
1554 {bfin_hardware_loop ();})
1556 (define_insn "loop_end"
1558 (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*h*f,m")
1560 (label_ref (match_operand 1 "" ""))
1565 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1566 (clobber (match_scratch:SI 2 "=X,&r,&r"))]
1569 /* loop end %0 %l1 */
1572 [(set_attr "length" "6,10,14")])
1576 (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "")
1578 (label_ref (match_operand 1 "" ""))
1583 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1584 (clobber (match_scratch:SI 2 "=&r"))]
1586 [(set (match_dup 2) (match_dup 0))
1587 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1588 (set (match_dup 0) (match_dup 2))
1589 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1591 (if_then_else (eq (reg:BI REG_CC)
1593 (label_ref (match_dup 1))
1597 (define_insn "lsetup_with_autoinit"
1598 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1599 (label_ref (match_operand 1 "" "")))
1600 (set (match_operand:SI 2 "lb_register_operand" "=l")
1601 (label_ref (match_operand 3 "" "")))
1602 (set (match_operand:SI 4 "lc_register_operand" "=k")
1603 (match_operand:SI 5 "register_operand" "a"))]
1605 "LSETUP (%1, %3) %4 = %5;"
1606 [(set_attr "length" "4")])
1608 (define_insn "lsetup_without_autoinit"
1609 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1610 (label_ref (match_operand 1 "" "")))
1611 (set (match_operand:SI 2 "lb_register_operand" "=l")
1612 (label_ref (match_operand 3 "" "")))
1613 (use (match_operand:SI 4 "lc_register_operand" "k"))]
1615 "LSETUP (%1, %3) %4;"
1616 [(set_attr "length" "4")])
1618 ;; Call instructions..
1620 ;; The explicit MEM inside the UNSPEC prevents the compiler from moving
1621 ;; the load before a branch after a NULL test, or before a store that
1622 ;; initializes a function descriptor.
1624 (define_insn_and_split "load_funcdescsi"
1625 [(set (match_operand:SI 0 "register_operand" "=a")
1626 (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
1627 UNSPEC_VOLATILE_LOAD_FUNCDESC))]
1631 [(set (match_dup 0) (mem:SI (match_dup 1)))])
1633 (define_expand "call"
1634 [(parallel [(call (match_operand:SI 0 "" "")
1635 (match_operand 1 "" ""))
1636 (use (match_operand 2 "" ""))])]
1639 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
1643 (define_expand "sibcall"
1644 [(parallel [(call (match_operand:SI 0 "" "")
1645 (match_operand 1 "" ""))
1646 (use (match_operand 2 "" ""))
1650 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
1654 (define_expand "call_value"
1655 [(parallel [(set (match_operand 0 "register_operand" "")
1656 (call (match_operand:SI 1 "" "")
1657 (match_operand 2 "" "")))
1658 (use (match_operand 3 "" ""))])]
1661 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
1665 (define_expand "sibcall_value"
1666 [(parallel [(set (match_operand 0 "register_operand" "")
1667 (call (match_operand:SI 1 "" "")
1668 (match_operand 2 "" "")))
1669 (use (match_operand 3 "" ""))
1673 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
1677 (define_insn "*call_symbol_fdpic"
1678 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1679 (match_operand 1 "general_operand" "g"))
1680 (use (match_operand:SI 2 "register_operand" "Z"))
1681 (use (match_operand 3 "" ""))]
1682 "! SIBLING_CALL_P (insn)
1683 && GET_CODE (operands[0]) == SYMBOL_REF
1684 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1686 [(set_attr "type" "call")
1687 (set_attr "length" "4")])
1689 (define_insn "*sibcall_symbol_fdpic"
1690 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1691 (match_operand 1 "general_operand" "g"))
1692 (use (match_operand:SI 2 "register_operand" "Z"))
1693 (use (match_operand 3 "" ""))
1695 "SIBLING_CALL_P (insn)
1696 && GET_CODE (operands[0]) == SYMBOL_REF
1697 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1699 [(set_attr "type" "br")
1700 (set_attr "length" "4")])
1702 (define_insn "*call_value_symbol_fdpic"
1703 [(set (match_operand 0 "register_operand" "=d")
1704 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1705 (match_operand 2 "general_operand" "g")))
1706 (use (match_operand:SI 3 "register_operand" "Z"))
1707 (use (match_operand 4 "" ""))]
1708 "! SIBLING_CALL_P (insn)
1709 && GET_CODE (operands[1]) == SYMBOL_REF
1710 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1712 [(set_attr "type" "call")
1713 (set_attr "length" "4")])
1715 (define_insn "*sibcall_value_symbol_fdpic"
1716 [(set (match_operand 0 "register_operand" "=d")
1717 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1718 (match_operand 2 "general_operand" "g")))
1719 (use (match_operand:SI 3 "register_operand" "Z"))
1720 (use (match_operand 4 "" ""))
1722 "SIBLING_CALL_P (insn)
1723 && GET_CODE (operands[1]) == SYMBOL_REF
1724 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1726 [(set_attr "type" "br")
1727 (set_attr "length" "4")])
1729 (define_insn "*call_insn_fdpic"
1730 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1731 (match_operand 1 "general_operand" "g"))
1732 (use (match_operand:SI 2 "register_operand" "Z"))
1733 (use (match_operand 3 "" ""))]
1734 "! SIBLING_CALL_P (insn)"
1736 [(set_attr "type" "call")
1737 (set_attr "length" "2")])
1739 (define_insn "*sibcall_insn_fdpic"
1740 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1741 (match_operand 1 "general_operand" "g"))
1742 (use (match_operand:SI 2 "register_operand" "Z"))
1743 (use (match_operand 3 "" ""))
1745 "SIBLING_CALL_P (insn)"
1747 [(set_attr "type" "br")
1748 (set_attr "length" "2")])
1750 (define_insn "*call_value_insn_fdpic"
1751 [(set (match_operand 0 "register_operand" "=d")
1752 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1753 (match_operand 2 "general_operand" "g")))
1754 (use (match_operand:SI 3 "register_operand" "Z"))
1755 (use (match_operand 4 "" ""))]
1756 "! SIBLING_CALL_P (insn)"
1758 [(set_attr "type" "call")
1759 (set_attr "length" "2")])
1761 (define_insn "*sibcall_value_insn_fdpic"
1762 [(set (match_operand 0 "register_operand" "=d")
1763 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1764 (match_operand 2 "general_operand" "g")))
1765 (use (match_operand:SI 3 "register_operand" "Z"))
1766 (use (match_operand 4 "" ""))
1768 "SIBLING_CALL_P (insn)"
1770 [(set_attr "type" "br")
1771 (set_attr "length" "2")])
1773 (define_insn "*call_symbol"
1774 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1775 (match_operand 1 "general_operand" "g"))
1776 (use (match_operand 2 "" ""))]
1777 "! SIBLING_CALL_P (insn)
1778 && !TARGET_ID_SHARED_LIBRARY
1779 && GET_CODE (operands[0]) == SYMBOL_REF
1780 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1782 [(set_attr "type" "call")
1783 (set_attr "length" "4")])
1785 (define_insn "*sibcall_symbol"
1786 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1787 (match_operand 1 "general_operand" "g"))
1788 (use (match_operand 2 "" ""))
1790 "SIBLING_CALL_P (insn)
1791 && !TARGET_ID_SHARED_LIBRARY
1792 && GET_CODE (operands[0]) == SYMBOL_REF
1793 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1795 [(set_attr "type" "br")
1796 (set_attr "length" "4")])
1798 (define_insn "*call_value_symbol"
1799 [(set (match_operand 0 "register_operand" "=d")
1800 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1801 (match_operand 2 "general_operand" "g")))
1802 (use (match_operand 3 "" ""))]
1803 "! SIBLING_CALL_P (insn)
1804 && !TARGET_ID_SHARED_LIBRARY
1805 && GET_CODE (operands[1]) == SYMBOL_REF
1806 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
1808 [(set_attr "type" "call")
1809 (set_attr "length" "4")])
1811 (define_insn "*sibcall_value_symbol"
1812 [(set (match_operand 0 "register_operand" "=d")
1813 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1814 (match_operand 2 "general_operand" "g")))
1815 (use (match_operand 3 "" ""))
1817 "SIBLING_CALL_P (insn)
1818 && !TARGET_ID_SHARED_LIBRARY
1819 && GET_CODE (operands[1]) == SYMBOL_REF
1820 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
1822 [(set_attr "type" "br")
1823 (set_attr "length" "4")])
1825 (define_insn "*call_insn"
1826 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
1827 (match_operand 1 "general_operand" "g"))
1828 (use (match_operand 2 "" ""))]
1829 "! SIBLING_CALL_P (insn)"
1831 [(set_attr "type" "call")
1832 (set_attr "length" "2")])
1834 (define_insn "*sibcall_insn"
1835 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
1836 (match_operand 1 "general_operand" "g"))
1837 (use (match_operand 2 "" ""))
1839 "SIBLING_CALL_P (insn)"
1841 [(set_attr "type" "br")
1842 (set_attr "length" "2")])
1844 (define_insn "*call_value_insn"
1845 [(set (match_operand 0 "register_operand" "=d")
1846 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
1847 (match_operand 2 "general_operand" "g")))
1848 (use (match_operand 3 "" ""))]
1849 "! SIBLING_CALL_P (insn)"
1851 [(set_attr "type" "call")
1852 (set_attr "length" "2")])
1854 (define_insn "*sibcall_value_insn"
1855 [(set (match_operand 0 "register_operand" "=d")
1856 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
1857 (match_operand 2 "general_operand" "g")))
1858 (use (match_operand 3 "" ""))
1860 "SIBLING_CALL_P (insn)"
1862 [(set_attr "type" "br")
1863 (set_attr "length" "2")])
1865 ;; Block move patterns
1867 ;; We cheat. This copies one more word than operand 2 indicates.
1869 (define_insn "rep_movsi"
1870 [(set (match_operand:SI 0 "register_operand" "=&a")
1871 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
1872 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1875 (set (match_operand:SI 1 "register_operand" "=&b")
1876 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
1877 (ashift:SI (match_dup 2) (const_int 2)))
1879 (set (mem:BLK (match_dup 3))
1880 (mem:BLK (match_dup 4)))
1882 (clobber (match_scratch:HI 5 "=&d"))
1883 (clobber (reg:SI REG_LT1))
1884 (clobber (reg:SI REG_LC1))
1885 (clobber (reg:SI REG_LB1))]
1887 "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
1888 [(set_attr "type" "misc")
1889 (set_attr "length" "16")
1890 (set_attr "seq_insns" "multi")])
1892 (define_insn "rep_movhi"
1893 [(set (match_operand:SI 0 "register_operand" "=&a")
1894 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
1895 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1898 (set (match_operand:SI 1 "register_operand" "=&b")
1899 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
1900 (ashift:SI (match_dup 2) (const_int 1)))
1902 (set (mem:BLK (match_dup 3))
1903 (mem:BLK (match_dup 4)))
1905 (clobber (match_scratch:HI 5 "=&d"))
1906 (clobber (reg:SI REG_LT1))
1907 (clobber (reg:SI REG_LC1))
1908 (clobber (reg:SI REG_LB1))]
1910 "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
1911 [(set_attr "type" "misc")
1912 (set_attr "length" "16")
1913 (set_attr "seq_insns" "multi")])
1915 (define_expand "movmemsi"
1916 [(match_operand:BLK 0 "general_operand" "")
1917 (match_operand:BLK 1 "general_operand" "")
1918 (match_operand:SI 2 "const_int_operand" "")
1919 (match_operand:SI 3 "const_int_operand" "")]
1922 if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
1927 ;; Conditional branch patterns
1928 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
1930 ;; The only outcome of this pattern is that global variables
1931 ;; bfin_compare_op[01] are set for use in bcond patterns.
1933 (define_expand "cmpbi"
1934 [(set (cc0) (compare (match_operand:BI 0 "register_operand" "")
1935 (match_operand:BI 1 "immediate_operand" "")))]
1938 bfin_compare_op0 = operands[0];
1939 bfin_compare_op1 = operands[1];
1943 (define_expand "cmpsi"
1944 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
1945 (match_operand:SI 1 "reg_or_const_int_operand" "")))]
1948 bfin_compare_op0 = operands[0];
1949 bfin_compare_op1 = operands[1];
1953 (define_insn "compare_eq"
1954 [(set (match_operand:BI 0 "register_operand" "=C,C")
1955 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
1956 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
1959 [(set_attr "type" "compare")])
1961 (define_insn "compare_ne"
1962 [(set (match_operand:BI 0 "register_operand" "=C,C")
1963 (ne:BI (match_operand:SI 1 "register_operand" "d,a")
1964 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
1967 [(set_attr "type" "compare")])
1969 (define_insn "compare_lt"
1970 [(set (match_operand:BI 0 "register_operand" "=C,C")
1971 (lt:BI (match_operand:SI 1 "register_operand" "d,a")
1972 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
1975 [(set_attr "type" "compare")])
1977 (define_insn "compare_le"
1978 [(set (match_operand:BI 0 "register_operand" "=C,C")
1979 (le:BI (match_operand:SI 1 "register_operand" "d,a")
1980 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
1983 [(set_attr "type" "compare")])
1985 (define_insn "compare_leu"
1986 [(set (match_operand:BI 0 "register_operand" "=C,C")
1987 (leu:BI (match_operand:SI 1 "register_operand" "d,a")
1988 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
1991 [(set_attr "type" "compare")])
1993 (define_insn "compare_ltu"
1994 [(set (match_operand:BI 0 "register_operand" "=C,C")
1995 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
1996 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
1999 [(set_attr "type" "compare")])
2001 (define_expand "beq"
2002 [(set (match_dup 1) (match_dup 2))
2004 (if_then_else (match_dup 3)
2005 (label_ref (match_operand 0 "" ""))
2009 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2010 operands[1] = bfin_cc_rtx; /* hard register: CC */
2011 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2012 /* If we have a BImode input, then we already have a compare result, and
2013 do not need to emit another comparison. */
2014 if (GET_MODE (bfin_compare_op0) == BImode)
2016 gcc_assert (bfin_compare_op1 == const0_rtx);
2017 emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0]));
2021 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2024 (define_expand "bne"
2025 [(set (match_dup 1) (match_dup 2))
2027 (if_then_else (match_dup 3)
2028 (label_ref (match_operand 0 "" ""))
2032 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2033 /* If we have a BImode input, then we already have a compare result, and
2034 do not need to emit another comparison. */
2035 if (GET_MODE (bfin_compare_op0) == BImode)
2037 rtx cmp = gen_rtx_NE (BImode, op0, op1);
2039 gcc_assert (bfin_compare_op1 == const0_rtx);
2040 emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
2044 operands[1] = bfin_cc_rtx; /* hard register: CC */
2045 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2046 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2049 (define_expand "bgt"
2050 [(set (match_dup 1) (match_dup 2))
2052 (if_then_else (match_dup 3)
2053 (label_ref (match_operand 0 "" ""))
2057 operands[1] = bfin_cc_rtx;
2058 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2059 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2062 (define_expand "bgtu"
2063 [(set (match_dup 1) (match_dup 2))
2065 (if_then_else (match_dup 3)
2066 (label_ref (match_operand 0 "" ""))
2070 operands[1] = bfin_cc_rtx;
2071 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2072 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2075 (define_expand "blt"
2076 [(set (match_dup 1) (match_dup 2))
2078 (if_then_else (match_dup 3)
2079 (label_ref (match_operand 0 "" ""))
2083 operands[1] = bfin_cc_rtx;
2084 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2085 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2088 (define_expand "bltu"
2089 [(set (match_dup 1) (match_dup 2))
2091 (if_then_else (match_dup 3)
2092 (label_ref (match_operand 0 "" ""))
2096 operands[1] = bfin_cc_rtx;
2097 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2098 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2102 (define_expand "bge"
2103 [(set (match_dup 1) (match_dup 2))
2105 (if_then_else (match_dup 3)
2106 (label_ref (match_operand 0 "" ""))
2110 operands[1] = bfin_cc_rtx;
2111 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2112 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2115 (define_expand "bgeu"
2116 [(set (match_dup 1) (match_dup 2))
2118 (if_then_else (match_dup 3)
2119 (label_ref (match_operand 0 "" ""))
2123 operands[1] = bfin_cc_rtx;
2124 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2125 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2128 (define_expand "ble"
2129 [(set (match_dup 1) (match_dup 2))
2131 (if_then_else (match_dup 3)
2132 (label_ref (match_operand 0 "" ""))
2136 operands[1] = bfin_cc_rtx;
2137 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2138 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2141 (define_expand "bleu"
2142 [(set (match_dup 1) (match_dup 2))
2144 (if_then_else (match_dup 3)
2145 (label_ref (match_operand 0 "" ""))
2150 operands[1] = bfin_cc_rtx;
2151 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2152 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2155 (define_insn "cbranchbi4"
2158 (match_operator 0 "bfin_cbranch_operator"
2159 [(match_operand:BI 1 "register_operand" "C")
2160 (match_operand:BI 2 "immediate_operand" "P0")])
2161 (label_ref (match_operand 3 "" ""))
2165 asm_conditional_branch (insn, operands, 0, 0);
2168 [(set_attr "type" "brcc")])
2170 ;; Special cbranch patterns to deal with the speculative load problem - see
2171 ;; bfin_reorg for details.
2173 (define_insn "cbranch_predicted_taken"
2176 (match_operator 0 "bfin_cbranch_operator"
2177 [(match_operand:BI 1 "register_operand" "C")
2178 (match_operand:BI 2 "immediate_operand" "P0")])
2179 (label_ref (match_operand 3 "" ""))
2181 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2184 asm_conditional_branch (insn, operands, 0, 1);
2187 [(set_attr "type" "brcc")])
2189 (define_insn "cbranch_with_nops"
2192 (match_operator 0 "bfin_cbranch_operator"
2193 [(match_operand:BI 1 "register_operand" "C")
2194 (match_operand:BI 2 "immediate_operand" "P0")])
2195 (label_ref (match_operand 3 "" ""))
2197 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2200 asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
2203 [(set_attr "type" "brcc")
2204 (set_attr "length" "6")])
2207 (define_expand "seq"
2208 [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3)))
2209 (set (match_operand:SI 0 "register_operand" "")
2210 (ne:SI (match_dup 1) (const_int 0)))]
2213 operands[2] = bfin_compare_op0;
2214 operands[3] = bfin_compare_op1;
2215 operands[1] = bfin_cc_rtx;
2218 (define_expand "slt"
2219 [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3)))
2220 (set (match_operand:SI 0 "register_operand" "")
2221 (ne:SI (match_dup 1) (const_int 0)))]
2224 operands[2] = bfin_compare_op0;
2225 operands[3] = bfin_compare_op1;
2226 operands[1] = bfin_cc_rtx;
2229 (define_expand "sle"
2230 [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3)))
2231 (set (match_operand:SI 0 "register_operand" "")
2232 (ne:SI (match_dup 1) (const_int 0)))]
2235 operands[2] = bfin_compare_op0;
2236 operands[3] = bfin_compare_op1;
2237 operands[1] = bfin_cc_rtx;
2240 (define_expand "sltu"
2241 [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3)))
2242 (set (match_operand:SI 0 "register_operand" "")
2243 (ne:SI (match_dup 1) (const_int 0)))]
2246 operands[2] = bfin_compare_op0;
2247 operands[3] = bfin_compare_op1;
2248 operands[1] = bfin_cc_rtx;
2251 (define_expand "sleu"
2252 [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
2253 (set (match_operand:SI 0 "register_operand" "")
2254 (ne:SI (match_dup 1) (const_int 0)))]
2257 operands[2] = bfin_compare_op0;
2258 operands[3] = bfin_compare_op1;
2259 operands[1] = bfin_cc_rtx;
2267 ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
2268 (define_insn "movsibi"
2269 [(set (match_operand:BI 0 "register_operand" "=C")
2270 (ne:BI (match_operand:SI 1 "register_operand" "d")
2274 [(set_attr "length" "2")])
2276 (define_insn "movbisi"
2277 [(set (match_operand:SI 0 "register_operand" "=d")
2278 (ne:SI (match_operand:BI 1 "register_operand" "C")
2282 [(set_attr "length" "2")])
2285 [(set (match_operand:BI 0 "register_operand" "=C")
2286 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2289 "%0 = ! %0;" /* NOT CC;" */
2290 [(set_attr "type" "compare")])
2292 ;; Vector and DSP insns
2295 [(set (match_operand:SI 0 "register_operand" "=d")
2296 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2298 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2301 "%0 = ALIGN8(%1, %2);"
2302 [(set_attr "type" "dsp32")])
2305 [(set (match_operand:SI 0 "register_operand" "=d")
2306 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2308 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2311 "%0 = ALIGN16(%1, %2);"
2312 [(set_attr "type" "dsp32")])
2315 [(set (match_operand:SI 0 "register_operand" "=d")
2316 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2318 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2321 "%0 = ALIGN24(%1, %2);"
2322 [(set_attr "type" "dsp32")])
2324 ;; Prologue and epilogue.
2326 (define_expand "prologue"
2329 "bfin_expand_prologue (); DONE;")
2331 (define_expand "epilogue"
2334 "bfin_expand_epilogue (1, 0); DONE;")
2336 (define_expand "sibcall_epilogue"
2339 "bfin_expand_epilogue (0, 0); DONE;")
2341 (define_expand "eh_return"
2342 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")]
2343 UNSPEC_VOLATILE_EH_RETURN)]
2346 emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]);
2347 emit_insn (gen_eh_return_internal ());
2352 (define_insn_and_split "eh_return_internal"
2353 [(unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN)]
2358 "bfin_expand_epilogue (1, 1); DONE;")
2361 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2362 (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
2363 (set (reg:SI REG_FP)
2364 (plus:SI (reg:SI REG_SP) (const_int -8)))
2365 (set (reg:SI REG_SP)
2366 (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
2369 [(set_attr "length" "4")])
2371 (define_insn "unlink"
2372 [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
2373 (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
2374 (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
2377 [(set_attr "length" "4")])
2379 ;; This pattern is slightly clumsy. The stack adjust must be the final SET in
2380 ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
2381 ;; where on the stack, since it goes through all elements of the parallel in
2383 (define_insn "push_multiple"
2384 [(match_parallel 0 "push_multiple_operation"
2385 [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
2388 output_push_multiple (insn, operands);
2392 (define_insn "pop_multiple"
2393 [(match_parallel 0 "pop_multiple_operation"
2394 [(set (reg:SI REG_SP)
2395 (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
2398 output_pop_multiple (insn, operands);
2402 (define_insn "return_internal"
2404 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)]
2407 switch (INTVAL (operands[0]))
2413 case INTERRUPT_HANDLER:
2421 (define_insn "csync"
2422 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2425 [(set_attr "type" "sync")])
2427 (define_insn "ssync"
2428 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
2431 [(set_attr "type" "sync")])
2434 [(trap_if (const_int 1) (const_int 3))]
2437 [(set_attr "type" "misc")
2438 (set_attr "length" "2")])
2440 (define_insn "trapifcc"
2441 [(trap_if (reg:BI REG_CC) (const_int 3))]
2443 "if !cc jump 4 (bp); excpt 3;"
2444 [(set_attr "type" "misc")
2445 (set_attr "length" "4")
2446 (set_attr "seq_insns" "multi")])
2448 ;;; Vector instructions
2450 ;; First, all sorts of move variants
2452 (define_insn "movhi_low2high"
2453 [(set (match_operand:V2HI 0 "register_operand" "=d")
2455 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2456 (parallel [(const_int 0)]))
2457 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2458 (parallel [(const_int 0)]))))]
2461 [(set_attr "type" "dsp32")])
2463 (define_insn "movhi_high2high"
2464 [(set (match_operand:V2HI 0 "register_operand" "=d")
2466 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2467 (parallel [(const_int 0)]))
2468 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2469 (parallel [(const_int 1)]))))]
2472 [(set_attr "type" "dsp32")])
2474 (define_insn "movhi_low2low"
2475 [(set (match_operand:V2HI 0 "register_operand" "=d")
2477 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2478 (parallel [(const_int 0)]))
2479 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2480 (parallel [(const_int 1)]))))]
2483 [(set_attr "type" "dsp32")])
2485 (define_insn "movhi_high2low"
2486 [(set (match_operand:V2HI 0 "register_operand" "=d")
2488 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2489 (parallel [(const_int 1)]))
2490 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2491 (parallel [(const_int 1)]))))]
2494 [(set_attr "type" "dsp32")])
2496 (define_insn "movhiv2hi_low"
2497 [(set (match_operand:V2HI 0 "register_operand" "=d")
2499 (match_operand:HI 2 "register_operand" "d")
2500 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2501 (parallel [(const_int 1)]))))]
2504 [(set_attr "type" "dsp32")])
2506 (define_insn "movhiv2hi_high"
2507 [(set (match_operand:V2HI 0 "register_operand" "=d")
2509 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2510 (parallel [(const_int 0)]))
2511 (match_operand:HI 2 "register_operand" "d")))]
2514 [(set_attr "type" "dsp32")])
2516 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2517 ;; The order of operands is intentional to match the VDSP builtin (high word
2518 ;; is passed first).
2519 (define_insn_and_split "composev2hi"
2520 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
2521 (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
2522 (match_operand:HI 1 "register_operand" "d,d")))]
2530 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
2535 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2537 [(set_attr "type" "dsp32")])
2539 ; Like composev2hi, but operating on elements of V2HI vectors.
2540 ; Useful on its own, and as a combiner bridge for the multiply and
2542 (define_insn "packv2hi"
2543 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d")
2544 (vec_concat:V2HI (vec_select:HI
2545 (match_operand:V2HI 1 "register_operand" "d,d,d,d")
2546 (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")]))
2548 (match_operand:V2HI 2 "register_operand" "d,d,d,d")
2549 (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))]
2552 %0 = PACK (%h2,%h1);
2553 %0 = PACK (%h2,%d1);
2554 %0 = PACK (%d2,%h1);
2555 %0 = PACK (%d2,%d1);"
2556 [(set_attr "type" "dsp32")])
2558 (define_insn "movv2hi_hi"
2559 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2560 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2561 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2567 [(set_attr "type" "dsp32")])
2569 (define_expand "movv2hi_hi_low"
2570 [(set (match_operand:HI 0 "register_operand" "")
2571 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2572 (parallel [(const_int 0)])))]
2576 (define_expand "movv2hi_hi_high"
2577 [(set (match_operand:HI 0 "register_operand" "")
2578 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2579 (parallel [(const_int 1)])))]
2583 ;; Unusual arithmetic operations on 16 bit registers.
2585 (define_insn "ssaddhi3"
2586 [(set (match_operand:HI 0 "register_operand" "=d")
2587 (ss_plus:HI (match_operand:HI 1 "register_operand" "d")
2588 (match_operand:HI 2 "register_operand" "d")))]
2590 "%h0 = %h1 + %h2 (S);"
2591 [(set_attr "type" "dsp32")])
2593 (define_insn "sssubhi3"
2594 [(set (match_operand:HI 0 "register_operand" "=d")
2595 (ss_minus:HI (match_operand:HI 1 "register_operand" "d")
2596 (match_operand:HI 2 "register_operand" "d")))]
2598 "%h0 = %h1 - %h2 (S);"
2599 [(set_attr "type" "dsp32")])
2601 ;; V2HI vector insns
2603 (define_insn "addv2hi3"
2604 [(set (match_operand:V2HI 0 "register_operand" "=d")
2605 (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2606 (match_operand:V2HI 2 "register_operand" "d")))]
2609 [(set_attr "type" "dsp32")])
2611 (define_insn "ssaddv2hi3"
2612 [(set (match_operand:V2HI 0 "register_operand" "=d")
2613 (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2614 (match_operand:V2HI 2 "register_operand" "d")))]
2616 "%0 = %1 +|+ %2 (S);"
2617 [(set_attr "type" "dsp32")])
2619 (define_insn "subv2hi3"
2620 [(set (match_operand:V2HI 0 "register_operand" "=d")
2621 (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2622 (match_operand:V2HI 2 "register_operand" "d")))]
2625 [(set_attr "type" "dsp32")])
2627 (define_insn "sssubv2hi3"
2628 [(set (match_operand:V2HI 0 "register_operand" "=d")
2629 (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2630 (match_operand:V2HI 2 "register_operand" "d")))]
2632 "%0 = %1 -|- %2 (S);"
2633 [(set_attr "type" "dsp32")])
2635 (define_insn "addsubv2hi3"
2636 [(set (match_operand:V2HI 0 "register_operand" "=d")
2638 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2639 (parallel [(const_int 0)]))
2640 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2641 (parallel [(const_int 0)])))
2642 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2643 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2646 [(set_attr "type" "dsp32")])
2648 (define_insn "subaddv2hi3"
2649 [(set (match_operand:V2HI 0 "register_operand" "=d")
2651 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2652 (parallel [(const_int 0)]))
2653 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2654 (parallel [(const_int 0)])))
2655 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2656 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2659 [(set_attr "type" "dsp32")])
2661 (define_insn "ssaddsubv2hi3"
2662 [(set (match_operand:V2HI 0 "register_operand" "=d")
2664 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2665 (parallel [(const_int 0)]))
2666 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2667 (parallel [(const_int 0)])))
2668 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2669 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2671 "%0 = %1 +|- %2 (S);"
2672 [(set_attr "type" "dsp32")])
2674 (define_insn "sssubaddv2hi3"
2675 [(set (match_operand:V2HI 0 "register_operand" "=d")
2677 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2678 (parallel [(const_int 0)]))
2679 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2680 (parallel [(const_int 0)])))
2681 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2682 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2684 "%0 = %1 -|+ %2 (S);"
2685 [(set_attr "type" "dsp32")])
2687 (define_insn "sublohiv2hi3"
2688 [(set (match_operand:HI 0 "register_operand" "=d")
2689 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2690 (parallel [(const_int 1)]))
2691 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2692 (parallel [(const_int 0)]))))]
2695 [(set_attr "type" "dsp32")])
2697 (define_insn "subhilov2hi3"
2698 [(set (match_operand:HI 0 "register_operand" "=d")
2699 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2700 (parallel [(const_int 0)]))
2701 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2702 (parallel [(const_int 1)]))))]
2705 [(set_attr "type" "dsp32")])
2707 (define_insn "sssublohiv2hi3"
2708 [(set (match_operand:HI 0 "register_operand" "=d")
2709 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2710 (parallel [(const_int 1)]))
2711 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2712 (parallel [(const_int 0)]))))]
2714 "%h0 = %d1 - %h2 (S);"
2715 [(set_attr "type" "dsp32")])
2717 (define_insn "sssubhilov2hi3"
2718 [(set (match_operand:HI 0 "register_operand" "=d")
2719 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2720 (parallel [(const_int 0)]))
2721 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2722 (parallel [(const_int 1)]))))]
2724 "%h0 = %h1 - %d2 (S);"
2725 [(set_attr "type" "dsp32")])
2727 (define_insn "addlohiv2hi3"
2728 [(set (match_operand:HI 0 "register_operand" "=d")
2729 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2730 (parallel [(const_int 1)]))
2731 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2732 (parallel [(const_int 0)]))))]
2735 [(set_attr "type" "dsp32")])
2737 (define_insn "addhilov2hi3"
2738 [(set (match_operand:HI 0 "register_operand" "=d")
2739 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2740 (parallel [(const_int 0)]))
2741 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2742 (parallel [(const_int 1)]))))]
2745 [(set_attr "type" "dsp32")])
2747 (define_insn "ssaddlohiv2hi3"
2748 [(set (match_operand:HI 0 "register_operand" "=d")
2749 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2750 (parallel [(const_int 1)]))
2751 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2752 (parallel [(const_int 0)]))))]
2754 "%h0 = %d1 + %h2 (S);"
2755 [(set_attr "type" "dsp32")])
2757 (define_insn "ssaddhilov2hi3"
2758 [(set (match_operand:HI 0 "register_operand" "=d")
2759 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2760 (parallel [(const_int 0)]))
2761 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2762 (parallel [(const_int 1)]))))]
2764 "%h0 = %h1 + %d2 (S);"
2765 [(set_attr "type" "dsp32")])
2767 (define_insn "sminv2hi3"
2768 [(set (match_operand:V2HI 0 "register_operand" "=d")
2769 (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
2770 (match_operand:V2HI 2 "register_operand" "d")))]
2772 "%0 = MIN (%1, %2) (V);"
2773 [(set_attr "type" "dsp32")])
2775 (define_insn "smaxv2hi3"
2776 [(set (match_operand:V2HI 0 "register_operand" "=d")
2777 (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
2778 (match_operand:V2HI 2 "register_operand" "d")))]
2780 "%0 = MAX (%1, %2) (V);"
2781 [(set_attr "type" "dsp32")])
2785 ;; The Blackfin allows a lot of different options, and we need many patterns to
2786 ;; cover most of the hardware's abilities.
2787 ;; There are a few simple patterns using MULT rtx codes, but most of them use
2788 ;; an unspec with a const_int operand that determines which flag to use in the
2790 ;; There are variants for single and parallel multiplications.
2791 ;; There are variants which just use 16 bit lowparts as inputs, and variants
2792 ;; which allow the user to choose just which halves to use as input values.
2793 ;; There are variants which set D registers, variants which set accumulators,
2794 ;; variants which set both, some of them optionally using the accumulators as
2795 ;; inputs for multiply-accumulate operations.
2797 (define_insn "flag_mulhi"
2798 [(set (match_operand:HI 0 "register_operand" "=d")
2799 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2800 (match_operand:HI 2 "register_operand" "d")
2801 (match_operand 3 "const_int_operand" "n")]
2802 UNSPEC_MUL_WITH_FLAG))]
2804 "%h0 = %h1 * %h2 %M3;"
2805 [(set_attr "type" "dsp32")])
2807 (define_insn "flag_mulhisi"
2808 [(set (match_operand:SI 0 "register_operand" "=d")
2809 (unspec:SI [(match_operand:HI 1 "register_operand" "d")
2810 (match_operand:HI 2 "register_operand" "d")
2811 (match_operand 3 "const_int_operand" "n")]
2812 UNSPEC_MUL_WITH_FLAG))]
2814 "%0 = %h1 * %h2 %M3;"
2815 [(set_attr "type" "dsp32")])
2817 (define_insn "flag_mulhisi_parts"
2818 [(set (match_operand:SI 0 "register_operand" "=d")
2819 (unspec:SI [(vec_select:HI
2820 (match_operand:V2HI 1 "register_operand" "d")
2821 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2823 (match_operand:V2HI 2 "register_operand" "d")
2824 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
2825 (match_operand 5 "const_int_operand" "n")]
2826 UNSPEC_MUL_WITH_FLAG))]
2829 const char *templates[] = {
2830 "%0 = %h1 * %h2 %M5;",
2831 "%0 = %d1 * %h2 %M5;",
2832 "%0 = %h1 * %d2 %M5;",
2833 "%0 = %d1 * %d2 %M5;" };
2834 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
2835 return templates[alt];
2837 [(set_attr "type" "dsp32")])
2839 (define_insn "flag_machi"
2840 [(set (match_operand:HI 0 "register_operand" "=d")
2841 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2842 (match_operand:HI 2 "register_operand" "d")
2843 (match_operand 3 "register_operand" "A")
2844 (match_operand 4 "const01_operand" "P0P1")
2845 (match_operand 5 "const_int_operand" "n")]
2846 UNSPEC_MAC_WITH_FLAG))
2847 (set (match_operand:PDI 6 "register_operand" "=A")
2848 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
2849 (match_dup 4) (match_dup 5)]
2850 UNSPEC_MAC_WITH_FLAG))]
2852 "%h0 = (A0 %b4 %h1 * %h2) %M6;"
2853 [(set_attr "type" "dsp32")])
2855 (define_insn "flag_machi_acconly"
2856 [(set (match_operand:PDI 0 "register_operand" "=e")
2857 (unspec:PDI [(match_operand:HI 1 "register_operand" "d")
2858 (match_operand:HI 2 "register_operand" "d")
2859 (match_operand 3 "register_operand" "A")
2860 (match_operand 4 "const01_operand" "P0P1")
2861 (match_operand 5 "const_int_operand" "n")]
2862 UNSPEC_MAC_WITH_FLAG))]
2864 "%0 %b4 %h1 * %h2 %M6;"
2865 [(set_attr "type" "dsp32")])
2867 (define_insn "flag_macinithi"
2868 [(set (match_operand:HI 0 "register_operand" "=d")
2869 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2870 (match_operand:HI 2 "register_operand" "d")
2871 (match_operand 3 "const_int_operand" "n")]
2872 UNSPEC_MAC_WITH_FLAG))
2873 (set (match_operand:PDI 4 "register_operand" "=A")
2874 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
2875 UNSPEC_MAC_WITH_FLAG))]
2877 "%h0 = (A0 = %h1 * %h2) %M3;"
2878 [(set_attr "type" "dsp32")])
2880 (define_insn "flag_macinit1hi"
2881 [(set (match_operand:PDI 0 "register_operand" "=e")
2882 (unspec:PDI [(match_operand:HI 1 "register_operand" "d")
2883 (match_operand:HI 2 "register_operand" "d")
2884 (match_operand 3 "const_int_operand" "n")]
2885 UNSPEC_MAC_WITH_FLAG))]
2887 "%0 = %h1 * %h2 %M3;"
2888 [(set_attr "type" "dsp32")])
2890 (define_insn "mulv2hi3"
2891 [(set (match_operand:V2HI 0 "register_operand" "=d")
2892 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
2893 (match_operand:V2HI 2 "register_operand" "d")))]
2895 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS);"
2896 [(set_attr "type" "dsp32")])
2898 (define_insn "flag_mulv2hi"
2899 [(set (match_operand:V2HI 0 "register_operand" "=d")
2900 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
2901 (match_operand:V2HI 2 "register_operand" "d")
2902 (match_operand 3 "const_int_operand" "n")]
2903 UNSPEC_MUL_WITH_FLAG))]
2905 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3;"
2906 [(set_attr "type" "dsp32")])
2908 (define_insn "flag_mulv2hi_parts"
2909 [(set (match_operand:V2HI 0 "register_operand" "=d")
2910 (unspec:V2HI [(vec_concat:V2HI
2912 (match_operand:V2HI 1 "register_operand" "d")
2913 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2916 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
2918 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2919 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
2920 (vec_select:HI (match_dup 2)
2921 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
2922 (match_operand 7 "const_int_operand" "n")]
2923 UNSPEC_MUL_WITH_FLAG))]
2926 const char *templates[] = {
2927 "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7;",
2928 "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7;",
2929 "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7;",
2930 "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7;",
2931 "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7;",
2932 "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7;",
2933 "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7;",
2934 "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7;",
2935 "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7;",
2936 "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7;",
2937 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7;",
2938 "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7;",
2939 "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7;",
2940 "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7;",
2941 "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7;",
2942 "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7;" };
2943 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
2944 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
2945 return templates[alt];
2947 [(set_attr "type" "dsp32")])
2949 ;; A slightly complicated pattern.
2950 ;; Operand 0 is the halfword output; operand 11 is the accumulator output
2951 ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
2952 ;; parts of these 2x16 bit registers to use.
2953 ;; Operand 7 is the accumulator input.
2954 ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
2955 ;; Operand 10 is the macflag to be used.
2956 (define_insn "flag_macv2hi_parts"
2957 [(set (match_operand:V2HI 0 "register_operand" "=d")
2958 (unspec:V2HI [(vec_concat:V2HI
2960 (match_operand:V2HI 1 "register_operand" "d")
2961 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2964 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
2966 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2967 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
2968 (vec_select:HI (match_dup 2)
2969 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
2970 (match_operand:V2PDI 7 "register_operand" "e")
2971 (match_operand 8 "const01_operand" "P0P1")
2972 (match_operand 9 "const01_operand" "P0P1")
2973 (match_operand 10 "const_int_operand" "n")]
2974 UNSPEC_MAC_WITH_FLAG))
2975 (set (match_operand:V2PDI 11 "register_operand" "=e")
2976 (unspec:V2PDI [(vec_concat:V2HI
2977 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
2978 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
2980 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
2981 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
2982 (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
2983 UNSPEC_MAC_WITH_FLAG))]
2986 const char *templates[] = {
2987 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10;",
2988 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10;",
2989 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10;",
2990 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10;",
2991 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10;",
2992 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10;",
2993 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10;",
2994 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10;",
2995 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10;",
2996 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10;",
2997 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10;",
2998 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10;",
2999 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10;",
3000 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10;",
3001 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10;",
3002 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10;" };
3003 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3004 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3005 return templates[alt];
3007 [(set_attr "type" "dsp32")])
3009 (define_insn "flag_macv2hi_parts_acconly"
3010 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3011 (unspec:V2PDI [(vec_concat:V2HI
3013 (match_operand:V2HI 1 "register_operand" "d")
3014 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3017 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3019 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3020 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3021 (vec_select:HI (match_dup 2)
3022 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3023 (match_operand:V2PDI 7 "register_operand" "e")
3024 (match_operand 8 "const01_operand" "P0P1")
3025 (match_operand 9 "const01_operand" "P0P1")
3026 (match_operand 10 "const_int_operand" "n")]
3027 UNSPEC_MAC_WITH_FLAG))]
3030 const char *templates[] = {
3031 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10;",
3032 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10;",
3033 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10;",
3034 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10;",
3035 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10;",
3036 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10;",
3037 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10;",
3038 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10;",
3039 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10;",
3040 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10;",
3041 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10;",
3042 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10;",
3043 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10;",
3044 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10;",
3045 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10;",
3046 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10;" };
3047 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3048 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3049 return templates[alt];
3051 [(set_attr "type" "dsp32")])
3053 ;; Same as above, but initializing the accumulators and therefore a couple fewer
3054 ;; necessary operands.
3055 (define_insn "flag_macinitv2hi_parts"
3056 [(set (match_operand:V2HI 0 "register_operand" "=d")
3057 (unspec:V2HI [(vec_concat:V2HI
3059 (match_operand:V2HI 1 "register_operand" "d")
3060 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3063 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3065 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3066 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3067 (vec_select:HI (match_dup 2)
3068 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3069 (match_operand 7 "const_int_operand" "n")]
3070 UNSPEC_MAC_WITH_FLAG))
3071 (set (match_operand:V2PDI 8 "register_operand" "=e")
3072 (unspec:V2PDI [(vec_concat:V2HI
3073 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3074 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3076 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3077 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3079 UNSPEC_MAC_WITH_FLAG))]
3082 const char *templates[] = {
3083 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7;",
3084 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7;",
3085 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7;",
3086 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7;",
3087 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7;",
3088 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7;",
3089 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7;",
3090 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7;",
3091 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7;",
3092 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7;",
3093 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7;",
3094 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7;",
3095 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7;",
3096 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7;",
3097 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7;",
3098 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7;" };
3099 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3100 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3101 return templates[alt];
3103 [(set_attr "type" "dsp32")])
3105 (define_insn "flag_macinit1v2hi_parts"
3106 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3107 (unspec:V2PDI [(vec_concat:V2HI
3109 (match_operand:V2HI 1 "register_operand" "d")
3110 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3113 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3115 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3116 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3117 (vec_select:HI (match_dup 2)
3118 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3119 (match_operand 7 "const_int_operand" "n")]
3120 UNSPEC_MAC_WITH_FLAG))]
3123 const char *templates[] = {
3124 "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7;",
3125 "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7;",
3126 "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7;",
3127 "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7;",
3128 "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7;",
3129 "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7;",
3130 "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7;",
3131 "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7;",
3132 "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7;",
3133 "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7;",
3134 "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7;",
3135 "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7;",
3136 "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7;",
3137 "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7;",
3138 "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7;",
3139 "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7;" };
3140 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3141 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3142 return templates[alt];
3144 [(set_attr "type" "dsp32")])
3146 (define_insn "mulhisi_ll"
3147 [(set (match_operand:SI 0 "register_operand" "=d")
3148 (mult:SI (sign_extend:SI
3149 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3150 (parallel [(const_int 0)])))
3152 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3153 (parallel [(const_int 0)])))))]
3155 "%0 = %h1 * %h2 (IS);"
3156 [(set_attr "type" "dsp32")])
3158 (define_insn "mulhisi_lh"
3159 [(set (match_operand:SI 0 "register_operand" "=d")
3160 (mult:SI (sign_extend:SI
3161 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3162 (parallel [(const_int 0)])))
3164 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3165 (parallel [(const_int 1)])))))]
3167 "%0 = %h1 * %d2 (IS);"
3168 [(set_attr "type" "dsp32")])
3170 (define_insn "mulhisi_hl"
3171 [(set (match_operand:SI 0 "register_operand" "=d")
3172 (mult:SI (sign_extend:SI
3173 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3174 (parallel [(const_int 1)])))
3176 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3177 (parallel [(const_int 0)])))))]
3179 "%0 = %d1 * %h2 (IS);"
3180 [(set_attr "type" "dsp32")])
3182 (define_insn "mulhisi_hh"
3183 [(set (match_operand:SI 0 "register_operand" "=d")
3184 (mult:SI (sign_extend:SI
3185 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3186 (parallel [(const_int 1)])))
3188 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3189 (parallel [(const_int 1)])))))]
3191 "%0 = %d1 * %d2 (IS);"
3192 [(set_attr "type" "dsp32")])
3194 (define_insn "ssnegv2hi2"
3195 [(set (match_operand:V2HI 0 "register_operand" "=d")
3196 (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3199 [(set_attr "type" "dsp32")])
3201 (define_insn "absv2hi2"
3202 [(set (match_operand:V2HI 0 "register_operand" "=d")
3203 (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3206 [(set_attr "type" "dsp32")])
3210 (define_insn "ssashiftv2hi3"
3211 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3213 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3214 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3216 (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
3219 %0 = ASHIFT %1 BY %2 (V, S);
3220 %0 = %1 >>> %2 (V,S);
3221 %0 = %1 << %2 (V,S);"
3222 [(set_attr "type" "dsp32")])
3224 (define_insn "ssashifthi3"
3225 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3227 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3228 (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3230 (ss_ashift:HI (match_dup 1) (match_dup 2))))]
3233 %0 = ASHIFT %1 BY %2 (V, S);
3234 %0 = %1 >>> %2 (V,S);
3235 %0 = %1 << %2 (V,S);"
3236 [(set_attr "type" "dsp32")])
3238 (define_insn "lshiftv2hi3"
3239 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3241 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3242 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3244 (ashift:V2HI (match_dup 1) (match_dup 2))))]
3247 %0 = LSHIFT %1 BY %2 (V);
3250 [(set_attr "type" "dsp32")])
3252 (define_insn "lshifthi3"
3253 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3255 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3256 (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3258 (ashift:HI (match_dup 1) (match_dup 2))))]
3261 %0 = LSHIFT %1 BY %2 (V);
3264 [(set_attr "type" "dsp32")])