1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known
;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost
;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx
*uid_log_links
;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick
;
323 /* Reset to label_tick for each label. */
325 static int label_tick_ebb_start
;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode
;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid
;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
347 enum { UNDO_RTX
, UNDO_INT
, UNDO_MODE
} kind
;
348 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
349 union { rtx
*r
; int *i
; } where
;
352 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
353 num_undo says how many are currently recorded.
355 other_insn is nonzero if we have modified some other insn in the process
356 of working on subst_insn. It must be verified too. */
365 static struct undobuf undobuf
;
367 /* Number of times the pseudo being substituted for
368 was found and replaced. */
370 static int n_occurrences
;
372 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
374 unsigned HOST_WIDE_INT
,
375 unsigned HOST_WIDE_INT
*);
376 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
378 unsigned int, unsigned int *);
379 static void do_SUBST (rtx
*, rtx
);
380 static void do_SUBST_INT (int *, int);
381 static void init_reg_last (void);
382 static void setup_incoming_promotions (rtx
);
383 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
384 static int cant_combine_insn_p (rtx
);
385 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
386 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
387 static int contains_muldiv (rtx
);
388 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
389 static void undo_all (void);
390 static void undo_commit (void);
391 static rtx
*find_split_point (rtx
*, rtx
);
392 static rtx
subst (rtx
, rtx
, rtx
, int, int);
393 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
394 static rtx
simplify_if_then_else (rtx
);
395 static rtx
simplify_set (rtx
);
396 static rtx
simplify_logical (rtx
);
397 static rtx
expand_compound_operation (rtx
);
398 static const_rtx
expand_field_assignment (const_rtx
);
399 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
400 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
401 static rtx
extract_left_shift (rtx
, int);
402 static rtx
make_compound_operation (rtx
, enum rtx_code
);
403 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
404 unsigned HOST_WIDE_INT
*);
405 static rtx
canon_reg_for_combine (rtx
, rtx
);
406 static rtx
force_to_mode (rtx
, enum machine_mode
,
407 unsigned HOST_WIDE_INT
, int);
408 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
409 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
410 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
411 static rtx
make_field_assignment (rtx
);
412 static rtx
apply_distributive_law (rtx
);
413 static rtx
distribute_and_simplify_rtx (rtx
, int);
414 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
415 unsigned HOST_WIDE_INT
);
416 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
417 unsigned HOST_WIDE_INT
);
418 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
419 HOST_WIDE_INT
, enum machine_mode
, int *);
420 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
421 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
423 static int recog_for_combine (rtx
*, rtx
, rtx
*);
424 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
425 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
426 static void update_table_tick (rtx
);
427 static void record_value_for_reg (rtx
, rtx
, rtx
);
428 static void check_conversions (rtx
, rtx
);
429 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
430 static void record_dead_and_set_regs (rtx
);
431 static int get_last_value_validate (rtx
*, rtx
, int, int);
432 static rtx
get_last_value (const_rtx
);
433 static int use_crosses_set_p (const_rtx
, int);
434 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
435 static int reg_dead_at_p (rtx
, rtx
);
436 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
437 static int reg_bitfield_target_p (rtx
, rtx
);
438 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
439 static void distribute_links (rtx
);
440 static void mark_used_regs_combine (rtx
);
441 static void record_promoted_value (rtx
, rtx
);
442 static int unmentioned_reg_p_1 (rtx
*, void *);
443 static bool unmentioned_reg_p (rtx
, rtx
);
444 static void record_truncated_value (rtx
);
445 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
446 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
449 /* It is not safe to use ordinary gen_lowpart in combine.
450 See comments in gen_lowpart_for_combine. */
451 #undef RTL_HOOKS_GEN_LOWPART
452 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
454 /* Our implementation of gen_lowpart never emits a new pseudo. */
455 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
456 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
458 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
459 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
461 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
462 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
464 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
465 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
467 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
470 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
471 PATTERN can not be split. Otherwise, it returns an insn sequence.
472 This is a wrapper around split_insns which ensures that the
473 reg_stat vector is made larger if the splitter creates a new
477 combine_split_insns (rtx pattern
, rtx insn
)
482 ret
= split_insns (pattern
, insn
);
483 nregs
= max_reg_num ();
484 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
485 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
489 /* This is used by find_single_use to locate an rtx in LOC that
490 contains exactly one use of DEST, which is typically either a REG
491 or CC0. It returns a pointer to the innermost rtx expression
492 containing DEST. Appearances of DEST that are being used to
493 totally replace it are not counted. */
496 find_single_use_1 (rtx dest
, rtx
*loc
)
499 enum rtx_code code
= GET_CODE (x
);
517 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
518 of a REG that occupies all of the REG, the insn uses DEST if
519 it is mentioned in the destination or the source. Otherwise, we
520 need just check the source. */
521 if (GET_CODE (SET_DEST (x
)) != CC0
522 && GET_CODE (SET_DEST (x
)) != PC
523 && !REG_P (SET_DEST (x
))
524 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
525 && REG_P (SUBREG_REG (SET_DEST (x
)))
526 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
527 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
528 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
529 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
532 return find_single_use_1 (dest
, &SET_SRC (x
));
536 return find_single_use_1 (dest
, &XEXP (x
, 0));
542 /* If it wasn't one of the common cases above, check each expression and
543 vector of this code. Look for a unique usage of DEST. */
545 fmt
= GET_RTX_FORMAT (code
);
546 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
550 if (dest
== XEXP (x
, i
)
551 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
552 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
555 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
558 result
= this_result
;
559 else if (this_result
)
560 /* Duplicate usage. */
563 else if (fmt
[i
] == 'E')
567 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
569 if (XVECEXP (x
, i
, j
) == dest
571 && REG_P (XVECEXP (x
, i
, j
))
572 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
575 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
578 result
= this_result
;
579 else if (this_result
)
589 /* See if DEST, produced in INSN, is used only a single time in the
590 sequel. If so, return a pointer to the innermost rtx expression in which
593 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
595 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
596 care about REG_DEAD notes or LOG_LINKS.
598 Otherwise, we find the single use by finding an insn that has a
599 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
600 only referenced once in that insn, we know that it must be the first
601 and last insn referencing DEST. */
604 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
613 next
= NEXT_INSN (insn
);
615 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
618 result
= find_single_use_1 (dest
, &PATTERN (next
));
628 for (next
= next_nonnote_insn (insn
);
629 next
!= 0 && !LABEL_P (next
);
630 next
= next_nonnote_insn (next
))
631 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
633 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
634 if (XEXP (link
, 0) == insn
)
639 result
= find_single_use_1 (dest
, &PATTERN (next
));
649 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
650 insn. The substitution can be undone by undo_all. If INTO is already
651 set to NEWVAL, do not record this change. Because computing NEWVAL might
652 also call SUBST, we have to compute it before we put anything into
656 do_SUBST (rtx
*into
, rtx newval
)
661 if (oldval
== newval
)
664 /* We'd like to catch as many invalid transformations here as
665 possible. Unfortunately, there are way too many mode changes
666 that are perfectly valid, so we'd waste too much effort for
667 little gain doing the checks here. Focus on catching invalid
668 transformations involving integer constants. */
669 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
670 && GET_CODE (newval
) == CONST_INT
)
672 /* Sanity check that we're replacing oldval with a CONST_INT
673 that is a valid sign-extension for the original mode. */
674 gcc_assert (INTVAL (newval
)
675 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
677 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
678 CONST_INT is not valid, because after the replacement, the
679 original mode would be gone. Unfortunately, we can't tell
680 when do_SUBST is called to replace the operand thereof, so we
681 perform this test on oldval instead, checking whether an
682 invalid replacement took place before we got here. */
683 gcc_assert (!(GET_CODE (oldval
) == SUBREG
684 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
685 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
686 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
690 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
692 buf
= XNEW (struct undo
);
694 buf
->kind
= UNDO_RTX
;
696 buf
->old_contents
.r
= oldval
;
699 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
702 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
704 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
705 for the value of a HOST_WIDE_INT value (including CONST_INT) is
709 do_SUBST_INT (int *into
, int newval
)
714 if (oldval
== newval
)
718 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
720 buf
= XNEW (struct undo
);
722 buf
->kind
= UNDO_INT
;
724 buf
->old_contents
.i
= oldval
;
727 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
730 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
732 /* Similar to SUBST, but just substitute the mode. This is used when
733 changing the mode of a pseudo-register, so that any other
734 references to the entry in the regno_reg_rtx array will change as
738 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
741 enum machine_mode oldval
= GET_MODE (*into
);
743 if (oldval
== newval
)
747 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
749 buf
= XNEW (struct undo
);
751 buf
->kind
= UNDO_MODE
;
753 buf
->old_contents
.m
= oldval
;
754 adjust_reg_mode (*into
, newval
);
756 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
759 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
761 /* Subroutine of try_combine. Determine whether the combine replacement
762 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
763 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
764 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
765 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
766 function returns false, if the costs of all instructions can be
767 estimated, and the replacements are more expensive than the original
771 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
,
774 int i1_cost
, i2_cost
, i3_cost
;
775 int new_i2_cost
, new_i3_cost
;
776 int old_cost
, new_cost
;
778 /* Lookup the original insn_rtx_costs. */
779 i2_cost
= INSN_COST (i2
);
780 i3_cost
= INSN_COST (i3
);
784 i1_cost
= INSN_COST (i1
);
785 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
786 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
790 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
794 /* Calculate the replacement insn_rtx_costs. */
795 new_i3_cost
= insn_rtx_cost (newpat
);
798 new_i2_cost
= insn_rtx_cost (newi2pat
);
799 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
800 ? new_i2_cost
+ new_i3_cost
: 0;
804 new_cost
= new_i3_cost
;
808 if (undobuf
.other_insn
)
810 int old_other_cost
, new_other_cost
;
812 old_other_cost
= INSN_COST (undobuf
.other_insn
);
813 new_other_cost
= insn_rtx_cost (newotherpat
);
814 if (old_other_cost
> 0 && new_other_cost
> 0)
816 old_cost
+= old_other_cost
;
817 new_cost
+= new_other_cost
;
823 /* Disallow this recombination if both new_cost and old_cost are
824 greater than zero, and new_cost is greater than old cost. */
826 && new_cost
> old_cost
)
833 "rejecting combination of insns %d, %d and %d\n",
834 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
835 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
836 i1_cost
, i2_cost
, i3_cost
, old_cost
);
841 "rejecting combination of insns %d and %d\n",
842 INSN_UID (i2
), INSN_UID (i3
));
843 fprintf (dump_file
, "original costs %d + %d = %d\n",
844 i2_cost
, i3_cost
, old_cost
);
849 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
850 new_i2_cost
, new_i3_cost
, new_cost
);
853 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
859 /* Update the uid_insn_cost array with the replacement costs. */
860 INSN_COST (i2
) = new_i2_cost
;
861 INSN_COST (i3
) = new_i3_cost
;
869 /* Delete any insns that copy a register to itself. */
872 delete_noop_moves (void)
879 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
881 next
= NEXT_INSN (insn
);
882 if (INSN_P (insn
) && noop_move_p (insn
))
886 /* If we're about to remove the first insn of a libcall
887 then move the libcall note to the next real insn and
888 update the retval note. */
889 if ((note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
))
890 && XEXP (note
, 0) != insn
)
892 rtx new_libcall_insn
= next_real_insn (insn
);
893 rtx retval_note
= find_reg_note (XEXP (note
, 0),
894 REG_RETVAL
, NULL_RTX
);
895 REG_NOTES (new_libcall_insn
)
896 = gen_rtx_INSN_LIST (REG_LIBCALL
, XEXP (note
, 0),
897 REG_NOTES (new_libcall_insn
));
898 XEXP (retval_note
, 0) = new_libcall_insn
;
902 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
904 delete_insn_and_edges (insn
);
911 /* Fill in log links field for all insns. */
914 create_log_links (void)
918 struct df_ref
**def_vec
, **use_vec
;
920 next_use
= XCNEWVEC (rtx
, max_reg_num ());
922 /* Pass through each block from the end, recording the uses of each
923 register and establishing log links when def is encountered.
924 Note that we do not clear next_use array in order to save time,
925 so we have to test whether the use is in the same basic block as def.
927 There are a few cases below when we do not consider the definition or
928 usage -- these are taken from original flow.c did. Don't ask me why it is
929 done this way; I don't know and if it works, I don't want to know. */
933 FOR_BB_INSNS_REVERSE (bb
, insn
)
938 /* Log links are created only once. */
939 gcc_assert (!LOG_LINKS (insn
));
941 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
943 struct df_ref
*def
= *def_vec
;
944 int regno
= DF_REF_REGNO (def
);
947 if (!next_use
[regno
])
950 /* Do not consider if it is pre/post modification in MEM. */
951 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
954 /* Do not make the log link for frame pointer. */
955 if ((regno
== FRAME_POINTER_REGNUM
956 && (! reload_completed
|| frame_pointer_needed
))
957 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
958 || (regno
== HARD_FRAME_POINTER_REGNUM
959 && (! reload_completed
|| frame_pointer_needed
))
961 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
962 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
967 use_insn
= next_use
[regno
];
968 if (BLOCK_FOR_INSN (use_insn
) == bb
)
972 We don't build a LOG_LINK for hard registers contained
973 in ASM_OPERANDs. If these registers get replaced,
974 we might wind up changing the semantics of the insn,
975 even if reload can make what appear to be valid
976 assignments later. */
977 if (regno
>= FIRST_PSEUDO_REGISTER
978 || asm_noperands (PATTERN (use_insn
)) < 0)
980 /* Don't add duplicate links between instructions. */
982 for (links
= LOG_LINKS (use_insn
); links
;
983 links
= XEXP (links
, 1))
984 if (insn
== XEXP (links
, 0))
988 LOG_LINKS (use_insn
) =
989 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
992 next_use
[regno
] = NULL_RTX
;
995 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
997 struct df_ref
*use
= *use_vec
;
998 int regno
= DF_REF_REGNO (use
);
1000 /* Do not consider the usage of the stack pointer
1001 by function call. */
1002 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1005 next_use
[regno
] = insn
;
1013 /* Clear LOG_LINKS fields of insns. */
1016 clear_log_links (void)
1020 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1022 free_INSN_LIST_list (&LOG_LINKS (insn
));
1028 /* Main entry point for combiner. F is the first insn of the function.
1029 NREGS is the first unused pseudo-reg number.
1031 Return nonzero if the combiner has turned an indirect jump
1032 instruction into a direct jump. */
1034 combine_instructions (rtx f
, unsigned int nregs
)
1040 rtx links
, nextlinks
;
1043 int new_direct_jump_p
= 0;
1045 for (first
= f
; first
&& !INSN_P (first
); )
1046 first
= NEXT_INSN (first
);
1050 combine_attempts
= 0;
1053 combine_successes
= 0;
1055 rtl_hooks
= combine_rtl_hooks
;
1057 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1059 init_recog_no_volatile ();
1061 /* Allocate array for insn info. */
1062 max_uid_known
= get_max_uid ();
1063 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1064 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1066 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1068 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1069 problems when, for example, we have j <<= 1 in a loop. */
1071 nonzero_sign_valid
= 0;
1073 /* Scan all SETs and see if we can deduce anything about what
1074 bits are known to be zero for some registers and how many copies
1075 of the sign bit are known to exist for those registers.
1077 Also set any known values so that we can use it while searching
1078 for what bits are known to be set. */
1080 label_tick
= label_tick_ebb_start
= 1;
1082 setup_incoming_promotions (first
);
1084 create_log_links ();
1085 FOR_EACH_BB (this_basic_block
)
1090 FOR_BB_INSNS (this_basic_block
, insn
)
1091 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1093 subst_low_luid
= DF_INSN_LUID (insn
);
1096 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1098 record_dead_and_set_regs (insn
);
1101 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1102 if (REG_NOTE_KIND (links
) == REG_INC
)
1103 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1107 /* Record the current insn_rtx_cost of this instruction. */
1108 if (NONJUMP_INSN_P (insn
))
1109 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
));
1111 fprintf(dump_file
, "insn_cost %d: %d\n",
1112 INSN_UID (insn
), INSN_COST (insn
));
1114 else if (LABEL_P (insn
))
1115 label_tick_ebb_start
= label_tick
;
1118 nonzero_sign_valid
= 1;
1120 /* Now scan all the insns in forward order. */
1122 label_tick
= label_tick_ebb_start
= 1;
1124 setup_incoming_promotions (first
);
1126 FOR_EACH_BB (this_basic_block
)
1131 for (insn
= BB_HEAD (this_basic_block
);
1132 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1133 insn
= next
? next
: NEXT_INSN (insn
))
1138 /* See if we know about function return values before this
1139 insn based upon SUBREG flags. */
1140 check_conversions (insn
, PATTERN (insn
));
1142 /* Try this insn with each insn it links back to. */
1144 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1145 if ((next
= try_combine (insn
, XEXP (links
, 0),
1146 NULL_RTX
, &new_direct_jump_p
)) != 0)
1149 /* Try each sequence of three linked insns ending with this one. */
1151 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1153 rtx link
= XEXP (links
, 0);
1155 /* If the linked insn has been replaced by a note, then there
1156 is no point in pursuing this chain any further. */
1160 for (nextlinks
= LOG_LINKS (link
);
1162 nextlinks
= XEXP (nextlinks
, 1))
1163 if ((next
= try_combine (insn
, link
,
1164 XEXP (nextlinks
, 0),
1165 &new_direct_jump_p
)) != 0)
1170 /* Try to combine a jump insn that uses CC0
1171 with a preceding insn that sets CC0, and maybe with its
1172 logical predecessor as well.
1173 This is how we make decrement-and-branch insns.
1174 We need this special code because data flow connections
1175 via CC0 do not get entered in LOG_LINKS. */
1178 && (prev
= prev_nonnote_insn (insn
)) != 0
1179 && NONJUMP_INSN_P (prev
)
1180 && sets_cc0_p (PATTERN (prev
)))
1182 if ((next
= try_combine (insn
, prev
,
1183 NULL_RTX
, &new_direct_jump_p
)) != 0)
1186 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1187 nextlinks
= XEXP (nextlinks
, 1))
1188 if ((next
= try_combine (insn
, prev
,
1189 XEXP (nextlinks
, 0),
1190 &new_direct_jump_p
)) != 0)
1194 /* Do the same for an insn that explicitly references CC0. */
1195 if (NONJUMP_INSN_P (insn
)
1196 && (prev
= prev_nonnote_insn (insn
)) != 0
1197 && NONJUMP_INSN_P (prev
)
1198 && sets_cc0_p (PATTERN (prev
))
1199 && GET_CODE (PATTERN (insn
)) == SET
1200 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1202 if ((next
= try_combine (insn
, prev
,
1203 NULL_RTX
, &new_direct_jump_p
)) != 0)
1206 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1207 nextlinks
= XEXP (nextlinks
, 1))
1208 if ((next
= try_combine (insn
, prev
,
1209 XEXP (nextlinks
, 0),
1210 &new_direct_jump_p
)) != 0)
1214 /* Finally, see if any of the insns that this insn links to
1215 explicitly references CC0. If so, try this insn, that insn,
1216 and its predecessor if it sets CC0. */
1217 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1218 if (NONJUMP_INSN_P (XEXP (links
, 0))
1219 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1220 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1221 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1222 && NONJUMP_INSN_P (prev
)
1223 && sets_cc0_p (PATTERN (prev
))
1224 && (next
= try_combine (insn
, XEXP (links
, 0),
1225 prev
, &new_direct_jump_p
)) != 0)
1229 /* Try combining an insn with two different insns whose results it
1231 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1232 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1233 nextlinks
= XEXP (nextlinks
, 1))
1234 if ((next
= try_combine (insn
, XEXP (links
, 0),
1235 XEXP (nextlinks
, 0),
1236 &new_direct_jump_p
)) != 0)
1239 /* Try this insn with each REG_EQUAL note it links back to. */
1240 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1243 rtx temp
= XEXP (links
, 0);
1244 if ((set
= single_set (temp
)) != 0
1245 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1246 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1247 /* Avoid using a register that may already been marked
1248 dead by an earlier instruction. */
1249 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1250 && (GET_MODE (note
) == VOIDmode
1251 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1252 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1254 /* Temporarily replace the set's source with the
1255 contents of the REG_EQUAL note. The insn will
1256 be deleted or recognized by try_combine. */
1257 rtx orig
= SET_SRC (set
);
1258 SET_SRC (set
) = note
;
1260 i2mod_old_rhs
= copy_rtx (orig
);
1261 i2mod_new_rhs
= copy_rtx (note
);
1262 next
= try_combine (insn
, i2mod
, NULL_RTX
,
1263 &new_direct_jump_p
);
1267 SET_SRC (set
) = orig
;
1272 record_dead_and_set_regs (insn
);
1277 else if (LABEL_P (insn
))
1278 label_tick_ebb_start
= label_tick
;
1284 new_direct_jump_p
|= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links
);
1289 free (uid_insn_cost
);
1290 VEC_free (reg_stat_type
, heap
, reg_stat
);
1293 struct undo
*undo
, *next
;
1294 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1302 total_attempts
+= combine_attempts
;
1303 total_merges
+= combine_merges
;
1304 total_extras
+= combine_extras
;
1305 total_successes
+= combine_successes
;
1307 nonzero_sign_valid
= 0;
1308 rtl_hooks
= general_rtl_hooks
;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p
;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i
= 0; VEC_iterate (reg_stat_type
, reg_stat
, i
, p
); ++i
)
1325 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first
)
1334 bool strictly_local
= false;
1336 if (!targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
1339 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1340 arg
= TREE_CHAIN (arg
))
1342 rtx reg
= DECL_INCOMING_RTL (arg
);
1344 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1346 /* Only continue if the incoming argument is in a register. */
1350 /* Determine, if possible, whether all call sites of the current
1351 function lie within the current compilation unit. (This does
1352 take into account the exporting of a function via taking its
1353 address, and so forth.) */
1354 if (flag_unit_at_a_time
)
1355 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1357 /* The mode and signedness of the argument before any promotions happen
1358 (equal to the mode of the pseudo holding it at that stage). */
1359 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1360 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1362 /* The mode and signedness of the argument after any source language and
1363 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1364 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1365 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1367 /* The mode and signedness of the argument as it is actually passed,
1368 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1369 mode3
= promote_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
, 1);
1371 /* The mode of the register in which the argument is being passed. */
1372 mode4
= GET_MODE (reg
);
1374 /* Eliminate sign extensions in the callee when possible. Only
1376 (a) a mode promotion has occurred;
1377 (b) the mode of the register is the same as the mode of
1378 the argument as it is passed; and
1379 (c) the signedness does not change across any of the promotions; and
1380 (d) when no language-level promotions (which we cannot guarantee
1381 will have been done by an external caller) are necessary,
1382 unless we know that this function is only ever called from
1383 the current compilation unit -- all of whose call sites will
1384 do the mode1 --> mode2 promotion. */
1388 && (mode1
== mode2
|| strictly_local
))
1390 /* Record that the value was promoted from mode1 to mode3,
1391 so that any sign extension at the head of the current
1392 function may be eliminated. */
1394 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1395 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1396 record_value_for_reg (reg
, first
, x
);
1401 /* Called via note_stores. If X is a pseudo that is narrower than
1402 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1404 If we are setting only a portion of X and we can't figure out what
1405 portion, assume all bits will be used since we don't know what will
1408 Similarly, set how many bits of X are known to be copies of the sign bit
1409 at all locations in the function. This is the smallest number implied
1413 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1415 rtx insn
= (rtx
) data
;
1419 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1420 /* If this register is undefined at the start of the file, we can't
1421 say what its contents were. */
1422 && ! REGNO_REG_SET_P
1423 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1424 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1426 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1428 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1430 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1431 rsp
->sign_bit_copies
= 1;
1435 /* If this register is being initialized using itself, and the
1436 register is uninitialized in this basic block, and there are
1437 no LOG_LINKS which set the register, then part of the
1438 register is uninitialized. In that case we can't assume
1439 anything about the number of nonzero bits.
1441 ??? We could do better if we checked this in
1442 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1443 could avoid making assumptions about the insn which initially
1444 sets the register, while still using the information in other
1445 insns. We would have to be careful to check every insn
1446 involved in the combination. */
1449 && reg_referenced_p (x
, PATTERN (insn
))
1450 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1455 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1457 if (dead_or_set_p (XEXP (link
, 0), x
))
1462 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1463 rsp
->sign_bit_copies
= 1;
1468 /* If this is a complex assignment, see if we can convert it into a
1469 simple assignment. */
1470 set
= expand_field_assignment (set
);
1472 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1473 set what we know about X. */
1475 if (SET_DEST (set
) == x
1476 || (GET_CODE (SET_DEST (set
)) == SUBREG
1477 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1478 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1479 && SUBREG_REG (SET_DEST (set
)) == x
))
1481 rtx src
= SET_SRC (set
);
1483 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1484 /* If X is narrower than a word and SRC is a non-negative
1485 constant that would appear negative in the mode of X,
1486 sign-extend it for use in reg_stat[].nonzero_bits because some
1487 machines (maybe most) will actually do the sign-extension
1488 and this is the conservative approach.
1490 ??? For 2.5, try to tighten up the MD files in this regard
1491 instead of this kludge. */
1493 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1494 && GET_CODE (src
) == CONST_INT
1496 && 0 != (INTVAL (src
)
1497 & ((HOST_WIDE_INT
) 1
1498 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1499 src
= GEN_INT (INTVAL (src
)
1500 | ((HOST_WIDE_INT
) (-1)
1501 << GET_MODE_BITSIZE (GET_MODE (x
))));
1504 /* Don't call nonzero_bits if it cannot change anything. */
1505 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1506 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1507 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1508 if (rsp
->sign_bit_copies
== 0
1509 || rsp
->sign_bit_copies
> num
)
1510 rsp
->sign_bit_copies
= num
;
1514 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1515 rsp
->sign_bit_copies
= 1;
1520 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1521 insns that were previously combined into I3 or that will be combined
1522 into the merger of INSN and I3.
1524 Return 0 if the combination is not allowed for any reason.
1526 If the combination is allowed, *PDEST will be set to the single
1527 destination of INSN and *PSRC to the single source, and this function
1531 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1532 rtx
*pdest
, rtx
*psrc
)
1541 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1542 && next_active_insn (succ
) == i3
)
1543 : next_active_insn (insn
) == i3
);
1545 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1546 or a PARALLEL consisting of such a SET and CLOBBERs.
1548 If INSN has CLOBBER parallel parts, ignore them for our processing.
1549 By definition, these happen during the execution of the insn. When it
1550 is merged with another insn, all bets are off. If they are, in fact,
1551 needed and aren't also supplied in I3, they may be added by
1552 recog_for_combine. Otherwise, it won't match.
1554 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1557 Get the source and destination of INSN. If more than one, can't
1560 if (GET_CODE (PATTERN (insn
)) == SET
)
1561 set
= PATTERN (insn
);
1562 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1563 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1565 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1567 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1570 switch (GET_CODE (elt
))
1572 /* This is important to combine floating point insns
1573 for the SH4 port. */
1575 /* Combining an isolated USE doesn't make sense.
1576 We depend here on combinable_i3pat to reject them. */
1577 /* The code below this loop only verifies that the inputs of
1578 the SET in INSN do not change. We call reg_set_between_p
1579 to verify that the REG in the USE does not change between
1581 If the USE in INSN was for a pseudo register, the matching
1582 insn pattern will likely match any register; combining this
1583 with any other USE would only be safe if we knew that the
1584 used registers have identical values, or if there was
1585 something to tell them apart, e.g. different modes. For
1586 now, we forgo such complicated tests and simply disallow
1587 combining of USES of pseudo registers with any other USE. */
1588 if (REG_P (XEXP (elt
, 0))
1589 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1591 rtx i3pat
= PATTERN (i3
);
1592 int i
= XVECLEN (i3pat
, 0) - 1;
1593 unsigned int regno
= REGNO (XEXP (elt
, 0));
1597 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1599 if (GET_CODE (i3elt
) == USE
1600 && REG_P (XEXP (i3elt
, 0))
1601 && (REGNO (XEXP (i3elt
, 0)) == regno
1602 ? reg_set_between_p (XEXP (elt
, 0),
1603 PREV_INSN (insn
), i3
)
1604 : regno
>= FIRST_PSEUDO_REGISTER
))
1611 /* We can ignore CLOBBERs. */
1616 /* Ignore SETs whose result isn't used but not those that
1617 have side-effects. */
1618 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1619 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1620 || INTVAL (XEXP (note
, 0)) <= 0)
1621 && ! side_effects_p (elt
))
1624 /* If we have already found a SET, this is a second one and
1625 so we cannot combine with this insn. */
1633 /* Anything else means we can't combine. */
1639 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1640 so don't do anything with it. */
1641 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1650 set
= expand_field_assignment (set
);
1651 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1653 /* Don't eliminate a store in the stack pointer. */
1654 if (dest
== stack_pointer_rtx
1655 /* Don't combine with an insn that sets a register to itself if it has
1656 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1657 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1658 /* Can't merge an ASM_OPERANDS. */
1659 || GET_CODE (src
) == ASM_OPERANDS
1660 /* Can't merge a function call. */
1661 || GET_CODE (src
) == CALL
1662 /* Don't eliminate a function call argument. */
1664 && (find_reg_fusage (i3
, USE
, dest
)
1666 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1667 && global_regs
[REGNO (dest
)])))
1668 /* Don't substitute into an incremented register. */
1669 || FIND_REG_INC_NOTE (i3
, dest
)
1670 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1671 /* Don't substitute into a non-local goto, this confuses CFG. */
1672 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1674 /* Don't combine the end of a libcall into anything. */
1675 /* ??? This gives worse code, and appears to be unnecessary, since no
1676 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1677 use REG_RETVAL notes for noconflict blocks, but other code here
1678 makes sure that those insns don't disappear. */
1679 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1681 /* Make sure that DEST is not used after SUCC but before I3. */
1682 || (succ
&& ! all_adjacent
1683 && reg_used_between_p (dest
, succ
, i3
))
1684 /* Make sure that the value that is to be substituted for the register
1685 does not use any registers whose values alter in between. However,
1686 If the insns are adjacent, a use can't cross a set even though we
1687 think it might (this can happen for a sequence of insns each setting
1688 the same destination; last_set of that register might point to
1689 a NOTE). If INSN has a REG_EQUIV note, the register is always
1690 equivalent to the memory so the substitution is valid even if there
1691 are intervening stores. Also, don't move a volatile asm or
1692 UNSPEC_VOLATILE across any other insns. */
1695 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1696 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1697 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1698 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1699 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1700 better register allocation by not doing the combine. */
1701 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1702 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1703 /* Don't combine across a CALL_INSN, because that would possibly
1704 change whether the life span of some REGs crosses calls or not,
1705 and it is a pain to update that information.
1706 Exception: if source is a constant, moving it later can't hurt.
1707 Accept that as a special case. */
1708 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1711 /* DEST must either be a REG or CC0. */
1714 /* If register alignment is being enforced for multi-word items in all
1715 cases except for parameters, it is possible to have a register copy
1716 insn referencing a hard register that is not allowed to contain the
1717 mode being copied and which would not be valid as an operand of most
1718 insns. Eliminate this problem by not combining with such an insn.
1720 Also, on some machines we don't want to extend the life of a hard
1724 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1725 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1726 /* Don't extend the life of a hard register unless it is
1727 user variable (if we have few registers) or it can't
1728 fit into the desired register (meaning something special
1730 Also avoid substituting a return register into I3, because
1731 reload can't handle a conflict with constraints of other
1733 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1734 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1737 else if (GET_CODE (dest
) != CC0
)
1741 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1742 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1743 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1745 /* Don't substitute for a register intended as a clobberable
1747 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1748 if (rtx_equal_p (reg
, dest
))
1751 /* If the clobber represents an earlyclobber operand, we must not
1752 substitute an expression containing the clobbered register.
1753 As we do not analyze the constraint strings here, we have to
1754 make the conservative assumption. However, if the register is
1755 a fixed hard reg, the clobber cannot represent any operand;
1756 we leave it up to the machine description to either accept or
1757 reject use-and-clobber patterns. */
1759 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1760 || !fixed_regs
[REGNO (reg
)])
1761 if (reg_overlap_mentioned_p (reg
, src
))
1765 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1766 or not), reject, unless nothing volatile comes between it and I3 */
1768 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1770 /* Make sure succ doesn't contain a volatile reference. */
1771 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1774 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1775 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1779 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1780 to be an explicit register variable, and was chosen for a reason. */
1782 if (GET_CODE (src
) == ASM_OPERANDS
1783 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1786 /* If there are any volatile insns between INSN and I3, reject, because
1787 they might affect machine state. */
1789 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1790 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1793 /* If INSN contains an autoincrement or autodecrement, make sure that
1794 register is not used between there and I3, and not already used in
1795 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1796 Also insist that I3 not be a jump; if it were one
1797 and the incremented register were spilled, we would lose. */
1800 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1801 if (REG_NOTE_KIND (link
) == REG_INC
1803 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1804 || (pred
!= NULL_RTX
1805 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1806 || (succ
!= NULL_RTX
1807 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1808 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1813 /* Don't combine an insn that follows a CC0-setting insn.
1814 An insn that uses CC0 must not be separated from the one that sets it.
1815 We do, however, allow I2 to follow a CC0-setting insn if that insn
1816 is passed as I1; in that case it will be deleted also.
1817 We also allow combining in this case if all the insns are adjacent
1818 because that would leave the two CC0 insns adjacent as well.
1819 It would be more logical to test whether CC0 occurs inside I1 or I2,
1820 but that would be much slower, and this ought to be equivalent. */
1822 p
= prev_nonnote_insn (insn
);
1823 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1828 /* If we get here, we have passed all the tests and the combination is
1837 /* LOC is the location within I3 that contains its pattern or the component
1838 of a PARALLEL of the pattern. We validate that it is valid for combining.
1840 One problem is if I3 modifies its output, as opposed to replacing it
1841 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1842 so would produce an insn that is not equivalent to the original insns.
1846 (set (reg:DI 101) (reg:DI 100))
1847 (set (subreg:SI (reg:DI 101) 0) <foo>)
1849 This is NOT equivalent to:
1851 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1852 (set (reg:DI 101) (reg:DI 100))])
1854 Not only does this modify 100 (in which case it might still be valid
1855 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1857 We can also run into a problem if I2 sets a register that I1
1858 uses and I1 gets directly substituted into I3 (not via I2). In that
1859 case, we would be getting the wrong value of I2DEST into I3, so we
1860 must reject the combination. This case occurs when I2 and I1 both
1861 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1862 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1863 of a SET must prevent combination from occurring.
1865 Before doing the above check, we first try to expand a field assignment
1866 into a set of logical operations.
1868 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1869 we place a register that is both set and used within I3. If more than one
1870 such register is detected, we fail.
1872 Return 1 if the combination is valid, zero otherwise. */
1875 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1876 int i1_not_in_src
, rtx
*pi3dest_killed
)
1880 if (GET_CODE (x
) == SET
)
1883 rtx dest
= SET_DEST (set
);
1884 rtx src
= SET_SRC (set
);
1885 rtx inner_dest
= dest
;
1888 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1889 || GET_CODE (inner_dest
) == SUBREG
1890 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1891 inner_dest
= XEXP (inner_dest
, 0);
1893 /* Check for the case where I3 modifies its output, as discussed
1894 above. We don't want to prevent pseudos from being combined
1895 into the address of a MEM, so only prevent the combination if
1896 i1 or i2 set the same MEM. */
1897 if ((inner_dest
!= dest
&&
1898 (!MEM_P (inner_dest
)
1899 || rtx_equal_p (i2dest
, inner_dest
)
1900 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1901 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1902 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1904 /* This is the same test done in can_combine_p except we can't test
1905 all_adjacent; we don't have to, since this instruction will stay
1906 in place, thus we are not considering increasing the lifetime of
1909 Also, if this insn sets a function argument, combining it with
1910 something that might need a spill could clobber a previous
1911 function argument; the all_adjacent test in can_combine_p also
1912 checks this; here, we do a more specific test for this case. */
1914 || (REG_P (inner_dest
)
1915 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1916 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1917 GET_MODE (inner_dest
))))
1918 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1921 /* If DEST is used in I3, it is being killed in this insn, so
1922 record that for later. We have to consider paradoxical
1923 subregs here, since they kill the whole register, but we
1924 ignore partial subregs, STRICT_LOW_PART, etc.
1925 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1926 STACK_POINTER_REGNUM, since these are always considered to be
1927 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1929 if (GET_CODE (subdest
) == SUBREG
1930 && (GET_MODE_SIZE (GET_MODE (subdest
))
1931 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
1932 subdest
= SUBREG_REG (subdest
);
1935 && reg_referenced_p (subdest
, PATTERN (i3
))
1936 && REGNO (subdest
) != FRAME_POINTER_REGNUM
1937 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1938 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
1940 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1941 && (REGNO (subdest
) != ARG_POINTER_REGNUM
1942 || ! fixed_regs
[REGNO (subdest
)])
1944 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
1946 if (*pi3dest_killed
)
1949 *pi3dest_killed
= subdest
;
1953 else if (GET_CODE (x
) == PARALLEL
)
1957 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1958 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1959 i1_not_in_src
, pi3dest_killed
))
1966 /* Return 1 if X is an arithmetic expression that contains a multiplication
1967 and division. We don't count multiplications by powers of two here. */
1970 contains_muldiv (rtx x
)
1972 switch (GET_CODE (x
))
1974 case MOD
: case DIV
: case UMOD
: case UDIV
:
1978 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1979 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1982 return contains_muldiv (XEXP (x
, 0))
1983 || contains_muldiv (XEXP (x
, 1));
1986 return contains_muldiv (XEXP (x
, 0));
1992 /* Determine whether INSN can be used in a combination. Return nonzero if
1993 not. This is used in try_combine to detect early some cases where we
1994 can't perform combinations. */
1997 cant_combine_insn_p (rtx insn
)
2002 /* If this isn't really an insn, we can't do anything.
2003 This can occur when flow deletes an insn that it has merged into an
2004 auto-increment address. */
2005 if (! INSN_P (insn
))
2008 /* Never combine loads and stores involving hard regs that are likely
2009 to be spilled. The register allocator can usually handle such
2010 reg-reg moves by tying. If we allow the combiner to make
2011 substitutions of likely-spilled regs, reload might die.
2012 As an exception, we allow combinations involving fixed regs; these are
2013 not available to the register allocator so there's no risk involved. */
2015 set
= single_set (insn
);
2018 src
= SET_SRC (set
);
2019 dest
= SET_DEST (set
);
2020 if (GET_CODE (src
) == SUBREG
)
2021 src
= SUBREG_REG (src
);
2022 if (GET_CODE (dest
) == SUBREG
)
2023 dest
= SUBREG_REG (dest
);
2024 if (REG_P (src
) && REG_P (dest
)
2025 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
2026 && ! fixed_regs
[REGNO (src
)]
2027 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
2028 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
2029 && ! fixed_regs
[REGNO (dest
)]
2030 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
2036 struct likely_spilled_retval_info
2038 unsigned regno
, nregs
;
2042 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2043 hard registers that are known to be written to / clobbered in full. */
2045 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2047 struct likely_spilled_retval_info
*info
= data
;
2048 unsigned regno
, nregs
;
2051 if (!REG_P (XEXP (set
, 0)))
2054 if (regno
>= info
->regno
+ info
->nregs
)
2056 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2057 if (regno
+ nregs
<= info
->regno
)
2059 new_mask
= (2U << (nregs
- 1)) - 1;
2060 if (regno
< info
->regno
)
2061 new_mask
>>= info
->regno
- regno
;
2063 new_mask
<<= regno
- info
->regno
;
2064 info
->mask
&= ~new_mask
;
2067 /* Return nonzero iff part of the return value is live during INSN, and
2068 it is likely spilled. This can happen when more than one insn is needed
2069 to copy the return value, e.g. when we consider to combine into the
2070 second copy insn for a complex value. */
2073 likely_spilled_retval_p (rtx insn
)
2075 rtx use
= BB_END (this_basic_block
);
2077 unsigned regno
, nregs
;
2078 /* We assume here that no machine mode needs more than
2079 32 hard registers when the value overlaps with a register
2080 for which FUNCTION_VALUE_REGNO_P is true. */
2082 struct likely_spilled_retval_info info
;
2084 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2086 reg
= XEXP (PATTERN (use
), 0);
2087 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
2089 regno
= REGNO (reg
);
2090 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2093 mask
= (2U << (nregs
- 1)) - 1;
2095 /* Disregard parts of the return value that are set later. */
2099 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2101 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2104 /* Check if any of the (probably) live return value registers is
2109 if ((mask
& 1 << nregs
)
2110 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
2116 /* Adjust INSN after we made a change to its destination.
2118 Changing the destination can invalidate notes that say something about
2119 the results of the insn and a LOG_LINK pointing to the insn. */
2122 adjust_for_new_dest (rtx insn
)
2124 /* For notes, be conservative and simply remove them. */
2125 remove_reg_equal_equiv_notes (insn
);
2127 /* The new insn will have a destination that was previously the destination
2128 of an insn just above it. Call distribute_links to make a LOG_LINK from
2129 the next use of that destination. */
2130 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2132 df_insn_rescan (insn
);
2135 /* Return TRUE if combine can reuse reg X in mode MODE.
2136 ADDED_SETS is nonzero if the original set is still required. */
2138 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2146 /* Allow hard registers if the new mode is legal, and occupies no more
2147 registers than the old mode. */
2148 if (regno
< FIRST_PSEUDO_REGISTER
)
2149 return (HARD_REGNO_MODE_OK (regno
, mode
)
2150 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2151 >= hard_regno_nregs
[regno
][mode
]));
2153 /* Or a pseudo that is only used once. */
2154 return (REG_N_SETS (regno
) == 1 && !added_sets
2155 && !REG_USERVAR_P (x
));
2159 /* Check whether X, the destination of a set, refers to part of
2160 the register specified by REG. */
2163 reg_subword_p (rtx x
, rtx reg
)
2165 /* Check that reg is an integer mode register. */
2166 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2169 if (GET_CODE (x
) == STRICT_LOW_PART
2170 || GET_CODE (x
) == ZERO_EXTRACT
)
2173 return GET_CODE (x
) == SUBREG
2174 && SUBREG_REG (x
) == reg
2175 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2179 /* Try to combine the insns I1 and I2 into I3.
2180 Here I1 and I2 appear earlier than I3.
2181 I1 can be zero; then we combine just I2 into I3.
2183 If we are combining three insns and the resulting insn is not recognized,
2184 try splitting it into two insns. If that happens, I2 and I3 are retained
2185 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2188 Return 0 if the combination does not work. Then nothing is changed.
2189 If we did the combination, return the insn at which combine should
2192 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2193 new direct jump instruction. */
2196 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
2198 /* New patterns for I3 and I2, respectively. */
2199 rtx newpat
, newi2pat
= 0;
2200 rtvec newpat_vec_with_clobbers
= 0;
2201 int substed_i2
= 0, substed_i1
= 0;
2202 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2203 int added_sets_1
, added_sets_2
;
2204 /* Total number of SETs to put into I3. */
2206 /* Nonzero if I2's body now appears in I3. */
2208 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2209 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2210 /* Contains I3 if the destination of I3 is used in its source, which means
2211 that the old life of I3 is being killed. If that usage is placed into
2212 I2 and not in I3, a REG_DEAD note must be made. */
2213 rtx i3dest_killed
= 0;
2214 /* SET_DEST and SET_SRC of I2 and I1. */
2215 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
2216 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2217 rtx i1pat
= 0, i2pat
= 0;
2218 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2219 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2220 int i2dest_killed
= 0, i1dest_killed
= 0;
2221 int i1_feeds_i3
= 0;
2222 /* Notes that must be added to REG_NOTES in I3 and I2. */
2223 rtx new_i3_notes
, new_i2_notes
;
2224 /* Notes that we substituted I3 into I2 instead of the normal case. */
2225 int i3_subst_into_i2
= 0;
2226 /* Notes that I1, I2 or I3 is a MULT operation. */
2234 rtx new_other_notes
;
2237 /* Exit early if one of the insns involved can't be used for
2239 if (cant_combine_insn_p (i3
)
2240 || cant_combine_insn_p (i2
)
2241 || (i1
&& cant_combine_insn_p (i1
))
2242 || likely_spilled_retval_p (i3
)
2243 /* We also can't do anything if I3 has a
2244 REG_LIBCALL note since we don't want to disrupt the contiguity of a
2247 /* ??? This gives worse code, and appears to be unnecessary, since no
2248 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
2249 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
2255 undobuf
.other_insn
= 0;
2257 /* Reset the hard register usage information. */
2258 CLEAR_HARD_REG_SET (newpat_used_regs
);
2260 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2261 code below, set I1 to be the earlier of the two insns. */
2262 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2263 temp
= i1
, i1
= i2
, i2
= temp
;
2265 added_links_insn
= 0;
2267 /* First check for one important special-case that the code below will
2268 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2269 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2270 we may be able to replace that destination with the destination of I3.
2271 This occurs in the common code where we compute both a quotient and
2272 remainder into a structure, in which case we want to do the computation
2273 directly into the structure to avoid register-register copies.
2275 Note that this case handles both multiple sets in I2 and also
2276 cases where I2 has a number of CLOBBER or PARALLELs.
2278 We make very conservative checks below and only try to handle the
2279 most common cases of this. For example, we only handle the case
2280 where I2 and I3 are adjacent to avoid making difficult register
2283 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2284 && REG_P (SET_SRC (PATTERN (i3
)))
2285 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2286 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2287 && GET_CODE (PATTERN (i2
)) == PARALLEL
2288 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2289 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2290 below would need to check what is inside (and reg_overlap_mentioned_p
2291 doesn't support those codes anyway). Don't allow those destinations;
2292 the resulting insn isn't likely to be recognized anyway. */
2293 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2294 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2295 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2296 SET_DEST (PATTERN (i3
)))
2297 && next_real_insn (i2
) == i3
)
2299 rtx p2
= PATTERN (i2
);
2301 /* Make sure that the destination of I3,
2302 which we are going to substitute into one output of I2,
2303 is not used within another output of I2. We must avoid making this:
2304 (parallel [(set (mem (reg 69)) ...)
2305 (set (reg 69) ...)])
2306 which is not well-defined as to order of actions.
2307 (Besides, reload can't handle output reloads for this.)
2309 The problem can also happen if the dest of I3 is a memory ref,
2310 if another dest in I2 is an indirect memory ref. */
2311 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2312 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2313 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2314 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2315 SET_DEST (XVECEXP (p2
, 0, i
))))
2318 if (i
== XVECLEN (p2
, 0))
2319 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2320 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2321 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2322 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2327 subst_low_luid
= DF_INSN_LUID (i2
);
2329 added_sets_2
= added_sets_1
= 0;
2330 i2dest
= SET_SRC (PATTERN (i3
));
2331 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2333 /* Replace the dest in I2 with our dest and make the resulting
2334 insn the new pattern for I3. Then skip to where we
2335 validate the pattern. Everything was set up above. */
2336 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
2337 SET_DEST (PATTERN (i3
)));
2340 i3_subst_into_i2
= 1;
2341 goto validate_replacement
;
2345 /* If I2 is setting a pseudo to a constant and I3 is setting some
2346 sub-part of it to another constant, merge them by making a new
2349 && (temp
= single_set (i2
)) != 0
2350 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
2351 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2352 && GET_CODE (PATTERN (i3
)) == SET
2353 && (GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
2354 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2355 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2357 rtx dest
= SET_DEST (PATTERN (i3
));
2361 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2363 if (GET_CODE (XEXP (dest
, 1)) == CONST_INT
2364 && GET_CODE (XEXP (dest
, 2)) == CONST_INT
)
2366 width
= INTVAL (XEXP (dest
, 1));
2367 offset
= INTVAL (XEXP (dest
, 2));
2368 dest
= XEXP (dest
, 0);
2369 if (BITS_BIG_ENDIAN
)
2370 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2375 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2376 dest
= XEXP (dest
, 0);
2377 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2383 /* If this is the low part, we're done. */
2384 if (subreg_lowpart_p (dest
))
2386 /* Handle the case where inner is twice the size of outer. */
2387 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2388 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2389 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2390 /* Otherwise give up for now. */
2396 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2397 <= HOST_BITS_PER_WIDE_INT
* 2))
2399 HOST_WIDE_INT mhi
, ohi
, ihi
;
2400 HOST_WIDE_INT mlo
, olo
, ilo
;
2401 rtx inner
= SET_SRC (PATTERN (i3
));
2402 rtx outer
= SET_SRC (temp
);
2404 if (GET_CODE (outer
) == CONST_INT
)
2406 olo
= INTVAL (outer
);
2407 ohi
= olo
< 0 ? -1 : 0;
2411 olo
= CONST_DOUBLE_LOW (outer
);
2412 ohi
= CONST_DOUBLE_HIGH (outer
);
2415 if (GET_CODE (inner
) == CONST_INT
)
2417 ilo
= INTVAL (inner
);
2418 ihi
= ilo
< 0 ? -1 : 0;
2422 ilo
= CONST_DOUBLE_LOW (inner
);
2423 ihi
= CONST_DOUBLE_HIGH (inner
);
2426 if (width
< HOST_BITS_PER_WIDE_INT
)
2428 mlo
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
2431 else if (width
< HOST_BITS_PER_WIDE_INT
* 2)
2433 mhi
= ((unsigned HOST_WIDE_INT
) 1
2434 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
2446 if (offset
>= HOST_BITS_PER_WIDE_INT
)
2448 mhi
= mlo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2450 ihi
= ilo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2453 else if (offset
> 0)
2455 mhi
= (mhi
<< offset
) | ((unsigned HOST_WIDE_INT
) mlo
2456 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2457 mlo
= mlo
<< offset
;
2458 ihi
= (ihi
<< offset
) | ((unsigned HOST_WIDE_INT
) ilo
2459 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2460 ilo
= ilo
<< offset
;
2463 olo
= (olo
& ~mlo
) | ilo
;
2464 ohi
= (ohi
& ~mhi
) | ihi
;
2468 subst_low_luid
= DF_INSN_LUID (i2
);
2469 added_sets_2
= added_sets_1
= 0;
2470 i2dest
= SET_DEST (temp
);
2471 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2473 SUBST (SET_SRC (temp
),
2474 immed_double_const (olo
, ohi
, GET_MODE (SET_DEST (temp
))));
2476 newpat
= PATTERN (i2
);
2477 goto validate_replacement
;
2482 /* If we have no I1 and I2 looks like:
2483 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2485 make up a dummy I1 that is
2488 (set (reg:CC X) (compare:CC Y (const_int 0)))
2490 (We can ignore any trailing CLOBBERs.)
2492 This undoes a previous combination and allows us to match a branch-and-
2495 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2496 && XVECLEN (PATTERN (i2
), 0) >= 2
2497 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2498 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2500 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2501 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2502 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2503 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2504 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2505 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2507 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2508 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2513 /* We make I1 with the same INSN_UID as I2. This gives it
2514 the same DF_INSN_LUID for value tracking. Our fake I1 will
2515 never appear in the insn stream so giving it the same INSN_UID
2516 as I2 will not cause a problem. */
2518 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2519 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
2520 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
);
2522 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2523 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2524 SET_DEST (PATTERN (i1
)));
2529 /* Verify that I2 and I1 are valid for combining. */
2530 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
2531 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
2537 /* Record whether I2DEST is used in I2SRC and similarly for the other
2538 cases. Knowing this will help in register status updating below. */
2539 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2540 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2541 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2542 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2543 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2545 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2547 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
2549 /* Ensure that I3's pattern can be the destination of combines. */
2550 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
2551 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
2558 /* See if any of the insns is a MULT operation. Unless one is, we will
2559 reject a combination that is, since it must be slower. Be conservative
2561 if (GET_CODE (i2src
) == MULT
2562 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2563 || (GET_CODE (PATTERN (i3
)) == SET
2564 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2567 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2568 We used to do this EXCEPT in one case: I3 has a post-inc in an
2569 output operand. However, that exception can give rise to insns like
2571 which is a famous insn on the PDP-11 where the value of r3 used as the
2572 source was model-dependent. Avoid this sort of thing. */
2575 if (!(GET_CODE (PATTERN (i3
)) == SET
2576 && REG_P (SET_SRC (PATTERN (i3
)))
2577 && MEM_P (SET_DEST (PATTERN (i3
)))
2578 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2579 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2580 /* It's not the exception. */
2583 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2584 if (REG_NOTE_KIND (link
) == REG_INC
2585 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2587 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2594 /* See if the SETs in I1 or I2 need to be kept around in the merged
2595 instruction: whenever the value set there is still needed past I3.
2596 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2598 For the SET in I1, we have two cases: If I1 and I2 independently
2599 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2600 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2601 in I1 needs to be kept around unless I1DEST dies or is set in either
2602 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2603 I1DEST. If so, we know I1 feeds into I2. */
2605 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2608 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2609 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2611 /* If the set in I2 needs to be kept around, we must make a copy of
2612 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2613 PATTERN (I2), we are only substituting for the original I1DEST, not into
2614 an already-substituted copy. This also prevents making self-referential
2615 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2620 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2621 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2623 i2pat
= copy_rtx (PATTERN (i2
));
2628 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2629 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2631 i1pat
= copy_rtx (PATTERN (i1
));
2636 /* Substitute in the latest insn for the regs set by the earlier ones. */
2638 maxreg
= max_reg_num ();
2643 /* Many machines that don't use CC0 have insns that can both perform an
2644 arithmetic operation and set the condition code. These operations will
2645 be represented as a PARALLEL with the first element of the vector
2646 being a COMPARE of an arithmetic operation with the constant zero.
2647 The second element of the vector will set some pseudo to the result
2648 of the same arithmetic operation. If we simplify the COMPARE, we won't
2649 match such a pattern and so will generate an extra insn. Here we test
2650 for this case, where both the comparison and the operation result are
2651 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2652 I2SRC. Later we will make the PARALLEL that contains I2. */
2654 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2655 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2656 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2657 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2659 #ifdef SELECT_CC_MODE
2661 enum machine_mode compare_mode
;
2664 newpat
= PATTERN (i3
);
2665 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2669 #ifdef SELECT_CC_MODE
2670 /* See if a COMPARE with the operand we substituted in should be done
2671 with the mode that is currently being used. If not, do the same
2672 processing we do in `subst' for a SET; namely, if the destination
2673 is used only once, try to replace it with a register of the proper
2674 mode and also replace the COMPARE. */
2675 if (undobuf
.other_insn
== 0
2676 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2677 &undobuf
.other_insn
))
2678 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2680 != GET_MODE (SET_DEST (newpat
))))
2682 if (can_change_dest_mode(SET_DEST (newpat
), added_sets_2
,
2685 unsigned int regno
= REGNO (SET_DEST (newpat
));
2688 if (regno
< FIRST_PSEUDO_REGISTER
)
2689 new_dest
= gen_rtx_REG (compare_mode
, regno
);
2692 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2693 new_dest
= regno_reg_rtx
[regno
];
2696 SUBST (SET_DEST (newpat
), new_dest
);
2697 SUBST (XEXP (*cc_use
, 0), new_dest
);
2698 SUBST (SET_SRC (newpat
),
2699 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2702 undobuf
.other_insn
= 0;
2709 /* It is possible that the source of I2 or I1 may be performing
2710 an unneeded operation, such as a ZERO_EXTEND of something
2711 that is known to have the high part zero. Handle that case
2712 by letting subst look at the innermost one of them.
2714 Another way to do this would be to have a function that tries
2715 to simplify a single insn instead of merging two or more
2716 insns. We don't do this because of the potential of infinite
2717 loops and because of the potential extra memory required.
2718 However, doing it the way we are is a bit of a kludge and
2719 doesn't catch all cases.
2721 But only do this if -fexpensive-optimizations since it slows
2722 things down and doesn't usually win.
2724 This is not done in the COMPARE case above because the
2725 unmodified I2PAT is used in the PARALLEL and so a pattern
2726 with a modified I2SRC would not match. */
2728 if (flag_expensive_optimizations
)
2730 /* Pass pc_rtx so no substitutions are done, just
2734 subst_low_luid
= DF_INSN_LUID (i1
);
2735 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2739 subst_low_luid
= DF_INSN_LUID (i2
);
2740 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2744 n_occurrences
= 0; /* `subst' counts here */
2746 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2747 need to make a unique copy of I2SRC each time we substitute it
2748 to avoid self-referential rtl. */
2750 subst_low_luid
= DF_INSN_LUID (i2
);
2751 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2752 ! i1_feeds_i3
&& i1dest_in_i1src
);
2755 /* Record whether i2's body now appears within i3's body. */
2756 i2_is_used
= n_occurrences
;
2759 /* If we already got a failure, don't try to do more. Otherwise,
2760 try to substitute in I1 if we have it. */
2762 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2764 /* Check that an autoincrement side-effect on I1 has not been lost.
2765 This happens if I1DEST is mentioned in I2 and dies there, and
2766 has disappeared from the new pattern. */
2767 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2769 && dead_or_set_p (i2
, i1dest
)
2770 && !reg_overlap_mentioned_p (i1dest
, newpat
))
2771 /* Before we can do this substitution, we must redo the test done
2772 above (see detailed comments there) that ensures that I1DEST
2773 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2774 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, 0, 0))
2781 subst_low_luid
= DF_INSN_LUID (i1
);
2782 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2786 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2787 to count all the ways that I2SRC and I1SRC can be used. */
2788 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2789 && i2_is_used
+ added_sets_2
> 1)
2790 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2791 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2793 /* Fail if we tried to make a new register. */
2794 || max_reg_num () != maxreg
2795 /* Fail if we couldn't do something and have a CLOBBER. */
2796 || GET_CODE (newpat
) == CLOBBER
2797 /* Fail if this new pattern is a MULT and we didn't have one before
2798 at the outer level. */
2799 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2806 /* If the actions of the earlier insns must be kept
2807 in addition to substituting them into the latest one,
2808 we must make a new PARALLEL for the latest insn
2809 to hold additional the SETs. */
2811 if (added_sets_1
|| added_sets_2
)
2815 if (GET_CODE (newpat
) == PARALLEL
)
2817 rtvec old
= XVEC (newpat
, 0);
2818 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2819 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2820 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2821 sizeof (old
->elem
[0]) * old
->num_elem
);
2826 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2827 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2828 XVECEXP (newpat
, 0, 0) = old
;
2832 XVECEXP (newpat
, 0, --total_sets
) = i1pat
;
2836 /* If there is no I1, use I2's body as is. We used to also not do
2837 the subst call below if I2 was substituted into I3,
2838 but that could lose a simplification. */
2840 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2842 /* See comment where i2pat is assigned. */
2843 XVECEXP (newpat
, 0, --total_sets
)
2844 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2848 /* We come here when we are replacing a destination in I2 with the
2849 destination of I3. */
2850 validate_replacement
:
2852 /* Note which hard regs this insn has as inputs. */
2853 mark_used_regs_combine (newpat
);
2855 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2856 consider splitting this pattern, we might need these clobbers. */
2857 if (i1
&& GET_CODE (newpat
) == PARALLEL
2858 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2860 int len
= XVECLEN (newpat
, 0);
2862 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2863 for (i
= 0; i
< len
; i
++)
2864 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2867 /* Is the result of combination a valid instruction? */
2868 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2870 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2871 the second SET's destination is a register that is unused and isn't
2872 marked as an instruction that might trap in an EH region. In that case,
2873 we just need the first SET. This can occur when simplifying a divmod
2874 insn. We *must* test for this case here because the code below that
2875 splits two independent SETs doesn't handle this case correctly when it
2876 updates the register status.
2878 It's pointless doing this if we originally had two sets, one from
2879 i3, and one from i2. Combining then splitting the parallel results
2880 in the original i2 again plus an invalid insn (which we delete).
2881 The net effect is only to move instructions around, which makes
2882 debug info less accurate.
2884 Also check the case where the first SET's destination is unused.
2885 That would not cause incorrect code, but does cause an unneeded
2888 if (insn_code_number
< 0
2889 && !(added_sets_2
&& i1
== 0)
2890 && GET_CODE (newpat
) == PARALLEL
2891 && XVECLEN (newpat
, 0) == 2
2892 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2893 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2894 && asm_noperands (newpat
) < 0)
2896 rtx set0
= XVECEXP (newpat
, 0, 0);
2897 rtx set1
= XVECEXP (newpat
, 0, 1);
2900 if (((REG_P (SET_DEST (set1
))
2901 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2902 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2903 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2904 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2905 || INTVAL (XEXP (note
, 0)) <= 0)
2906 && ! side_effects_p (SET_SRC (set1
)))
2909 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2912 else if (((REG_P (SET_DEST (set0
))
2913 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2914 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2915 && find_reg_note (i3
, REG_UNUSED
,
2916 SUBREG_REG (SET_DEST (set0
)))))
2917 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2918 || INTVAL (XEXP (note
, 0)) <= 0)
2919 && ! side_effects_p (SET_SRC (set0
)))
2922 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2924 if (insn_code_number
>= 0)
2926 /* If we will be able to accept this, we have made a
2927 change to the destination of I3. This requires us to
2928 do a few adjustments. */
2930 PATTERN (i3
) = newpat
;
2931 adjust_for_new_dest (i3
);
2936 /* If we were combining three insns and the result is a simple SET
2937 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2938 insns. There are two ways to do this. It can be split using a
2939 machine-specific method (like when you have an addition of a large
2940 constant) or by combine in the function find_split_point. */
2942 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2943 && asm_noperands (newpat
) < 0)
2945 rtx parallel
, m_split
, *split
;
2947 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2948 use I2DEST as a scratch register will help. In the latter case,
2949 convert I2DEST to the mode of the source of NEWPAT if we can. */
2951 m_split
= combine_split_insns (newpat
, i3
);
2953 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2954 inputs of NEWPAT. */
2956 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2957 possible to try that as a scratch reg. This would require adding
2958 more code to make it work though. */
2960 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
2962 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
2964 /* First try to split using the original register as a
2965 scratch register. */
2966 parallel
= gen_rtx_PARALLEL (VOIDmode
,
2967 gen_rtvec (2, newpat
,
2968 gen_rtx_CLOBBER (VOIDmode
,
2970 m_split
= combine_split_insns (parallel
, i3
);
2972 /* If that didn't work, try changing the mode of I2DEST if
2975 && new_mode
!= GET_MODE (i2dest
)
2976 && new_mode
!= VOIDmode
2977 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
2979 enum machine_mode old_mode
= GET_MODE (i2dest
);
2982 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
2983 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
2986 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
2987 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
2990 parallel
= (gen_rtx_PARALLEL
2992 gen_rtvec (2, newpat
,
2993 gen_rtx_CLOBBER (VOIDmode
,
2995 m_split
= combine_split_insns (parallel
, i3
);
2998 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3002 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3003 buf
= undobuf
.undos
;
3004 undobuf
.undos
= buf
->next
;
3005 buf
->next
= undobuf
.frees
;
3006 undobuf
.frees
= buf
;
3011 /* If recog_for_combine has discarded clobbers, try to use them
3012 again for the split. */
3013 if (m_split
== 0 && newpat_vec_with_clobbers
)
3015 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3016 m_split
= combine_split_insns (parallel
, i3
);
3019 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3021 m_split
= PATTERN (m_split
);
3022 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3023 if (insn_code_number
>= 0)
3026 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3027 && (next_real_insn (i2
) == i3
3028 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3031 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3032 newi2pat
= PATTERN (m_split
);
3034 i3set
= single_set (NEXT_INSN (m_split
));
3035 i2set
= single_set (m_split
);
3037 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3039 /* If I2 or I3 has multiple SETs, we won't know how to track
3040 register status, so don't use these insns. If I2's destination
3041 is used between I2 and I3, we also can't use these insns. */
3043 if (i2_code_number
>= 0 && i2set
&& i3set
3044 && (next_real_insn (i2
) == i3
3045 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3046 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3048 if (insn_code_number
>= 0)
3051 /* It is possible that both insns now set the destination of I3.
3052 If so, we must show an extra use of it. */
3054 if (insn_code_number
>= 0)
3056 rtx new_i3_dest
= SET_DEST (i3set
);
3057 rtx new_i2_dest
= SET_DEST (i2set
);
3059 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3060 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3061 || GET_CODE (new_i3_dest
) == SUBREG
)
3062 new_i3_dest
= XEXP (new_i3_dest
, 0);
3064 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3065 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3066 || GET_CODE (new_i2_dest
) == SUBREG
)
3067 new_i2_dest
= XEXP (new_i2_dest
, 0);
3069 if (REG_P (new_i3_dest
)
3070 && REG_P (new_i2_dest
)
3071 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3072 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3076 /* If we can split it and use I2DEST, go ahead and see if that
3077 helps things be recognized. Verify that none of the registers
3078 are set between I2 and I3. */
3079 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
3083 /* We need I2DEST in the proper mode. If it is a hard register
3084 or the only use of a pseudo, we can change its mode.
3085 Make sure we don't change a hard register to have a mode that
3086 isn't valid for it, or change the number of registers. */
3087 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3088 || GET_MODE (*split
) == VOIDmode
3089 || can_change_dest_mode (i2dest
, added_sets_2
,
3091 && (next_real_insn (i2
) == i3
3092 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3093 /* We can't overwrite I2DEST if its value is still used by
3095 && ! reg_referenced_p (i2dest
, newpat
))
3097 rtx newdest
= i2dest
;
3098 enum rtx_code split_code
= GET_CODE (*split
);
3099 enum machine_mode split_mode
= GET_MODE (*split
);
3100 bool subst_done
= false;
3101 newi2pat
= NULL_RTX
;
3103 /* Get NEWDEST as a register in the proper mode. We have already
3104 validated that we can do this. */
3105 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3107 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3108 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3111 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3112 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3116 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3117 an ASHIFT. This can occur if it was inside a PLUS and hence
3118 appeared to be a memory address. This is a kludge. */
3119 if (split_code
== MULT
3120 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
3121 && INTVAL (XEXP (*split
, 1)) > 0
3122 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
3124 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3125 XEXP (*split
, 0), GEN_INT (i
)));
3126 /* Update split_code because we may not have a multiply
3128 split_code
= GET_CODE (*split
);
3131 #ifdef INSN_SCHEDULING
3132 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3133 be written as a ZERO_EXTEND. */
3134 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3136 #ifdef LOAD_EXTEND_OP
3137 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3138 what it really is. */
3139 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3141 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3142 SUBREG_REG (*split
)));
3145 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3146 SUBREG_REG (*split
)));
3150 /* Attempt to split binary operators using arithmetic identities. */
3151 if (BINARY_P (SET_SRC (newpat
))
3152 && split_mode
== GET_MODE (SET_SRC (newpat
))
3153 && ! side_effects_p (SET_SRC (newpat
)))
3155 rtx setsrc
= SET_SRC (newpat
);
3156 enum machine_mode mode
= GET_MODE (setsrc
);
3157 enum rtx_code code
= GET_CODE (setsrc
);
3158 rtx src_op0
= XEXP (setsrc
, 0);
3159 rtx src_op1
= XEXP (setsrc
, 1);
3161 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3162 if (rtx_equal_p (src_op0
, src_op1
))
3164 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3165 SUBST (XEXP (setsrc
, 0), newdest
);
3166 SUBST (XEXP (setsrc
, 1), newdest
);
3169 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3170 else if ((code
== PLUS
|| code
== MULT
)
3171 && GET_CODE (src_op0
) == code
3172 && GET_CODE (XEXP (src_op0
, 0)) == code
3173 && (INTEGRAL_MODE_P (mode
)
3174 || (FLOAT_MODE_P (mode
)
3175 && flag_unsafe_math_optimizations
)))
3177 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3178 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3179 rtx r
= XEXP (src_op0
, 1);
3182 /* Split both "((X op Y) op X) op Y" and
3183 "((X op Y) op Y) op X" as "T op T" where T is
3185 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3186 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3188 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3190 SUBST (XEXP (setsrc
, 0), newdest
);
3191 SUBST (XEXP (setsrc
, 1), newdest
);
3194 /* Split "((X op X) op Y) op Y)" as "T op T" where
3196 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3198 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3199 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3200 SUBST (XEXP (setsrc
, 0), newdest
);
3201 SUBST (XEXP (setsrc
, 1), newdest
);
3209 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3210 SUBST (*split
, newdest
);
3213 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3215 /* recog_for_combine might have added CLOBBERs to newi2pat.
3216 Make sure NEWPAT does not depend on the clobbered regs. */
3217 if (GET_CODE (newi2pat
) == PARALLEL
)
3218 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3219 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3221 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3222 if (reg_overlap_mentioned_p (reg
, newpat
))
3229 /* If the split point was a MULT and we didn't have one before,
3230 don't use one now. */
3231 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3232 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3236 /* Check for a case where we loaded from memory in a narrow mode and
3237 then sign extended it, but we need both registers. In that case,
3238 we have a PARALLEL with both loads from the same memory location.
3239 We can split this into a load from memory followed by a register-register
3240 copy. This saves at least one insn, more if register allocation can
3243 We cannot do this if the destination of the first assignment is a
3244 condition code register or cc0. We eliminate this case by making sure
3245 the SET_DEST and SET_SRC have the same mode.
3247 We cannot do this if the destination of the second assignment is
3248 a register that we have already assumed is zero-extended. Similarly
3249 for a SUBREG of such a register. */
3251 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3252 && GET_CODE (newpat
) == PARALLEL
3253 && XVECLEN (newpat
, 0) == 2
3254 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3255 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3256 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3257 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3258 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3259 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3260 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3261 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3263 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3264 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3265 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3267 && VEC_index (reg_stat_type
, reg_stat
,
3268 REGNO (temp
))->nonzero_bits
!= 0
3269 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3270 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3271 && (VEC_index (reg_stat_type
, reg_stat
,
3272 REGNO (temp
))->nonzero_bits
3273 != GET_MODE_MASK (word_mode
))))
3274 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3275 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3277 && VEC_index (reg_stat_type
, reg_stat
,
3278 REGNO (temp
))->nonzero_bits
!= 0
3279 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3280 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3281 && (VEC_index (reg_stat_type
, reg_stat
,
3282 REGNO (temp
))->nonzero_bits
3283 != GET_MODE_MASK (word_mode
)))))
3284 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3285 SET_SRC (XVECEXP (newpat
, 0, 1)))
3286 && ! find_reg_note (i3
, REG_UNUSED
,
3287 SET_DEST (XVECEXP (newpat
, 0, 0))))
3291 newi2pat
= XVECEXP (newpat
, 0, 0);
3292 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3293 newpat
= XVECEXP (newpat
, 0, 1);
3294 SUBST (SET_SRC (newpat
),
3295 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3296 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3298 if (i2_code_number
>= 0)
3299 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3301 if (insn_code_number
>= 0)
3305 /* Similarly, check for a case where we have a PARALLEL of two independent
3306 SETs but we started with three insns. In this case, we can do the sets
3307 as two separate insns. This case occurs when some SET allows two
3308 other insns to combine, but the destination of that SET is still live. */
3310 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3311 && GET_CODE (newpat
) == PARALLEL
3312 && XVECLEN (newpat
, 0) == 2
3313 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3314 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3315 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3316 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3317 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3318 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3319 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3321 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3322 XVECEXP (newpat
, 0, 0))
3323 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3324 XVECEXP (newpat
, 0, 1))
3325 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3326 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1))))
3328 /* We cannot split the parallel into two sets if both sets
3330 && ! (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3331 && reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1)))
3335 /* Normally, it doesn't matter which of the two is done first,
3336 but it does if one references cc0. In that case, it has to
3339 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
3341 newi2pat
= XVECEXP (newpat
, 0, 0);
3342 newpat
= XVECEXP (newpat
, 0, 1);
3347 newi2pat
= XVECEXP (newpat
, 0, 1);
3348 newpat
= XVECEXP (newpat
, 0, 0);
3351 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3353 if (i2_code_number
>= 0)
3354 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3357 /* If it still isn't recognized, fail and change things back the way they
3359 if ((insn_code_number
< 0
3360 /* Is the result a reasonable ASM_OPERANDS? */
3361 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3367 /* If we had to change another insn, make sure it is valid also. */
3368 if (undobuf
.other_insn
)
3370 CLEAR_HARD_REG_SET (newpat_used_regs
);
3372 other_pat
= PATTERN (undobuf
.other_insn
);
3373 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3376 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3384 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3385 they are adjacent to each other or not. */
3387 rtx p
= prev_nonnote_insn (i3
);
3388 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3389 && sets_cc0_p (newi2pat
))
3397 /* Only allow this combination if insn_rtx_costs reports that the
3398 replacement instructions are cheaper than the originals. */
3399 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3405 /* We now know that we can do this combination. Merge the insns and
3406 update the status of registers and LOG_LINKS. */
3408 if (undobuf
.other_insn
)
3412 PATTERN (undobuf
.other_insn
) = other_pat
;
3414 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3415 are still valid. Then add any non-duplicate notes added by
3416 recog_for_combine. */
3417 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3419 next
= XEXP (note
, 1);
3421 if (REG_NOTE_KIND (note
) == REG_UNUSED
3422 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3423 remove_note (undobuf
.other_insn
, note
);
3426 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3427 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3436 /* I3 now uses what used to be its destination and which is now
3437 I2's destination. This requires us to do a few adjustments. */
3438 PATTERN (i3
) = newpat
;
3439 adjust_for_new_dest (i3
);
3441 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3444 However, some later insn might be using I2's dest and have
3445 a LOG_LINK pointing at I3. We must remove this link.
3446 The simplest way to remove the link is to point it at I1,
3447 which we know will be a NOTE. */
3449 /* newi2pat is usually a SET here; however, recog_for_combine might
3450 have added some clobbers. */
3451 if (GET_CODE (newi2pat
) == PARALLEL
)
3452 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3454 ni2dest
= SET_DEST (newi2pat
);
3456 for (insn
= NEXT_INSN (i3
);
3457 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3458 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3459 insn
= NEXT_INSN (insn
))
3461 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3463 for (link
= LOG_LINKS (insn
); link
;
3464 link
= XEXP (link
, 1))
3465 if (XEXP (link
, 0) == i3
)
3466 XEXP (link
, 0) = i1
;
3474 rtx i3notes
, i2notes
, i1notes
= 0;
3475 rtx i3links
, i2links
, i1links
= 0;
3478 /* Compute which registers we expect to eliminate. newi2pat may be setting
3479 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3480 same as i3dest, in which case newi2pat may be setting i1dest. */
3481 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3482 || i2dest_in_i2src
|| i2dest_in_i1src
3485 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
3486 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3490 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3492 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3493 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3495 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3497 /* Ensure that we do not have something that should not be shared but
3498 occurs multiple times in the new insns. Check this by first
3499 resetting all the `used' flags and then copying anything is shared. */
3501 reset_used_flags (i3notes
);
3502 reset_used_flags (i2notes
);
3503 reset_used_flags (i1notes
);
3504 reset_used_flags (newpat
);
3505 reset_used_flags (newi2pat
);
3506 if (undobuf
.other_insn
)
3507 reset_used_flags (PATTERN (undobuf
.other_insn
));
3509 i3notes
= copy_rtx_if_shared (i3notes
);
3510 i2notes
= copy_rtx_if_shared (i2notes
);
3511 i1notes
= copy_rtx_if_shared (i1notes
);
3512 newpat
= copy_rtx_if_shared (newpat
);
3513 newi2pat
= copy_rtx_if_shared (newi2pat
);
3514 if (undobuf
.other_insn
)
3515 reset_used_flags (PATTERN (undobuf
.other_insn
));
3517 INSN_CODE (i3
) = insn_code_number
;
3518 PATTERN (i3
) = newpat
;
3520 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3522 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3524 reset_used_flags (call_usage
);
3525 call_usage
= copy_rtx (call_usage
);
3528 replace_rtx (call_usage
, i2dest
, i2src
);
3531 replace_rtx (call_usage
, i1dest
, i1src
);
3533 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
3536 if (undobuf
.other_insn
)
3537 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
3539 /* We had one special case above where I2 had more than one set and
3540 we replaced a destination of one of those sets with the destination
3541 of I3. In that case, we have to update LOG_LINKS of insns later
3542 in this basic block. Note that this (expensive) case is rare.
3544 Also, in this case, we must pretend that all REG_NOTEs for I2
3545 actually came from I3, so that REG_UNUSED notes from I2 will be
3546 properly handled. */
3548 if (i3_subst_into_i2
)
3550 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
3551 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
3552 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
3553 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
3554 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
3555 && ! find_reg_note (i2
, REG_UNUSED
,
3556 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
3557 for (temp
= NEXT_INSN (i2
);
3558 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3559 || BB_HEAD (this_basic_block
) != temp
);
3560 temp
= NEXT_INSN (temp
))
3561 if (temp
!= i3
&& INSN_P (temp
))
3562 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
3563 if (XEXP (link
, 0) == i2
)
3564 XEXP (link
, 0) = i3
;
3569 while (XEXP (link
, 1))
3570 link
= XEXP (link
, 1);
3571 XEXP (link
, 1) = i2notes
;
3585 INSN_CODE (i2
) = i2_code_number
;
3586 PATTERN (i2
) = newi2pat
;
3589 SET_INSN_DELETED (i2
);
3595 SET_INSN_DELETED (i1
);
3598 /* Get death notes for everything that is now used in either I3 or
3599 I2 and used to die in a previous insn. If we built two new
3600 patterns, move from I1 to I2 then I2 to I3 so that we get the
3601 proper movement on registers that I2 modifies. */
3605 move_deaths (newi2pat
, NULL_RTX
, DF_INSN_LUID (i1
), i2
, &midnotes
);
3606 move_deaths (newpat
, newi2pat
, DF_INSN_LUID (i1
), i3
, &midnotes
);
3609 move_deaths (newpat
, NULL_RTX
, i1
? DF_INSN_LUID (i1
) : DF_INSN_LUID (i2
),
3612 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3614 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
3617 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
3620 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
3623 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3626 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3627 know these are REG_UNUSED and want them to go to the desired insn,
3628 so we always pass it as i3. */
3630 if (newi2pat
&& new_i2_notes
)
3631 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3634 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3636 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3637 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3638 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3639 in that case, it might delete I2. Similarly for I2 and I1.
3640 Show an additional death due to the REG_DEAD note we make here. If
3641 we discard it in distribute_notes, we will decrement it again. */
3645 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
3646 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3648 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
3650 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3652 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3656 if (i2dest_in_i2src
)
3658 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3659 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3660 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3662 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3663 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3664 NULL_RTX
, NULL_RTX
);
3667 if (i1dest_in_i1src
)
3669 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3670 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3671 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3673 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3674 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3675 NULL_RTX
, NULL_RTX
);
3678 distribute_links (i3links
);
3679 distribute_links (i2links
);
3680 distribute_links (i1links
);
3685 rtx i2_insn
= 0, i2_val
= 0, set
;
3687 /* The insn that used to set this register doesn't exist, and
3688 this life of the register may not exist either. See if one of
3689 I3's links points to an insn that sets I2DEST. If it does,
3690 that is now the last known value for I2DEST. If we don't update
3691 this and I2 set the register to a value that depended on its old
3692 contents, we will get confused. If this insn is used, thing
3693 will be set correctly in combine_instructions. */
3695 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3696 if ((set
= single_set (XEXP (link
, 0))) != 0
3697 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3698 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3700 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3702 /* If the reg formerly set in I2 died only once and that was in I3,
3703 zero its use count so it won't make `reload' do any work. */
3705 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3706 && ! i2dest_in_i2src
)
3708 regno
= REGNO (i2dest
);
3709 INC_REG_N_SETS (regno
, -1);
3713 if (i1
&& REG_P (i1dest
))
3716 rtx i1_insn
= 0, i1_val
= 0, set
;
3718 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3719 if ((set
= single_set (XEXP (link
, 0))) != 0
3720 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3721 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3723 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3725 regno
= REGNO (i1dest
);
3726 if (! added_sets_1
&& ! i1dest_in_i1src
)
3727 INC_REG_N_SETS (regno
, -1);
3730 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3731 been made to this insn. The order of
3732 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3733 can affect nonzero_bits of newpat */
3735 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
3736 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
3738 /* Set new_direct_jump_p if a new return or simple jump instruction
3741 If I3 is now an unconditional jump, ensure that it has a
3742 BARRIER following it since it may have initially been a
3743 conditional jump. It may also be the last nonnote insn. */
3745 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
3747 *new_direct_jump_p
= 1;
3748 mark_jump_label (PATTERN (i3
), i3
, 0);
3750 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
3751 || !BARRIER_P (temp
))
3752 emit_barrier_after (i3
);
3755 if (undobuf
.other_insn
!= NULL_RTX
3756 && (returnjump_p (undobuf
.other_insn
)
3757 || any_uncondjump_p (undobuf
.other_insn
)))
3759 *new_direct_jump_p
= 1;
3761 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
3762 || !BARRIER_P (temp
))
3763 emit_barrier_after (undobuf
.other_insn
);
3766 /* An NOOP jump does not need barrier, but it does need cleaning up
3768 if (GET_CODE (newpat
) == SET
3769 && SET_SRC (newpat
) == pc_rtx
3770 && SET_DEST (newpat
) == pc_rtx
)
3771 *new_direct_jump_p
= 1;
3774 if (undobuf
.other_insn
!= NULL_RTX
)
3778 fprintf (dump_file
, "modifying other_insn ");
3779 dump_insn_slim (dump_file
, undobuf
.other_insn
);
3781 df_insn_rescan (undobuf
.other_insn
);
3784 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
3788 fprintf (dump_file
, "modifying insn i1 ");
3789 dump_insn_slim (dump_file
, i1
);
3791 df_insn_rescan (i1
);
3794 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
3798 fprintf (dump_file
, "modifying insn i2 ");
3799 dump_insn_slim (dump_file
, i2
);
3801 df_insn_rescan (i2
);
3804 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
3808 fprintf (dump_file
, "modifying insn i3 ");
3809 dump_insn_slim (dump_file
, i3
);
3811 df_insn_rescan (i3
);
3814 combine_successes
++;
3817 if (added_links_insn
3818 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
3819 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
3820 return added_links_insn
;
3822 return newi2pat
? i2
: i3
;
3825 /* Undo all the modifications recorded in undobuf. */
3830 struct undo
*undo
, *next
;
3832 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3838 *undo
->where
.r
= undo
->old_contents
.r
;
3841 *undo
->where
.i
= undo
->old_contents
.i
;
3844 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
3850 undo
->next
= undobuf
.frees
;
3851 undobuf
.frees
= undo
;
3857 /* We've committed to accepting the changes we made. Move all
3858 of the undos to the free list. */
3863 struct undo
*undo
, *next
;
3865 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3868 undo
->next
= undobuf
.frees
;
3869 undobuf
.frees
= undo
;
3874 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3875 where we have an arithmetic expression and return that point. LOC will
3878 try_combine will call this function to see if an insn can be split into
3882 find_split_point (rtx
*loc
, rtx insn
)
3885 enum rtx_code code
= GET_CODE (x
);
3887 unsigned HOST_WIDE_INT len
= 0;
3888 HOST_WIDE_INT pos
= 0;
3890 rtx inner
= NULL_RTX
;
3892 /* First special-case some codes. */
3896 #ifdef INSN_SCHEDULING
3897 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3899 if (MEM_P (SUBREG_REG (x
)))
3902 return find_split_point (&SUBREG_REG (x
), insn
);
3906 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3907 using LO_SUM and HIGH. */
3908 if (GET_CODE (XEXP (x
, 0)) == CONST
3909 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3912 gen_rtx_LO_SUM (Pmode
,
3913 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3915 return &XEXP (XEXP (x
, 0), 0);
3919 /* If we have a PLUS whose second operand is a constant and the
3920 address is not valid, perhaps will can split it up using
3921 the machine-specific way to split large constants. We use
3922 the first pseudo-reg (one of the virtual regs) as a placeholder;
3923 it will not remain in the result. */
3924 if (GET_CODE (XEXP (x
, 0)) == PLUS
3925 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3926 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3928 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3929 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
3933 /* This should have produced two insns, each of which sets our
3934 placeholder. If the source of the second is a valid address,
3935 we can make put both sources together and make a split point
3939 && NEXT_INSN (seq
) != NULL_RTX
3940 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3941 && NONJUMP_INSN_P (seq
)
3942 && GET_CODE (PATTERN (seq
)) == SET
3943 && SET_DEST (PATTERN (seq
)) == reg
3944 && ! reg_mentioned_p (reg
,
3945 SET_SRC (PATTERN (seq
)))
3946 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3947 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3948 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3949 && memory_address_p (GET_MODE (x
),
3950 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3952 rtx src1
= SET_SRC (PATTERN (seq
));
3953 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3955 /* Replace the placeholder in SRC2 with SRC1. If we can
3956 find where in SRC2 it was placed, that can become our
3957 split point and we can replace this address with SRC2.
3958 Just try two obvious places. */
3960 src2
= replace_rtx (src2
, reg
, src1
);
3962 if (XEXP (src2
, 0) == src1
)
3963 split
= &XEXP (src2
, 0);
3964 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3965 && XEXP (XEXP (src2
, 0), 0) == src1
)
3966 split
= &XEXP (XEXP (src2
, 0), 0);
3970 SUBST (XEXP (x
, 0), src2
);
3975 /* If that didn't work, perhaps the first operand is complex and
3976 needs to be computed separately, so make a split point there.
3977 This will occur on machines that just support REG + CONST
3978 and have a constant moved through some previous computation. */
3980 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3981 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3982 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3983 return &XEXP (XEXP (x
, 0), 0);
3986 /* If we have a PLUS whose first operand is complex, try computing it
3987 separately by making a split there. */
3988 if (GET_CODE (XEXP (x
, 0)) == PLUS
3989 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0))
3990 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
3991 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3992 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3993 return &XEXP (XEXP (x
, 0), 0);
3998 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3999 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4000 we need to put the operand into a register. So split at that
4003 if (SET_DEST (x
) == cc0_rtx
4004 && GET_CODE (SET_SRC (x
)) != COMPARE
4005 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4006 && !OBJECT_P (SET_SRC (x
))
4007 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4008 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4009 return &SET_SRC (x
);
4012 /* See if we can split SET_SRC as it stands. */
4013 split
= find_split_point (&SET_SRC (x
), insn
);
4014 if (split
&& split
!= &SET_SRC (x
))
4017 /* See if we can split SET_DEST as it stands. */
4018 split
= find_split_point (&SET_DEST (x
), insn
);
4019 if (split
&& split
!= &SET_DEST (x
))
4022 /* See if this is a bitfield assignment with everything constant. If
4023 so, this is an IOR of an AND, so split it into that. */
4024 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4025 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4026 <= HOST_BITS_PER_WIDE_INT
)
4027 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
4028 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
4029 && GET_CODE (SET_SRC (x
)) == CONST_INT
4030 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4031 + INTVAL (XEXP (SET_DEST (x
), 2)))
4032 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4033 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4035 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4036 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4037 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4038 rtx dest
= XEXP (SET_DEST (x
), 0);
4039 enum machine_mode mode
= GET_MODE (dest
);
4040 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
4043 if (BITS_BIG_ENDIAN
)
4044 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4046 or_mask
= gen_int_mode (src
<< pos
, mode
);
4049 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4052 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4054 simplify_gen_binary (IOR
, mode
,
4055 simplify_gen_binary (AND
, mode
,
4060 SUBST (SET_DEST (x
), dest
);
4062 split
= find_split_point (&SET_SRC (x
), insn
);
4063 if (split
&& split
!= &SET_SRC (x
))
4067 /* Otherwise, see if this is an operation that we can split into two.
4068 If so, try to split that. */
4069 code
= GET_CODE (SET_SRC (x
));
4074 /* If we are AND'ing with a large constant that is only a single
4075 bit and the result is only being used in a context where we
4076 need to know if it is zero or nonzero, replace it with a bit
4077 extraction. This will avoid the large constant, which might
4078 have taken more than one insn to make. If the constant were
4079 not a valid argument to the AND but took only one insn to make,
4080 this is no worse, but if it took more than one insn, it will
4083 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
4084 && REG_P (XEXP (SET_SRC (x
), 0))
4085 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4086 && REG_P (SET_DEST (x
))
4087 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4088 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4089 && XEXP (*split
, 0) == SET_DEST (x
)
4090 && XEXP (*split
, 1) == const0_rtx
)
4092 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4093 XEXP (SET_SRC (x
), 0),
4094 pos
, NULL_RTX
, 1, 1, 0, 0);
4095 if (extraction
!= 0)
4097 SUBST (SET_SRC (x
), extraction
);
4098 return find_split_point (loc
, insn
);
4104 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4105 is known to be on, this can be converted into a NEG of a shift. */
4106 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4107 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4108 && 1 <= (pos
= exact_log2
4109 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4110 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4112 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4116 gen_rtx_LSHIFTRT (mode
,
4117 XEXP (SET_SRC (x
), 0),
4120 split
= find_split_point (&SET_SRC (x
), insn
);
4121 if (split
&& split
!= &SET_SRC (x
))
4127 inner
= XEXP (SET_SRC (x
), 0);
4129 /* We can't optimize if either mode is a partial integer
4130 mode as we don't know how many bits are significant
4132 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4133 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4137 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4143 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
4144 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
4146 inner
= XEXP (SET_SRC (x
), 0);
4147 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4148 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4150 if (BITS_BIG_ENDIAN
)
4151 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4152 unsignedp
= (code
== ZERO_EXTRACT
);
4160 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4162 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4164 /* For unsigned, we have a choice of a shift followed by an
4165 AND or two shifts. Use two shifts for field sizes where the
4166 constant might be too large. We assume here that we can
4167 always at least get 8-bit constants in an AND insn, which is
4168 true for every current RISC. */
4170 if (unsignedp
&& len
<= 8)
4175 (mode
, gen_lowpart (mode
, inner
),
4177 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
4179 split
= find_split_point (&SET_SRC (x
), insn
);
4180 if (split
&& split
!= &SET_SRC (x
))
4187 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4188 gen_rtx_ASHIFT (mode
,
4189 gen_lowpart (mode
, inner
),
4190 GEN_INT (GET_MODE_BITSIZE (mode
)
4192 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4194 split
= find_split_point (&SET_SRC (x
), insn
);
4195 if (split
&& split
!= &SET_SRC (x
))
4200 /* See if this is a simple operation with a constant as the second
4201 operand. It might be that this constant is out of range and hence
4202 could be used as a split point. */
4203 if (BINARY_P (SET_SRC (x
))
4204 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4205 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4206 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4207 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4208 return &XEXP (SET_SRC (x
), 1);
4210 /* Finally, see if this is a simple operation with its first operand
4211 not in a register. The operation might require this operand in a
4212 register, so return it as a split point. We can always do this
4213 because if the first operand were another operation, we would have
4214 already found it as a split point. */
4215 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4216 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4217 return &XEXP (SET_SRC (x
), 0);
4223 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4224 it is better to write this as (not (ior A B)) so we can split it.
4225 Similarly for IOR. */
4226 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4229 gen_rtx_NOT (GET_MODE (x
),
4230 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4232 XEXP (XEXP (x
, 0), 0),
4233 XEXP (XEXP (x
, 1), 0))));
4234 return find_split_point (loc
, insn
);
4237 /* Many RISC machines have a large set of logical insns. If the
4238 second operand is a NOT, put it first so we will try to split the
4239 other operand first. */
4240 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4242 rtx tem
= XEXP (x
, 0);
4243 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4244 SUBST (XEXP (x
, 1), tem
);
4252 /* Otherwise, select our actions depending on our rtx class. */
4253 switch (GET_RTX_CLASS (code
))
4255 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4257 split
= find_split_point (&XEXP (x
, 2), insn
);
4260 /* ... fall through ... */
4262 case RTX_COMM_ARITH
:
4264 case RTX_COMM_COMPARE
:
4265 split
= find_split_point (&XEXP (x
, 1), insn
);
4268 /* ... fall through ... */
4270 /* Some machines have (and (shift ...) ...) insns. If X is not
4271 an AND, but XEXP (X, 0) is, use it as our split point. */
4272 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4273 return &XEXP (x
, 0);
4275 split
= find_split_point (&XEXP (x
, 0), insn
);
4281 /* Otherwise, we don't have a split point. */
4286 /* Throughout X, replace FROM with TO, and return the result.
4287 The result is TO if X is FROM;
4288 otherwise the result is X, but its contents may have been modified.
4289 If they were modified, a record was made in undobuf so that
4290 undo_all will (among other things) return X to its original state.
4292 If the number of changes necessary is too much to record to undo,
4293 the excess changes are not made, so the result is invalid.
4294 The changes already made can still be undone.
4295 undobuf.num_undo is incremented for such changes, so by testing that
4296 the caller can tell whether the result is valid.
4298 `n_occurrences' is incremented each time FROM is replaced.
4300 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4302 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4303 by copying if `n_occurrences' is nonzero. */
4306 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4308 enum rtx_code code
= GET_CODE (x
);
4309 enum machine_mode op0_mode
= VOIDmode
;
4314 /* Two expressions are equal if they are identical copies of a shared
4315 RTX or if they are both registers with the same register number
4318 #define COMBINE_RTX_EQUAL_P(X,Y) \
4320 || (REG_P (X) && REG_P (Y) \
4321 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4323 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4326 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4329 /* If X and FROM are the same register but different modes, they
4330 will not have been seen as equal above. However, the log links code
4331 will make a LOG_LINKS entry for that case. If we do nothing, we
4332 will try to rerecognize our original insn and, when it succeeds,
4333 we will delete the feeding insn, which is incorrect.
4335 So force this insn not to match in this (rare) case. */
4336 if (! in_dest
&& code
== REG
&& REG_P (from
)
4337 && reg_overlap_mentioned_p (x
, from
))
4338 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4340 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4341 of which may contain things that can be combined. */
4342 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4345 /* It is possible to have a subexpression appear twice in the insn.
4346 Suppose that FROM is a register that appears within TO.
4347 Then, after that subexpression has been scanned once by `subst',
4348 the second time it is scanned, TO may be found. If we were
4349 to scan TO here, we would find FROM within it and create a
4350 self-referent rtl structure which is completely wrong. */
4351 if (COMBINE_RTX_EQUAL_P (x
, to
))
4354 /* Parallel asm_operands need special attention because all of the
4355 inputs are shared across the arms. Furthermore, unsharing the
4356 rtl results in recognition failures. Failure to handle this case
4357 specially can result in circular rtl.
4359 Solve this by doing a normal pass across the first entry of the
4360 parallel, and only processing the SET_DESTs of the subsequent
4363 if (code
== PARALLEL
4364 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4365 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4367 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4369 /* If this substitution failed, this whole thing fails. */
4370 if (GET_CODE (new) == CLOBBER
4371 && XEXP (new, 0) == const0_rtx
)
4374 SUBST (XVECEXP (x
, 0, 0), new);
4376 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4378 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4381 && GET_CODE (dest
) != CC0
4382 && GET_CODE (dest
) != PC
)
4384 new = subst (dest
, from
, to
, 0, unique_copy
);
4386 /* If this substitution failed, this whole thing fails. */
4387 if (GET_CODE (new) == CLOBBER
4388 && XEXP (new, 0) == const0_rtx
)
4391 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
4397 len
= GET_RTX_LENGTH (code
);
4398 fmt
= GET_RTX_FORMAT (code
);
4400 /* We don't need to process a SET_DEST that is a register, CC0,
4401 or PC, so set up to skip this common case. All other cases
4402 where we want to suppress replacing something inside a
4403 SET_SRC are handled via the IN_DEST operand. */
4405 && (REG_P (SET_DEST (x
))
4406 || GET_CODE (SET_DEST (x
)) == CC0
4407 || GET_CODE (SET_DEST (x
)) == PC
))
4410 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4413 op0_mode
= GET_MODE (XEXP (x
, 0));
4415 for (i
= 0; i
< len
; i
++)
4420 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4422 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
4424 new = (unique_copy
&& n_occurrences
4425 ? copy_rtx (to
) : to
);
4430 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
4433 /* If this substitution failed, this whole thing
4435 if (GET_CODE (new) == CLOBBER
4436 && XEXP (new, 0) == const0_rtx
)
4440 SUBST (XVECEXP (x
, i
, j
), new);
4443 else if (fmt
[i
] == 'e')
4445 /* If this is a register being set, ignore it. */
4449 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
4451 || code
== STRICT_LOW_PART
))
4454 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
4456 /* In general, don't install a subreg involving two
4457 modes not tieable. It can worsen register
4458 allocation, and can even make invalid reload
4459 insns, since the reg inside may need to be copied
4460 from in the outside mode, and that may be invalid
4461 if it is an fp reg copied in integer mode.
4463 We allow two exceptions to this: It is valid if
4464 it is inside another SUBREG and the mode of that
4465 SUBREG and the mode of the inside of TO is
4466 tieable and it is valid if X is a SET that copies
4469 if (GET_CODE (to
) == SUBREG
4470 && ! MODES_TIEABLE_P (GET_MODE (to
),
4471 GET_MODE (SUBREG_REG (to
)))
4472 && ! (code
== SUBREG
4473 && MODES_TIEABLE_P (GET_MODE (x
),
4474 GET_MODE (SUBREG_REG (to
))))
4476 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
4479 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4481 #ifdef CANNOT_CHANGE_MODE_CLASS
4484 && REGNO (to
) < FIRST_PSEUDO_REGISTER
4485 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
4488 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4491 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
4495 /* If we are in a SET_DEST, suppress most cases unless we
4496 have gone inside a MEM, in which case we want to
4497 simplify the address. We assume here that things that
4498 are actually part of the destination have their inner
4499 parts in the first expression. This is true for SUBREG,
4500 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4501 things aside from REG and MEM that should appear in a
4503 new = subst (XEXP (x
, i
), from
, to
,
4505 && (code
== SUBREG
|| code
== STRICT_LOW_PART
4506 || code
== ZERO_EXTRACT
))
4508 && i
== 0), unique_copy
);
4510 /* If we found that we will have to reject this combination,
4511 indicate that by returning the CLOBBER ourselves, rather than
4512 an expression containing it. This will speed things up as
4513 well as prevent accidents where two CLOBBERs are considered
4514 to be equal, thus producing an incorrect simplification. */
4516 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
4519 if (GET_CODE (x
) == SUBREG
4520 && (GET_CODE (new) == CONST_INT
4521 || GET_CODE (new) == CONST_DOUBLE
))
4523 enum machine_mode mode
= GET_MODE (x
);
4525 x
= simplify_subreg (GET_MODE (x
), new,
4526 GET_MODE (SUBREG_REG (x
)),
4529 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
4531 else if (GET_CODE (new) == CONST_INT
4532 && GET_CODE (x
) == ZERO_EXTEND
)
4534 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
4535 new, GET_MODE (XEXP (x
, 0)));
4539 SUBST (XEXP (x
, i
), new);
4544 /* Check if we are loading something from the constant pool via float
4545 extension; in this case we would undo compress_float_constant
4546 optimization and degenerate constant load to an immediate value. */
4547 if (GET_CODE (x
) == FLOAT_EXTEND
4548 && MEM_P (XEXP (x
, 0))
4549 && MEM_READONLY_P (XEXP (x
, 0)))
4551 rtx tmp
= avoid_constant_pool_reference (x
);
4556 /* Try to simplify X. If the simplification changed the code, it is likely
4557 that further simplification will help, so loop, but limit the number
4558 of repetitions that will be performed. */
4560 for (i
= 0; i
< 4; i
++)
4562 /* If X is sufficiently simple, don't bother trying to do anything
4564 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
4565 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
4567 if (GET_CODE (x
) == code
)
4570 code
= GET_CODE (x
);
4572 /* We no longer know the original mode of operand 0 since we
4573 have changed the form of X) */
4574 op0_mode
= VOIDmode
;
4580 /* Simplify X, a piece of RTL. We just operate on the expression at the
4581 outer level; call `subst' to simplify recursively. Return the new
4584 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4585 if we are inside a SET_DEST. */
4588 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
4590 enum rtx_code code
= GET_CODE (x
);
4591 enum machine_mode mode
= GET_MODE (x
);
4595 /* If this is a commutative operation, put a constant last and a complex
4596 expression first. We don't need to do this for comparisons here. */
4597 if (COMMUTATIVE_ARITH_P (x
)
4598 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
4601 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4602 SUBST (XEXP (x
, 1), temp
);
4605 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4606 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4607 things. Check for cases where both arms are testing the same
4610 Don't do anything if all operands are very simple. */
4613 && ((!OBJECT_P (XEXP (x
, 0))
4614 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4615 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
4616 || (!OBJECT_P (XEXP (x
, 1))
4617 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
4618 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
4620 && (!OBJECT_P (XEXP (x
, 0))
4621 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4622 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
4624 rtx cond
, true_rtx
, false_rtx
;
4626 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
4628 /* If everything is a comparison, what we have is highly unlikely
4629 to be simpler, so don't use it. */
4630 && ! (COMPARISON_P (x
)
4631 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
4633 rtx cop1
= const0_rtx
;
4634 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
4636 if (cond_code
== NE
&& COMPARISON_P (cond
))
4639 /* Simplify the alternative arms; this may collapse the true and
4640 false arms to store-flag values. Be careful to use copy_rtx
4641 here since true_rtx or false_rtx might share RTL with x as a
4642 result of the if_then_else_cond call above. */
4643 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4644 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4646 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4647 is unlikely to be simpler. */
4648 if (general_operand (true_rtx
, VOIDmode
)
4649 && general_operand (false_rtx
, VOIDmode
))
4651 enum rtx_code reversed
;
4653 /* Restarting if we generate a store-flag expression will cause
4654 us to loop. Just drop through in this case. */
4656 /* If the result values are STORE_FLAG_VALUE and zero, we can
4657 just make the comparison operation. */
4658 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4659 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
4661 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4662 && ((reversed
= reversed_comparison_code_parts
4663 (cond_code
, cond
, cop1
, NULL
))
4665 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
4668 /* Likewise, we can make the negate of a comparison operation
4669 if the result values are - STORE_FLAG_VALUE and zero. */
4670 else if (GET_CODE (true_rtx
) == CONST_INT
4671 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
4672 && false_rtx
== const0_rtx
)
4673 x
= simplify_gen_unary (NEG
, mode
,
4674 simplify_gen_relational (cond_code
,
4678 else if (GET_CODE (false_rtx
) == CONST_INT
4679 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
4680 && true_rtx
== const0_rtx
4681 && ((reversed
= reversed_comparison_code_parts
4682 (cond_code
, cond
, cop1
, NULL
))
4684 x
= simplify_gen_unary (NEG
, mode
,
4685 simplify_gen_relational (reversed
,
4690 return gen_rtx_IF_THEN_ELSE (mode
,
4691 simplify_gen_relational (cond_code
,
4696 true_rtx
, false_rtx
);
4698 code
= GET_CODE (x
);
4699 op0_mode
= VOIDmode
;
4704 /* Try to fold this expression in case we have constants that weren't
4707 switch (GET_RTX_CLASS (code
))
4710 if (op0_mode
== VOIDmode
)
4711 op0_mode
= GET_MODE (XEXP (x
, 0));
4712 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
4715 case RTX_COMM_COMPARE
:
4717 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
4718 if (cmp_mode
== VOIDmode
)
4720 cmp_mode
= GET_MODE (XEXP (x
, 1));
4721 if (cmp_mode
== VOIDmode
)
4722 cmp_mode
= op0_mode
;
4724 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
4725 XEXP (x
, 0), XEXP (x
, 1));
4728 case RTX_COMM_ARITH
:
4730 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4732 case RTX_BITFIELD_OPS
:
4734 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
4735 XEXP (x
, 1), XEXP (x
, 2));
4744 code
= GET_CODE (temp
);
4745 op0_mode
= VOIDmode
;
4746 mode
= GET_MODE (temp
);
4749 /* First see if we can apply the inverse distributive law. */
4750 if (code
== PLUS
|| code
== MINUS
4751 || code
== AND
|| code
== IOR
|| code
== XOR
)
4753 x
= apply_distributive_law (x
);
4754 code
= GET_CODE (x
);
4755 op0_mode
= VOIDmode
;
4758 /* If CODE is an associative operation not otherwise handled, see if we
4759 can associate some operands. This can win if they are constants or
4760 if they are logically related (i.e. (a & b) & a). */
4761 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
4762 || code
== AND
|| code
== IOR
|| code
== XOR
4763 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
4764 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
4765 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
4767 if (GET_CODE (XEXP (x
, 0)) == code
)
4769 rtx other
= XEXP (XEXP (x
, 0), 0);
4770 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
4771 rtx inner_op1
= XEXP (x
, 1);
4774 /* Make sure we pass the constant operand if any as the second
4775 one if this is a commutative operation. */
4776 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
4778 rtx tem
= inner_op0
;
4779 inner_op0
= inner_op1
;
4782 inner
= simplify_binary_operation (code
== MINUS
? PLUS
4783 : code
== DIV
? MULT
4785 mode
, inner_op0
, inner_op1
);
4787 /* For commutative operations, try the other pair if that one
4789 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
4791 other
= XEXP (XEXP (x
, 0), 1);
4792 inner
= simplify_binary_operation (code
, mode
,
4793 XEXP (XEXP (x
, 0), 0),
4798 return simplify_gen_binary (code
, mode
, other
, inner
);
4802 /* A little bit of algebraic simplification here. */
4806 /* Ensure that our address has any ASHIFTs converted to MULT in case
4807 address-recognizing predicates are called later. */
4808 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
4809 SUBST (XEXP (x
, 0), temp
);
4813 if (op0_mode
== VOIDmode
)
4814 op0_mode
= GET_MODE (SUBREG_REG (x
));
4816 /* See if this can be moved to simplify_subreg. */
4817 if (CONSTANT_P (SUBREG_REG (x
))
4818 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
4819 /* Don't call gen_lowpart if the inner mode
4820 is VOIDmode and we cannot simplify it, as SUBREG without
4821 inner mode is invalid. */
4822 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
4823 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
4824 return gen_lowpart (mode
, SUBREG_REG (x
));
4826 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
4830 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4836 /* Don't change the mode of the MEM if that would change the meaning
4838 if (MEM_P (SUBREG_REG (x
))
4839 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4840 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4841 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4843 /* Note that we cannot do any narrowing for non-constants since
4844 we might have been counting on using the fact that some bits were
4845 zero. We now do this in the SET. */
4850 temp
= expand_compound_operation (XEXP (x
, 0));
4852 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4853 replaced by (lshiftrt X C). This will convert
4854 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4856 if (GET_CODE (temp
) == ASHIFTRT
4857 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4858 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4859 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4860 INTVAL (XEXP (temp
, 1)));
4862 /* If X has only a single bit that might be nonzero, say, bit I, convert
4863 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4864 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4865 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4866 or a SUBREG of one since we'd be making the expression more
4867 complex if it was just a register. */
4870 && ! (GET_CODE (temp
) == SUBREG
4871 && REG_P (SUBREG_REG (temp
)))
4872 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4874 rtx temp1
= simplify_shift_const
4875 (NULL_RTX
, ASHIFTRT
, mode
,
4876 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4877 GET_MODE_BITSIZE (mode
) - 1 - i
),
4878 GET_MODE_BITSIZE (mode
) - 1 - i
);
4880 /* If all we did was surround TEMP with the two shifts, we
4881 haven't improved anything, so don't use it. Otherwise,
4882 we are better off with TEMP1. */
4883 if (GET_CODE (temp1
) != ASHIFTRT
4884 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4885 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4891 /* We can't handle truncation to a partial integer mode here
4892 because we don't know the real bitsize of the partial
4894 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4897 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4898 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4899 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4901 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4902 GET_MODE_MASK (mode
), 0));
4904 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4905 whose value is a comparison can be replaced with a subreg if
4906 STORE_FLAG_VALUE permits. */
4907 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4908 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4909 && (temp
= get_last_value (XEXP (x
, 0)))
4910 && COMPARISON_P (temp
))
4911 return gen_lowpart (mode
, XEXP (x
, 0));
4916 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4917 using cc0, in which case we want to leave it as a COMPARE
4918 so we can distinguish it from a register-register-copy. */
4919 if (XEXP (x
, 1) == const0_rtx
)
4922 /* x - 0 is the same as x unless x's mode has signed zeros and
4923 allows rounding towards -infinity. Under those conditions,
4925 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4926 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4927 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4933 /* (const (const X)) can become (const X). Do it this way rather than
4934 returning the inner CONST since CONST can be shared with a
4936 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4937 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4942 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4943 can add in an offset. find_split_point will split this address up
4944 again if it doesn't match. */
4945 if (GET_CODE (XEXP (x
, 0)) == HIGH
4946 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4952 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4953 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4954 bit-field and can be replaced by either a sign_extend or a
4955 sign_extract. The `and' may be a zero_extend and the two
4956 <c>, -<c> constants may be reversed. */
4957 if (GET_CODE (XEXP (x
, 0)) == XOR
4958 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4959 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4960 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4961 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4962 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4963 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4964 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4965 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4966 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4967 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4968 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4969 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4970 == (unsigned int) i
+ 1))))
4971 return simplify_shift_const
4972 (NULL_RTX
, ASHIFTRT
, mode
,
4973 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4974 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4975 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4976 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4978 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4979 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4980 the bitsize of the mode - 1. This allows simplification of
4981 "a = (b & 8) == 0;" */
4982 if (XEXP (x
, 1) == constm1_rtx
4983 && !REG_P (XEXP (x
, 0))
4984 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4985 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4986 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4987 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4988 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4989 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4990 GET_MODE_BITSIZE (mode
) - 1),
4991 GET_MODE_BITSIZE (mode
) - 1);
4993 /* If we are adding two things that have no bits in common, convert
4994 the addition into an IOR. This will often be further simplified,
4995 for example in cases like ((a & 1) + (a & 2)), which can
4998 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4999 && (nonzero_bits (XEXP (x
, 0), mode
)
5000 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5002 /* Try to simplify the expression further. */
5003 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5004 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5006 /* If we could, great. If not, do not go ahead with the IOR
5007 replacement, since PLUS appears in many special purpose
5008 address arithmetic instructions. */
5009 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5015 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5016 (and <foo> (const_int pow2-1)) */
5017 if (GET_CODE (XEXP (x
, 1)) == AND
5018 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5019 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5020 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5021 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5022 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5026 /* If we have (mult (plus A B) C), apply the distributive law and then
5027 the inverse distributive law to see if things simplify. This
5028 occurs mostly in addresses, often when unrolling loops. */
5030 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5032 rtx result
= distribute_and_simplify_rtx (x
, 0);
5037 /* Try simplify a*(b/c) as (a*b)/c. */
5038 if (FLOAT_MODE_P (mode
) && flag_associative_math
5039 && GET_CODE (XEXP (x
, 0)) == DIV
)
5041 rtx tem
= simplify_binary_operation (MULT
, mode
,
5042 XEXP (XEXP (x
, 0), 0),
5045 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5050 /* If this is a divide by a power of two, treat it as a shift if
5051 its first operand is a shift. */
5052 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5053 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
5054 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5055 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5056 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5057 || GET_CODE (XEXP (x
, 0)) == ROTATE
5058 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5059 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5063 case GT
: case GTU
: case GE
: case GEU
:
5064 case LT
: case LTU
: case LE
: case LEU
:
5065 case UNEQ
: case LTGT
:
5066 case UNGT
: case UNGE
:
5067 case UNLT
: case UNLE
:
5068 case UNORDERED
: case ORDERED
:
5069 /* If the first operand is a condition code, we can't do anything
5071 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5072 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5073 && ! CC0_P (XEXP (x
, 0))))
5075 rtx op0
= XEXP (x
, 0);
5076 rtx op1
= XEXP (x
, 1);
5077 enum rtx_code new_code
;
5079 if (GET_CODE (op0
) == COMPARE
)
5080 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5082 /* Simplify our comparison, if possible. */
5083 new_code
= simplify_comparison (code
, &op0
, &op1
);
5085 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5086 if only the low-order bit is possibly nonzero in X (such as when
5087 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5088 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5089 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5092 Remove any ZERO_EXTRACT we made when thinking this was a
5093 comparison. It may now be simpler to use, e.g., an AND. If a
5094 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5095 the call to make_compound_operation in the SET case. */
5097 if (STORE_FLAG_VALUE
== 1
5098 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5099 && op1
== const0_rtx
5100 && mode
== GET_MODE (op0
)
5101 && nonzero_bits (op0
, mode
) == 1)
5102 return gen_lowpart (mode
,
5103 expand_compound_operation (op0
));
5105 else if (STORE_FLAG_VALUE
== 1
5106 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5107 && op1
== const0_rtx
5108 && mode
== GET_MODE (op0
)
5109 && (num_sign_bit_copies (op0
, mode
)
5110 == GET_MODE_BITSIZE (mode
)))
5112 op0
= expand_compound_operation (op0
);
5113 return simplify_gen_unary (NEG
, mode
,
5114 gen_lowpart (mode
, op0
),
5118 else if (STORE_FLAG_VALUE
== 1
5119 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5120 && op1
== const0_rtx
5121 && mode
== GET_MODE (op0
)
5122 && nonzero_bits (op0
, mode
) == 1)
5124 op0
= expand_compound_operation (op0
);
5125 return simplify_gen_binary (XOR
, mode
,
5126 gen_lowpart (mode
, op0
),
5130 else if (STORE_FLAG_VALUE
== 1
5131 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5132 && op1
== const0_rtx
5133 && mode
== GET_MODE (op0
)
5134 && (num_sign_bit_copies (op0
, mode
)
5135 == GET_MODE_BITSIZE (mode
)))
5137 op0
= expand_compound_operation (op0
);
5138 return plus_constant (gen_lowpart (mode
, op0
), 1);
5141 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5143 if (STORE_FLAG_VALUE
== -1
5144 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5145 && op1
== const0_rtx
5146 && (num_sign_bit_copies (op0
, mode
)
5147 == GET_MODE_BITSIZE (mode
)))
5148 return gen_lowpart (mode
,
5149 expand_compound_operation (op0
));
5151 else if (STORE_FLAG_VALUE
== -1
5152 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5153 && op1
== const0_rtx
5154 && mode
== GET_MODE (op0
)
5155 && nonzero_bits (op0
, mode
) == 1)
5157 op0
= expand_compound_operation (op0
);
5158 return simplify_gen_unary (NEG
, mode
,
5159 gen_lowpart (mode
, op0
),
5163 else if (STORE_FLAG_VALUE
== -1
5164 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5165 && op1
== const0_rtx
5166 && mode
== GET_MODE (op0
)
5167 && (num_sign_bit_copies (op0
, mode
)
5168 == GET_MODE_BITSIZE (mode
)))
5170 op0
= expand_compound_operation (op0
);
5171 return simplify_gen_unary (NOT
, mode
,
5172 gen_lowpart (mode
, op0
),
5176 /* If X is 0/1, (eq X 0) is X-1. */
5177 else if (STORE_FLAG_VALUE
== -1
5178 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5179 && op1
== const0_rtx
5180 && mode
== GET_MODE (op0
)
5181 && nonzero_bits (op0
, mode
) == 1)
5183 op0
= expand_compound_operation (op0
);
5184 return plus_constant (gen_lowpart (mode
, op0
), -1);
5187 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5188 one bit that might be nonzero, we can convert (ne x 0) to
5189 (ashift x c) where C puts the bit in the sign bit. Remove any
5190 AND with STORE_FLAG_VALUE when we are done, since we are only
5191 going to test the sign bit. */
5192 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5193 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5194 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5195 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5196 && op1
== const0_rtx
5197 && mode
== GET_MODE (op0
)
5198 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5200 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5201 expand_compound_operation (op0
),
5202 GET_MODE_BITSIZE (mode
) - 1 - i
);
5203 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5209 /* If the code changed, return a whole new comparison. */
5210 if (new_code
!= code
)
5211 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5213 /* Otherwise, keep this operation, but maybe change its operands.
5214 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5215 SUBST (XEXP (x
, 0), op0
);
5216 SUBST (XEXP (x
, 1), op1
);
5221 return simplify_if_then_else (x
);
5227 /* If we are processing SET_DEST, we are done. */
5231 return expand_compound_operation (x
);
5234 return simplify_set (x
);
5238 return simplify_logical (x
);
5245 /* If this is a shift by a constant amount, simplify it. */
5246 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5247 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5248 INTVAL (XEXP (x
, 1)));
5250 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5252 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5254 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5266 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5269 simplify_if_then_else (rtx x
)
5271 enum machine_mode mode
= GET_MODE (x
);
5272 rtx cond
= XEXP (x
, 0);
5273 rtx true_rtx
= XEXP (x
, 1);
5274 rtx false_rtx
= XEXP (x
, 2);
5275 enum rtx_code true_code
= GET_CODE (cond
);
5276 int comparison_p
= COMPARISON_P (cond
);
5279 enum rtx_code false_code
;
5282 /* Simplify storing of the truth value. */
5283 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5284 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5285 XEXP (cond
, 0), XEXP (cond
, 1));
5287 /* Also when the truth value has to be reversed. */
5289 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5290 && (reversed
= reversed_comparison (cond
, mode
)))
5293 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5294 in it is being compared against certain values. Get the true and false
5295 comparisons and see if that says anything about the value of each arm. */
5298 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5300 && REG_P (XEXP (cond
, 0)))
5303 rtx from
= XEXP (cond
, 0);
5304 rtx true_val
= XEXP (cond
, 1);
5305 rtx false_val
= true_val
;
5308 /* If FALSE_CODE is EQ, swap the codes and arms. */
5310 if (false_code
== EQ
)
5312 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5313 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5316 /* If we are comparing against zero and the expression being tested has
5317 only a single bit that might be nonzero, that is its value when it is
5318 not equal to zero. Similarly if it is known to be -1 or 0. */
5320 if (true_code
== EQ
&& true_val
== const0_rtx
5321 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5324 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5326 else if (true_code
== EQ
&& true_val
== const0_rtx
5327 && (num_sign_bit_copies (from
, GET_MODE (from
))
5328 == GET_MODE_BITSIZE (GET_MODE (from
))))
5331 false_val
= constm1_rtx
;
5334 /* Now simplify an arm if we know the value of the register in the
5335 branch and it is used in the arm. Be careful due to the potential
5336 of locally-shared RTL. */
5338 if (reg_mentioned_p (from
, true_rtx
))
5339 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5341 pc_rtx
, pc_rtx
, 0, 0);
5342 if (reg_mentioned_p (from
, false_rtx
))
5343 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5345 pc_rtx
, pc_rtx
, 0, 0);
5347 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5348 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5350 true_rtx
= XEXP (x
, 1);
5351 false_rtx
= XEXP (x
, 2);
5352 true_code
= GET_CODE (cond
);
5355 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5356 reversed, do so to avoid needing two sets of patterns for
5357 subtract-and-branch insns. Similarly if we have a constant in the true
5358 arm, the false arm is the same as the first operand of the comparison, or
5359 the false arm is more complicated than the true arm. */
5362 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5363 && (true_rtx
== pc_rtx
5364 || (CONSTANT_P (true_rtx
)
5365 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
5366 || true_rtx
== const0_rtx
5367 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5368 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5369 && !OBJECT_P (false_rtx
))
5370 || reg_mentioned_p (true_rtx
, false_rtx
)
5371 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5373 true_code
= reversed_comparison_code (cond
, NULL
);
5374 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5375 SUBST (XEXP (x
, 1), false_rtx
);
5376 SUBST (XEXP (x
, 2), true_rtx
);
5378 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5381 /* It is possible that the conditional has been simplified out. */
5382 true_code
= GET_CODE (cond
);
5383 comparison_p
= COMPARISON_P (cond
);
5386 /* If the two arms are identical, we don't need the comparison. */
5388 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5391 /* Convert a == b ? b : a to "a". */
5392 if (true_code
== EQ
&& ! side_effects_p (cond
)
5393 && !HONOR_NANS (mode
)
5394 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5395 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5397 else if (true_code
== NE
&& ! side_effects_p (cond
)
5398 && !HONOR_NANS (mode
)
5399 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5400 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5403 /* Look for cases where we have (abs x) or (neg (abs X)). */
5405 if (GET_MODE_CLASS (mode
) == MODE_INT
5407 && XEXP (cond
, 1) == const0_rtx
5408 && GET_CODE (false_rtx
) == NEG
5409 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5410 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5411 && ! side_effects_p (true_rtx
))
5416 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5420 simplify_gen_unary (NEG
, mode
,
5421 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5427 /* Look for MIN or MAX. */
5429 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5431 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5432 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5433 && ! side_effects_p (cond
))
5438 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5441 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5444 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5447 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5452 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5453 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5454 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5455 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5456 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5457 neither 1 or -1, but it isn't worth checking for. */
5459 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5461 && GET_MODE_CLASS (mode
) == MODE_INT
5462 && ! side_effects_p (x
))
5464 rtx t
= make_compound_operation (true_rtx
, SET
);
5465 rtx f
= make_compound_operation (false_rtx
, SET
);
5466 rtx cond_op0
= XEXP (cond
, 0);
5467 rtx cond_op1
= XEXP (cond
, 1);
5468 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
5469 enum machine_mode m
= mode
;
5470 rtx z
= 0, c1
= NULL_RTX
;
5472 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5473 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5474 || GET_CODE (t
) == ASHIFT
5475 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5476 && rtx_equal_p (XEXP (t
, 0), f
))
5477 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5479 /* If an identity-zero op is commutative, check whether there
5480 would be a match if we swapped the operands. */
5481 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5482 || GET_CODE (t
) == XOR
)
5483 && rtx_equal_p (XEXP (t
, 1), f
))
5484 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5485 else if (GET_CODE (t
) == SIGN_EXTEND
5486 && (GET_CODE (XEXP (t
, 0)) == PLUS
5487 || GET_CODE (XEXP (t
, 0)) == MINUS
5488 || GET_CODE (XEXP (t
, 0)) == IOR
5489 || GET_CODE (XEXP (t
, 0)) == XOR
5490 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5491 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5492 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5493 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5494 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5495 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5496 && (num_sign_bit_copies (f
, GET_MODE (f
))
5498 (GET_MODE_BITSIZE (mode
)
5499 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5501 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5502 extend_op
= SIGN_EXTEND
;
5503 m
= GET_MODE (XEXP (t
, 0));
5505 else if (GET_CODE (t
) == SIGN_EXTEND
5506 && (GET_CODE (XEXP (t
, 0)) == PLUS
5507 || GET_CODE (XEXP (t
, 0)) == IOR
5508 || GET_CODE (XEXP (t
, 0)) == XOR
)
5509 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5510 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5511 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5512 && (num_sign_bit_copies (f
, GET_MODE (f
))
5514 (GET_MODE_BITSIZE (mode
)
5515 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5517 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5518 extend_op
= SIGN_EXTEND
;
5519 m
= GET_MODE (XEXP (t
, 0));
5521 else if (GET_CODE (t
) == ZERO_EXTEND
5522 && (GET_CODE (XEXP (t
, 0)) == PLUS
5523 || GET_CODE (XEXP (t
, 0)) == MINUS
5524 || GET_CODE (XEXP (t
, 0)) == IOR
5525 || GET_CODE (XEXP (t
, 0)) == XOR
5526 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5527 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5528 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5529 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5530 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5531 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5532 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5533 && ((nonzero_bits (f
, GET_MODE (f
))
5534 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5537 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5538 extend_op
= ZERO_EXTEND
;
5539 m
= GET_MODE (XEXP (t
, 0));
5541 else if (GET_CODE (t
) == ZERO_EXTEND
5542 && (GET_CODE (XEXP (t
, 0)) == PLUS
5543 || GET_CODE (XEXP (t
, 0)) == IOR
5544 || GET_CODE (XEXP (t
, 0)) == XOR
)
5545 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5546 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5547 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5548 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5549 && ((nonzero_bits (f
, GET_MODE (f
))
5550 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5553 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5554 extend_op
= ZERO_EXTEND
;
5555 m
= GET_MODE (XEXP (t
, 0));
5560 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5561 cond_op0
, cond_op1
),
5562 pc_rtx
, pc_rtx
, 0, 0);
5563 temp
= simplify_gen_binary (MULT
, m
, temp
,
5564 simplify_gen_binary (MULT
, m
, c1
,
5566 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5567 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5569 if (extend_op
!= UNKNOWN
)
5570 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5576 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5577 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5578 negation of a single bit, we can convert this operation to a shift. We
5579 can actually do this more generally, but it doesn't seem worth it. */
5581 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5582 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5583 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5584 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5585 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5586 == GET_MODE_BITSIZE (mode
))
5587 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5589 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5590 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5592 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5593 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5594 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5595 && GET_MODE (XEXP (cond
, 0)) == mode
5596 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5597 == nonzero_bits (XEXP (cond
, 0), mode
)
5598 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5599 return XEXP (cond
, 0);
5604 /* Simplify X, a SET expression. Return the new expression. */
5607 simplify_set (rtx x
)
5609 rtx src
= SET_SRC (x
);
5610 rtx dest
= SET_DEST (x
);
5611 enum machine_mode mode
5612 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5616 /* (set (pc) (return)) gets written as (return). */
5617 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5620 /* Now that we know for sure which bits of SRC we are using, see if we can
5621 simplify the expression for the object knowing that we only need the
5624 if (GET_MODE_CLASS (mode
) == MODE_INT
5625 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5627 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
5628 SUBST (SET_SRC (x
), src
);
5631 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5632 the comparison result and try to simplify it unless we already have used
5633 undobuf.other_insn. */
5634 if ((GET_MODE_CLASS (mode
) == MODE_CC
5635 || GET_CODE (src
) == COMPARE
5637 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5638 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5639 && COMPARISON_P (*cc_use
)
5640 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5642 enum rtx_code old_code
= GET_CODE (*cc_use
);
5643 enum rtx_code new_code
;
5645 int other_changed
= 0;
5646 enum machine_mode compare_mode
= GET_MODE (dest
);
5648 if (GET_CODE (src
) == COMPARE
)
5649 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5651 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5653 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5656 new_code
= old_code
;
5657 else if (!CONSTANT_P (tmp
))
5659 new_code
= GET_CODE (tmp
);
5660 op0
= XEXP (tmp
, 0);
5661 op1
= XEXP (tmp
, 1);
5665 rtx pat
= PATTERN (other_insn
);
5666 undobuf
.other_insn
= other_insn
;
5667 SUBST (*cc_use
, tmp
);
5669 /* Attempt to simplify CC user. */
5670 if (GET_CODE (pat
) == SET
)
5672 rtx
new = simplify_rtx (SET_SRC (pat
));
5673 if (new != NULL_RTX
)
5674 SUBST (SET_SRC (pat
), new);
5677 /* Convert X into a no-op move. */
5678 SUBST (SET_DEST (x
), pc_rtx
);
5679 SUBST (SET_SRC (x
), pc_rtx
);
5683 /* Simplify our comparison, if possible. */
5684 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5686 #ifdef SELECT_CC_MODE
5687 /* If this machine has CC modes other than CCmode, check to see if we
5688 need to use a different CC mode here. */
5689 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5690 compare_mode
= GET_MODE (op0
);
5692 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5695 /* If the mode changed, we have to change SET_DEST, the mode in the
5696 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5697 a hard register, just build new versions with the proper mode. If it
5698 is a pseudo, we lose unless it is only time we set the pseudo, in
5699 which case we can safely change its mode. */
5700 if (compare_mode
!= GET_MODE (dest
))
5702 if (can_change_dest_mode (dest
, 0, compare_mode
))
5704 unsigned int regno
= REGNO (dest
);
5707 if (regno
< FIRST_PSEUDO_REGISTER
)
5708 new_dest
= gen_rtx_REG (compare_mode
, regno
);
5711 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
5712 new_dest
= regno_reg_rtx
[regno
];
5715 SUBST (SET_DEST (x
), new_dest
);
5716 SUBST (XEXP (*cc_use
, 0), new_dest
);
5723 #endif /* SELECT_CC_MODE */
5725 /* If the code changed, we have to build a new comparison in
5726 undobuf.other_insn. */
5727 if (new_code
!= old_code
)
5729 int other_changed_previously
= other_changed
;
5730 unsigned HOST_WIDE_INT mask
;
5732 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5736 /* If the only change we made was to change an EQ into an NE or
5737 vice versa, OP0 has only one bit that might be nonzero, and OP1
5738 is zero, check if changing the user of the condition code will
5739 produce a valid insn. If it won't, we can keep the original code
5740 in that insn by surrounding our operation with an XOR. */
5742 if (((old_code
== NE
&& new_code
== EQ
)
5743 || (old_code
== EQ
&& new_code
== NE
))
5744 && ! other_changed_previously
&& op1
== const0_rtx
5745 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5746 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5748 rtx pat
= PATTERN (other_insn
), note
= 0;
5750 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5751 && ! check_asm_operands (pat
)))
5753 PUT_CODE (*cc_use
, old_code
);
5756 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5757 op0
, GEN_INT (mask
));
5763 undobuf
.other_insn
= other_insn
;
5766 /* If we are now comparing against zero, change our source if
5767 needed. If we do not use cc0, we always have a COMPARE. */
5768 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5770 SUBST (SET_SRC (x
), op0
);
5776 /* Otherwise, if we didn't previously have a COMPARE in the
5777 correct mode, we need one. */
5778 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5780 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5783 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5785 SUBST (SET_SRC (x
), op0
);
5788 /* Otherwise, update the COMPARE if needed. */
5789 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
5791 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5797 /* Get SET_SRC in a form where we have placed back any
5798 compound expressions. Then do the checks below. */
5799 src
= make_compound_operation (src
, SET
);
5800 SUBST (SET_SRC (x
), src
);
5803 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5804 and X being a REG or (subreg (reg)), we may be able to convert this to
5805 (set (subreg:m2 x) (op)).
5807 We can always do this if M1 is narrower than M2 because that means that
5808 we only care about the low bits of the result.
5810 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5811 perform a narrower operation than requested since the high-order bits will
5812 be undefined. On machine where it is defined, this transformation is safe
5813 as long as M1 and M2 have the same number of words. */
5815 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5816 && !OBJECT_P (SUBREG_REG (src
))
5817 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5819 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5820 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5821 #ifndef WORD_REGISTER_OPERATIONS
5822 && (GET_MODE_SIZE (GET_MODE (src
))
5823 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5825 #ifdef CANNOT_CHANGE_MODE_CLASS
5826 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5827 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5828 GET_MODE (SUBREG_REG (src
)),
5832 || (GET_CODE (dest
) == SUBREG
5833 && REG_P (SUBREG_REG (dest
)))))
5835 SUBST (SET_DEST (x
),
5836 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5838 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5840 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5844 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5847 && GET_CODE (src
) == SUBREG
5848 && subreg_lowpart_p (src
)
5849 && (GET_MODE_BITSIZE (GET_MODE (src
))
5850 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5852 rtx inner
= SUBREG_REG (src
);
5853 enum machine_mode inner_mode
= GET_MODE (inner
);
5855 /* Here we make sure that we don't have a sign bit on. */
5856 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5857 && (nonzero_bits (inner
, inner_mode
)
5858 < ((unsigned HOST_WIDE_INT
) 1
5859 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5861 SUBST (SET_SRC (x
), inner
);
5867 #ifdef LOAD_EXTEND_OP
5868 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5869 would require a paradoxical subreg. Replace the subreg with a
5870 zero_extend to avoid the reload that would otherwise be required. */
5872 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5873 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5874 && SUBREG_BYTE (src
) == 0
5875 && (GET_MODE_SIZE (GET_MODE (src
))
5876 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5877 && MEM_P (SUBREG_REG (src
)))
5880 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5881 GET_MODE (src
), SUBREG_REG (src
)));
5887 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5888 are comparing an item known to be 0 or -1 against 0, use a logical
5889 operation instead. Check for one of the arms being an IOR of the other
5890 arm with some value. We compute three terms to be IOR'ed together. In
5891 practice, at most two will be nonzero. Then we do the IOR's. */
5893 if (GET_CODE (dest
) != PC
5894 && GET_CODE (src
) == IF_THEN_ELSE
5895 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5896 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5897 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5898 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5899 #ifdef HAVE_conditional_move
5900 && ! can_conditionally_move_p (GET_MODE (src
))
5902 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5903 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5904 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5905 && ! side_effects_p (src
))
5907 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5908 ? XEXP (src
, 1) : XEXP (src
, 2));
5909 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5910 ? XEXP (src
, 2) : XEXP (src
, 1));
5911 rtx term1
= const0_rtx
, term2
, term3
;
5913 if (GET_CODE (true_rtx
) == IOR
5914 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5915 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5916 else if (GET_CODE (true_rtx
) == IOR
5917 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5918 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5919 else if (GET_CODE (false_rtx
) == IOR
5920 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5921 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5922 else if (GET_CODE (false_rtx
) == IOR
5923 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5924 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5926 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5927 XEXP (XEXP (src
, 0), 0), true_rtx
);
5928 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5929 simplify_gen_unary (NOT
, GET_MODE (src
),
5930 XEXP (XEXP (src
, 0), 0),
5935 simplify_gen_binary (IOR
, GET_MODE (src
),
5936 simplify_gen_binary (IOR
, GET_MODE (src
),
5943 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5944 whole thing fail. */
5945 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5947 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5950 /* Convert this into a field assignment operation, if possible. */
5951 return make_field_assignment (x
);
5954 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5958 simplify_logical (rtx x
)
5960 enum machine_mode mode
= GET_MODE (x
);
5961 rtx op0
= XEXP (x
, 0);
5962 rtx op1
= XEXP (x
, 1);
5964 switch (GET_CODE (x
))
5967 /* We can call simplify_and_const_int only if we don't lose
5968 any (sign) bits when converting INTVAL (op1) to
5969 "unsigned HOST_WIDE_INT". */
5970 if (GET_CODE (op1
) == CONST_INT
5971 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5972 || INTVAL (op1
) > 0))
5974 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5975 if (GET_CODE (x
) != AND
)
5982 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5983 apply the distributive law and then the inverse distributive
5984 law to see if things simplify. */
5985 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5987 rtx result
= distribute_and_simplify_rtx (x
, 0);
5991 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5993 rtx result
= distribute_and_simplify_rtx (x
, 1);
6000 /* If we have (ior (and A B) C), apply the distributive law and then
6001 the inverse distributive law to see if things simplify. */
6003 if (GET_CODE (op0
) == AND
)
6005 rtx result
= distribute_and_simplify_rtx (x
, 0);
6010 if (GET_CODE (op1
) == AND
)
6012 rtx result
= distribute_and_simplify_rtx (x
, 1);
6025 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6026 operations" because they can be replaced with two more basic operations.
6027 ZERO_EXTEND is also considered "compound" because it can be replaced with
6028 an AND operation, which is simpler, though only one operation.
6030 The function expand_compound_operation is called with an rtx expression
6031 and will convert it to the appropriate shifts and AND operations,
6032 simplifying at each stage.
6034 The function make_compound_operation is called to convert an expression
6035 consisting of shifts and ANDs into the equivalent compound expression.
6036 It is the inverse of this function, loosely speaking. */
6039 expand_compound_operation (rtx x
)
6041 unsigned HOST_WIDE_INT pos
= 0, len
;
6043 unsigned int modewidth
;
6046 switch (GET_CODE (x
))
6051 /* We can't necessarily use a const_int for a multiword mode;
6052 it depends on implicitly extending the value.
6053 Since we don't know the right way to extend it,
6054 we can't tell whether the implicit way is right.
6056 Even for a mode that is no wider than a const_int,
6057 we can't win, because we need to sign extend one of its bits through
6058 the rest of it, and we don't know which bit. */
6059 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
6062 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6063 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6064 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6065 reloaded. If not for that, MEM's would very rarely be safe.
6067 Reject MODEs bigger than a word, because we might not be able
6068 to reference a two-register group starting with an arbitrary register
6069 (and currently gen_lowpart might crash for a SUBREG). */
6071 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6074 /* Reject MODEs that aren't scalar integers because turning vector
6075 or complex modes into shifts causes problems. */
6077 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6080 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6081 /* If the inner object has VOIDmode (the only way this can happen
6082 is if it is an ASM_OPERANDS), we can't do anything since we don't
6083 know how much masking to do. */
6092 /* ... fall through ... */
6095 /* If the operand is a CLOBBER, just return it. */
6096 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6099 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
6100 || GET_CODE (XEXP (x
, 2)) != CONST_INT
6101 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6104 /* Reject MODEs that aren't scalar integers because turning vector
6105 or complex modes into shifts causes problems. */
6107 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6110 len
= INTVAL (XEXP (x
, 1));
6111 pos
= INTVAL (XEXP (x
, 2));
6113 /* This should stay within the object being extracted, fail otherwise. */
6114 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6117 if (BITS_BIG_ENDIAN
)
6118 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6125 /* Convert sign extension to zero extension, if we know that the high
6126 bit is not set, as this is easier to optimize. It will be converted
6127 back to cheaper alternative in make_extraction. */
6128 if (GET_CODE (x
) == SIGN_EXTEND
6129 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6130 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6131 & ~(((unsigned HOST_WIDE_INT
)
6132 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6136 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6137 rtx temp2
= expand_compound_operation (temp
);
6139 /* Make sure this is a profitable operation. */
6140 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
6142 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
6148 /* We can optimize some special cases of ZERO_EXTEND. */
6149 if (GET_CODE (x
) == ZERO_EXTEND
)
6151 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6152 know that the last value didn't have any inappropriate bits
6154 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6155 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6156 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6157 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6158 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6159 return XEXP (XEXP (x
, 0), 0);
6161 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6162 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6163 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6164 && subreg_lowpart_p (XEXP (x
, 0))
6165 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6166 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6167 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6168 return SUBREG_REG (XEXP (x
, 0));
6170 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6171 is a comparison and STORE_FLAG_VALUE permits. This is like
6172 the first case, but it works even when GET_MODE (x) is larger
6173 than HOST_WIDE_INT. */
6174 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6175 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6176 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6177 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6178 <= HOST_BITS_PER_WIDE_INT
)
6179 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6180 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6181 return XEXP (XEXP (x
, 0), 0);
6183 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6184 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6185 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6186 && subreg_lowpart_p (XEXP (x
, 0))
6187 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6188 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6189 <= HOST_BITS_PER_WIDE_INT
)
6190 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6191 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6192 return SUBREG_REG (XEXP (x
, 0));
6196 /* If we reach here, we want to return a pair of shifts. The inner
6197 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6198 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6199 logical depending on the value of UNSIGNEDP.
6201 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6202 converted into an AND of a shift.
6204 We must check for the case where the left shift would have a negative
6205 count. This can happen in a case like (x >> 31) & 255 on machines
6206 that can't shift by a constant. On those machines, we would first
6207 combine the shift with the AND to produce a variable-position
6208 extraction. Then the constant of 31 would be substituted in to produce
6209 a such a position. */
6211 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6212 if (modewidth
+ len
>= pos
)
6214 enum machine_mode mode
= GET_MODE (x
);
6215 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6216 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6218 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6219 tem
, modewidth
- pos
- len
);
6220 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6221 mode
, tem
, modewidth
- len
);
6223 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6224 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6225 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6228 ((HOST_WIDE_INT
) 1 << len
) - 1);
6230 /* Any other cases we can't handle. */
6233 /* If we couldn't do this for some reason, return the original
6235 if (GET_CODE (tem
) == CLOBBER
)
6241 /* X is a SET which contains an assignment of one object into
6242 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6243 or certain SUBREGS). If possible, convert it into a series of
6246 We half-heartedly support variable positions, but do not at all
6247 support variable lengths. */
6250 expand_field_assignment (const_rtx x
)
6253 rtx pos
; /* Always counts from low bit. */
6255 rtx mask
, cleared
, masked
;
6256 enum machine_mode compute_mode
;
6258 /* Loop until we find something we can't simplify. */
6261 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6262 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6264 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6265 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6266 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6268 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6269 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
6271 inner
= XEXP (SET_DEST (x
), 0);
6272 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6273 pos
= XEXP (SET_DEST (x
), 2);
6275 /* A constant position should stay within the width of INNER. */
6276 if (GET_CODE (pos
) == CONST_INT
6277 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6280 if (BITS_BIG_ENDIAN
)
6282 if (GET_CODE (pos
) == CONST_INT
)
6283 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6285 else if (GET_CODE (pos
) == MINUS
6286 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
6287 && (INTVAL (XEXP (pos
, 1))
6288 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6289 /* If position is ADJUST - X, new position is X. */
6290 pos
= XEXP (pos
, 0);
6292 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6293 GEN_INT (GET_MODE_BITSIZE (
6300 /* A SUBREG between two modes that occupy the same numbers of words
6301 can be done by moving the SUBREG to the source. */
6302 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6303 /* We need SUBREGs to compute nonzero_bits properly. */
6304 && nonzero_sign_valid
6305 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6306 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6307 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6308 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6310 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6312 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6319 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6320 inner
= SUBREG_REG (inner
);
6322 compute_mode
= GET_MODE (inner
);
6324 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6325 if (! SCALAR_INT_MODE_P (compute_mode
))
6327 enum machine_mode imode
;
6329 /* Don't do anything for vector or complex integral types. */
6330 if (! FLOAT_MODE_P (compute_mode
))
6333 /* Try to find an integral mode to pun with. */
6334 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6335 if (imode
== BLKmode
)
6338 compute_mode
= imode
;
6339 inner
= gen_lowpart (imode
, inner
);
6342 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6343 if (len
>= HOST_BITS_PER_WIDE_INT
)
6346 /* Now compute the equivalent expression. Make a copy of INNER
6347 for the SET_DEST in case it is a MEM into which we will substitute;
6348 we don't want shared RTL in that case. */
6349 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6350 cleared
= simplify_gen_binary (AND
, compute_mode
,
6351 simplify_gen_unary (NOT
, compute_mode
,
6352 simplify_gen_binary (ASHIFT
,
6357 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6358 simplify_gen_binary (
6360 gen_lowpart (compute_mode
, SET_SRC (x
)),
6364 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6365 simplify_gen_binary (IOR
, compute_mode
,
6372 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6373 it is an RTX that represents a variable starting position; otherwise,
6374 POS is the (constant) starting bit position (counted from the LSB).
6376 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6379 IN_DEST is nonzero if this is a reference in the destination of a
6380 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6381 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6384 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6385 ZERO_EXTRACT should be built even for bits starting at bit 0.
6387 MODE is the desired mode of the result (if IN_DEST == 0).
6389 The result is an RTX for the extraction or NULL_RTX if the target
6393 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6394 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6395 int in_dest
, int in_compare
)
6397 /* This mode describes the size of the storage area
6398 to fetch the overall value from. Within that, we
6399 ignore the POS lowest bits, etc. */
6400 enum machine_mode is_mode
= GET_MODE (inner
);
6401 enum machine_mode inner_mode
;
6402 enum machine_mode wanted_inner_mode
;
6403 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6404 enum machine_mode pos_mode
= word_mode
;
6405 enum machine_mode extraction_mode
= word_mode
;
6406 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6408 rtx orig_pos_rtx
= pos_rtx
;
6409 HOST_WIDE_INT orig_pos
;
6411 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6413 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6414 consider just the QI as the memory to extract from.
6415 The subreg adds or removes high bits; its mode is
6416 irrelevant to the meaning of this extraction,
6417 since POS and LEN count from the lsb. */
6418 if (MEM_P (SUBREG_REG (inner
)))
6419 is_mode
= GET_MODE (SUBREG_REG (inner
));
6420 inner
= SUBREG_REG (inner
);
6422 else if (GET_CODE (inner
) == ASHIFT
6423 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6424 && pos_rtx
== 0 && pos
== 0
6425 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6427 /* We're extracting the least significant bits of an rtx
6428 (ashift X (const_int C)), where LEN > C. Extract the
6429 least significant (LEN - C) bits of X, giving an rtx
6430 whose mode is MODE, then shift it left C times. */
6431 new = make_extraction (mode
, XEXP (inner
, 0),
6432 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6433 unsignedp
, in_dest
, in_compare
);
6435 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6438 inner_mode
= GET_MODE (inner
);
6440 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6441 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6443 /* See if this can be done without an extraction. We never can if the
6444 width of the field is not the same as that of some integer mode. For
6445 registers, we can only avoid the extraction if the position is at the
6446 low-order bit and this is either not in the destination or we have the
6447 appropriate STRICT_LOW_PART operation available.
6449 For MEM, we can avoid an extract if the field starts on an appropriate
6450 boundary and we can change the mode of the memory reference. */
6452 if (tmode
!= BLKmode
6453 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6455 && (inner_mode
== tmode
6457 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
6458 GET_MODE_BITSIZE (inner_mode
))
6459 || reg_truncated_to_mode (tmode
, inner
))
6462 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6463 || (MEM_P (inner
) && pos_rtx
== 0
6465 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6466 : BITS_PER_UNIT
)) == 0
6467 /* We can't do this if we are widening INNER_MODE (it
6468 may not be aligned, for one thing). */
6469 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6470 && (inner_mode
== tmode
6471 || (! mode_dependent_address_p (XEXP (inner
, 0))
6472 && ! MEM_VOLATILE_P (inner
))))))
6474 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6475 field. If the original and current mode are the same, we need not
6476 adjust the offset. Otherwise, we do if bytes big endian.
6478 If INNER is not a MEM, get a piece consisting of just the field
6479 of interest (in this case POS % BITS_PER_WORD must be 0). */
6483 HOST_WIDE_INT offset
;
6485 /* POS counts from lsb, but make OFFSET count in memory order. */
6486 if (BYTES_BIG_ENDIAN
)
6487 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6489 offset
= pos
/ BITS_PER_UNIT
;
6491 new = adjust_address_nv (inner
, tmode
, offset
);
6493 else if (REG_P (inner
))
6495 if (tmode
!= inner_mode
)
6497 /* We can't call gen_lowpart in a DEST since we
6498 always want a SUBREG (see below) and it would sometimes
6499 return a new hard register. */
6502 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6504 if (WORDS_BIG_ENDIAN
6505 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6506 final_word
= ((GET_MODE_SIZE (inner_mode
)
6507 - GET_MODE_SIZE (tmode
))
6508 / UNITS_PER_WORD
) - final_word
;
6510 final_word
*= UNITS_PER_WORD
;
6511 if (BYTES_BIG_ENDIAN
&&
6512 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6513 final_word
+= (GET_MODE_SIZE (inner_mode
)
6514 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6516 /* Avoid creating invalid subregs, for example when
6517 simplifying (x>>32)&255. */
6518 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
6521 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6524 new = gen_lowpart (tmode
, inner
);
6530 new = force_to_mode (inner
, tmode
,
6531 len
>= HOST_BITS_PER_WIDE_INT
6532 ? ~(unsigned HOST_WIDE_INT
) 0
6533 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6536 /* If this extraction is going into the destination of a SET,
6537 make a STRICT_LOW_PART unless we made a MEM. */
6540 return (MEM_P (new) ? new
6541 : (GET_CODE (new) != SUBREG
6542 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6543 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6548 if (GET_CODE (new) == CONST_INT
)
6549 return gen_int_mode (INTVAL (new), mode
);
6551 /* If we know that no extraneous bits are set, and that the high
6552 bit is not set, convert the extraction to the cheaper of
6553 sign and zero extension, that are equivalent in these cases. */
6554 if (flag_expensive_optimizations
6555 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6556 && ((nonzero_bits (new, tmode
)
6557 & ~(((unsigned HOST_WIDE_INT
)
6558 GET_MODE_MASK (tmode
))
6562 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6563 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6565 /* Prefer ZERO_EXTENSION, since it gives more information to
6567 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6572 /* Otherwise, sign- or zero-extend unless we already are in the
6575 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6579 /* Unless this is a COMPARE or we have a funny memory reference,
6580 don't do anything with zero-extending field extracts starting at
6581 the low-order bit since they are simple AND operations. */
6582 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6583 && ! in_compare
&& unsignedp
)
6586 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6587 if the position is not a constant and the length is not 1. In all
6588 other cases, we would only be going outside our object in cases when
6589 an original shift would have been undefined. */
6591 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6592 || (pos_rtx
!= 0 && len
!= 1)))
6595 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6596 and the mode for the result. */
6597 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6599 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6600 pos_mode
= mode_for_extraction (EP_insv
, 2);
6601 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6604 if (! in_dest
&& unsignedp
6605 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6607 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6608 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6609 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6612 if (! in_dest
&& ! unsignedp
6613 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6615 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6616 pos_mode
= mode_for_extraction (EP_extv
, 3);
6617 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6620 /* Never narrow an object, since that might not be safe. */
6622 if (mode
!= VOIDmode
6623 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6624 extraction_mode
= mode
;
6626 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6627 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6628 pos_mode
= GET_MODE (pos_rtx
);
6630 /* If this is not from memory, the desired mode is the preferred mode
6631 for an extraction pattern's first input operand, or word_mode if there
6634 wanted_inner_mode
= wanted_inner_reg_mode
;
6637 /* Be careful not to go beyond the extracted object and maintain the
6638 natural alignment of the memory. */
6639 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
6640 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
6641 > GET_MODE_BITSIZE (wanted_inner_mode
))
6643 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
6644 gcc_assert (wanted_inner_mode
!= VOIDmode
);
6647 /* If we have to change the mode of memory and cannot, the desired mode
6648 is EXTRACTION_MODE. */
6649 if (inner_mode
!= wanted_inner_mode
6650 && (mode_dependent_address_p (XEXP (inner
, 0))
6651 || MEM_VOLATILE_P (inner
)
6653 wanted_inner_mode
= extraction_mode
;
6658 if (BITS_BIG_ENDIAN
)
6660 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6661 BITS_BIG_ENDIAN style. If position is constant, compute new
6662 position. Otherwise, build subtraction.
6663 Note that POS is relative to the mode of the original argument.
6664 If it's a MEM we need to recompute POS relative to that.
6665 However, if we're extracting from (or inserting into) a register,
6666 we want to recompute POS relative to wanted_inner_mode. */
6667 int width
= (MEM_P (inner
)
6668 ? GET_MODE_BITSIZE (is_mode
)
6669 : GET_MODE_BITSIZE (wanted_inner_mode
));
6672 pos
= width
- len
- pos
;
6675 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6676 /* POS may be less than 0 now, but we check for that below.
6677 Note that it can only be less than 0 if !MEM_P (inner). */
6680 /* If INNER has a wider mode, and this is a constant extraction, try to
6681 make it smaller and adjust the byte to point to the byte containing
6683 if (wanted_inner_mode
!= VOIDmode
6684 && inner_mode
!= wanted_inner_mode
6686 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6688 && ! mode_dependent_address_p (XEXP (inner
, 0))
6689 && ! MEM_VOLATILE_P (inner
))
6693 /* The computations below will be correct if the machine is big
6694 endian in both bits and bytes or little endian in bits and bytes.
6695 If it is mixed, we must adjust. */
6697 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6698 adjust OFFSET to compensate. */
6699 if (BYTES_BIG_ENDIAN
6700 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6701 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6703 /* We can now move to the desired byte. */
6704 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
6705 * GET_MODE_SIZE (wanted_inner_mode
);
6706 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6708 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6709 && is_mode
!= wanted_inner_mode
)
6710 offset
= (GET_MODE_SIZE (is_mode
)
6711 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6713 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6716 /* If INNER is not memory, we can always get it into the proper mode. If we
6717 are changing its mode, POS must be a constant and smaller than the size
6719 else if (!MEM_P (inner
))
6721 if (GET_MODE (inner
) != wanted_inner_mode
6723 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6729 inner
= force_to_mode (inner
, wanted_inner_mode
,
6731 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6732 ? ~(unsigned HOST_WIDE_INT
) 0
6733 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6738 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6739 have to zero extend. Otherwise, we can just use a SUBREG. */
6741 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6743 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6745 /* If we know that no extraneous bits are set, and that the high
6746 bit is not set, convert extraction to cheaper one - either
6747 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6749 if (flag_expensive_optimizations
6750 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6751 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6752 & ~(((unsigned HOST_WIDE_INT
)
6753 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6757 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6759 /* Prefer ZERO_EXTENSION, since it gives more information to
6761 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6766 else if (pos_rtx
!= 0
6767 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6768 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6770 /* Make POS_RTX unless we already have it and it is correct. If we don't
6771 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6773 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6774 pos_rtx
= orig_pos_rtx
;
6776 else if (pos_rtx
== 0)
6777 pos_rtx
= GEN_INT (pos
);
6779 /* Make the required operation. See if we can use existing rtx. */
6780 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6781 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6783 new = gen_lowpart (mode
, new);
6788 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6789 with any other operations in X. Return X without that shift if so. */
6792 extract_left_shift (rtx x
, int count
)
6794 enum rtx_code code
= GET_CODE (x
);
6795 enum machine_mode mode
= GET_MODE (x
);
6801 /* This is the shift itself. If it is wide enough, we will return
6802 either the value being shifted if the shift count is equal to
6803 COUNT or a shift for the difference. */
6804 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6805 && INTVAL (XEXP (x
, 1)) >= count
)
6806 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6807 INTVAL (XEXP (x
, 1)) - count
);
6811 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6812 return simplify_gen_unary (code
, mode
, tem
, mode
);
6816 case PLUS
: case IOR
: case XOR
: case AND
:
6817 /* If we can safely shift this constant and we find the inner shift,
6818 make a new operation. */
6819 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6820 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6821 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6822 return simplify_gen_binary (code
, mode
, tem
,
6823 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6834 /* Look at the expression rooted at X. Look for expressions
6835 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6836 Form these expressions.
6838 Return the new rtx, usually just X.
6840 Also, for machines like the VAX that don't have logical shift insns,
6841 try to convert logical to arithmetic shift operations in cases where
6842 they are equivalent. This undoes the canonicalizations to logical
6843 shifts done elsewhere.
6845 We try, as much as possible, to re-use rtl expressions to save memory.
6847 IN_CODE says what kind of expression we are processing. Normally, it is
6848 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6849 being kludges), it is MEM. When processing the arguments of a comparison
6850 or a COMPARE against zero, it is COMPARE. */
6853 make_compound_operation (rtx x
, enum rtx_code in_code
)
6855 enum rtx_code code
= GET_CODE (x
);
6856 enum machine_mode mode
= GET_MODE (x
);
6857 int mode_width
= GET_MODE_BITSIZE (mode
);
6859 enum rtx_code next_code
;
6865 /* Select the code to be used in recursive calls. Once we are inside an
6866 address, we stay there. If we have a comparison, set to COMPARE,
6867 but once inside, go back to our default of SET. */
6869 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6870 : ((code
== COMPARE
|| COMPARISON_P (x
))
6871 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6872 : in_code
== COMPARE
? SET
: in_code
);
6874 /* Process depending on the code of this operation. If NEW is set
6875 nonzero, it will be returned. */
6880 /* Convert shifts by constants into multiplications if inside
6882 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6883 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6884 && INTVAL (XEXP (x
, 1)) >= 0)
6886 new = make_compound_operation (XEXP (x
, 0), next_code
);
6887 new = gen_rtx_MULT (mode
, new,
6888 GEN_INT ((HOST_WIDE_INT
) 1
6889 << INTVAL (XEXP (x
, 1))));
6894 /* If the second operand is not a constant, we can't do anything
6896 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6899 /* If the constant is a power of two minus one and the first operand
6900 is a logical right shift, make an extraction. */
6901 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6902 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6904 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6905 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6906 0, in_code
== COMPARE
);
6909 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6910 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6911 && subreg_lowpart_p (XEXP (x
, 0))
6912 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6913 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6915 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6917 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6918 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6919 0, in_code
== COMPARE
);
6921 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6922 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6923 || GET_CODE (XEXP (x
, 0)) == IOR
)
6924 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6925 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6926 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6928 /* Apply the distributive law, and then try to make extractions. */
6929 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6930 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6932 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6934 new = make_compound_operation (new, in_code
);
6937 /* If we are have (and (rotate X C) M) and C is larger than the number
6938 of bits in M, this is an extraction. */
6940 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6941 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6942 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6943 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6945 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6946 new = make_extraction (mode
, new,
6947 (GET_MODE_BITSIZE (mode
)
6948 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6949 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6952 /* On machines without logical shifts, if the operand of the AND is
6953 a logical shift and our mask turns off all the propagated sign
6954 bits, we can replace the logical shift with an arithmetic shift. */
6955 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6956 && !have_insn_for (LSHIFTRT
, mode
)
6957 && have_insn_for (ASHIFTRT
, mode
)
6958 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6959 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6960 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6961 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6963 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6965 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6966 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6968 gen_rtx_ASHIFTRT (mode
,
6969 make_compound_operation
6970 (XEXP (XEXP (x
, 0), 0), next_code
),
6971 XEXP (XEXP (x
, 0), 1)));
6974 /* If the constant is one less than a power of two, this might be
6975 representable by an extraction even if no shift is present.
6976 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6977 we are in a COMPARE. */
6978 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6979 new = make_extraction (mode
,
6980 make_compound_operation (XEXP (x
, 0),
6982 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6984 /* If we are in a comparison and this is an AND with a power of two,
6985 convert this into the appropriate bit extract. */
6986 else if (in_code
== COMPARE
6987 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6988 new = make_extraction (mode
,
6989 make_compound_operation (XEXP (x
, 0),
6991 i
, NULL_RTX
, 1, 1, 0, 1);
6996 /* If the sign bit is known to be zero, replace this with an
6997 arithmetic shift. */
6998 if (have_insn_for (ASHIFTRT
, mode
)
6999 && ! have_insn_for (LSHIFTRT
, mode
)
7000 && mode_width
<= HOST_BITS_PER_WIDE_INT
7001 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7003 new = gen_rtx_ASHIFTRT (mode
,
7004 make_compound_operation (XEXP (x
, 0),
7010 /* ... fall through ... */
7016 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7017 this is a SIGN_EXTRACT. */
7018 if (GET_CODE (rhs
) == CONST_INT
7019 && GET_CODE (lhs
) == ASHIFT
7020 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7021 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
7023 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
7024 new = make_extraction (mode
, new,
7025 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7026 NULL_RTX
, mode_width
- INTVAL (rhs
),
7027 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7031 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7032 If so, try to merge the shifts into a SIGN_EXTEND. We could
7033 also do this for some cases of SIGN_EXTRACT, but it doesn't
7034 seem worth the effort; the case checked for occurs on Alpha. */
7037 && ! (GET_CODE (lhs
) == SUBREG
7038 && (OBJECT_P (SUBREG_REG (lhs
))))
7039 && GET_CODE (rhs
) == CONST_INT
7040 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7041 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7042 new = make_extraction (mode
, make_compound_operation (new, next_code
),
7043 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7044 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7049 /* Call ourselves recursively on the inner expression. If we are
7050 narrowing the object and it has a different RTL code from
7051 what it originally did, do this SUBREG as a force_to_mode. */
7053 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
7057 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
7063 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
7064 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
7065 && subreg_lowpart_p (x
))
7067 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
7070 /* If we have something other than a SUBREG, we might have
7071 done an expansion, so rerun ourselves. */
7072 if (GET_CODE (newer
) != SUBREG
)
7073 newer
= make_compound_operation (newer
, in_code
);
7089 x
= gen_lowpart (mode
, new);
7090 code
= GET_CODE (x
);
7093 /* Now recursively process each operand of this operation. */
7094 fmt
= GET_RTX_FORMAT (code
);
7095 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7098 new = make_compound_operation (XEXP (x
, i
), next_code
);
7099 SUBST (XEXP (x
, i
), new);
7102 /* If this is a commutative operation, the changes to the operands
7103 may have made it noncanonical. */
7104 if (COMMUTATIVE_ARITH_P (x
)
7105 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7108 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7109 SUBST (XEXP (x
, 1), tem
);
7115 /* Given M see if it is a value that would select a field of bits
7116 within an item, but not the entire word. Return -1 if not.
7117 Otherwise, return the starting position of the field, where 0 is the
7120 *PLEN is set to the length of the field. */
7123 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7125 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7126 int pos
= exact_log2 (m
& -m
);
7130 /* Now shift off the low-order zero bits and see if we have a
7131 power of two minus 1. */
7132 len
= exact_log2 ((m
>> pos
) + 1);
7141 /* If X refers to a register that equals REG in value, replace these
7142 references with REG. */
7144 canon_reg_for_combine (rtx x
, rtx reg
)
7151 enum rtx_code code
= GET_CODE (x
);
7152 switch (GET_RTX_CLASS (code
))
7155 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7156 if (op0
!= XEXP (x
, 0))
7157 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7162 case RTX_COMM_ARITH
:
7163 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7164 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7165 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7166 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7170 case RTX_COMM_COMPARE
:
7171 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7172 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7173 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7174 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7175 GET_MODE (op0
), op0
, op1
);
7179 case RTX_BITFIELD_OPS
:
7180 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7181 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7182 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7183 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7184 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7185 GET_MODE (op0
), op0
, op1
, op2
);
7190 if (rtx_equal_p (get_last_value (reg
), x
)
7191 || rtx_equal_p (reg
, get_last_value (x
)))
7200 fmt
= GET_RTX_FORMAT (code
);
7202 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7205 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7206 if (op
!= XEXP (x
, i
))
7216 else if (fmt
[i
] == 'E')
7219 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7221 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7222 if (op
!= XVECEXP (x
, i
, j
))
7229 XVECEXP (x
, i
, j
) = op
;
7240 /* Return X converted to MODE. If the value is already truncated to
7241 MODE we can just return a subreg even though in the general case we
7242 would need an explicit truncation. */
7245 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7247 if (GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (mode
)
7248 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7249 GET_MODE_BITSIZE (GET_MODE (x
)))
7250 || (REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7251 return gen_lowpart (mode
, x
);
7253 return simplify_gen_unary (TRUNCATE
, mode
, x
, GET_MODE (x
));
7256 /* See if X can be simplified knowing that we will only refer to it in
7257 MODE and will only refer to those bits that are nonzero in MASK.
7258 If other bits are being computed or if masking operations are done
7259 that select a superset of the bits in MASK, they can sometimes be
7262 Return a possibly simplified expression, but always convert X to
7263 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7265 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7266 are all off in X. This is used when X will be complemented, by either
7267 NOT, NEG, or XOR. */
7270 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7273 enum rtx_code code
= GET_CODE (x
);
7274 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7275 enum machine_mode op_mode
;
7276 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7279 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7280 code below will do the wrong thing since the mode of such an
7281 expression is VOIDmode.
7283 Also do nothing if X is a CLOBBER; this can happen if X was
7284 the return value from a call to gen_lowpart. */
7285 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7288 /* We want to perform the operation is its present mode unless we know
7289 that the operation is valid in MODE, in which case we do the operation
7291 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7292 && have_insn_for (code
, mode
))
7293 ? mode
: GET_MODE (x
));
7295 /* It is not valid to do a right-shift in a narrower mode
7296 than the one it came in with. */
7297 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7298 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7299 op_mode
= GET_MODE (x
);
7301 /* Truncate MASK to fit OP_MODE. */
7303 mask
&= GET_MODE_MASK (op_mode
);
7305 /* When we have an arithmetic operation, or a shift whose count we
7306 do not know, we need to assume that all bits up to the highest-order
7307 bit in MASK will be needed. This is how we form such a mask. */
7308 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7309 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7311 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7314 /* Determine what bits of X are guaranteed to be (non)zero. */
7315 nonzero
= nonzero_bits (x
, mode
);
7317 /* If none of the bits in X are needed, return a zero. */
7318 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
7321 /* If X is a CONST_INT, return a new one. Do this here since the
7322 test below will fail. */
7323 if (GET_CODE (x
) == CONST_INT
)
7325 if (SCALAR_INT_MODE_P (mode
))
7326 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7329 x
= GEN_INT (INTVAL (x
) & mask
);
7330 return gen_lowpart_common (mode
, x
);
7334 /* If X is narrower than MODE and we want all the bits in X's mode, just
7335 get X in the proper mode. */
7336 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7337 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7338 return gen_lowpart (mode
, x
);
7343 /* If X is a (clobber (const_int)), return it since we know we are
7344 generating something that won't match. */
7351 x
= expand_compound_operation (x
);
7352 if (GET_CODE (x
) != code
)
7353 return force_to_mode (x
, mode
, mask
, next_select
);
7357 if (subreg_lowpart_p (x
)
7358 /* We can ignore the effect of this SUBREG if it narrows the mode or
7359 if the constant masks to zero all the bits the mode doesn't
7361 && ((GET_MODE_SIZE (GET_MODE (x
))
7362 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7364 & GET_MODE_MASK (GET_MODE (x
))
7365 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7366 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
7370 /* If this is an AND with a constant, convert it into an AND
7371 whose constant is the AND of that constant with MASK. If it
7372 remains an AND of MASK, delete it since it is redundant. */
7374 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7376 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7377 mask
& INTVAL (XEXP (x
, 1)));
7379 /* If X is still an AND, see if it is an AND with a mask that
7380 is just some low-order bits. If so, and it is MASK, we don't
7383 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7384 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7388 /* If it remains an AND, try making another AND with the bits
7389 in the mode mask that aren't in MASK turned on. If the
7390 constant in the AND is wide enough, this might make a
7391 cheaper constant. */
7393 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7394 && GET_MODE_MASK (GET_MODE (x
)) != mask
7395 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7397 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7398 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7399 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7402 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7403 number, sign extend it. */
7404 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7405 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7406 cval
|= (HOST_WIDE_INT
) -1 << width
;
7408 y
= simplify_gen_binary (AND
, GET_MODE (x
),
7409 XEXP (x
, 0), GEN_INT (cval
));
7410 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7420 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7421 low-order bits (as in an alignment operation) and FOO is already
7422 aligned to that boundary, mask C1 to that boundary as well.
7423 This may eliminate that PLUS and, later, the AND. */
7426 unsigned int width
= GET_MODE_BITSIZE (mode
);
7427 unsigned HOST_WIDE_INT smask
= mask
;
7429 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7430 number, sign extend it. */
7432 if (width
< HOST_BITS_PER_WIDE_INT
7433 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7434 smask
|= (HOST_WIDE_INT
) -1 << width
;
7436 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7437 && exact_log2 (- smask
) >= 0
7438 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7439 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7440 return force_to_mode (plus_constant (XEXP (x
, 0),
7441 (INTVAL (XEXP (x
, 1)) & smask
)),
7442 mode
, smask
, next_select
);
7445 /* ... fall through ... */
7448 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7449 most significant bit in MASK since carries from those bits will
7450 affect the bits we are interested in. */
7455 /* If X is (minus C Y) where C's least set bit is larger than any bit
7456 in the mask, then we may replace with (neg Y). */
7457 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7458 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7459 & -INTVAL (XEXP (x
, 0))))
7462 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7464 return force_to_mode (x
, mode
, mask
, next_select
);
7467 /* Similarly, if C contains every bit in the fuller_mask, then we may
7468 replace with (not Y). */
7469 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7470 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7471 == INTVAL (XEXP (x
, 0))))
7473 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7474 XEXP (x
, 1), GET_MODE (x
));
7475 return force_to_mode (x
, mode
, mask
, next_select
);
7483 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7484 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7485 operation which may be a bitfield extraction. Ensure that the
7486 constant we form is not wider than the mode of X. */
7488 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7489 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7490 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7491 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7492 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7493 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7494 + floor_log2 (INTVAL (XEXP (x
, 1))))
7495 < GET_MODE_BITSIZE (GET_MODE (x
)))
7496 && (INTVAL (XEXP (x
, 1))
7497 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7499 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7500 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7501 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7502 XEXP (XEXP (x
, 0), 0), temp
);
7503 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7504 XEXP (XEXP (x
, 0), 1));
7505 return force_to_mode (x
, mode
, mask
, next_select
);
7509 /* For most binary operations, just propagate into the operation and
7510 change the mode if we have an operation of that mode. */
7512 op0
= gen_lowpart_or_truncate (op_mode
,
7513 force_to_mode (XEXP (x
, 0), mode
, mask
,
7515 op1
= gen_lowpart_or_truncate (op_mode
,
7516 force_to_mode (XEXP (x
, 1), mode
, mask
,
7519 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7520 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7524 /* For left shifts, do the same, but just for the first operand.
7525 However, we cannot do anything with shifts where we cannot
7526 guarantee that the counts are smaller than the size of the mode
7527 because such a count will have a different meaning in a
7530 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7531 && INTVAL (XEXP (x
, 1)) >= 0
7532 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7533 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7534 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7535 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7538 /* If the shift count is a constant and we can do arithmetic in
7539 the mode of the shift, refine which bits we need. Otherwise, use the
7540 conservative form of the mask. */
7541 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7542 && INTVAL (XEXP (x
, 1)) >= 0
7543 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7544 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7545 mask
>>= INTVAL (XEXP (x
, 1));
7549 op0
= gen_lowpart_or_truncate (op_mode
,
7550 force_to_mode (XEXP (x
, 0), op_mode
,
7551 mask
, next_select
));
7553 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7554 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7558 /* Here we can only do something if the shift count is a constant,
7559 this shift constant is valid for the host, and we can do arithmetic
7562 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7563 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7564 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7566 rtx inner
= XEXP (x
, 0);
7567 unsigned HOST_WIDE_INT inner_mask
;
7569 /* Select the mask of the bits we need for the shift operand. */
7570 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7572 /* We can only change the mode of the shift if we can do arithmetic
7573 in the mode of the shift and INNER_MASK is no wider than the
7574 width of X's mode. */
7575 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7576 op_mode
= GET_MODE (x
);
7578 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
7580 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7581 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7584 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7585 shift and AND produces only copies of the sign bit (C2 is one less
7586 than a power of two), we can do this with just a shift. */
7588 if (GET_CODE (x
) == LSHIFTRT
7589 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7590 /* The shift puts one of the sign bit copies in the least significant
7592 && ((INTVAL (XEXP (x
, 1))
7593 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7594 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7595 && exact_log2 (mask
+ 1) >= 0
7596 /* Number of bits left after the shift must be more than the mask
7598 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7599 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7600 /* Must be more sign bit copies than the mask needs. */
7601 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7602 >= exact_log2 (mask
+ 1)))
7603 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7604 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7605 - exact_log2 (mask
+ 1)));
7610 /* If we are just looking for the sign bit, we don't need this shift at
7611 all, even if it has a variable count. */
7612 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7613 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7614 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7615 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7617 /* If this is a shift by a constant, get a mask that contains those bits
7618 that are not copies of the sign bit. We then have two cases: If
7619 MASK only includes those bits, this can be a logical shift, which may
7620 allow simplifications. If MASK is a single-bit field not within
7621 those bits, we are requesting a copy of the sign bit and hence can
7622 shift the sign bit to the appropriate location. */
7624 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7625 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7629 /* If the considered data is wider than HOST_WIDE_INT, we can't
7630 represent a mask for all its bits in a single scalar.
7631 But we only care about the lower bits, so calculate these. */
7633 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7635 nonzero
= ~(HOST_WIDE_INT
) 0;
7637 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7638 is the number of bits a full-width mask would have set.
7639 We need only shift if these are fewer than nonzero can
7640 hold. If not, we must keep all bits set in nonzero. */
7642 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7643 < HOST_BITS_PER_WIDE_INT
)
7644 nonzero
>>= INTVAL (XEXP (x
, 1))
7645 + HOST_BITS_PER_WIDE_INT
7646 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7650 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7651 nonzero
>>= INTVAL (XEXP (x
, 1));
7654 if ((mask
& ~nonzero
) == 0)
7656 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
7657 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
7658 if (GET_CODE (x
) != ASHIFTRT
)
7659 return force_to_mode (x
, mode
, mask
, next_select
);
7662 else if ((i
= exact_log2 (mask
)) >= 0)
7664 x
= simplify_shift_const
7665 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7666 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7668 if (GET_CODE (x
) != ASHIFTRT
)
7669 return force_to_mode (x
, mode
, mask
, next_select
);
7673 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7674 even if the shift count isn't a constant. */
7676 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7677 XEXP (x
, 0), XEXP (x
, 1));
7681 /* If this is a zero- or sign-extension operation that just affects bits
7682 we don't care about, remove it. Be sure the call above returned
7683 something that is still a shift. */
7685 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7686 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7687 && INTVAL (XEXP (x
, 1)) >= 0
7688 && (INTVAL (XEXP (x
, 1))
7689 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7690 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7691 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7692 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7699 /* If the shift count is constant and we can do computations
7700 in the mode of X, compute where the bits we care about are.
7701 Otherwise, we can't do anything. Don't change the mode of
7702 the shift or propagate MODE into the shift, though. */
7703 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7704 && INTVAL (XEXP (x
, 1)) >= 0)
7706 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7707 GET_MODE (x
), GEN_INT (mask
),
7709 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7711 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7712 INTVAL (temp
), next_select
));
7717 /* If we just want the low-order bit, the NEG isn't needed since it
7718 won't change the low-order bit. */
7720 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
7722 /* We need any bits less significant than the most significant bit in
7723 MASK since carries from those bits will affect the bits we are
7729 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7730 same as the XOR case above. Ensure that the constant we form is not
7731 wider than the mode of X. */
7733 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7734 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7735 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7736 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7737 < GET_MODE_BITSIZE (GET_MODE (x
)))
7738 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7740 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7742 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7743 XEXP (XEXP (x
, 0), 0), temp
);
7744 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7745 temp
, XEXP (XEXP (x
, 0), 1));
7747 return force_to_mode (x
, mode
, mask
, next_select
);
7750 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7751 use the full mask inside the NOT. */
7755 op0
= gen_lowpart_or_truncate (op_mode
,
7756 force_to_mode (XEXP (x
, 0), mode
, mask
,
7758 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7759 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7763 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7764 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7765 which is equal to STORE_FLAG_VALUE. */
7766 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7767 && GET_MODE (XEXP (x
, 0)) == mode
7768 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7769 && (nonzero_bits (XEXP (x
, 0), mode
)
7770 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7771 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7776 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7777 written in a narrower mode. We play it safe and do not do so. */
7780 gen_lowpart_or_truncate (GET_MODE (x
),
7781 force_to_mode (XEXP (x
, 1), mode
,
7782 mask
, next_select
)));
7784 gen_lowpart_or_truncate (GET_MODE (x
),
7785 force_to_mode (XEXP (x
, 2), mode
,
7786 mask
, next_select
)));
7793 /* Ensure we return a value of the proper mode. */
7794 return gen_lowpart_or_truncate (mode
, x
);
7797 /* Return nonzero if X is an expression that has one of two values depending on
7798 whether some other value is zero or nonzero. In that case, we return the
7799 value that is being tested, *PTRUE is set to the value if the rtx being
7800 returned has a nonzero value, and *PFALSE is set to the other alternative.
7802 If we return zero, we set *PTRUE and *PFALSE to X. */
7805 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7807 enum machine_mode mode
= GET_MODE (x
);
7808 enum rtx_code code
= GET_CODE (x
);
7809 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7810 unsigned HOST_WIDE_INT nz
;
7812 /* If we are comparing a value against zero, we are done. */
7813 if ((code
== NE
|| code
== EQ
)
7814 && XEXP (x
, 1) == const0_rtx
)
7816 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7817 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7821 /* If this is a unary operation whose operand has one of two values, apply
7822 our opcode to compute those values. */
7823 else if (UNARY_P (x
)
7824 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7826 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7827 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7828 GET_MODE (XEXP (x
, 0)));
7832 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7833 make can't possibly match and would suppress other optimizations. */
7834 else if (code
== COMPARE
)
7837 /* If this is a binary operation, see if either side has only one of two
7838 values. If either one does or if both do and they are conditional on
7839 the same value, compute the new true and false values. */
7840 else if (BINARY_P (x
))
7842 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7843 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7845 if ((cond0
!= 0 || cond1
!= 0)
7846 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7848 /* If if_then_else_cond returned zero, then true/false are the
7849 same rtl. We must copy one of them to prevent invalid rtl
7852 true0
= copy_rtx (true0
);
7853 else if (cond1
== 0)
7854 true1
= copy_rtx (true1
);
7856 if (COMPARISON_P (x
))
7858 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7860 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7865 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7866 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7869 return cond0
? cond0
: cond1
;
7872 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7873 operands is zero when the other is nonzero, and vice-versa,
7874 and STORE_FLAG_VALUE is 1 or -1. */
7876 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7877 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7879 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7881 rtx op0
= XEXP (XEXP (x
, 0), 1);
7882 rtx op1
= XEXP (XEXP (x
, 1), 1);
7884 cond0
= XEXP (XEXP (x
, 0), 0);
7885 cond1
= XEXP (XEXP (x
, 1), 0);
7887 if (COMPARISON_P (cond0
)
7888 && COMPARISON_P (cond1
)
7889 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7890 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7891 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7892 || ((swap_condition (GET_CODE (cond0
))
7893 == reversed_comparison_code (cond1
, NULL
))
7894 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7895 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7896 && ! side_effects_p (x
))
7898 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7899 *pfalse
= simplify_gen_binary (MULT
, mode
,
7901 ? simplify_gen_unary (NEG
, mode
,
7909 /* Similarly for MULT, AND and UMIN, except that for these the result
7911 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7912 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7913 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7915 cond0
= XEXP (XEXP (x
, 0), 0);
7916 cond1
= XEXP (XEXP (x
, 1), 0);
7918 if (COMPARISON_P (cond0
)
7919 && COMPARISON_P (cond1
)
7920 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7921 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7922 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7923 || ((swap_condition (GET_CODE (cond0
))
7924 == reversed_comparison_code (cond1
, NULL
))
7925 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7926 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7927 && ! side_effects_p (x
))
7929 *ptrue
= *pfalse
= const0_rtx
;
7935 else if (code
== IF_THEN_ELSE
)
7937 /* If we have IF_THEN_ELSE already, extract the condition and
7938 canonicalize it if it is NE or EQ. */
7939 cond0
= XEXP (x
, 0);
7940 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7941 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7942 return XEXP (cond0
, 0);
7943 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7945 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7946 return XEXP (cond0
, 0);
7952 /* If X is a SUBREG, we can narrow both the true and false values
7953 if the inner expression, if there is a condition. */
7954 else if (code
== SUBREG
7955 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7958 true0
= simplify_gen_subreg (mode
, true0
,
7959 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7960 false0
= simplify_gen_subreg (mode
, false0
,
7961 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7962 if (true0
&& false0
)
7970 /* If X is a constant, this isn't special and will cause confusions
7971 if we treat it as such. Likewise if it is equivalent to a constant. */
7972 else if (CONSTANT_P (x
)
7973 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7976 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7977 will be least confusing to the rest of the compiler. */
7978 else if (mode
== BImode
)
7980 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7984 /* If X is known to be either 0 or -1, those are the true and
7985 false values when testing X. */
7986 else if (x
== constm1_rtx
|| x
== const0_rtx
7987 || (mode
!= VOIDmode
7988 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7990 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7994 /* Likewise for 0 or a single bit. */
7995 else if (SCALAR_INT_MODE_P (mode
)
7996 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7997 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7999 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8003 /* Otherwise fail; show no condition with true and false values the same. */
8004 *ptrue
= *pfalse
= x
;
8008 /* Return the value of expression X given the fact that condition COND
8009 is known to be true when applied to REG as its first operand and VAL
8010 as its second. X is known to not be shared and so can be modified in
8013 We only handle the simplest cases, and specifically those cases that
8014 arise with IF_THEN_ELSE expressions. */
8017 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8019 enum rtx_code code
= GET_CODE (x
);
8024 if (side_effects_p (x
))
8027 /* If either operand of the condition is a floating point value,
8028 then we have to avoid collapsing an EQ comparison. */
8030 && rtx_equal_p (x
, reg
)
8031 && ! FLOAT_MODE_P (GET_MODE (x
))
8032 && ! FLOAT_MODE_P (GET_MODE (val
)))
8035 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8038 /* If X is (abs REG) and we know something about REG's relationship
8039 with zero, we may be able to simplify this. */
8041 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8044 case GE
: case GT
: case EQ
:
8047 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8049 GET_MODE (XEXP (x
, 0)));
8054 /* The only other cases we handle are MIN, MAX, and comparisons if the
8055 operands are the same as REG and VAL. */
8057 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8059 if (rtx_equal_p (XEXP (x
, 0), val
))
8060 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8062 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8064 if (COMPARISON_P (x
))
8066 if (comparison_dominates_p (cond
, code
))
8067 return const_true_rtx
;
8069 code
= reversed_comparison_code (x
, NULL
);
8071 && comparison_dominates_p (cond
, code
))
8076 else if (code
== SMAX
|| code
== SMIN
8077 || code
== UMIN
|| code
== UMAX
)
8079 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8081 /* Do not reverse the condition when it is NE or EQ.
8082 This is because we cannot conclude anything about
8083 the value of 'SMAX (x, y)' when x is not equal to y,
8084 but we can when x equals y. */
8085 if ((code
== SMAX
|| code
== UMAX
)
8086 && ! (cond
== EQ
|| cond
== NE
))
8087 cond
= reverse_condition (cond
);
8092 return unsignedp
? x
: XEXP (x
, 1);
8094 return unsignedp
? x
: XEXP (x
, 0);
8096 return unsignedp
? XEXP (x
, 1) : x
;
8098 return unsignedp
? XEXP (x
, 0) : x
;
8105 else if (code
== SUBREG
)
8107 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8108 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8110 if (SUBREG_REG (x
) != r
)
8112 /* We must simplify subreg here, before we lose track of the
8113 original inner_mode. */
8114 new = simplify_subreg (GET_MODE (x
), r
,
8115 inner_mode
, SUBREG_BYTE (x
));
8119 SUBST (SUBREG_REG (x
), r
);
8124 /* We don't have to handle SIGN_EXTEND here, because even in the
8125 case of replacing something with a modeless CONST_INT, a
8126 CONST_INT is already (supposed to be) a valid sign extension for
8127 its narrower mode, which implies it's already properly
8128 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8129 story is different. */
8130 else if (code
== ZERO_EXTEND
)
8132 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8133 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8135 if (XEXP (x
, 0) != r
)
8137 /* We must simplify the zero_extend here, before we lose
8138 track of the original inner_mode. */
8139 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8144 SUBST (XEXP (x
, 0), r
);
8150 fmt
= GET_RTX_FORMAT (code
);
8151 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8154 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8155 else if (fmt
[i
] == 'E')
8156 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8157 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8164 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8165 assignment as a field assignment. */
8168 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8170 if (x
== y
|| rtx_equal_p (x
, y
))
8173 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8176 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8177 Note that all SUBREGs of MEM are paradoxical; otherwise they
8178 would have been rewritten. */
8179 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8180 && MEM_P (SUBREG_REG (y
))
8181 && rtx_equal_p (SUBREG_REG (y
),
8182 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8185 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8186 && MEM_P (SUBREG_REG (x
))
8187 && rtx_equal_p (SUBREG_REG (x
),
8188 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8191 /* We used to see if get_last_value of X and Y were the same but that's
8192 not correct. In one direction, we'll cause the assignment to have
8193 the wrong destination and in the case, we'll import a register into this
8194 insn that might have already have been dead. So fail if none of the
8195 above cases are true. */
8199 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8200 Return that assignment if so.
8202 We only handle the most common cases. */
8205 make_field_assignment (rtx x
)
8207 rtx dest
= SET_DEST (x
);
8208 rtx src
= SET_SRC (x
);
8213 unsigned HOST_WIDE_INT len
;
8215 enum machine_mode mode
;
8217 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8218 a clear of a one-bit field. We will have changed it to
8219 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8222 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8223 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
8224 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8225 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8227 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8230 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8234 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8235 && subreg_lowpart_p (XEXP (src
, 0))
8236 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8237 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8238 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8239 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
8240 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8241 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8243 assign
= make_extraction (VOIDmode
, dest
, 0,
8244 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8247 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8251 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8253 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8254 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8255 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8257 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8260 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8264 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8265 SRC is an AND with all bits of that field set, then we can discard
8267 if (GET_CODE (dest
) == ZERO_EXTRACT
8268 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
8269 && GET_CODE (src
) == AND
8270 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
8272 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8273 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8274 unsigned HOST_WIDE_INT ze_mask
;
8276 if (width
>= HOST_BITS_PER_WIDE_INT
)
8279 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8281 /* Complete overlap. We can remove the source AND. */
8282 if ((and_mask
& ze_mask
) == ze_mask
)
8283 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8285 /* Partial overlap. We can reduce the source AND. */
8286 if ((and_mask
& ze_mask
) != and_mask
)
8288 mode
= GET_MODE (src
);
8289 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8290 gen_int_mode (and_mask
& ze_mask
, mode
));
8291 return gen_rtx_SET (VOIDmode
, dest
, src
);
8295 /* The other case we handle is assignments into a constant-position
8296 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8297 a mask that has all one bits except for a group of zero bits and
8298 OTHER is known to have zeros where C1 has ones, this is such an
8299 assignment. Compute the position and length from C1. Shift OTHER
8300 to the appropriate position, force it to the required mode, and
8301 make the extraction. Check for the AND in both operands. */
8303 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8306 rhs
= expand_compound_operation (XEXP (src
, 0));
8307 lhs
= expand_compound_operation (XEXP (src
, 1));
8309 if (GET_CODE (rhs
) == AND
8310 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
8311 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8312 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8313 else if (GET_CODE (lhs
) == AND
8314 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
8315 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8316 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8320 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8321 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8322 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8323 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8326 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
8330 /* The mode to use for the source is the mode of the assignment, or of
8331 what is inside a possible STRICT_LOW_PART. */
8332 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
8333 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
8335 /* Shift OTHER right POS places and make it the source, restricting it
8336 to the proper length and mode. */
8338 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
8342 src
= force_to_mode (src
, mode
,
8343 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8344 ? ~(unsigned HOST_WIDE_INT
) 0
8345 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8348 /* If SRC is masked by an AND that does not make a difference in
8349 the value being stored, strip it. */
8350 if (GET_CODE (assign
) == ZERO_EXTRACT
8351 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
8352 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
8353 && GET_CODE (src
) == AND
8354 && GET_CODE (XEXP (src
, 1)) == CONST_INT
8355 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
8356 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
8357 src
= XEXP (src
, 0);
8359 return gen_rtx_SET (VOIDmode
, assign
, src
);
8362 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8366 apply_distributive_law (rtx x
)
8368 enum rtx_code code
= GET_CODE (x
);
8369 enum rtx_code inner_code
;
8370 rtx lhs
, rhs
, other
;
8373 /* Distributivity is not true for floating point as it can change the
8374 value. So we don't do it unless -funsafe-math-optimizations. */
8375 if (FLOAT_MODE_P (GET_MODE (x
))
8376 && ! flag_unsafe_math_optimizations
)
8379 /* The outer operation can only be one of the following: */
8380 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
8381 && code
!= PLUS
&& code
!= MINUS
)
8387 /* If either operand is a primitive we can't do anything, so get out
8389 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
8392 lhs
= expand_compound_operation (lhs
);
8393 rhs
= expand_compound_operation (rhs
);
8394 inner_code
= GET_CODE (lhs
);
8395 if (inner_code
!= GET_CODE (rhs
))
8398 /* See if the inner and outer operations distribute. */
8405 /* These all distribute except over PLUS. */
8406 if (code
== PLUS
|| code
== MINUS
)
8411 if (code
!= PLUS
&& code
!= MINUS
)
8416 /* This is also a multiply, so it distributes over everything. */
8420 /* Non-paradoxical SUBREGs distributes over all operations,
8421 provided the inner modes and byte offsets are the same, this
8422 is an extraction of a low-order part, we don't convert an fp
8423 operation to int or vice versa, this is not a vector mode,
8424 and we would not be converting a single-word operation into a
8425 multi-word operation. The latter test is not required, but
8426 it prevents generating unneeded multi-word operations. Some
8427 of the previous tests are redundant given the latter test,
8428 but are retained because they are required for correctness.
8430 We produce the result slightly differently in this case. */
8432 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8433 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8434 || ! subreg_lowpart_p (lhs
)
8435 || (GET_MODE_CLASS (GET_MODE (lhs
))
8436 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8437 || (GET_MODE_SIZE (GET_MODE (lhs
))
8438 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8439 || VECTOR_MODE_P (GET_MODE (lhs
))
8440 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
8441 /* Result might need to be truncated. Don't change mode if
8442 explicit truncation is needed. */
8443 || !TRULY_NOOP_TRUNCATION
8444 (GET_MODE_BITSIZE (GET_MODE (x
)),
8445 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
8448 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8449 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8450 return gen_lowpart (GET_MODE (x
), tem
);
8456 /* Set LHS and RHS to the inner operands (A and B in the example
8457 above) and set OTHER to the common operand (C in the example).
8458 There is only one way to do this unless the inner operation is
8460 if (COMMUTATIVE_ARITH_P (lhs
)
8461 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8462 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8463 else if (COMMUTATIVE_ARITH_P (lhs
)
8464 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8465 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8466 else if (COMMUTATIVE_ARITH_P (lhs
)
8467 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8468 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8469 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8470 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8474 /* Form the new inner operation, seeing if it simplifies first. */
8475 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8477 /* There is one exception to the general way of distributing:
8478 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8479 if (code
== XOR
&& inner_code
== IOR
)
8482 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8485 /* We may be able to continuing distributing the result, so call
8486 ourselves recursively on the inner operation before forming the
8487 outer operation, which we return. */
8488 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8489 apply_distributive_law (tem
), other
);
8492 /* See if X is of the form (* (+ A B) C), and if so convert to
8493 (+ (* A C) (* B C)) and try to simplify.
8495 Most of the time, this results in no change. However, if some of
8496 the operands are the same or inverses of each other, simplifications
8499 For example, (and (ior A B) (not B)) can occur as the result of
8500 expanding a bit field assignment. When we apply the distributive
8501 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8502 which then simplifies to (and (A (not B))).
8504 Note that no checks happen on the validity of applying the inverse
8505 distributive law. This is pointless since we can do it in the
8506 few places where this routine is called.
8508 N is the index of the term that is decomposed (the arithmetic operation,
8509 i.e. (+ A B) in the first example above). !N is the index of the term that
8510 is distributed, i.e. of C in the first example above. */
8512 distribute_and_simplify_rtx (rtx x
, int n
)
8514 enum machine_mode mode
;
8515 enum rtx_code outer_code
, inner_code
;
8516 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8518 decomposed
= XEXP (x
, n
);
8519 if (!ARITHMETIC_P (decomposed
))
8522 mode
= GET_MODE (x
);
8523 outer_code
= GET_CODE (x
);
8524 distributed
= XEXP (x
, !n
);
8526 inner_code
= GET_CODE (decomposed
);
8527 inner_op0
= XEXP (decomposed
, 0);
8528 inner_op1
= XEXP (decomposed
, 1);
8530 /* Special case (and (xor B C) (not A)), which is equivalent to
8531 (xor (ior A B) (ior A C)) */
8532 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8534 distributed
= XEXP (distributed
, 0);
8540 /* Distribute the second term. */
8541 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8542 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8546 /* Distribute the first term. */
8547 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8548 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8551 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8553 if (GET_CODE (tmp
) != outer_code
8554 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8560 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8561 in MODE. Return an equivalent form, if different from (and VAROP
8562 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8565 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
8566 unsigned HOST_WIDE_INT constop
)
8568 unsigned HOST_WIDE_INT nonzero
;
8569 unsigned HOST_WIDE_INT orig_constop
;
8574 orig_constop
= constop
;
8575 if (GET_CODE (varop
) == CLOBBER
)
8578 /* Simplify VAROP knowing that we will be only looking at some of the
8581 Note by passing in CONSTOP, we guarantee that the bits not set in
8582 CONSTOP are not significant and will never be examined. We must
8583 ensure that is the case by explicitly masking out those bits
8584 before returning. */
8585 varop
= force_to_mode (varop
, mode
, constop
, 0);
8587 /* If VAROP is a CLOBBER, we will fail so return it. */
8588 if (GET_CODE (varop
) == CLOBBER
)
8591 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8592 to VAROP and return the new constant. */
8593 if (GET_CODE (varop
) == CONST_INT
)
8594 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8596 /* See what bits may be nonzero in VAROP. Unlike the general case of
8597 a call to nonzero_bits, here we don't care about bits outside
8600 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8602 /* Turn off all bits in the constant that are known to already be zero.
8603 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8604 which is tested below. */
8608 /* If we don't have any bits left, return zero. */
8612 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8613 a power of two, we can replace this with an ASHIFT. */
8614 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8615 && (i
= exact_log2 (constop
)) >= 0)
8616 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8618 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8619 or XOR, then try to apply the distributive law. This may eliminate
8620 operations if either branch can be simplified because of the AND.
8621 It may also make some cases more complex, but those cases probably
8622 won't match a pattern either with or without this. */
8624 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8628 apply_distributive_law
8629 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8630 simplify_and_const_int (NULL_RTX
,
8634 simplify_and_const_int (NULL_RTX
,
8639 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8640 the AND and see if one of the operands simplifies to zero. If so, we
8641 may eliminate it. */
8643 if (GET_CODE (varop
) == PLUS
8644 && exact_log2 (constop
+ 1) >= 0)
8648 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8649 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8650 if (o0
== const0_rtx
)
8652 if (o1
== const0_rtx
)
8656 /* Make a SUBREG if necessary. If we can't make it, fail. */
8657 varop
= gen_lowpart (mode
, varop
);
8658 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
8661 /* If we are only masking insignificant bits, return VAROP. */
8662 if (constop
== nonzero
)
8665 if (varop
== orig_varop
&& constop
== orig_constop
)
8668 /* Otherwise, return an AND. */
8669 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
8673 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8676 Return an equivalent form, if different from X. Otherwise, return X. If
8677 X is zero, we are to always construct the equivalent form. */
8680 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8681 unsigned HOST_WIDE_INT constop
)
8683 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
8688 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
8689 gen_int_mode (constop
, mode
));
8690 if (GET_MODE (x
) != mode
)
8691 x
= gen_lowpart (mode
, x
);
8695 /* Given a REG, X, compute which bits in X can be nonzero.
8696 We don't care about bits outside of those defined in MODE.
8698 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8699 a shift, AND, or zero_extract, we can do better. */
8702 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
8703 const_rtx known_x ATTRIBUTE_UNUSED
,
8704 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8705 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8706 unsigned HOST_WIDE_INT
*nonzero
)
8711 /* If X is a register whose nonzero bits value is current, use it.
8712 Otherwise, if X is a register whose value we can find, use that
8713 value. Otherwise, use the previously-computed global nonzero bits
8714 for this register. */
8716 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
8717 if (rsp
->last_set_value
!= 0
8718 && (rsp
->last_set_mode
== mode
8719 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
8720 && GET_MODE_CLASS (mode
) == MODE_INT
))
8721 && ((rsp
->last_set_label
>= label_tick_ebb_start
8722 && rsp
->last_set_label
< label_tick
)
8723 || (rsp
->last_set_label
== label_tick
8724 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
8725 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8726 && REG_N_SETS (REGNO (x
)) == 1
8728 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
8730 *nonzero
&= rsp
->last_set_nonzero_bits
;
8734 tem
= get_last_value (x
);
8738 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8739 /* If X is narrower than MODE and TEM is a non-negative
8740 constant that would appear negative in the mode of X,
8741 sign-extend it for use in reg_nonzero_bits because some
8742 machines (maybe most) will actually do the sign-extension
8743 and this is the conservative approach.
8745 ??? For 2.5, try to tighten up the MD files in this regard
8746 instead of this kludge. */
8748 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8749 && GET_CODE (tem
) == CONST_INT
8751 && 0 != (INTVAL (tem
)
8752 & ((HOST_WIDE_INT
) 1
8753 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8754 tem
= GEN_INT (INTVAL (tem
)
8755 | ((HOST_WIDE_INT
) (-1)
8756 << GET_MODE_BITSIZE (GET_MODE (x
))));
8760 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
8762 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
8764 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8765 /* We don't know anything about the upper bits. */
8766 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8773 /* Return the number of bits at the high-order end of X that are known to
8774 be equal to the sign bit. X will be used in mode MODE; if MODE is
8775 VOIDmode, X will be used in its own mode. The returned value will always
8776 be between 1 and the number of bits in MODE. */
8779 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
8780 const_rtx known_x ATTRIBUTE_UNUSED
,
8781 enum machine_mode known_mode
8783 unsigned int known_ret ATTRIBUTE_UNUSED
,
8784 unsigned int *result
)
8789 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
8790 if (rsp
->last_set_value
!= 0
8791 && rsp
->last_set_mode
== mode
8792 && ((rsp
->last_set_label
>= label_tick_ebb_start
8793 && rsp
->last_set_label
< label_tick
)
8794 || (rsp
->last_set_label
== label_tick
8795 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
8796 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8797 && REG_N_SETS (REGNO (x
)) == 1
8799 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
8801 *result
= rsp
->last_set_sign_bit_copies
;
8805 tem
= get_last_value (x
);
8809 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
8810 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8811 *result
= rsp
->sign_bit_copies
;
8816 /* Return the number of "extended" bits there are in X, when interpreted
8817 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8818 unsigned quantities, this is the number of high-order zero bits.
8819 For signed quantities, this is the number of copies of the sign bit
8820 minus 1. In both case, this function returns the number of "spare"
8821 bits. For example, if two quantities for which this function returns
8822 at least 1 are added, the addition is known not to overflow.
8824 This function will always return 0 unless called during combine, which
8825 implies that it must be called from a define_split. */
8828 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
8830 if (nonzero_sign_valid
== 0)
8834 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8835 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8836 - floor_log2 (nonzero_bits (x
, mode
)))
8838 : num_sign_bit_copies (x
, mode
) - 1);
8841 /* This function is called from `simplify_shift_const' to merge two
8842 outer operations. Specifically, we have already found that we need
8843 to perform operation *POP0 with constant *PCONST0 at the outermost
8844 position. We would now like to also perform OP1 with constant CONST1
8845 (with *POP0 being done last).
8847 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8848 the resulting operation. *PCOMP_P is set to 1 if we would need to
8849 complement the innermost operand, otherwise it is unchanged.
8851 MODE is the mode in which the operation will be done. No bits outside
8852 the width of this mode matter. It is assumed that the width of this mode
8853 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8855 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8856 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8857 result is simply *PCONST0.
8859 If the resulting operation cannot be expressed as one operation, we
8860 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8863 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8865 enum rtx_code op0
= *pop0
;
8866 HOST_WIDE_INT const0
= *pconst0
;
8868 const0
&= GET_MODE_MASK (mode
);
8869 const1
&= GET_MODE_MASK (mode
);
8871 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8875 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8878 if (op1
== UNKNOWN
|| op0
== SET
)
8881 else if (op0
== UNKNOWN
)
8882 op0
= op1
, const0
= const1
;
8884 else if (op0
== op1
)
8908 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8909 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8912 /* If the two constants aren't the same, we can't do anything. The
8913 remaining six cases can all be done. */
8914 else if (const0
!= const1
)
8922 /* (a & b) | b == b */
8924 else /* op1 == XOR */
8925 /* (a ^ b) | b == a | b */
8931 /* (a & b) ^ b == (~a) & b */
8932 op0
= AND
, *pcomp_p
= 1;
8933 else /* op1 == IOR */
8934 /* (a | b) ^ b == a & ~b */
8935 op0
= AND
, const0
= ~const0
;
8940 /* (a | b) & b == b */
8942 else /* op1 == XOR */
8943 /* (a ^ b) & b) == (~a) & b */
8950 /* Check for NO-OP cases. */
8951 const0
&= GET_MODE_MASK (mode
);
8953 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8955 else if (const0
== 0 && op0
== AND
)
8957 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8961 /* ??? Slightly redundant with the above mask, but not entirely.
8962 Moving this above means we'd have to sign-extend the mode mask
8963 for the final test. */
8964 const0
= trunc_int_for_mode (const0
, mode
);
8972 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8973 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8974 simplify it. Otherwise, return a simplified value.
8976 The shift is normally computed in the widest mode we find in VAROP, as
8977 long as it isn't a different number of words than RESULT_MODE. Exceptions
8978 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8981 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
8982 rtx varop
, int orig_count
)
8984 enum rtx_code orig_code
= code
;
8985 rtx orig_varop
= varop
;
8987 enum machine_mode mode
= result_mode
;
8988 enum machine_mode shift_mode
, tmode
;
8989 unsigned int mode_words
8990 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8991 /* We form (outer_op (code varop count) (outer_const)). */
8992 enum rtx_code outer_op
= UNKNOWN
;
8993 HOST_WIDE_INT outer_const
= 0;
8994 int complement_p
= 0;
8997 /* Make sure and truncate the "natural" shift on the way in. We don't
8998 want to do this inside the loop as it makes it more difficult to
9000 if (SHIFT_COUNT_TRUNCATED
)
9001 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9003 /* If we were given an invalid count, don't do anything except exactly
9004 what was requested. */
9006 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9011 /* Unless one of the branches of the `if' in this loop does a `continue',
9012 we will `break' the loop after the `if'. */
9016 /* If we have an operand of (clobber (const_int 0)), fail. */
9017 if (GET_CODE (varop
) == CLOBBER
)
9020 /* If we discovered we had to complement VAROP, leave. Making a NOT
9021 here would cause an infinite loop. */
9025 /* Convert ROTATERT to ROTATE. */
9026 if (code
== ROTATERT
)
9028 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9030 if (VECTOR_MODE_P (result_mode
))
9031 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9033 count
= bitsize
- count
;
9036 /* We need to determine what mode we will do the shift in. If the
9037 shift is a right shift or a ROTATE, we must always do it in the mode
9038 it was originally done in. Otherwise, we can do it in MODE, the
9039 widest mode encountered. */
9041 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9042 ? result_mode
: mode
);
9044 /* Handle cases where the count is greater than the size of the mode
9045 minus 1. For ASHIFT, use the size minus one as the count (this can
9046 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9047 take the count modulo the size. For other shifts, the result is
9050 Since these shifts are being produced by the compiler by combining
9051 multiple operations, each of which are defined, we know what the
9052 result is supposed to be. */
9054 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9056 if (code
== ASHIFTRT
)
9057 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9058 else if (code
== ROTATE
|| code
== ROTATERT
)
9059 count
%= GET_MODE_BITSIZE (shift_mode
);
9062 /* We can't simply return zero because there may be an
9070 /* An arithmetic right shift of a quantity known to be -1 or 0
9072 if (code
== ASHIFTRT
9073 && (num_sign_bit_copies (varop
, shift_mode
)
9074 == GET_MODE_BITSIZE (shift_mode
)))
9080 /* If we are doing an arithmetic right shift and discarding all but
9081 the sign bit copies, this is equivalent to doing a shift by the
9082 bitsize minus one. Convert it into that shift because it will often
9083 allow other simplifications. */
9085 if (code
== ASHIFTRT
9086 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9087 >= GET_MODE_BITSIZE (shift_mode
)))
9088 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9090 /* We simplify the tests below and elsewhere by converting
9091 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9092 `make_compound_operation' will convert it to an ASHIFTRT for
9093 those machines (such as VAX) that don't have an LSHIFTRT. */
9094 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9096 && ((nonzero_bits (varop
, shift_mode
)
9097 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9101 if (((code
== LSHIFTRT
9102 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9103 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9105 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9106 && !((nonzero_bits (varop
, shift_mode
) << count
)
9107 & GET_MODE_MASK (shift_mode
))))
9108 && !side_effects_p (varop
))
9111 switch (GET_CODE (varop
))
9117 new = expand_compound_operation (varop
);
9126 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9127 minus the width of a smaller mode, we can do this with a
9128 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9129 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9130 && ! mode_dependent_address_p (XEXP (varop
, 0))
9131 && ! MEM_VOLATILE_P (varop
)
9132 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9133 MODE_INT
, 1)) != BLKmode
)
9135 new = adjust_address_nv (varop
, tmode
,
9136 BYTES_BIG_ENDIAN
? 0
9137 : count
/ BITS_PER_UNIT
);
9139 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9140 : ZERO_EXTEND
, mode
, new);
9147 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9148 the same number of words as what we've seen so far. Then store
9149 the widest mode in MODE. */
9150 if (subreg_lowpart_p (varop
)
9151 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9152 > GET_MODE_SIZE (GET_MODE (varop
)))
9153 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9154 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9157 varop
= SUBREG_REG (varop
);
9158 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9159 mode
= GET_MODE (varop
);
9165 /* Some machines use MULT instead of ASHIFT because MULT
9166 is cheaper. But it is still better on those machines to
9167 merge two shifts into one. */
9168 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9169 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9172 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9174 GEN_INT (exact_log2 (
9175 INTVAL (XEXP (varop
, 1)))));
9181 /* Similar, for when divides are cheaper. */
9182 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9183 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9186 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9188 GEN_INT (exact_log2 (
9189 INTVAL (XEXP (varop
, 1)))));
9195 /* If we are extracting just the sign bit of an arithmetic
9196 right shift, that shift is not needed. However, the sign
9197 bit of a wider mode may be different from what would be
9198 interpreted as the sign bit in a narrower mode, so, if
9199 the result is narrower, don't discard the shift. */
9200 if (code
== LSHIFTRT
9201 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9202 && (GET_MODE_BITSIZE (result_mode
)
9203 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9205 varop
= XEXP (varop
, 0);
9209 /* ... fall through ... */
9214 /* Here we have two nested shifts. The result is usually the
9215 AND of a new shift with a mask. We compute the result below. */
9216 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9217 && INTVAL (XEXP (varop
, 1)) >= 0
9218 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9219 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9220 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9221 && !VECTOR_MODE_P (result_mode
))
9223 enum rtx_code first_code
= GET_CODE (varop
);
9224 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9225 unsigned HOST_WIDE_INT mask
;
9228 /* We have one common special case. We can't do any merging if
9229 the inner code is an ASHIFTRT of a smaller mode. However, if
9230 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9231 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9232 we can convert it to
9233 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9234 This simplifies certain SIGN_EXTEND operations. */
9235 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9236 && count
== (GET_MODE_BITSIZE (result_mode
)
9237 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9239 /* C3 has the low-order C1 bits zero. */
9241 mask
= (GET_MODE_MASK (mode
)
9242 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9244 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9245 XEXP (varop
, 0), mask
);
9246 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9248 count
= first_count
;
9253 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9254 than C1 high-order bits equal to the sign bit, we can convert
9255 this to either an ASHIFT or an ASHIFTRT depending on the
9258 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9260 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9261 && GET_MODE (varop
) == shift_mode
9262 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9265 varop
= XEXP (varop
, 0);
9266 count
-= first_count
;
9276 /* There are some cases we can't do. If CODE is ASHIFTRT,
9277 we can only do this if FIRST_CODE is also ASHIFTRT.
9279 We can't do the case when CODE is ROTATE and FIRST_CODE is
9282 If the mode of this shift is not the mode of the outer shift,
9283 we can't do this if either shift is a right shift or ROTATE.
9285 Finally, we can't do any of these if the mode is too wide
9286 unless the codes are the same.
9288 Handle the case where the shift codes are the same
9291 if (code
== first_code
)
9293 if (GET_MODE (varop
) != result_mode
9294 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9298 count
+= first_count
;
9299 varop
= XEXP (varop
, 0);
9303 if (code
== ASHIFTRT
9304 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9305 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9306 || (GET_MODE (varop
) != result_mode
9307 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9308 || first_code
== ROTATE
9309 || code
== ROTATE
)))
9312 /* To compute the mask to apply after the shift, shift the
9313 nonzero bits of the inner shift the same way the
9314 outer shift will. */
9316 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9319 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
9322 /* Give up if we can't compute an outer operation to use. */
9324 || GET_CODE (mask_rtx
) != CONST_INT
9325 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9327 result_mode
, &complement_p
))
9330 /* If the shifts are in the same direction, we add the
9331 counts. Otherwise, we subtract them. */
9332 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9333 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9334 count
+= first_count
;
9336 count
-= first_count
;
9338 /* If COUNT is positive, the new shift is usually CODE,
9339 except for the two exceptions below, in which case it is
9340 FIRST_CODE. If the count is negative, FIRST_CODE should
9343 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9344 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9347 code
= first_code
, count
= -count
;
9349 varop
= XEXP (varop
, 0);
9353 /* If we have (A << B << C) for any shift, we can convert this to
9354 (A << C << B). This wins if A is a constant. Only try this if
9355 B is not a constant. */
9357 else if (GET_CODE (varop
) == code
9358 && GET_CODE (XEXP (varop
, 0)) == CONST_INT
9359 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
)
9361 rtx
new = simplify_const_binary_operation (code
, mode
,
9364 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9371 if (VECTOR_MODE_P (mode
))
9374 /* Make this fit the case below. */
9375 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9376 GEN_INT (GET_MODE_MASK (mode
)));
9382 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9383 with C the size of VAROP - 1 and the shift is logical if
9384 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9385 we have an (le X 0) operation. If we have an arithmetic shift
9386 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9387 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9389 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9390 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9391 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9392 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9393 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9394 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9397 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9400 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9401 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9406 /* If we have (shift (logical)), move the logical to the outside
9407 to allow it to possibly combine with another logical and the
9408 shift to combine with another shift. This also canonicalizes to
9409 what a ZERO_EXTRACT looks like. Also, some machines have
9410 (and (shift)) insns. */
9412 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9413 /* We can't do this if we have (ashiftrt (xor)) and the
9414 constant has its sign bit set in shift_mode. */
9415 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9416 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9418 && (new = simplify_const_binary_operation (code
, result_mode
,
9420 GEN_INT (count
))) != 0
9421 && GET_CODE (new) == CONST_INT
9422 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9423 INTVAL (new), result_mode
, &complement_p
))
9425 varop
= XEXP (varop
, 0);
9429 /* If we can't do that, try to simplify the shift in each arm of the
9430 logical expression, make a new logical expression, and apply
9431 the inverse distributive law. This also can't be done
9432 for some (ashiftrt (xor)). */
9433 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9434 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9435 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9438 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9439 XEXP (varop
, 0), count
);
9440 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9441 XEXP (varop
, 1), count
);
9443 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9445 varop
= apply_distributive_law (varop
);
9453 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9454 says that the sign bit can be tested, FOO has mode MODE, C is
9455 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9456 that may be nonzero. */
9457 if (code
== LSHIFTRT
9458 && XEXP (varop
, 1) == const0_rtx
9459 && GET_MODE (XEXP (varop
, 0)) == result_mode
9460 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9461 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9462 && STORE_FLAG_VALUE
== -1
9463 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9464 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9465 (HOST_WIDE_INT
) 1, result_mode
,
9468 varop
= XEXP (varop
, 0);
9475 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9476 than the number of bits in the mode is equivalent to A. */
9477 if (code
== LSHIFTRT
9478 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9479 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9481 varop
= XEXP (varop
, 0);
9486 /* NEG commutes with ASHIFT since it is multiplication. Move the
9487 NEG outside to allow shifts to combine. */
9489 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9490 (HOST_WIDE_INT
) 0, result_mode
,
9493 varop
= XEXP (varop
, 0);
9499 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9500 is one less than the number of bits in the mode is
9501 equivalent to (xor A 1). */
9502 if (code
== LSHIFTRT
9503 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9504 && XEXP (varop
, 1) == constm1_rtx
9505 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9506 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9507 (HOST_WIDE_INT
) 1, result_mode
,
9511 varop
= XEXP (varop
, 0);
9515 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9516 that might be nonzero in BAR are those being shifted out and those
9517 bits are known zero in FOO, we can replace the PLUS with FOO.
9518 Similarly in the other operand order. This code occurs when
9519 we are computing the size of a variable-size array. */
9521 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9522 && count
< HOST_BITS_PER_WIDE_INT
9523 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9524 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9525 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9527 varop
= XEXP (varop
, 0);
9530 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9531 && count
< HOST_BITS_PER_WIDE_INT
9532 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9533 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9535 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9536 & nonzero_bits (XEXP (varop
, 1),
9539 varop
= XEXP (varop
, 1);
9543 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9545 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9546 && (new = simplify_const_binary_operation (ASHIFT
, result_mode
,
9548 GEN_INT (count
))) != 0
9549 && GET_CODE (new) == CONST_INT
9550 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9551 INTVAL (new), result_mode
, &complement_p
))
9553 varop
= XEXP (varop
, 0);
9557 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9558 signbit', and attempt to change the PLUS to an XOR and move it to
9559 the outer operation as is done above in the AND/IOR/XOR case
9560 leg for shift(logical). See details in logical handling above
9561 for reasoning in doing so. */
9562 if (code
== LSHIFTRT
9563 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9564 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9565 && (new = simplify_const_binary_operation (code
, result_mode
,
9567 GEN_INT (count
))) != 0
9568 && GET_CODE (new) == CONST_INT
9569 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9570 INTVAL (new), result_mode
, &complement_p
))
9572 varop
= XEXP (varop
, 0);
9579 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9580 with C the size of VAROP - 1 and the shift is logical if
9581 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9582 we have a (gt X 0) operation. If the shift is arithmetic with
9583 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9584 we have a (neg (gt X 0)) operation. */
9586 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9587 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9588 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9589 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9590 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9591 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9592 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9595 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9598 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9599 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9606 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9607 if the truncate does not affect the value. */
9608 if (code
== LSHIFTRT
9609 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9610 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9611 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9612 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9613 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9615 rtx varop_inner
= XEXP (varop
, 0);
9618 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9619 XEXP (varop_inner
, 0),
9621 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9622 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9635 /* We need to determine what mode to do the shift in. If the shift is
9636 a right shift or ROTATE, we must always do it in the mode it was
9637 originally done in. Otherwise, we can do it in MODE, the widest mode
9638 encountered. The code we care about is that of the shift that will
9639 actually be done, not the shift that was originally requested. */
9641 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9642 ? result_mode
: mode
);
9644 /* We have now finished analyzing the shift. The result should be
9645 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9646 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9647 to the result of the shift. OUTER_CONST is the relevant constant,
9648 but we must turn off all bits turned off in the shift. */
9650 if (outer_op
== UNKNOWN
9651 && orig_code
== code
&& orig_count
== count
9652 && varop
== orig_varop
9653 && shift_mode
== GET_MODE (varop
))
9656 /* Make a SUBREG if necessary. If we can't make it, fail. */
9657 varop
= gen_lowpart (shift_mode
, varop
);
9658 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9661 /* If we have an outer operation and we just made a shift, it is
9662 possible that we could have simplified the shift were it not
9663 for the outer operation. So try to do the simplification
9666 if (outer_op
!= UNKNOWN
)
9667 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
9672 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
9674 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9675 turn off all the bits that the shift would have turned off. */
9676 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9677 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9678 GET_MODE_MASK (result_mode
) >> orig_count
);
9680 /* Do the remainder of the processing in RESULT_MODE. */
9681 x
= gen_lowpart_or_truncate (result_mode
, x
);
9683 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9686 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9688 if (outer_op
!= UNKNOWN
)
9690 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9691 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9693 if (outer_op
== AND
)
9694 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9695 else if (outer_op
== SET
)
9697 /* This means that we have determined that the result is
9698 equivalent to a constant. This should be rare. */
9699 if (!side_effects_p (x
))
9700 x
= GEN_INT (outer_const
);
9702 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9703 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9705 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9706 GEN_INT (outer_const
));
9712 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9713 The result of the shift is RESULT_MODE. If we cannot simplify it,
9714 return X or, if it is NULL, synthesize the expression with
9715 simplify_gen_binary. Otherwise, return a simplified value.
9717 The shift is normally computed in the widest mode we find in VAROP, as
9718 long as it isn't a different number of words than RESULT_MODE. Exceptions
9719 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9722 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
9723 rtx varop
, int count
)
9725 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
9730 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
9731 if (GET_MODE (x
) != result_mode
)
9732 x
= gen_lowpart (result_mode
, x
);
9737 /* Like recog, but we receive the address of a pointer to a new pattern.
9738 We try to match the rtx that the pointer points to.
9739 If that fails, we may try to modify or replace the pattern,
9740 storing the replacement into the same pointer object.
9742 Modifications include deletion or addition of CLOBBERs.
9744 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9745 the CLOBBERs are placed.
9747 The value is the final insn code from the pattern ultimately matched,
9751 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9754 int insn_code_number
;
9755 int num_clobbers_to_add
= 0;
9758 rtx old_notes
, old_pat
;
9760 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9761 we use to indicate that something didn't match. If we find such a
9762 thing, force rejection. */
9763 if (GET_CODE (pat
) == PARALLEL
)
9764 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9765 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9766 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9769 old_pat
= PATTERN (insn
);
9770 old_notes
= REG_NOTES (insn
);
9771 PATTERN (insn
) = pat
;
9772 REG_NOTES (insn
) = 0;
9774 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9775 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
9777 if (insn_code_number
< 0)
9778 fputs ("Failed to match this instruction:\n", dump_file
);
9780 fputs ("Successfully matched this instruction:\n", dump_file
);
9781 print_rtl_single (dump_file
, pat
);
9784 /* If it isn't, there is the possibility that we previously had an insn
9785 that clobbered some register as a side effect, but the combined
9786 insn doesn't need to do that. So try once more without the clobbers
9787 unless this represents an ASM insn. */
9789 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9790 && GET_CODE (pat
) == PARALLEL
)
9794 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9795 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9798 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9802 SUBST_INT (XVECLEN (pat
, 0), pos
);
9805 pat
= XVECEXP (pat
, 0, 0);
9807 PATTERN (insn
) = pat
;
9808 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9809 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
9811 if (insn_code_number
< 0)
9812 fputs ("Failed to match this instruction:\n", dump_file
);
9814 fputs ("Successfully matched this instruction:\n", dump_file
);
9815 print_rtl_single (dump_file
, pat
);
9818 PATTERN (insn
) = old_pat
;
9819 REG_NOTES (insn
) = old_notes
;
9821 /* Recognize all noop sets, these will be killed by followup pass. */
9822 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9823 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9825 /* If we had any clobbers to add, make a new pattern than contains
9826 them. Then check to make sure that all of them are dead. */
9827 if (num_clobbers_to_add
)
9829 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9830 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9832 + num_clobbers_to_add
)
9833 : num_clobbers_to_add
+ 1));
9835 if (GET_CODE (pat
) == PARALLEL
)
9836 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9837 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9839 XVECEXP (newpat
, 0, 0) = pat
;
9841 add_clobbers (newpat
, insn_code_number
);
9843 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9844 i
< XVECLEN (newpat
, 0); i
++)
9846 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9847 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9849 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
9851 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
9852 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9853 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9862 return insn_code_number
;
9865 /* Like gen_lowpart_general but for use by combine. In combine it
9866 is not possible to create any new pseudoregs. However, it is
9867 safe to create invalid memory addresses, because combine will
9868 try to recognize them and all they will do is make the combine
9871 If for some reason this cannot do its job, an rtx
9872 (clobber (const_int 0)) is returned.
9873 An insn containing that will not be recognized. */
9876 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9878 enum machine_mode imode
= GET_MODE (x
);
9879 unsigned int osize
= GET_MODE_SIZE (omode
);
9880 unsigned int isize
= GET_MODE_SIZE (imode
);
9886 /* Return identity if this is a CONST or symbolic reference. */
9888 && (GET_CODE (x
) == CONST
9889 || GET_CODE (x
) == SYMBOL_REF
9890 || GET_CODE (x
) == LABEL_REF
))
9893 /* We can only support MODE being wider than a word if X is a
9894 constant integer or has a mode the same size. */
9895 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9896 && ! ((imode
== VOIDmode
9897 && (GET_CODE (x
) == CONST_INT
9898 || GET_CODE (x
) == CONST_DOUBLE
))
9902 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9903 won't know what to do. So we will strip off the SUBREG here and
9904 process normally. */
9905 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9909 /* For use in case we fall down into the address adjustments
9910 further below, we need to adjust the known mode and size of
9911 x; imode and isize, since we just adjusted x. */
9912 imode
= GET_MODE (x
);
9917 isize
= GET_MODE_SIZE (imode
);
9920 result
= gen_lowpart_common (omode
, x
);
9929 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9931 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9934 /* If we want to refer to something bigger than the original memref,
9935 generate a paradoxical subreg instead. That will force a reload
9936 of the original memref X. */
9938 return gen_rtx_SUBREG (omode
, x
, 0);
9940 if (WORDS_BIG_ENDIAN
)
9941 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9943 /* Adjust the address so that the address-after-the-data is
9945 if (BYTES_BIG_ENDIAN
)
9946 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9948 return adjust_address_nv (x
, omode
, offset
);
9951 /* If X is a comparison operator, rewrite it in a new mode. This
9952 probably won't match, but may allow further simplifications. */
9953 else if (COMPARISON_P (x
))
9954 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9956 /* If we couldn't simplify X any other way, just enclose it in a
9957 SUBREG. Normally, this SUBREG won't match, but some patterns may
9958 include an explicit SUBREG or we may simplify it further in combine. */
9964 offset
= subreg_lowpart_offset (omode
, imode
);
9965 if (imode
== VOIDmode
)
9967 imode
= int_mode_for_mode (omode
);
9968 x
= gen_lowpart_common (imode
, x
);
9972 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9978 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9981 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9982 comparison code that will be tested.
9984 The result is a possibly different comparison code to use. *POP0 and
9985 *POP1 may be updated.
9987 It is possible that we might detect that a comparison is either always
9988 true or always false. However, we do not perform general constant
9989 folding in combine, so this knowledge isn't useful. Such tautologies
9990 should have been detected earlier. Hence we ignore all such cases. */
9992 static enum rtx_code
9993 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9999 enum machine_mode mode
, tmode
;
10001 /* Try a few ways of applying the same transformation to both operands. */
10004 #ifndef WORD_REGISTER_OPERATIONS
10005 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10006 so check specially. */
10007 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10008 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10009 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10010 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10011 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10012 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10013 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10014 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10015 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10016 && XEXP (op0
, 1) == XEXP (op1
, 1)
10017 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10018 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10019 && (INTVAL (XEXP (op0
, 1))
10020 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10021 - (GET_MODE_BITSIZE
10022 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10024 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10025 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10029 /* If both operands are the same constant shift, see if we can ignore the
10030 shift. We can if the shift is a rotate or if the bits shifted out of
10031 this shift are known to be zero for both inputs and if the type of
10032 comparison is compatible with the shift. */
10033 if (GET_CODE (op0
) == GET_CODE (op1
)
10034 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10035 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10036 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10037 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10038 || (GET_CODE (op0
) == ASHIFTRT
10039 && (code
!= GTU
&& code
!= LTU
10040 && code
!= GEU
&& code
!= LEU
)))
10041 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10042 && INTVAL (XEXP (op0
, 1)) >= 0
10043 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10044 && XEXP (op0
, 1) == XEXP (op1
, 1))
10046 enum machine_mode mode
= GET_MODE (op0
);
10047 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10048 int shift_count
= INTVAL (XEXP (op0
, 1));
10050 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10051 mask
&= (mask
>> shift_count
) << shift_count
;
10052 else if (GET_CODE (op0
) == ASHIFT
)
10053 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10055 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10056 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10057 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10062 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10063 SUBREGs are of the same mode, and, in both cases, the AND would
10064 be redundant if the comparison was done in the narrower mode,
10065 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10066 and the operand's possibly nonzero bits are 0xffffff01; in that case
10067 if we only care about QImode, we don't need the AND). This case
10068 occurs if the output mode of an scc insn is not SImode and
10069 STORE_FLAG_VALUE == 1 (e.g., the 386).
10071 Similarly, check for a case where the AND's are ZERO_EXTEND
10072 operations from some narrower mode even though a SUBREG is not
10075 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10076 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10077 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10079 rtx inner_op0
= XEXP (op0
, 0);
10080 rtx inner_op1
= XEXP (op1
, 0);
10081 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10082 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10085 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10086 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10087 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10088 && (GET_MODE (SUBREG_REG (inner_op0
))
10089 == GET_MODE (SUBREG_REG (inner_op1
)))
10090 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10091 <= HOST_BITS_PER_WIDE_INT
)
10092 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10093 GET_MODE (SUBREG_REG (inner_op0
)))))
10094 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10095 GET_MODE (SUBREG_REG (inner_op1
))))))
10097 op0
= SUBREG_REG (inner_op0
);
10098 op1
= SUBREG_REG (inner_op1
);
10100 /* The resulting comparison is always unsigned since we masked
10101 off the original sign bit. */
10102 code
= unsigned_condition (code
);
10108 for (tmode
= GET_CLASS_NARROWEST_MODE
10109 (GET_MODE_CLASS (GET_MODE (op0
)));
10110 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10111 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10113 op0
= gen_lowpart (tmode
, inner_op0
);
10114 op1
= gen_lowpart (tmode
, inner_op1
);
10115 code
= unsigned_condition (code
);
10124 /* If both operands are NOT, we can strip off the outer operation
10125 and adjust the comparison code for swapped operands; similarly for
10126 NEG, except that this must be an equality comparison. */
10127 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10128 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10129 && (code
== EQ
|| code
== NE
)))
10130 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10136 /* If the first operand is a constant, swap the operands and adjust the
10137 comparison code appropriately, but don't do this if the second operand
10138 is already a constant integer. */
10139 if (swap_commutative_operands_p (op0
, op1
))
10141 tem
= op0
, op0
= op1
, op1
= tem
;
10142 code
= swap_condition (code
);
10145 /* We now enter a loop during which we will try to simplify the comparison.
10146 For the most part, we only are concerned with comparisons with zero,
10147 but some things may really be comparisons with zero but not start
10148 out looking that way. */
10150 while (GET_CODE (op1
) == CONST_INT
)
10152 enum machine_mode mode
= GET_MODE (op0
);
10153 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10154 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10155 int equality_comparison_p
;
10156 int sign_bit_comparison_p
;
10157 int unsigned_comparison_p
;
10158 HOST_WIDE_INT const_op
;
10160 /* We only want to handle integral modes. This catches VOIDmode,
10161 CCmode, and the floating-point modes. An exception is that we
10162 can handle VOIDmode if OP0 is a COMPARE or a comparison
10165 if (GET_MODE_CLASS (mode
) != MODE_INT
10166 && ! (mode
== VOIDmode
10167 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10170 /* Get the constant we are comparing against and turn off all bits
10171 not on in our mode. */
10172 const_op
= INTVAL (op1
);
10173 if (mode
!= VOIDmode
)
10174 const_op
= trunc_int_for_mode (const_op
, mode
);
10175 op1
= GEN_INT (const_op
);
10177 /* If we are comparing against a constant power of two and the value
10178 being compared can only have that single bit nonzero (e.g., it was
10179 `and'ed with that bit), we can replace this with a comparison
10182 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10183 || code
== LT
|| code
== LTU
)
10184 && mode_width
<= HOST_BITS_PER_WIDE_INT
10185 && exact_log2 (const_op
) >= 0
10186 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10188 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10189 op1
= const0_rtx
, const_op
= 0;
10192 /* Similarly, if we are comparing a value known to be either -1 or
10193 0 with -1, change it to the opposite comparison against zero. */
10196 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10197 || code
== GEU
|| code
== LTU
)
10198 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10200 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10201 op1
= const0_rtx
, const_op
= 0;
10204 /* Do some canonicalizations based on the comparison code. We prefer
10205 comparisons against zero and then prefer equality comparisons.
10206 If we can reduce the size of a constant, we will do that too. */
10211 /* < C is equivalent to <= (C - 1) */
10215 op1
= GEN_INT (const_op
);
10217 /* ... fall through to LE case below. */
10223 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10227 op1
= GEN_INT (const_op
);
10231 /* If we are doing a <= 0 comparison on a value known to have
10232 a zero sign bit, we can replace this with == 0. */
10233 else if (const_op
== 0
10234 && mode_width
<= HOST_BITS_PER_WIDE_INT
10235 && (nonzero_bits (op0
, mode
)
10236 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10241 /* >= C is equivalent to > (C - 1). */
10245 op1
= GEN_INT (const_op
);
10247 /* ... fall through to GT below. */
10253 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10257 op1
= GEN_INT (const_op
);
10261 /* If we are doing a > 0 comparison on a value known to have
10262 a zero sign bit, we can replace this with != 0. */
10263 else if (const_op
== 0
10264 && mode_width
<= HOST_BITS_PER_WIDE_INT
10265 && (nonzero_bits (op0
, mode
)
10266 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10271 /* < C is equivalent to <= (C - 1). */
10275 op1
= GEN_INT (const_op
);
10277 /* ... fall through ... */
10280 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10281 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10282 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10284 const_op
= 0, op1
= const0_rtx
;
10292 /* unsigned <= 0 is equivalent to == 0 */
10296 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10297 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10298 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10300 const_op
= 0, op1
= const0_rtx
;
10306 /* >= C is equivalent to > (C - 1). */
10310 op1
= GEN_INT (const_op
);
10312 /* ... fall through ... */
10315 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10316 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10317 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10319 const_op
= 0, op1
= const0_rtx
;
10327 /* unsigned > 0 is equivalent to != 0 */
10331 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10332 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10333 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10335 const_op
= 0, op1
= const0_rtx
;
10344 /* Compute some predicates to simplify code below. */
10346 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10347 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10348 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10351 /* If this is a sign bit comparison and we can do arithmetic in
10352 MODE, say that we will only be needing the sign bit of OP0. */
10353 if (sign_bit_comparison_p
10354 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10355 op0
= force_to_mode (op0
, mode
,
10357 << (GET_MODE_BITSIZE (mode
) - 1)),
10360 /* Now try cases based on the opcode of OP0. If none of the cases
10361 does a "continue", we exit this loop immediately after the
10364 switch (GET_CODE (op0
))
10367 /* If we are extracting a single bit from a variable position in
10368 a constant that has only a single bit set and are comparing it
10369 with zero, we can convert this into an equality comparison
10370 between the position and the location of the single bit. */
10371 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10372 have already reduced the shift count modulo the word size. */
10373 if (!SHIFT_COUNT_TRUNCATED
10374 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10375 && XEXP (op0
, 1) == const1_rtx
10376 && equality_comparison_p
&& const_op
== 0
10377 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10379 if (BITS_BIG_ENDIAN
)
10381 enum machine_mode new_mode
10382 = mode_for_extraction (EP_extzv
, 1);
10383 if (new_mode
== MAX_MACHINE_MODE
)
10384 i
= BITS_PER_WORD
- 1 - i
;
10388 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10392 op0
= XEXP (op0
, 2);
10396 /* Result is nonzero iff shift count is equal to I. */
10397 code
= reverse_condition (code
);
10401 /* ... fall through ... */
10404 tem
= expand_compound_operation (op0
);
10413 /* If testing for equality, we can take the NOT of the constant. */
10414 if (equality_comparison_p
10415 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10417 op0
= XEXP (op0
, 0);
10422 /* If just looking at the sign bit, reverse the sense of the
10424 if (sign_bit_comparison_p
)
10426 op0
= XEXP (op0
, 0);
10427 code
= (code
== GE
? LT
: GE
);
10433 /* If testing for equality, we can take the NEG of the constant. */
10434 if (equality_comparison_p
10435 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10437 op0
= XEXP (op0
, 0);
10442 /* The remaining cases only apply to comparisons with zero. */
10446 /* When X is ABS or is known positive,
10447 (neg X) is < 0 if and only if X != 0. */
10449 if (sign_bit_comparison_p
10450 && (GET_CODE (XEXP (op0
, 0)) == ABS
10451 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10452 && (nonzero_bits (XEXP (op0
, 0), mode
)
10453 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10455 op0
= XEXP (op0
, 0);
10456 code
= (code
== LT
? NE
: EQ
);
10460 /* If we have NEG of something whose two high-order bits are the
10461 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10462 if (num_sign_bit_copies (op0
, mode
) >= 2)
10464 op0
= XEXP (op0
, 0);
10465 code
= swap_condition (code
);
10471 /* If we are testing equality and our count is a constant, we
10472 can perform the inverse operation on our RHS. */
10473 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10474 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10475 op1
, XEXP (op0
, 1))) != 0)
10477 op0
= XEXP (op0
, 0);
10482 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10483 a particular bit. Convert it to an AND of a constant of that
10484 bit. This will be converted into a ZERO_EXTRACT. */
10485 if (const_op
== 0 && sign_bit_comparison_p
10486 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10487 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10489 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10492 - INTVAL (XEXP (op0
, 1)))));
10493 code
= (code
== LT
? NE
: EQ
);
10497 /* Fall through. */
10500 /* ABS is ignorable inside an equality comparison with zero. */
10501 if (const_op
== 0 && equality_comparison_p
)
10503 op0
= XEXP (op0
, 0);
10509 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10510 (compare FOO CONST) if CONST fits in FOO's mode and we
10511 are either testing inequality or have an unsigned
10512 comparison with ZERO_EXTEND or a signed comparison with
10513 SIGN_EXTEND. But don't do it if we don't have a compare
10514 insn of the given mode, since we'd have to revert it
10515 later on, and then we wouldn't know whether to sign- or
10517 mode
= GET_MODE (XEXP (op0
, 0));
10518 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10519 && ! unsigned_comparison_p
10520 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10521 && ((unsigned HOST_WIDE_INT
) const_op
10522 < (((unsigned HOST_WIDE_INT
) 1
10523 << (GET_MODE_BITSIZE (mode
) - 1))))
10524 && optab_handler (cmp_optab
, mode
)->insn_code
!= CODE_FOR_nothing
)
10526 op0
= XEXP (op0
, 0);
10532 /* Check for the case where we are comparing A - C1 with C2, that is
10534 (subreg:MODE (plus (A) (-C1))) op (C2)
10536 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10537 comparison in the wider mode. One of the following two conditions
10538 must be true in order for this to be valid:
10540 1. The mode extension results in the same bit pattern being added
10541 on both sides and the comparison is equality or unsigned. As
10542 C2 has been truncated to fit in MODE, the pattern can only be
10545 2. The mode extension results in the sign bit being copied on
10548 The difficulty here is that we have predicates for A but not for
10549 (A - C1) so we need to check that C1 is within proper bounds so
10550 as to perturbate A as little as possible. */
10552 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10553 && subreg_lowpart_p (op0
)
10554 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10555 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10556 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10558 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10559 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10560 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10563 && (unsigned HOST_WIDE_INT
) c1
10564 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10565 && (equality_comparison_p
|| unsigned_comparison_p
)
10566 /* (A - C1) zero-extends if it is positive and sign-extends
10567 if it is negative, C2 both zero- and sign-extends. */
10568 && ((0 == (nonzero_bits (a
, inner_mode
)
10569 & ~GET_MODE_MASK (mode
))
10571 /* (A - C1) sign-extends if it is positive and 1-extends
10572 if it is negative, C2 both sign- and 1-extends. */
10573 || (num_sign_bit_copies (a
, inner_mode
)
10574 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10577 || ((unsigned HOST_WIDE_INT
) c1
10578 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10579 /* (A - C1) always sign-extends, like C2. */
10580 && num_sign_bit_copies (a
, inner_mode
)
10581 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10582 - (mode_width
- 1))))
10584 op0
= SUBREG_REG (op0
);
10589 /* If the inner mode is narrower and we are extracting the low part,
10590 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10591 if (subreg_lowpart_p (op0
)
10592 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10593 /* Fall through */ ;
10597 /* ... fall through ... */
10600 mode
= GET_MODE (XEXP (op0
, 0));
10601 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10602 && (unsigned_comparison_p
|| equality_comparison_p
)
10603 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10604 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10605 && optab_handler (cmp_optab
, mode
)->insn_code
!= CODE_FOR_nothing
)
10607 op0
= XEXP (op0
, 0);
10613 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10614 this for equality comparisons due to pathological cases involving
10616 if (equality_comparison_p
10617 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10618 op1
, XEXP (op0
, 1))))
10620 op0
= XEXP (op0
, 0);
10625 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10626 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10627 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10629 op0
= XEXP (XEXP (op0
, 0), 0);
10630 code
= (code
== LT
? EQ
: NE
);
10636 /* We used to optimize signed comparisons against zero, but that
10637 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10638 arrive here as equality comparisons, or (GEU, LTU) are
10639 optimized away. No need to special-case them. */
10641 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10642 (eq B (minus A C)), whichever simplifies. We can only do
10643 this for equality comparisons due to pathological cases involving
10645 if (equality_comparison_p
10646 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10647 XEXP (op0
, 1), op1
)))
10649 op0
= XEXP (op0
, 0);
10654 if (equality_comparison_p
10655 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10656 XEXP (op0
, 0), op1
)))
10658 op0
= XEXP (op0
, 1);
10663 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10664 of bits in X minus 1, is one iff X > 0. */
10665 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10666 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10667 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10669 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10671 op0
= XEXP (op0
, 1);
10672 code
= (code
== GE
? LE
: GT
);
10678 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10679 if C is zero or B is a constant. */
10680 if (equality_comparison_p
10681 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10682 XEXP (op0
, 1), op1
)))
10684 op0
= XEXP (op0
, 0);
10691 case UNEQ
: case LTGT
:
10692 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10693 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10694 case UNORDERED
: case ORDERED
:
10695 /* We can't do anything if OP0 is a condition code value, rather
10696 than an actual data value. */
10698 || CC0_P (XEXP (op0
, 0))
10699 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10702 /* Get the two operands being compared. */
10703 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10704 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10706 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10708 /* Check for the cases where we simply want the result of the
10709 earlier test or the opposite of that result. */
10710 if (code
== NE
|| code
== EQ
10711 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10712 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10713 && (STORE_FLAG_VALUE
10714 & (((HOST_WIDE_INT
) 1
10715 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10716 && (code
== LT
|| code
== GE
)))
10718 enum rtx_code new_code
;
10719 if (code
== LT
|| code
== NE
)
10720 new_code
= GET_CODE (op0
);
10722 new_code
= reversed_comparison_code (op0
, NULL
);
10724 if (new_code
!= UNKNOWN
)
10735 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10737 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10738 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10739 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10741 op0
= XEXP (op0
, 1);
10742 code
= (code
== GE
? GT
: LE
);
10748 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10749 will be converted to a ZERO_EXTRACT later. */
10750 if (const_op
== 0 && equality_comparison_p
10751 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10752 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10754 op0
= simplify_and_const_int
10755 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
10757 XEXP (XEXP (op0
, 0), 1)),
10758 (HOST_WIDE_INT
) 1);
10762 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10763 zero and X is a comparison and C1 and C2 describe only bits set
10764 in STORE_FLAG_VALUE, we can compare with X. */
10765 if (const_op
== 0 && equality_comparison_p
10766 && mode_width
<= HOST_BITS_PER_WIDE_INT
10767 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10768 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10769 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10770 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10771 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10773 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10774 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10775 if ((~STORE_FLAG_VALUE
& mask
) == 0
10776 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10777 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10778 && COMPARISON_P (tem
))))
10780 op0
= XEXP (XEXP (op0
, 0), 0);
10785 /* If we are doing an equality comparison of an AND of a bit equal
10786 to the sign bit, replace this with a LT or GE comparison of
10787 the underlying value. */
10788 if (equality_comparison_p
10790 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10791 && mode_width
<= HOST_BITS_PER_WIDE_INT
10792 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10793 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10795 op0
= XEXP (op0
, 0);
10796 code
= (code
== EQ
? GE
: LT
);
10800 /* If this AND operation is really a ZERO_EXTEND from a narrower
10801 mode, the constant fits within that mode, and this is either an
10802 equality or unsigned comparison, try to do this comparison in
10807 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10808 -> (ne:DI (reg:SI 4) (const_int 0))
10810 unless TRULY_NOOP_TRUNCATION allows it or the register is
10811 known to hold a value of the required mode the
10812 transformation is invalid. */
10813 if ((equality_comparison_p
|| unsigned_comparison_p
)
10814 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10815 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10816 & GET_MODE_MASK (mode
))
10818 && const_op
>> i
== 0
10819 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
10820 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
10821 GET_MODE_BITSIZE (GET_MODE (op0
)))
10822 || (REG_P (XEXP (op0
, 0))
10823 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
10825 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10829 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10830 fits in both M1 and M2 and the SUBREG is either paradoxical
10831 or represents the low part, permute the SUBREG and the AND
10833 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10835 unsigned HOST_WIDE_INT c1
;
10836 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10837 /* Require an integral mode, to avoid creating something like
10839 if (SCALAR_INT_MODE_P (tmode
)
10840 /* It is unsafe to commute the AND into the SUBREG if the
10841 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10842 not defined. As originally written the upper bits
10843 have a defined value due to the AND operation.
10844 However, if we commute the AND inside the SUBREG then
10845 they no longer have defined values and the meaning of
10846 the code has been changed. */
10848 #ifdef WORD_REGISTER_OPERATIONS
10849 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10850 && mode_width
<= BITS_PER_WORD
)
10852 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10853 && subreg_lowpart_p (XEXP (op0
, 0))))
10854 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10855 && mode_width
<= HOST_BITS_PER_WIDE_INT
10856 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10857 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10858 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10860 && c1
!= GET_MODE_MASK (tmode
))
10862 op0
= simplify_gen_binary (AND
, tmode
,
10863 SUBREG_REG (XEXP (op0
, 0)),
10864 gen_int_mode (c1
, tmode
));
10865 op0
= gen_lowpart (mode
, op0
);
10870 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10871 if (const_op
== 0 && equality_comparison_p
10872 && XEXP (op0
, 1) == const1_rtx
10873 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10875 op0
= simplify_and_const_int
10876 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10877 code
= (code
== NE
? EQ
: NE
);
10881 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10882 (eq (and (lshiftrt X) 1) 0).
10883 Also handle the case where (not X) is expressed using xor. */
10884 if (const_op
== 0 && equality_comparison_p
10885 && XEXP (op0
, 1) == const1_rtx
10886 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10888 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10889 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10891 if (GET_CODE (shift_op
) == NOT
10892 || (GET_CODE (shift_op
) == XOR
10893 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10894 && GET_CODE (shift_count
) == CONST_INT
10895 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10896 && (INTVAL (XEXP (shift_op
, 1))
10897 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10899 op0
= simplify_and_const_int
10901 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10902 (HOST_WIDE_INT
) 1);
10903 code
= (code
== NE
? EQ
: NE
);
10910 /* If we have (compare (ashift FOO N) (const_int C)) and
10911 the high order N bits of FOO (N+1 if an inequality comparison)
10912 are known to be zero, we can do this by comparing FOO with C
10913 shifted right N bits so long as the low-order N bits of C are
10915 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10916 && INTVAL (XEXP (op0
, 1)) >= 0
10917 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10918 < HOST_BITS_PER_WIDE_INT
)
10920 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10921 && mode_width
<= HOST_BITS_PER_WIDE_INT
10922 && (nonzero_bits (XEXP (op0
, 0), mode
)
10923 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10924 + ! equality_comparison_p
))) == 0)
10926 /* We must perform a logical shift, not an arithmetic one,
10927 as we want the top N bits of C to be zero. */
10928 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10930 temp
>>= INTVAL (XEXP (op0
, 1));
10931 op1
= gen_int_mode (temp
, mode
);
10932 op0
= XEXP (op0
, 0);
10936 /* If we are doing a sign bit comparison, it means we are testing
10937 a particular bit. Convert it to the appropriate AND. */
10938 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10939 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10941 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10944 - INTVAL (XEXP (op0
, 1)))));
10945 code
= (code
== LT
? NE
: EQ
);
10949 /* If this an equality comparison with zero and we are shifting
10950 the low bit to the sign bit, we can convert this to an AND of the
10952 if (const_op
== 0 && equality_comparison_p
10953 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10954 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10957 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10958 (HOST_WIDE_INT
) 1);
10964 /* If this is an equality comparison with zero, we can do this
10965 as a logical shift, which might be much simpler. */
10966 if (equality_comparison_p
&& const_op
== 0
10967 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10969 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10971 INTVAL (XEXP (op0
, 1)));
10975 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10976 do the comparison in a narrower mode. */
10977 if (! unsigned_comparison_p
10978 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10979 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10980 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10981 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10982 MODE_INT
, 1)) != BLKmode
10983 && (((unsigned HOST_WIDE_INT
) const_op
10984 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10985 <= GET_MODE_MASK (tmode
)))
10987 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10991 /* Likewise if OP0 is a PLUS of a sign extension with a
10992 constant, which is usually represented with the PLUS
10993 between the shifts. */
10994 if (! unsigned_comparison_p
10995 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10996 && GET_CODE (XEXP (op0
, 0)) == PLUS
10997 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10998 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10999 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11000 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11001 MODE_INT
, 1)) != BLKmode
11002 && (((unsigned HOST_WIDE_INT
) const_op
11003 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11004 <= GET_MODE_MASK (tmode
)))
11006 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11007 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11008 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11009 add_const
, XEXP (op0
, 1));
11011 op0
= simplify_gen_binary (PLUS
, tmode
,
11012 gen_lowpart (tmode
, inner
),
11017 /* ... fall through ... */
11019 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11020 the low order N bits of FOO are known to be zero, we can do this
11021 by comparing FOO with C shifted left N bits so long as no
11022 overflow occurs. */
11023 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11024 && INTVAL (XEXP (op0
, 1)) >= 0
11025 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11026 && mode_width
<= HOST_BITS_PER_WIDE_INT
11027 && (nonzero_bits (XEXP (op0
, 0), mode
)
11028 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11029 && (((unsigned HOST_WIDE_INT
) const_op
11030 + (GET_CODE (op0
) != LSHIFTRT
11031 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11034 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11036 /* If the shift was logical, then we must make the condition
11038 if (GET_CODE (op0
) == LSHIFTRT
)
11039 code
= unsigned_condition (code
);
11041 const_op
<<= INTVAL (XEXP (op0
, 1));
11042 op1
= GEN_INT (const_op
);
11043 op0
= XEXP (op0
, 0);
11047 /* If we are using this shift to extract just the sign bit, we
11048 can replace this with an LT or GE comparison. */
11050 && (equality_comparison_p
|| sign_bit_comparison_p
)
11051 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11052 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11055 op0
= XEXP (op0
, 0);
11056 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11068 /* Now make any compound operations involved in this comparison. Then,
11069 check for an outmost SUBREG on OP0 that is not doing anything or is
11070 paradoxical. The latter transformation must only be performed when
11071 it is known that the "extra" bits will be the same in op0 and op1 or
11072 that they don't matter. There are three cases to consider:
11074 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11075 care bits and we can assume they have any convenient value. So
11076 making the transformation is safe.
11078 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11079 In this case the upper bits of op0 are undefined. We should not make
11080 the simplification in that case as we do not know the contents of
11083 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11084 UNKNOWN. In that case we know those bits are zeros or ones. We must
11085 also be sure that they are the same as the upper bits of op1.
11087 We can never remove a SUBREG for a non-equality comparison because
11088 the sign bit is in a different place in the underlying object. */
11090 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11091 op1
= make_compound_operation (op1
, SET
);
11093 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11094 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11095 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11096 && (code
== NE
|| code
== EQ
))
11098 if (GET_MODE_SIZE (GET_MODE (op0
))
11099 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11101 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11103 if (REG_P (SUBREG_REG (op0
)))
11105 op0
= SUBREG_REG (op0
);
11106 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11109 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11110 <= HOST_BITS_PER_WIDE_INT
)
11111 && (nonzero_bits (SUBREG_REG (op0
),
11112 GET_MODE (SUBREG_REG (op0
)))
11113 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11115 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11117 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11118 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11119 op0
= SUBREG_REG (op0
), op1
= tem
;
11123 /* We now do the opposite procedure: Some machines don't have compare
11124 insns in all modes. If OP0's mode is an integer mode smaller than a
11125 word and we can't do a compare in that mode, see if there is a larger
11126 mode for which we can do the compare. There are a number of cases in
11127 which we can use the wider mode. */
11129 mode
= GET_MODE (op0
);
11130 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11131 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11132 && ! have_insn_for (COMPARE
, mode
))
11133 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11135 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11136 tmode
= GET_MODE_WIDER_MODE (tmode
))
11137 if (have_insn_for (COMPARE
, tmode
))
11141 /* If the only nonzero bits in OP0 and OP1 are those in the
11142 narrower mode and this is an equality or unsigned comparison,
11143 we can use the wider mode. Similarly for sign-extended
11144 values, in which case it is true for all comparisons. */
11145 zero_extended
= ((code
== EQ
|| code
== NE
11146 || code
== GEU
|| code
== GTU
11147 || code
== LEU
|| code
== LTU
)
11148 && (nonzero_bits (op0
, tmode
)
11149 & ~GET_MODE_MASK (mode
)) == 0
11150 && ((GET_CODE (op1
) == CONST_INT
11151 || (nonzero_bits (op1
, tmode
)
11152 & ~GET_MODE_MASK (mode
)) == 0)));
11155 || ((num_sign_bit_copies (op0
, tmode
)
11156 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11157 - GET_MODE_BITSIZE (mode
)))
11158 && (num_sign_bit_copies (op1
, tmode
)
11159 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11160 - GET_MODE_BITSIZE (mode
)))))
11162 /* If OP0 is an AND and we don't have an AND in MODE either,
11163 make a new AND in the proper mode. */
11164 if (GET_CODE (op0
) == AND
11165 && !have_insn_for (AND
, mode
))
11166 op0
= simplify_gen_binary (AND
, tmode
,
11167 gen_lowpart (tmode
,
11169 gen_lowpart (tmode
,
11172 op0
= gen_lowpart (tmode
, op0
);
11173 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11174 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11175 op1
= gen_lowpart (tmode
, op1
);
11179 /* If this is a test for negative, we can make an explicit
11180 test of the sign bit. */
11182 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11183 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11185 op0
= simplify_gen_binary (AND
, tmode
,
11186 gen_lowpart (tmode
, op0
),
11187 GEN_INT ((HOST_WIDE_INT
) 1
11188 << (GET_MODE_BITSIZE (mode
)
11190 code
= (code
== LT
) ? NE
: EQ
;
11195 #ifdef CANONICALIZE_COMPARISON
11196 /* If this machine only supports a subset of valid comparisons, see if we
11197 can convert an unsupported one into a supported one. */
11198 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11207 /* Utility function for record_value_for_reg. Count number of
11212 enum rtx_code code
= GET_CODE (x
);
11216 if (GET_RTX_CLASS (code
) == '2'
11217 || GET_RTX_CLASS (code
) == 'c')
11219 rtx x0
= XEXP (x
, 0);
11220 rtx x1
= XEXP (x
, 1);
11223 return 1 + 2 * count_rtxs (x0
);
11225 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11226 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11227 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11228 return 2 + 2 * count_rtxs (x0
)
11229 + count_rtxs (x
== XEXP (x1
, 0)
11230 ? XEXP (x1
, 1) : XEXP (x1
, 0));
11232 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11233 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11234 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11235 return 2 + 2 * count_rtxs (x1
)
11236 + count_rtxs (x
== XEXP (x0
, 0)
11237 ? XEXP (x0
, 1) : XEXP (x0
, 0));
11240 fmt
= GET_RTX_FORMAT (code
);
11241 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11243 ret
+= count_rtxs (XEXP (x
, i
));
11248 /* Utility function for following routine. Called when X is part of a value
11249 being stored into last_set_value. Sets last_set_table_tick
11250 for each register mentioned. Similar to mention_regs in cse.c */
11253 update_table_tick (rtx x
)
11255 enum rtx_code code
= GET_CODE (x
);
11256 const char *fmt
= GET_RTX_FORMAT (code
);
11261 unsigned int regno
= REGNO (x
);
11262 unsigned int endregno
= END_REGNO (x
);
11265 for (r
= regno
; r
< endregno
; r
++)
11267 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
11268 rsp
->last_set_table_tick
= label_tick
;
11274 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11275 /* Note that we can't have an "E" in values stored; see
11276 get_last_value_validate. */
11279 /* Check for identical subexpressions. If x contains
11280 identical subexpression we only have to traverse one of
11282 if (i
== 0 && ARITHMETIC_P (x
))
11284 /* Note that at this point x1 has already been
11286 rtx x0
= XEXP (x
, 0);
11287 rtx x1
= XEXP (x
, 1);
11289 /* If x0 and x1 are identical then there is no need to
11294 /* If x0 is identical to a subexpression of x1 then while
11295 processing x1, x0 has already been processed. Thus we
11296 are done with x. */
11297 if (ARITHMETIC_P (x1
)
11298 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11301 /* If x1 is identical to a subexpression of x0 then we
11302 still have to process the rest of x0. */
11303 if (ARITHMETIC_P (x0
)
11304 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11306 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11311 update_table_tick (XEXP (x
, i
));
11315 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11316 are saying that the register is clobbered and we no longer know its
11317 value. If INSN is zero, don't update reg_stat[].last_set; this is
11318 only permitted with VALUE also zero and is used to invalidate the
11322 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11324 unsigned int regno
= REGNO (reg
);
11325 unsigned int endregno
= END_REGNO (reg
);
11327 reg_stat_type
*rsp
;
11329 /* If VALUE contains REG and we have a previous value for REG, substitute
11330 the previous value. */
11331 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11335 /* Set things up so get_last_value is allowed to see anything set up to
11337 subst_low_luid
= DF_INSN_LUID (insn
);
11338 tem
= get_last_value (reg
);
11340 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11341 it isn't going to be useful and will take a lot of time to process,
11342 so just use the CLOBBER. */
11346 if (ARITHMETIC_P (tem
)
11347 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11348 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11349 tem
= XEXP (tem
, 0);
11350 else if (count_occurrences (value
, reg
, 1) >= 2)
11352 /* If there are two or more occurrences of REG in VALUE,
11353 prevent the value from growing too much. */
11354 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
11355 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
11358 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11362 /* For each register modified, show we don't know its value, that
11363 we don't know about its bitwise content, that its value has been
11364 updated, and that we don't know the location of the death of the
11366 for (i
= regno
; i
< endregno
; i
++)
11368 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11371 rsp
->last_set
= insn
;
11373 rsp
->last_set_value
= 0;
11374 rsp
->last_set_mode
= 0;
11375 rsp
->last_set_nonzero_bits
= 0;
11376 rsp
->last_set_sign_bit_copies
= 0;
11377 rsp
->last_death
= 0;
11378 rsp
->truncated_to_mode
= 0;
11381 /* Mark registers that are being referenced in this value. */
11383 update_table_tick (value
);
11385 /* Now update the status of each register being set.
11386 If someone is using this register in this block, set this register
11387 to invalid since we will get confused between the two lives in this
11388 basic block. This makes using this register always invalid. In cse, we
11389 scan the table to invalidate all entries using this register, but this
11390 is too much work for us. */
11392 for (i
= regno
; i
< endregno
; i
++)
11394 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11395 rsp
->last_set_label
= label_tick
;
11397 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
11398 rsp
->last_set_invalid
= 1;
11400 rsp
->last_set_invalid
= 0;
11403 /* The value being assigned might refer to X (like in "x++;"). In that
11404 case, we must replace it with (clobber (const_int 0)) to prevent
11406 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11407 if (value
&& ! get_last_value_validate (&value
, insn
,
11408 rsp
->last_set_label
, 0))
11410 value
= copy_rtx (value
);
11411 if (! get_last_value_validate (&value
, insn
,
11412 rsp
->last_set_label
, 1))
11416 /* For the main register being modified, update the value, the mode, the
11417 nonzero bits, and the number of sign bit copies. */
11419 rsp
->last_set_value
= value
;
11423 enum machine_mode mode
= GET_MODE (reg
);
11424 subst_low_luid
= DF_INSN_LUID (insn
);
11425 rsp
->last_set_mode
= mode
;
11426 if (GET_MODE_CLASS (mode
) == MODE_INT
11427 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11428 mode
= nonzero_bits_mode
;
11429 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11430 rsp
->last_set_sign_bit_copies
11431 = num_sign_bit_copies (value
, GET_MODE (reg
));
11435 /* Called via note_stores from record_dead_and_set_regs to handle one
11436 SET or CLOBBER in an insn. DATA is the instruction in which the
11437 set is occurring. */
11440 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
11442 rtx record_dead_insn
= (rtx
) data
;
11444 if (GET_CODE (dest
) == SUBREG
)
11445 dest
= SUBREG_REG (dest
);
11447 if (!record_dead_insn
)
11450 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
11456 /* If we are setting the whole register, we know its value. Otherwise
11457 show that we don't know the value. We can handle SUBREG in
11459 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11460 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11461 else if (GET_CODE (setter
) == SET
11462 && GET_CODE (SET_DEST (setter
)) == SUBREG
11463 && SUBREG_REG (SET_DEST (setter
)) == dest
11464 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11465 && subreg_lowpart_p (SET_DEST (setter
)))
11466 record_value_for_reg (dest
, record_dead_insn
,
11467 gen_lowpart (GET_MODE (dest
),
11468 SET_SRC (setter
)));
11470 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11472 else if (MEM_P (dest
)
11473 /* Ignore pushes, they clobber nothing. */
11474 && ! push_operand (dest
, GET_MODE (dest
)))
11475 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
11478 /* Update the records of when each REG was most recently set or killed
11479 for the things done by INSN. This is the last thing done in processing
11480 INSN in the combiner loop.
11482 We update reg_stat[], in particular fields last_set, last_set_value,
11483 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11484 last_death, and also the similar information mem_last_set (which insn
11485 most recently modified memory) and last_call_luid (which insn was the
11486 most recent subroutine call). */
11489 record_dead_and_set_regs (rtx insn
)
11494 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11496 if (REG_NOTE_KIND (link
) == REG_DEAD
11497 && REG_P (XEXP (link
, 0)))
11499 unsigned int regno
= REGNO (XEXP (link
, 0));
11500 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
11502 for (i
= regno
; i
< endregno
; i
++)
11504 reg_stat_type
*rsp
;
11506 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11507 rsp
->last_death
= insn
;
11510 else if (REG_NOTE_KIND (link
) == REG_INC
)
11511 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11516 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11517 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11519 reg_stat_type
*rsp
;
11521 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11522 rsp
->last_set_invalid
= 1;
11523 rsp
->last_set
= insn
;
11524 rsp
->last_set_value
= 0;
11525 rsp
->last_set_mode
= 0;
11526 rsp
->last_set_nonzero_bits
= 0;
11527 rsp
->last_set_sign_bit_copies
= 0;
11528 rsp
->last_death
= 0;
11529 rsp
->truncated_to_mode
= 0;
11532 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
11534 /* We can't combine into a call pattern. Remember, though, that
11535 the return value register is set at this LUID. We could
11536 still replace a register with the return value from the
11537 wrong subroutine call! */
11538 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
11541 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11544 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11545 register present in the SUBREG, so for each such SUBREG go back and
11546 adjust nonzero and sign bit information of the registers that are
11547 known to have some zero/sign bits set.
11549 This is needed because when combine blows the SUBREGs away, the
11550 information on zero/sign bits is lost and further combines can be
11551 missed because of that. */
11554 record_promoted_value (rtx insn
, rtx subreg
)
11557 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11558 enum machine_mode mode
= GET_MODE (subreg
);
11560 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11563 for (links
= LOG_LINKS (insn
); links
;)
11565 reg_stat_type
*rsp
;
11567 insn
= XEXP (links
, 0);
11568 set
= single_set (insn
);
11570 if (! set
|| !REG_P (SET_DEST (set
))
11571 || REGNO (SET_DEST (set
)) != regno
11572 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11574 links
= XEXP (links
, 1);
11578 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11579 if (rsp
->last_set
== insn
)
11581 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11582 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11585 if (REG_P (SET_SRC (set
)))
11587 regno
= REGNO (SET_SRC (set
));
11588 links
= LOG_LINKS (insn
);
11595 /* Check if X, a register, is known to contain a value already
11596 truncated to MODE. In this case we can use a subreg to refer to
11597 the truncated value even though in the generic case we would need
11598 an explicit truncation. */
11601 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
11603 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
11604 enum machine_mode truncated
= rsp
->truncated_to_mode
;
11607 || rsp
->truncation_label
< label_tick_ebb_start
)
11609 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
11611 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
11612 GET_MODE_BITSIZE (truncated
)))
11617 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11618 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11619 a truncate into a subreg using this information. */
11622 record_truncated_value (rtx x
)
11624 enum machine_mode truncated_mode
;
11625 reg_stat_type
*rsp
;
11627 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
11629 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
11630 truncated_mode
= GET_MODE (x
);
11632 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
11635 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
11636 GET_MODE_BITSIZE (original_mode
)))
11639 x
= SUBREG_REG (x
);
11641 /* ??? For hard-regs we now record everything. We might be able to
11642 optimize this using last_set_mode. */
11643 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
11644 truncated_mode
= GET_MODE (x
);
11648 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
11649 if (rsp
->truncated_to_mode
== 0
11650 || rsp
->truncation_label
< label_tick_ebb_start
11651 || (GET_MODE_SIZE (truncated_mode
)
11652 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
11654 rsp
->truncated_to_mode
= truncated_mode
;
11655 rsp
->truncation_label
= label_tick
;
11659 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11660 found, note what it implies to the registers used in it. */
11663 check_conversions (rtx insn
, rtx x
)
11665 if (GET_CODE (x
) == SUBREG
|| REG_P (x
))
11667 if (GET_CODE (x
) == SUBREG
11668 && SUBREG_PROMOTED_VAR_P (x
)
11669 && REG_P (SUBREG_REG (x
)))
11670 record_promoted_value (insn
, x
);
11672 record_truncated_value (x
);
11676 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11679 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11683 check_conversions (insn
, XEXP (x
, i
));
11687 if (XVEC (x
, i
) != 0)
11688 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11689 check_conversions (insn
, XVECEXP (x
, i
, j
));
11695 /* Utility routine for the following function. Verify that all the registers
11696 mentioned in *LOC are valid when *LOC was part of a value set when
11697 label_tick == TICK. Return 0 if some are not.
11699 If REPLACE is nonzero, replace the invalid reference with
11700 (clobber (const_int 0)) and return 1. This replacement is useful because
11701 we often can get useful information about the form of a value (e.g., if
11702 it was produced by a shift that always produces -1 or 0) even though
11703 we don't know exactly what registers it was produced from. */
11706 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11709 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11710 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11715 unsigned int regno
= REGNO (x
);
11716 unsigned int endregno
= END_REGNO (x
);
11719 for (j
= regno
; j
< endregno
; j
++)
11721 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
11722 if (rsp
->last_set_invalid
11723 /* If this is a pseudo-register that was only set once and not
11724 live at the beginning of the function, it is always valid. */
11725 || (! (regno
>= FIRST_PSEUDO_REGISTER
11726 && REG_N_SETS (regno
) == 1
11727 && (!REGNO_REG_SET_P
11728 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
11729 && rsp
->last_set_label
> tick
))
11732 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11739 /* If this is a memory reference, make sure that there were
11740 no stores after it that might have clobbered the value. We don't
11741 have alias info, so we assume any store invalidates it. */
11742 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11743 && DF_INSN_LUID (insn
) <= mem_last_set
)
11746 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11750 for (i
= 0; i
< len
; i
++)
11754 /* Check for identical subexpressions. If x contains
11755 identical subexpression we only have to traverse one of
11757 if (i
== 1 && ARITHMETIC_P (x
))
11759 /* Note that at this point x0 has already been checked
11760 and found valid. */
11761 rtx x0
= XEXP (x
, 0);
11762 rtx x1
= XEXP (x
, 1);
11764 /* If x0 and x1 are identical then x is also valid. */
11768 /* If x1 is identical to a subexpression of x0 then
11769 while checking x0, x1 has already been checked. Thus
11770 it is valid and so as x. */
11771 if (ARITHMETIC_P (x0
)
11772 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11775 /* If x0 is identical to a subexpression of x1 then x is
11776 valid iff the rest of x1 is valid. */
11777 if (ARITHMETIC_P (x1
)
11778 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11780 get_last_value_validate (&XEXP (x1
,
11781 x0
== XEXP (x1
, 0) ? 1 : 0),
11782 insn
, tick
, replace
);
11785 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11789 /* Don't bother with these. They shouldn't occur anyway. */
11790 else if (fmt
[i
] == 'E')
11794 /* If we haven't found a reason for it to be invalid, it is valid. */
11798 /* Get the last value assigned to X, if known. Some registers
11799 in the value may be replaced with (clobber (const_int 0)) if their value
11800 is known longer known reliably. */
11803 get_last_value (const_rtx x
)
11805 unsigned int regno
;
11807 reg_stat_type
*rsp
;
11809 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11810 then convert it to the desired mode. If this is a paradoxical SUBREG,
11811 we cannot predict what values the "extra" bits might have. */
11812 if (GET_CODE (x
) == SUBREG
11813 && subreg_lowpart_p (x
)
11814 && (GET_MODE_SIZE (GET_MODE (x
))
11815 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11816 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11817 return gen_lowpart (GET_MODE (x
), value
);
11823 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11824 value
= rsp
->last_set_value
;
11826 /* If we don't have a value, or if it isn't for this basic block and
11827 it's either a hard register, set more than once, or it's a live
11828 at the beginning of the function, return 0.
11830 Because if it's not live at the beginning of the function then the reg
11831 is always set before being used (is never used without being set).
11832 And, if it's set only once, and it's always set before use, then all
11833 uses must have the same last value, even if it's not from this basic
11837 || (rsp
->last_set_label
< label_tick_ebb_start
11838 && (regno
< FIRST_PSEUDO_REGISTER
11839 || REG_N_SETS (regno
) != 1
11841 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
11844 /* If the value was set in a later insn than the ones we are processing,
11845 we can't use it even if the register was only set once. */
11846 if (rsp
->last_set_label
== label_tick
11847 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
11850 /* If the value has all its registers valid, return it. */
11851 if (get_last_value_validate (&value
, rsp
->last_set
,
11852 rsp
->last_set_label
, 0))
11855 /* Otherwise, make a copy and replace any invalid register with
11856 (clobber (const_int 0)). If that fails for some reason, return 0. */
11858 value
= copy_rtx (value
);
11859 if (get_last_value_validate (&value
, rsp
->last_set
,
11860 rsp
->last_set_label
, 1))
11866 /* Return nonzero if expression X refers to a REG or to memory
11867 that is set in an instruction more recent than FROM_LUID. */
11870 use_crosses_set_p (const_rtx x
, int from_luid
)
11874 enum rtx_code code
= GET_CODE (x
);
11878 unsigned int regno
= REGNO (x
);
11879 unsigned endreg
= END_REGNO (x
);
11881 #ifdef PUSH_ROUNDING
11882 /* Don't allow uses of the stack pointer to be moved,
11883 because we don't know whether the move crosses a push insn. */
11884 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11887 for (; regno
< endreg
; regno
++)
11889 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11891 && rsp
->last_set_label
== label_tick
11892 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
11898 if (code
== MEM
&& mem_last_set
> from_luid
)
11901 fmt
= GET_RTX_FORMAT (code
);
11903 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11908 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11909 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
11912 else if (fmt
[i
] == 'e'
11913 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
11919 /* Define three variables used for communication between the following
11922 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11923 static int reg_dead_flag
;
11925 /* Function called via note_stores from reg_dead_at_p.
11927 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11928 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11931 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
11933 unsigned int regno
, endregno
;
11938 regno
= REGNO (dest
);
11939 endregno
= END_REGNO (dest
);
11940 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11941 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11944 /* Return nonzero if REG is known to be dead at INSN.
11946 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11947 referencing REG, it is dead. If we hit a SET referencing REG, it is
11948 live. Otherwise, see if it is live or dead at the start of the basic
11949 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11950 must be assumed to be always live. */
11953 reg_dead_at_p (rtx reg
, rtx insn
)
11958 /* Set variables for reg_dead_at_p_1. */
11959 reg_dead_regno
= REGNO (reg
);
11960 reg_dead_endregno
= END_REGNO (reg
);
11964 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11965 we allow the machine description to decide whether use-and-clobber
11966 patterns are OK. */
11967 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11969 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11970 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11974 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11975 beginning of function. */
11976 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11977 insn
= prev_nonnote_insn (insn
))
11979 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11981 return reg_dead_flag
== 1 ? 1 : 0;
11983 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11987 /* Get the basic block that we were in. */
11989 block
= ENTRY_BLOCK_PTR
->next_bb
;
11992 FOR_EACH_BB (block
)
11993 if (insn
== BB_HEAD (block
))
11996 if (block
== EXIT_BLOCK_PTR
)
12000 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12001 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12007 /* Note hard registers in X that are used. */
12010 mark_used_regs_combine (rtx x
)
12012 RTX_CODE code
= GET_CODE (x
);
12013 unsigned int regno
;
12026 case ADDR_DIFF_VEC
:
12029 /* CC0 must die in the insn after it is set, so we don't need to take
12030 special note of it here. */
12036 /* If we are clobbering a MEM, mark any hard registers inside the
12037 address as used. */
12038 if (MEM_P (XEXP (x
, 0)))
12039 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12044 /* A hard reg in a wide mode may really be multiple registers.
12045 If so, mark all of them just like the first. */
12046 if (regno
< FIRST_PSEUDO_REGISTER
)
12048 /* None of this applies to the stack, frame or arg pointers. */
12049 if (regno
== STACK_POINTER_REGNUM
12050 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12051 || regno
== HARD_FRAME_POINTER_REGNUM
12053 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12054 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12056 || regno
== FRAME_POINTER_REGNUM
)
12059 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12065 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12067 rtx testreg
= SET_DEST (x
);
12069 while (GET_CODE (testreg
) == SUBREG
12070 || GET_CODE (testreg
) == ZERO_EXTRACT
12071 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12072 testreg
= XEXP (testreg
, 0);
12074 if (MEM_P (testreg
))
12075 mark_used_regs_combine (XEXP (testreg
, 0));
12077 mark_used_regs_combine (SET_SRC (x
));
12085 /* Recursively scan the operands of this expression. */
12088 const char *fmt
= GET_RTX_FORMAT (code
);
12090 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12093 mark_used_regs_combine (XEXP (x
, i
));
12094 else if (fmt
[i
] == 'E')
12098 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12099 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12105 /* Remove register number REGNO from the dead registers list of INSN.
12107 Return the note used to record the death, if there was one. */
12110 remove_death (unsigned int regno
, rtx insn
)
12112 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12115 remove_note (insn
, note
);
12120 /* For each register (hardware or pseudo) used within expression X, if its
12121 death is in an instruction with luid between FROM_LUID (inclusive) and
12122 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12123 list headed by PNOTES.
12125 That said, don't move registers killed by maybe_kill_insn.
12127 This is done when X is being merged by combination into TO_INSN. These
12128 notes will then be distributed as needed. */
12131 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12136 enum rtx_code code
= GET_CODE (x
);
12140 unsigned int regno
= REGNO (x
);
12141 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12143 /* Don't move the register if it gets killed in between from and to. */
12144 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12145 && ! reg_referenced_p (x
, maybe_kill_insn
))
12149 && DF_INSN_LUID (where_dead
) >= from_luid
12150 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12152 rtx note
= remove_death (regno
, where_dead
);
12154 /* It is possible for the call above to return 0. This can occur
12155 when last_death points to I2 or I1 that we combined with.
12156 In that case make a new note.
12158 We must also check for the case where X is a hard register
12159 and NOTE is a death note for a range of hard registers
12160 including X. In that case, we must put REG_DEAD notes for
12161 the remaining registers in place of NOTE. */
12163 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12164 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12165 > GET_MODE_SIZE (GET_MODE (x
))))
12167 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12168 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12169 unsigned int ourend
= END_HARD_REGNO (x
);
12172 for (i
= deadregno
; i
< deadend
; i
++)
12173 if (i
< regno
|| i
>= ourend
)
12174 REG_NOTES (where_dead
)
12175 = gen_rtx_EXPR_LIST (REG_DEAD
,
12177 REG_NOTES (where_dead
));
12180 /* If we didn't find any note, or if we found a REG_DEAD note that
12181 covers only part of the given reg, and we have a multi-reg hard
12182 register, then to be safe we must check for REG_DEAD notes
12183 for each register other than the first. They could have
12184 their own REG_DEAD notes lying around. */
12185 else if ((note
== 0
12187 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12188 < GET_MODE_SIZE (GET_MODE (x
)))))
12189 && regno
< FIRST_PSEUDO_REGISTER
12190 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12192 unsigned int ourend
= END_HARD_REGNO (x
);
12193 unsigned int i
, offset
;
12197 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12201 for (i
= regno
+ offset
; i
< ourend
; i
++)
12202 move_deaths (regno_reg_rtx
[i
],
12203 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12206 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12208 XEXP (note
, 1) = *pnotes
;
12212 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12218 else if (GET_CODE (x
) == SET
)
12220 rtx dest
= SET_DEST (x
);
12222 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12224 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12225 that accesses one word of a multi-word item, some
12226 piece of everything register in the expression is used by
12227 this insn, so remove any old death. */
12228 /* ??? So why do we test for equality of the sizes? */
12230 if (GET_CODE (dest
) == ZERO_EXTRACT
12231 || GET_CODE (dest
) == STRICT_LOW_PART
12232 || (GET_CODE (dest
) == SUBREG
12233 && (((GET_MODE_SIZE (GET_MODE (dest
))
12234 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12235 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12236 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12238 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12242 /* If this is some other SUBREG, we know it replaces the entire
12243 value, so use that as the destination. */
12244 if (GET_CODE (dest
) == SUBREG
)
12245 dest
= SUBREG_REG (dest
);
12247 /* If this is a MEM, adjust deaths of anything used in the address.
12248 For a REG (the only other possibility), the entire value is
12249 being replaced so the old value is not used in this insn. */
12252 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
12257 else if (GET_CODE (x
) == CLOBBER
)
12260 len
= GET_RTX_LENGTH (code
);
12261 fmt
= GET_RTX_FORMAT (code
);
12263 for (i
= 0; i
< len
; i
++)
12268 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12269 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
12272 else if (fmt
[i
] == 'e')
12273 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12277 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12278 pattern of an insn. X must be a REG. */
12281 reg_bitfield_target_p (rtx x
, rtx body
)
12285 if (GET_CODE (body
) == SET
)
12287 rtx dest
= SET_DEST (body
);
12289 unsigned int regno
, tregno
, endregno
, endtregno
;
12291 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12292 target
= XEXP (dest
, 0);
12293 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12294 target
= SUBREG_REG (XEXP (dest
, 0));
12298 if (GET_CODE (target
) == SUBREG
)
12299 target
= SUBREG_REG (target
);
12301 if (!REG_P (target
))
12304 tregno
= REGNO (target
), regno
= REGNO (x
);
12305 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12306 return target
== x
;
12308 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
12309 endregno
= end_hard_regno (GET_MODE (x
), regno
);
12311 return endregno
> tregno
&& regno
< endtregno
;
12314 else if (GET_CODE (body
) == PARALLEL
)
12315 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12316 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12322 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12323 as appropriate. I3 and I2 are the insns resulting from the combination
12324 insns including FROM (I2 may be zero).
12326 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12327 not need REG_DEAD notes because they are being substituted for. This
12328 saves searching in the most common cases.
12330 Each note in the list is either ignored or placed on some insns, depending
12331 on the type of note. */
12334 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
12337 rtx note
, next_note
;
12340 for (note
= notes
; note
; note
= next_note
)
12342 rtx place
= 0, place2
= 0;
12344 next_note
= XEXP (note
, 1);
12345 switch (REG_NOTE_KIND (note
))
12349 /* Doesn't matter much where we put this, as long as it's somewhere.
12350 It is preferable to keep these notes on branches, which is most
12351 likely to be i3. */
12355 case REG_VALUE_PROFILE
:
12356 /* Just get rid of this note, as it is unused later anyway. */
12359 case REG_NON_LOCAL_GOTO
:
12364 gcc_assert (i2
&& JUMP_P (i2
));
12369 case REG_EH_REGION
:
12370 /* These notes must remain with the call or trapping instruction. */
12373 else if (i2
&& CALL_P (i2
))
12377 gcc_assert (flag_non_call_exceptions
);
12378 if (may_trap_p (i3
))
12380 else if (i2
&& may_trap_p (i2
))
12382 /* ??? Otherwise assume we've combined things such that we
12383 can now prove that the instructions can't trap. Drop the
12384 note in this case. */
12390 /* These notes must remain with the call. It should not be
12391 possible for both I2 and I3 to be a call. */
12396 gcc_assert (i2
&& CALL_P (i2
));
12402 /* Any clobbers for i3 may still exist, and so we must process
12403 REG_UNUSED notes from that insn.
12405 Any clobbers from i2 or i1 can only exist if they were added by
12406 recog_for_combine. In that case, recog_for_combine created the
12407 necessary REG_UNUSED notes. Trying to keep any original
12408 REG_UNUSED notes from these insns can cause incorrect output
12409 if it is for the same register as the original i3 dest.
12410 In that case, we will notice that the register is set in i3,
12411 and then add a REG_UNUSED note for the destination of i3, which
12412 is wrong. However, it is possible to have REG_UNUSED notes from
12413 i2 or i1 for register which were both used and clobbered, so
12414 we keep notes from i2 or i1 if they will turn into REG_DEAD
12417 /* If this register is set or clobbered in I3, put the note there
12418 unless there is one already. */
12419 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12421 if (from_insn
!= i3
)
12424 if (! (REG_P (XEXP (note
, 0))
12425 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12426 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12429 /* Otherwise, if this register is used by I3, then this register
12430 now dies here, so we must put a REG_DEAD note here unless there
12432 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12433 && ! (REG_P (XEXP (note
, 0))
12434 ? find_regno_note (i3
, REG_DEAD
,
12435 REGNO (XEXP (note
, 0)))
12436 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12438 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12446 /* These notes say something about results of an insn. We can
12447 only support them if they used to be on I3 in which case they
12448 remain on I3. Otherwise they are ignored.
12450 If the note refers to an expression that is not a constant, we
12451 must also ignore the note since we cannot tell whether the
12452 equivalence is still true. It might be possible to do
12453 slightly better than this (we only have a problem if I2DEST
12454 or I1DEST is present in the expression), but it doesn't
12455 seem worth the trouble. */
12457 if (from_insn
== i3
12458 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12463 case REG_NO_CONFLICT
:
12464 /* These notes say something about how a register is used. They must
12465 be present on any use of the register in I2 or I3. */
12466 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12469 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12478 case REG_LABEL_TARGET
:
12479 case REG_LABEL_OPERAND
:
12480 /* This can show up in several ways -- either directly in the
12481 pattern, or hidden off in the constant pool with (or without?)
12482 a REG_EQUAL note. */
12483 /* ??? Ignore the without-reg_equal-note problem for now. */
12484 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12485 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12486 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12487 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12491 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12492 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12493 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12494 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12502 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12503 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12505 if (place
&& JUMP_P (place
)
12506 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
12507 && (JUMP_LABEL (place
) == NULL
12508 || JUMP_LABEL (place
) == XEXP (note
, 0)))
12510 rtx label
= JUMP_LABEL (place
);
12513 JUMP_LABEL (place
) = XEXP (note
, 0);
12514 else if (LABEL_P (label
))
12515 LABEL_NUSES (label
)--;
12518 if (place2
&& JUMP_P (place2
)
12519 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
12520 && (JUMP_LABEL (place2
) == NULL
12521 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
12523 rtx label
= JUMP_LABEL (place2
);
12526 JUMP_LABEL (place2
) = XEXP (note
, 0);
12527 else if (LABEL_P (label
))
12528 LABEL_NUSES (label
)--;
12534 /* This note says something about the value of a register prior
12535 to the execution of an insn. It is too much trouble to see
12536 if the note is still correct in all situations. It is better
12537 to simply delete it. */
12541 /* If the insn previously containing this note still exists,
12542 put it back where it was. Otherwise move it to the previous
12543 insn. Adjust the corresponding REG_LIBCALL note. */
12544 if (!NOTE_P (from_insn
))
12548 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12549 place
= prev_real_insn (from_insn
);
12551 XEXP (tem
, 0) = place
;
12552 /* If we're deleting the last remaining instruction of a
12553 libcall sequence, don't add the notes. */
12554 else if (XEXP (note
, 0) == from_insn
)
12556 /* Don't add the dangling REG_RETVAL note. */
12563 /* This is handled similarly to REG_RETVAL. */
12564 if (!NOTE_P (from_insn
))
12568 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12569 place
= next_real_insn (from_insn
);
12571 XEXP (tem
, 0) = place
;
12572 /* If we're deleting the last remaining instruction of a
12573 libcall sequence, don't add the notes. */
12574 else if (XEXP (note
, 0) == from_insn
)
12576 /* Don't add the dangling REG_LIBCALL note. */
12583 /* If we replaced the right hand side of FROM_INSN with a
12584 REG_EQUAL note, the original use of the dying register
12585 will not have been combined into I3 and I2. In such cases,
12586 FROM_INSN is guaranteed to be the first of the combined
12587 instructions, so we simply need to search back before
12588 FROM_INSN for the previous use or set of this register,
12589 then alter the notes there appropriately.
12591 If the register is used as an input in I3, it dies there.
12592 Similarly for I2, if it is nonzero and adjacent to I3.
12594 If the register is not used as an input in either I3 or I2
12595 and it is not one of the registers we were supposed to eliminate,
12596 there are two possibilities. We might have a non-adjacent I2
12597 or we might have somehow eliminated an additional register
12598 from a computation. For example, we might have had A & B where
12599 we discover that B will always be zero. In this case we will
12600 eliminate the reference to A.
12602 In both cases, we must search to see if we can find a previous
12603 use of A and put the death note there. */
12606 && from_insn
== i2mod
12607 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
12612 && CALL_P (from_insn
)
12613 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12615 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12617 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12618 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12620 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
12622 && reg_overlap_mentioned_p (XEXP (note
, 0),
12624 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12631 basic_block bb
= this_basic_block
;
12633 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
12635 if (! INSN_P (tem
))
12637 if (tem
== BB_HEAD (bb
))
12642 /* If the register is being set at TEM, see if that is all
12643 TEM is doing. If so, delete TEM. Otherwise, make this
12644 into a REG_UNUSED note instead. Don't delete sets to
12645 global register vars. */
12646 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12647 || !global_regs
[REGNO (XEXP (note
, 0))])
12648 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12650 rtx set
= single_set (tem
);
12651 rtx inner_dest
= 0;
12653 rtx cc0_setter
= NULL_RTX
;
12657 for (inner_dest
= SET_DEST (set
);
12658 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12659 || GET_CODE (inner_dest
) == SUBREG
12660 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12661 inner_dest
= XEXP (inner_dest
, 0))
12664 /* Verify that it was the set, and not a clobber that
12665 modified the register.
12667 CC0 targets must be careful to maintain setter/user
12668 pairs. If we cannot delete the setter due to side
12669 effects, mark the user with an UNUSED note instead
12672 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12673 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12675 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12676 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12677 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12681 /* Move the notes and links of TEM elsewhere.
12682 This might delete other dead insns recursively.
12683 First set the pattern to something that won't use
12685 rtx old_notes
= REG_NOTES (tem
);
12687 PATTERN (tem
) = pc_rtx
;
12688 REG_NOTES (tem
) = NULL
;
12690 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
12691 NULL_RTX
, NULL_RTX
);
12692 distribute_links (LOG_LINKS (tem
));
12694 SET_INSN_DELETED (tem
);
12697 /* Delete the setter too. */
12700 PATTERN (cc0_setter
) = pc_rtx
;
12701 old_notes
= REG_NOTES (cc0_setter
);
12702 REG_NOTES (cc0_setter
) = NULL
;
12704 distribute_notes (old_notes
, cc0_setter
,
12705 cc0_setter
, NULL_RTX
,
12706 NULL_RTX
, NULL_RTX
);
12707 distribute_links (LOG_LINKS (cc0_setter
));
12709 SET_INSN_DELETED (cc0_setter
);
12715 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12717 /* If there isn't already a REG_UNUSED note, put one
12718 here. Do not place a REG_DEAD note, even if
12719 the register is also used here; that would not
12720 match the algorithm used in lifetime analysis
12721 and can cause the consistency check in the
12722 scheduler to fail. */
12723 if (! find_regno_note (tem
, REG_UNUSED
,
12724 REGNO (XEXP (note
, 0))))
12729 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12731 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12735 /* If we are doing a 3->2 combination, and we have a
12736 register which formerly died in i3 and was not used
12737 by i2, which now no longer dies in i3 and is used in
12738 i2 but does not die in i2, and place is between i2
12739 and i3, then we may need to move a link from place to
12741 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
12743 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
12744 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12746 rtx links
= LOG_LINKS (place
);
12747 LOG_LINKS (place
) = 0;
12748 distribute_links (links
);
12753 if (tem
== BB_HEAD (bb
))
12759 /* If the register is set or already dead at PLACE, we needn't do
12760 anything with this note if it is still a REG_DEAD note.
12761 We check here if it is set at all, not if is it totally replaced,
12762 which is what `dead_or_set_p' checks, so also check for it being
12765 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12767 unsigned int regno
= REGNO (XEXP (note
, 0));
12768 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12770 if (dead_or_set_p (place
, XEXP (note
, 0))
12771 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12773 /* Unless the register previously died in PLACE, clear
12774 last_death. [I no longer understand why this is
12776 if (rsp
->last_death
!= place
)
12777 rsp
->last_death
= 0;
12781 rsp
->last_death
= place
;
12783 /* If this is a death note for a hard reg that is occupying
12784 multiple registers, ensure that we are still using all
12785 parts of the object. If we find a piece of the object
12786 that is unused, we must arrange for an appropriate REG_DEAD
12787 note to be added for it. However, we can't just emit a USE
12788 and tag the note to it, since the register might actually
12789 be dead; so we recourse, and the recursive call then finds
12790 the previous insn that used this register. */
12792 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12793 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12795 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
12799 for (i
= regno
; i
< endregno
; i
++)
12800 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12801 && ! find_regno_fusage (place
, USE
, i
))
12802 || dead_or_set_regno_p (place
, i
))
12807 /* Put only REG_DEAD notes for pieces that are
12808 not already dead or set. */
12810 for (i
= regno
; i
< endregno
;
12811 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12813 rtx piece
= regno_reg_rtx
[i
];
12814 basic_block bb
= this_basic_block
;
12816 if (! dead_or_set_p (place
, piece
)
12817 && ! reg_bitfield_target_p (piece
,
12821 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12823 distribute_notes (new_note
, place
, place
,
12824 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12826 else if (! refers_to_regno_p (i
, i
+ 1,
12827 PATTERN (place
), 0)
12828 && ! find_regno_fusage (place
, USE
, i
))
12829 for (tem
= PREV_INSN (place
); ;
12830 tem
= PREV_INSN (tem
))
12832 if (! INSN_P (tem
))
12834 if (tem
== BB_HEAD (bb
))
12838 if (dead_or_set_p (tem
, piece
)
12839 || reg_bitfield_target_p (piece
,
12843 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12858 /* Any other notes should not be present at this point in the
12860 gcc_unreachable ();
12865 XEXP (note
, 1) = REG_NOTES (place
);
12866 REG_NOTES (place
) = note
;
12871 = gen_rtx_fmt_ee (GET_CODE (note
), REG_NOTE_KIND (note
),
12872 XEXP (note
, 0), REG_NOTES (place2
));
12876 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12877 I3, I2, and I1 to new locations. This is also called to add a link
12878 pointing at I3 when I3's destination is changed. */
12881 distribute_links (rtx links
)
12883 rtx link
, next_link
;
12885 for (link
= links
; link
; link
= next_link
)
12891 next_link
= XEXP (link
, 1);
12893 /* If the insn that this link points to is a NOTE or isn't a single
12894 set, ignore it. In the latter case, it isn't clear what we
12895 can do other than ignore the link, since we can't tell which
12896 register it was for. Such links wouldn't be used by combine
12899 It is not possible for the destination of the target of the link to
12900 have been changed by combine. The only potential of this is if we
12901 replace I3, I2, and I1 by I3 and I2. But in that case the
12902 destination of I2 also remains unchanged. */
12904 if (NOTE_P (XEXP (link
, 0))
12905 || (set
= single_set (XEXP (link
, 0))) == 0)
12908 reg
= SET_DEST (set
);
12909 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12910 || GET_CODE (reg
) == STRICT_LOW_PART
)
12911 reg
= XEXP (reg
, 0);
12913 /* A LOG_LINK is defined as being placed on the first insn that uses
12914 a register and points to the insn that sets the register. Start
12915 searching at the next insn after the target of the link and stop
12916 when we reach a set of the register or the end of the basic block.
12918 Note that this correctly handles the link that used to point from
12919 I3 to I2. Also note that not much searching is typically done here
12920 since most links don't point very far away. */
12922 for (insn
= NEXT_INSN (XEXP (link
, 0));
12923 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12924 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12925 insn
= NEXT_INSN (insn
))
12926 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12928 if (reg_referenced_p (reg
, PATTERN (insn
)))
12932 else if (CALL_P (insn
)
12933 && find_reg_fusage (insn
, USE
, reg
))
12938 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12941 /* If we found a place to put the link, place it there unless there
12942 is already a link to the same insn as LINK at that point. */
12948 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12949 if (XEXP (link2
, 0) == XEXP (link
, 0))
12954 XEXP (link
, 1) = LOG_LINKS (place
);
12955 LOG_LINKS (place
) = link
;
12957 /* Set added_links_insn to the earliest insn we added a
12959 if (added_links_insn
== 0
12960 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
12961 added_links_insn
= place
;
12967 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12968 Check whether the expression pointer to by LOC is a register or
12969 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12970 Otherwise return zero. */
12973 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12978 && (REG_P (x
) || MEM_P (x
))
12979 && ! reg_mentioned_p (x
, (rtx
) expr
))
12984 /* Check for any register or memory mentioned in EQUIV that is not
12985 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12986 of EXPR where some registers may have been replaced by constants. */
12989 unmentioned_reg_p (rtx equiv
, rtx expr
)
12991 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12995 dump_combine_stats (FILE *file
)
12999 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13000 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13004 dump_combine_total_stats (FILE *file
)
13008 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13009 total_attempts
, total_merges
, total_extras
, total_successes
);
13013 gate_handle_combine (void)
13015 return (optimize
> 0);
13018 /* Try combining insns through substitution. */
13019 static unsigned int
13020 rest_of_handle_combine (void)
13022 int rebuild_jump_labels_after_combine
;
13024 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13025 df_note_add_problem ();
13028 regstat_init_n_sets_and_refs ();
13030 rebuild_jump_labels_after_combine
13031 = combine_instructions (get_insns (), max_reg_num ());
13033 /* Combining insns may have turned an indirect jump into a
13034 direct jump. Rebuild the JUMP_LABEL fields of jumping
13036 if (rebuild_jump_labels_after_combine
)
13038 timevar_push (TV_JUMP
);
13039 rebuild_jump_labels (get_insns ());
13041 timevar_pop (TV_JUMP
);
13044 regstat_free_n_sets_and_refs ();
13048 struct rtl_opt_pass pass_combine
=
13052 "combine", /* name */
13053 gate_handle_combine
, /* gate */
13054 rest_of_handle_combine
, /* execute */
13057 0, /* static_pass_number */
13058 TV_COMBINE
, /* tv_id */
13059 0, /* properties_required */
13060 0, /* properties_provided */
13061 0, /* properties_destroyed */
13062 0, /* todo_flags_start */
13064 TODO_df_finish
| TODO_verify_rtl_sharing
|
13065 TODO_ggc_collect
, /* todo_flags_finish */